Photoelectric conversion device and photoelectric conversion system

Abstract

In a photoelectric converter that performs pupil-splitting focus detection, the amount of output data is reduced by suppressing the occurrence of pairs that cannot be compressed by addition. [Solution] The photoelectric conversion device has a plurality of pixels that have first and second photoelectric conversion units and a charge holding unit and output a signal corresponding to the charge of the charge holding unit, a control unit that controls charge transfer to the charge holding unit, and a signal processing unit. Each row of the plurality of pixels has a first pixel that transfers the charge of the first photoelectric conversion unit by a first signal and the charge of the second photoelectric conversion unit by a second signal, and a second pixel that transfers the charge of the first photoelectric conversion unit by a second signal and the charge of the second photoelectric conversion unit by a first signal. The control unit performs a first read operation by the first signal and a second read operation by the first and second signals for each row. The signal processing unit outputs a signal based on the charge of the first photoelectric conversion unit of the first pixel and signals based on the charges of the first and second photoelectric conversion units of the first pixel, but does not output a signal based on the charge of the second photoelectric conversion unit of the second pixel.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

Background Art

[0002] Patent Document 1 discloses an imaging device that performs pupil division type focus detection on an imaging surface. Further, Patent Document 2 discloses an imaging device configured to easily generate a phase difference signal by mixing pixels that read data of one of two divided photoelectric conversion units and pixels that read data of the other.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the imaging device described in Patent Document 2, since pairs that cannot be compressed by addition are included in the data read simultaneously, the amount of data from reading to generation of the phase difference signal increases, and as a result, the circuit scale and power consumption may increase.

[0005] An object of the present invention is to provide a technique for suppressing the occurrence of pairs that cannot be compressed by addition and reducing the number of signals and the amount of signal processing in a photoelectric conversion device that performs pupil division type focus detection on an imaging surface.

Means for Solving the Problems

[0006] According to one disclosure of this specification, a pixel unit is arranged in a plurality of rows and a plurality of columns, each having a first photoelectric conversion unit and a second photoelectric conversion unit sharing a single microlens, a charge holding unit that holds charges transferred from the first photoelectric conversion unit and the second photoelectric conversion unit, and an output unit that outputs a signal corresponding to the amount of charge held by the charge holding unit, a control unit that controls the transfer of charge from the first photoelectric conversion unit and the second photoelectric conversion unit to the charge holding unit in the plurality of pixels on a row-by-row basis, and a signal processing unit that processes the signal output from the pixel unit, wherein the pixel unit has a first pixel to which the charge of the first photoelectric conversion unit is transferred to the charge holding unit by a first control signal, and the charge of the second photoelectric conversion unit is transferred to the charge holding unit by a second control signal, and the first photoelectric conversion unit A photoelectric converter is provided, having a second pixel in each row, the charge of which is transferred to the charge holding unit, and the charge of the second photoelectric converter being transferred to the charge holding unit by the first control signal, the control unit performs a first read operation for each row, supplying the first control signal and not supplying the second control signal, and a second read operation, supplying the first control signal and the second control signal, the signal processing unit outputs a first signal based on the amount of charge of the first photoelectric converter read from the first pixel in response to the first read operation, and a second signal based on the total amount of charge of the first and second photoelectric converters read from the first pixel in response to the second read operation, and does not output a third signal based on the amount of charge of the second photoelectric converter read from the second pixel in response to the first read operation. [Effects of the Invention]

[0007] According to the present invention, in a photoelectric conversion device that performs pupil-splitting focus detection on the imaging surface, it is possible to reduce the number of signals and the amount of signal processing by suppressing the occurrence of pairs that cannot be compressed by addition. [Brief explanation of the drawing]

[0008] [Figure 1] This block diagram shows the schematic configuration of a photoelectric conversion device according to the first embodiment. [Figure 2]This is an equivalent circuit diagram showing an example of the pixel configuration of a photoelectric converter according to the first embodiment. [Figure 3] This is a plan view of the pixels of a photoelectric converter according to the first embodiment. [Figure 4] This is a circuit diagram showing the connection relationship between the pixel unit and the AD conversion unit in the photoelectric conversion device according to the first embodiment. [Figure 5] This is a timing diagram showing the driving method of the photoelectric converter according to the first embodiment. [Figure 6] This is a block diagram showing an example of the configuration of the signal processing unit in the signal processing device according to the first embodiment. [Figure 7] This block diagram shows the schematic configuration of the photoelectric conversion device according to the second embodiment. [Figure 8] This is a block diagram showing an example of the configuration of the signal conversion unit in a photoelectric conversion device according to the second embodiment. [Figure 9] This figure shows the operation of the signal conversion unit in the photoelectric converter according to the second embodiment. [Figure 10] This is a timing diagram showing the driving method of the photoelectric converter according to the second embodiment. [Figure 11] This is a block diagram showing an example of the configuration of the signal processing unit in a photoelectric conversion device according to the second embodiment. [Figure 12] This block diagram shows the schematic configuration of the photoelectric conversion device according to the third embodiment. [Figure 13] This is a circuit diagram showing the connection relationship between the pixel unit and the AD conversion unit in the photoelectric conversion device according to the third embodiment. [Figure 14] This is a diagram (part 1) showing the operation of the signal summing unit in the photoelectric conversion device according to the third embodiment. [Figure 15] This is a diagram (part 1) showing the operation of the signal summing unit in the photoelectric conversion device according to the third embodiment. [Figure 16] This is a timing diagram showing the driving method of the photoelectric converter according to the third embodiment. [Figure 17] This is a block diagram showing an example of the configuration of the signal processing unit in a photoelectric conversion device according to the third embodiment. [Figure 18]It is a diagram showing the operation of the signal processing unit in the photoelectric conversion device according to the third embodiment. [Figure 19] It is a timing diagram showing another driving method of the photoelectric conversion device according to the third embodiment. [Figure 20] It is a block diagram showing the schematic configuration of the photoelectric conversion system according to the fourth embodiment. [Figure 21] It is a diagram showing a configuration example of the photoelectric conversion system and the moving body according to the fifth embodiment. [Figure 22] It is a block diagram showing the schematic configuration of the device according to the sixth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the embodiments described below, as an example of the photoelectric conversion device, an apparatus for imaging applications will be mainly described. However, each embodiment is not limited to this imaging apparatus, and is also applicable to other examples included in the photoelectric conversion device. For example, there are ranging devices (devices for distance measurement using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the amount of incident light), and the like.

[0010] In the following embodiments, the connection between circuit elements may be described. In this case, even if another element is interposed between the elements of interest, unless otherwise specified, the elements of interest are treated as being connected. For example, assume that element A is connected to one node of a capacitive element C having a plurality of nodes, and element B is connected to the other node. Even in such a case, unless otherwise specified, elements A and B are treated as being connected.

[0011] [First Embodiment] A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Figures 1 to 4. Figure 1 is a block diagram showing the schematic configuration of the photoelectric conversion device according to this embodiment. Figure 2 is an equivalent circuit diagram showing an example of the pixel configuration of the photoelectric conversion device according to this embodiment. Figure 3 is a plan view of the pixel of the photoelectric conversion device according to this embodiment. Figure 4 is a circuit diagram showing the connection relationship between the pixel unit and the AD conversion unit in the photoelectric conversion device according to this embodiment.

[0012] As shown in Figure 1, the photoelectric converter 100 according to this embodiment includes a pixel unit 10, a vertical scanning unit 20, an AD conversion unit 30, a signal output unit 80, and a timing generation unit 90. The pixel unit 10 is connected to the vertical scanning unit 20 and the AD conversion unit 30. The AD conversion unit 30 is connected to the signal output unit 80. The timing generation unit 90 is connected to the vertical scanning unit 20 and the AD conversion unit 30. The signal output unit 80 is connected to the signal processing unit 120. Note that the signal processing unit 120 may be provided by a separate signal processing unit 110, as shown in Figure 1, or it may be part of the photoelectric converter 100. In this specification, the functional block from the AD conversion unit 30 to the signal processing unit 120 is sometimes collectively referred to as the signal processing unit.

[0013] The pixel section 10 is provided with multiple pixels 12 arranged in a two-dimensional manner across multiple rows and columns. Each of the multiple pixels 12 includes a photoelectric conversion unit and outputs a pixel signal corresponding to the amount of incident light. Each pixel 12 has one microlens and a color filter that transmits light in a predetermined wavelength range. In addition to the effective pixels that output a pixel signal corresponding to the amount of incident light, the pixel section 10 may also include optical black pixels in which the photoelectric conversion unit is shielded from light, and dummy pixels that do not output a signal.

[0014] Figure 3 shows the color of the color filter in each pixel 12, represented by one of the symbols R (Red), G (Green), or B (Blue). A pixel 12 with the symbol R is equipped with a red filter that has a transmission wavelength range in the red wavelength range. A pixel 12 with the symbol G is equipped with a green filter that has a transmission wavelength range in the green wavelength range. A pixel 12 with the symbol B is equipped with a blue filter that has a transmission wavelength range in the blue wavelength range. Hereafter, a pixel 12 equipped with a red filter may be referred to as R pixel 12R, a pixel 12 equipped with a green filter as G pixel 12G, and a pixel 12 equipped with a blue filter as B pixel 12B.

[0015] The R, G, and B pixels can be arranged according to a so-called Bayer array. In a Bayer array, as shown in Figure 1, for example, in the smallest repeating unit, a 2x2 pixel block, two G pixels are placed at one diagonal position, and an R pixel and a B pixel are placed at the other diagonal position. The pixel section 10 is formed by repeatedly arranging these pixel blocks in the row and column directions. For example, in odd-numbered rows starting from the first row, R pixels and G pixels are arranged alternately from the left end, and in even-numbered rows starting from the second row, G pixels and B pixels are arranged alternately from the left end. Note that the color filter array does not necessarily have to be a Bayer array; other arrays may be used.

[0016] Each row of the pixel section 10 has a control line 14 extending in a first direction (horizontal direction in Figure 1). Each control line 14 is connected to a pixel 12 arranged in the first direction, forming a common signal line for these pixels 12. The first direction in which the control lines 14 extend is sometimes called the row direction or horizontal direction. Each control line 14 may contain multiple signal lines. The control lines 14 are connected to the vertical scanning section 20.

[0017] Each row of the pixel section 10 has a signal output line 16 extending in a second direction (vertical direction in Figure 1) that intersects with the first direction. Each signal output line 16 is connected to a pixel 12 arranged in the second direction, forming a common signal line for these pixels 12. The second direction in which the signal output lines 16 extend is sometimes called the column direction or the vertical direction. Each signal output line 16 may contain multiple signal lines. The signal output lines 16 are connected to the AD conversion unit 30.

[0018] The vertical scanning unit 20 is a control unit that generates control signals to drive the pixels 12 in response to control signals from the timing generation unit 90 and outputs the generated control signals to the pixel unit 10. Logic circuits such as shift registers and address decoders may be used in the vertical scanning unit 20. The vertical scanning unit 20 sequentially outputs control signals to the control lines 14 of each row, performing a so-called vertical scan that sequentially drives the pixels 12 of the pixel unit 10 row by row. The pixel signals read from the pixels 12 row by row are input to the AD conversion unit 30 via the signal output line 16.

[0019] The AD conversion unit 30 has multiple AD conversion circuits and multiple memories corresponding to each row of the pixel unit 10. The AD conversion circuit for each row converts the pixel signal output from the pixel 12 of the corresponding row via the signal output line 16 into a digital signal and temporarily holds it in the memory of the corresponding row. The digital signals held in the memory of each row are transferred to the signal output unit 80 by a sequential transfer operation, also known as horizontal scanning, in accordance with the control signal from the timing generation unit 90.

[0020] In the configuration example shown in Figure 1, the AD conversion unit 30 is divided into two blocks: one that processes the pixel signals of a column containing R pixels and G pixels, and another that processes the pixel signals of a column containing G pixels and B pixels. These blocks are arranged above and below the pixel unit 10. However, the AD conversion unit 30 does not necessarily need to be divided into multiple blocks.

[0021] The signal output unit 80 converts the digital signal transferred from the AD conversion unit 30 into a signal compliant with the system's protocol and transfers it to the signal processing unit 110 via the bus. The external interface circuit provided by the signal output unit 80 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit can be applied to the external interface circuit. Examples of SerDes transmission circuits include LVDS (Low Voltage Differential Signaling) circuits and SLVS (Scalable Low Voltage Signaling) circuits. The signal processing unit 110 has a signal processing unit 120 capable of focus detection by phase difference detection.

[0022] The timing generation unit 90 has the function of generating control signals to drive the vertical scanning unit 20 and the AD conversion unit 30 in response to a reference drive signal of the photoelectric converter from an external input or a setting signal of the photoelectric converter from communication, and outputting these control signals to these functional blocks. The signals supplied from the timing generation unit 90 to the vertical scanning unit 20 may include a vertical address signal and a control timing signal for the pixels 12. The signals supplied from the timing generation unit 90 to the AD conversion unit 30 may include a control timing signal and a horizontal scanning signal. At least a portion of the control signals for controlling the operation of these functional blocks may be configured to be supplied from outside the photoelectric converter 100.

[0023] Each of the multiple pixels 12 constituting the pixel section 10 has, for example, a photoelectric conversion section PDA, PDB, a transfer transistor M1A, M1B, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, as shown in Figure 2. The photoelectric conversion sections PDA, PDB may be composed of photoelectric conversion elements, such as photodiodes. The transfer transistors M1A, M1B, reset transistor M2, amplification transistor M3, and selection transistor M4 may be composed of N-type MOS transistors.

[0024] The photoelectric converter PDA has its anode connected to the ground voltage node and its cathode connected to the source of the transfer transistor M1A. The photoelectric converter PDB also has its anode connected to the ground voltage node and its cathode connected to the source of the transfer transistor M1B. The drains of transfer transistors M1A and M1B are connected to the source of the reset transistor M2 and the gate of the amplifier transistor M3. Node FD, to which the drains of transfer transistors M1A and M1B, the source of reset transistor M2, and the gate of amplifier transistor M3 are connected, is a so-called floating diffusion section. The floating diffusion section contains capacitive components (floating diffusion capacitance) and functions as a charge holder. Floating diffusion capacitance may include pn junction capacitance, transistor gate capacitance, wiring capacitance, etc. The drains of reset transistor M2 and amplifier transistor M3 are connected to the node to which the power supply voltage (voltage VDD) is supplied. The source of amplifier transistor M3 is connected to the drain of selection transistor M4. The source of the selection transistor M4 is connected to the signal output line 16 of the column corresponding to the pixel 12.

[0025] In the circuit configuration shown in Figure 2, each row of control lines 14 includes four signal lines connected to the gates of the transfer transistor M1A, M1B, M2, and M4. The gate of the transfer transistor M1A is supplied with one of the control signals tx1 or tx2 (control signal tx1 in pixel 12 of Figure 2) from the vertical scanning unit 20. The gate of the transfer transistor M1B is supplied with the other of the control signals tx1 or tx2 (control signal tx2 in pixel 12 of Figure 2) from the vertical scanning unit 20. The combination of transfer transistors M1A, M1B and control signals tx1, tx2 varies depending on the pixel 12, as will be described later. The gate of the reset transistor M2 is supplied with the control signal res from the vertical scanning unit 20. The gate of the selection transistor M4 is supplied with the control signal sel from the vertical scanning unit 20. When each transistor is composed of an N-type MOS transistor, the corresponding transistor is turned on when a high-level control signal is supplied from the vertical scanning unit 20. Furthermore, when a low-level control signal is supplied from the vertical scanning unit 20, the corresponding transistor is turned off.

[0026] In this embodiment, the explanation assumes that electrons are used as the signal charge among the electron-hole pairs generated in the photoelectric conversion units PDA and PDB by light incidence. When electrons are used as the signal charge, each transistor constituting the pixel 12 can be composed of an N-type MOS transistor as described above. However, the signal charge is not limited to electrons, and holes may also be used as the signal charge. When holes are used as the signal charge, the conductivity type of each transistor will be the opposite conductivity type to that described in this embodiment. Note that the names of the source and drain of the MOS transistor may differ depending on the conductivity type of the transistor and the function to be focused on. Some or all of the names of the source and drain used in this embodiment may also be referred to by the opposite names.

[0027] The photoelectric conversion units PDA and PDB convert incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and store the resulting charge. When the transfer transistor M1A is turned on, it transfers the charge held by the photoelectric conversion unit PDA to node FD. When the transfer transistor M1B is turned on, it transfers the charge held by the photoelectric conversion unit PDB to node FD. The charge transferred from the photoelectric conversion units PDA and PDB is held in the capacitance (stray diffusion capacitance) of node FD. As a result, node FD becomes potential corresponding to the amount of charge transferred from the photoelectric conversion units PDA and PDB through charge-voltage conversion by the stray diffusion capacitance.

[0028] The selection transistor M4, when turned on, connects the amplification transistor M3 to the signal output line 16. The amplification transistor M3 is configured such that a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source (not shown) via the selection transistor M4, forming an amplification section (source follower circuit) with its gate as the input node. As a result, the amplification transistor M3 outputs a signal based on the voltage of node FD to the signal output line 16 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are output sections that output a pixel signal corresponding to the amount of charge held at node FD.

[0029] The reset transistor M2 controls the supply of a voltage (voltage VDD) to node FD, which acts as a charge holder, for resetting node FD. When reset transistor M2 is turned on, it resets node FD to a voltage corresponding to voltage VDD. At the same time, by turning on transfer transistor M1A, it is also possible to reset the photoelectric conversion unit PDA to a voltage corresponding to voltage VDD. Furthermore, by turning on transfer transistor M1B at the same time, it is also possible to reset the photoelectric conversion unit PDB to a voltage corresponding to voltage VDD.

[0030] In this embodiment, the pixel 12 is equipped with a common node FD and amplification transistor M3 for the two photoelectric conversion units PDA and PDB. Therefore, by transferring the charge held by the photoelectric conversion unit PDA and the charge held by the photoelectric conversion unit PDB to the node FD at the same time, the charges held by the photoelectric conversion units PDA and PDB can be added on the node FD, and a signal based on the amount of added charge can be output. Alternatively, by transferring only one of the charges held by the photoelectric conversion unit PDA and the charge held by the photoelectric conversion unit PDB to the node FD, a signal based on the amount of charge held by one of the photoelectric conversion units PDA and PDB can be output.

[0031] Figure 3 is a plan view showing an example of the arrangement of two photoelectric conversion units PDA and PDB that constitute one pixel 12, and corresponds to a plan view of the pixel 12 as seen from the direction in which light is incident. Light is incident on the photoelectric conversion units PDA and PDB via a microlens ML and a color filter (not shown). Here, the photoelectric conversion units PDA and PDB that constitute one pixel 12 share one microlens ML, as shown in Figure 3. In other words, the photoelectric conversion units PDA and PDB are configured to receive light that has passed through different pupil regions of the light incident on the imaging optical system. That is, the microlens ML incidents light that has passed through the first pupil region of the optical system that forms an image on the pixel 10, for example, the exit pupil of the imaging lens, onto the photoelectric conversion unit PDA, and incidents light that has passed through a second pupil region different from the first pupil region onto the photoelectric conversion unit PDB. With this configuration, the charge-based signal generated by the photoelectric conversion unit PDA (hereinafter referred to as "Signal A") and the charge-based signal generated by the photoelectric conversion unit PDB (hereinafter referred to as "Signal B") can be used as phase difference detection signals for distance measurement. In addition, the signal based on the total charge generated by the photoelectric conversion units PDA and PDB (hereinafter referred to as "Signal A + Signal B") can be used as an image formation signal.

[0032] Figure 3 shows an example of the arrangement of the photoelectric conversion units PDA and PDB when the pupil region is divided horizontally (left and right). However, the photoelectric conversion units PDA and PDB may also be arranged to divide the pupil region vertically (up and down). Furthermore, the number of divisions in the pupil region does not necessarily have to be two; there may be more than two divisions.

[0033] Figure 4 is a circuit diagram showing the connection relationship between the pixel unit 10 and the AD conversion unit 30. Figure 4 shows eight pixels 12 arranged in the first row, columns 1 through 8, and eight pixels 12 arranged in the second row, columns 1 through 8, among the multiple pixels 12 that make up the pixel unit 10. Each pixel 12 is assumed to have a photoelectric conversion unit PDA on the left and a photoelectric conversion unit PDB on the right, similar to the layout in Figure 3. Also, Figure 4 assumes a configuration example in which the AD conversion unit 30 is divided into two blocks, similar to the block diagram in Figure 1.

[0034] In the pixel section 10, starting from the first row, R pixels 12R and G pixels 12G are arranged alternately in the odd-numbered rows. That is, R pixels 12R are arranged in the odd-numbered columns of the odd-numbered rows, and G pixels 12G are arranged in the even-numbered columns of the odd-numbered rows. In the pixel section 10, starting from the second row, G pixels 12G and B pixels 12B are arranged alternately in the even-numbered rows. That is, G pixels 12G are arranged in the odd-numbered columns of the even-numbered rows, and B pixels 12B are arranged in the even-numbered columns of the even-numbered rows.

[0035] Each row of the pixel section 10 is provided with a signal line for supplying control signal tx1 to the corresponding pixel 12 in that row, and a signal line for supplying control signal tx2 to the corresponding pixel 12 in that row. In Figure 4, symbols for distinguishing the corresponding pixel row are appended to the symbols for control signals tx1 and tx2. For example, control signal tx1 supplied to the nth row of pixel 12 is represented by the symbol tx1[n-1] with [n-1] appended, and control signal tx2 supplied to the (n+1)th row of pixel 12 is represented by the symbol tx2[n] with [n] appended.

[0036] The signal lines supplying control signals tx1 and tx2 to the pixels 12 in each row are connected to transfer transistors M1A and M1B for each 2x2 pixel block that constitutes the smallest repeating unit of the Bayer array. The connections to transfer transistors M1A and M1B differ between adjacent pixel blocks in the row direction. For example, in the R pixel 12R in the first row, first column, the G pixel 12G in the first row, second column, the G pixel 12G in the second row, first column, and the B pixel 12B in the second row, control signal tx1 is supplied to transfer transistor M1A and control signal tx2 is supplied to transfer transistor M1B. In the R pixel 12R in the first row, third column, the G pixel 12G in the first row, fourth column, the G pixel 12G in the second row, third column, and the B pixel 12B in the second row, control signal tx1 is supplied to transfer transistor M1B and control signal tx2 is supplied to transfer transistor M1A.

[0037] In other words, of two adjacent pixels 12 that are sensitive to the same color in the row direction, the transfer transistor M1A of one pixel 12 is supplied with the control signal tx1, and the transfer transistor M1A of the other pixel 12 is supplied with the control signal tx2. Then, the transfer transistor M1B of the same pixel 12 is supplied with the control signal tx2, and the transfer transistor M1B of the other pixel 12 is supplied with the control signal tx1.

[0038] In Figure 4, to illustrate the relationship between the control signals tx1 and tx2 and the photoelectric conversion units PDA and PDB where charge transfer takes place, black circles are placed between the signal lines to which the control signals tx1 and tx2 are supplied and the photoelectric conversion units PDA and PDB to indicate their correspondence.

[0039] The signal output lines 16 arranged in each row of the pixel section 10 are divided into a first set connected to the first block of the AD conversion unit 30 and a second set connected to the second block of the AD conversion unit 30. For example, in the configuration example of Figure 1, the AD conversion unit 30 located below the pixel section 10 may be the first block, and the AD conversion unit 30 located above the pixel section 10 may be the second block. The signal output lines 16 belonging to the first set may be the signal output lines 16 arranged in the odd-numbered rows of the pixel section 10, starting from the first row. The signal output lines 16 belonging to the second set may be the signal output lines 16 arranged in the even-numbered rows of the pixel section 10, starting from the second row. In this case, the first block of the AD conversion unit 30 processes the signals of the R pixels 12R and the signals of the G pixels 12G located in the same row as the R pixels 12R. Furthermore, the second block of the AD conversion unit 30 processes the signal of the B pixel 12B and the signal of the G pixel 12G, which is arranged in the same column as the B pixel 12B. Figure 4 shows only the first block of the AD conversion unit 30, which is connected to the first set of signal output lines 16. The second block of the AD conversion unit 30 is the same as the first block except that it is connected to the second set of signal output lines 16.

[0040] The AD conversion unit 30 has multiple column AD conversion units (column ADCs) 32 corresponding to the number of signal output lines 16 to which it is connected, and multiple switches SW1. Each of the multiple column AD conversion units 32 is connected to the signal output line 16 of the corresponding column. In Figure 4, the column AD conversion units 32 arranged to correspond to the 1st, 3rd, 5th, and 7th columns of the pixel unit 10 are distinguished by the symbols 32(0), 32(1), 32(2), and 32(3), respectively. One terminal of each of the multiple switches SW1 is connected to the column AD conversion unit 32 of the corresponding column. In Figure 4, the switches SW1 connected to the column AD conversion units 32(0), 32(1), 32(2), and 32(3) are distinguished by the symbols SW1(0), SW1(1), SW1(2), and SW1(3), respectively. The other terminal of switches SW1(0) and SW1(2) is connected to the horizontal transfer line 34A. The other terminals of switches SW1(1) and SW1(3) are connected to horizontal transfer line 34B.

[0041] The column AD conversion unit 32 has the function of converting the pixel signal output to the signal output line 16 from an analog signal to a digital signal. The column AD conversion unit 32 may be configured to include, for example, a ramp-type AD converter. The ramp-type AD converter has a comparator (not shown) that compares the pixel signal and the ramp signal, and holds the count value of a time measurement counter from the timing of the start of the signal comparison to the timing when the output signal of the comparator inverts as the digital value of the pixel signal. In Figure 4, the digital signals obtained by AD conversion in column ADC(0), column ADC(1), column ADC(2), and column ADC(3) are denoted by the symbols ado(0), ado(1), ado(2), and ado(3), respectively. Note that the AD converters constituting the column AD conversion unit 32 do not necessarily have to be ramp-type AD converters, but may be other AD converters such as ΔΣ type AD converters or successive approximation type AD converters.

[0042] The column AD conversion units 32 (column ADC(1), column ADC(3), ...) corresponding to the 3rd, 7th, ... columns of the pixel unit 10 are configured to accept the control signal psave. The control signal psave is a control signal that controls the on / off state of the column AD conversion units 32. For example, when the control signal psave is at a high level, the column AD conversion units 32(1), 32(3), ... are turned off, and when the control signal psave is at a low level, the column AD conversion units 32(1), 32(3), ... are turned on. Power consumption can be reduced by turning off the column AD conversion units 32(1), 32(3), ... when they are not in use and stopping the AD conversion operation. Note that turning off the column AD conversion units 32 means putting them into a state where they do not output AD conversion results, and this may include stopping the power supply to the column AD conversion units 32, or stopping the data supply or clock supply.

[0043] In Figure 4, the control signal psave is input to the column AD conversion unit 32 corresponding to the 3rd, 7th, ... columns. However, it is also possible to configure the system to input the control signal psave to the column AD conversion unit 32 (column ADC(0), column ADC(2), ...) corresponding to the 1st, 5th, ... columns. In this case, power consumption can be reduced by turning off the column AD conversion units 32(0), 32(2), ... when they are not in use.

[0044] Switches SW1(0), SW1(1), SW1(2), and SW1(3) are switches controlled by the control signals hadr(0), hadr(1), hadr(2), and hadr(3), respectively. For example, when the control signal hadr is at a high level, the corresponding switch SW1 is turned on, and when the control signal hadr is at a low level, the corresponding switch SW1 is turned off. The digital data held by the column AD conversion unit 32 is output to one of the horizontal transfer lines 34A or 34B connected to the corresponding column switch SW1 when that switch SW1 is turned on.

[0045] The signal output on horizontal transfer line 34A is output from the AD converter 30 via node N1A. Similarly, the signal output on horizontal transfer line 34B is output from the AD converter 30 via node N1B. In this specification, the signal propagation path from node N1A to the first input node of the signal processing unit 120 (node ​​N2A, described later) may be referred to as channel chA. The signal propagation path from node N1B to the second input node of the signal processing unit 120 (node ​​N2B, described later) may be referred to as channel chB.

[0046] Next, the driving method of the photoelectric converter according to this embodiment will be explained using Figure 5. Figure 5 is a timing diagram showing the driving method of the photoelectric converter according to this embodiment. Figure 5 shows the waveforms of the vertical synchronization signal VD, the horizontal synchronization signal HD, and the control signals tx1, tx2, res, sel, psave, the value of the digital signal ado, the column information selected by the control signal hadr, and the values ​​of the data output to channels chA and chB. The symbols [0] and [1] appended to the control signals tx1, tx2, res, sel represent the row number.

[0047] Immediately before time t1, the control signals tx1, tx2, sel and psave for each row are assumed to be at a low level, and the control signal res for each row is assumed to be at a high level.

[0048] At time t1, the timing generation unit 90 controls the vertical synchronization signal VD from a high level to a low level. This initiates the operation of one frame.

[0049] At the following time t2, the timing generation unit 90 controls the horizontal synchronization signal HD from a low level to a high level. This initiates the operation of one horizontal period. This one horizontal period becomes the acquisition period for the phase difference detection signal.

[0050] Similarly, at time t2, the timing generation unit 90 controls the control signal psave from a low level to a high level. This turns off the column AD conversion units 32(1), 32(3), ...

[0051] Also at time t2, the vertical scanning unit 20 controls the control signal res[0] of the first row from a high level to a low level, and controls the control signal sel[0] of the first row from a low level to a high level. As a result, the reset transistor M2 of the first row pixel 12 is turned off, and the reset state of node FD is released. In addition, the selection transistor M4 of the first row pixel 12 is turned on, and the first row pixel 12 enters a selected state where it can output a pixel signal.

[0052] During the period from time t3 to time t4, the vertical scanning unit 20 maintains the control signal tx2[0] of the first row at a low level, while controlling the control signal tx1[0] of the first row from a low level to a high level. As a result, the transfer transistor M1A or transfer transistor M1B of the first row pixel 12 that received the control signal tx1[0] turns on, and the charge accumulated in the photoelectric conversion unit PDA or photoelectric conversion unit PDB of the first row pixel 12 is transferred to node FD. Consequently, pixel signals based on the charge accumulated in the photoelectric conversion unit PDA of the first row pixel 12 are output to the signal output lines 16 of the first and fifth columns. In addition, pixel signals based on the charge accumulated in the photoelectric conversion unit PDB of the first row pixel 12 are output to the signal output lines 16 of the third and seventh columns. In other words, the row AD conversion units 32(0), 32(1), 32(2), 32(3), ... alternately read out pixel signals based on the charge stored in the photoelectric conversion unit PDA and pixel signals based on the charge stored in the photoelectric conversion unit PDB. In Figure 4, the photoelectric conversion units PDA and PDB, for which charge reading is performed during this period, are represented by white blocks, while the photoelectric conversion units PDA and PDB, for which no signal reading is performed during this period, are represented by diagonally lined blocks.

[0053] After time t4, the column AD conversion unit 32 of each column performs AD conversion from analog to digital for the pixel signals read out on the signal output line 16. Then, by time t5 after time t4, the results of the AD conversion in the column AD conversion unit 32 of each column are assumed to be finalized. Here, the value of the digital signal ado(0) output from column AD conversion unit 32(0) is assumed to be Da00, and the value of the digital signal ado(2) output from column AD conversion unit 32(2) is assumed to be Da02. Note that the column AD conversion units 32(1) and 32(3) are in the off state and data supply and clock supply are stopped, so the digital signals ado(1) and ado(3) output from column AD conversion units 32(1) and 32(3) are invalid signals. In Figure 4, these invalid signals are represented by shaded blocks.

[0054] At the following time t6, the timing generation unit 90 supplies a control signal (horizontal scanning signal) hadr to the AD conversion unit 30 and sequentially transfers the digital signals held by the column AD conversion unit 32 to the subsequent signal processing unit 120, two columns at a time. First, in the first cycle of horizontal scanning, the AD conversion unit 30 outputs the digital signal ado(0) held by the column AD conversion unit 32(0) to the horizontal transfer line 34A in response to the control signal hadr(0) input from the timing generation unit 90. The AD conversion unit 30 also outputs the digital signal ado(1) held by the column AD conversion unit 32(1) to the horizontal transfer line 34B in response to the control signal hadr(1) input from the timing generation unit 90. Next, in the following cycle of horizontal scanning, the AD conversion unit 30 outputs the digital signal ado(2) held by the column AD conversion unit 32(2) to the horizontal transfer line 34A in response to the control signal hadr(2) input from the timing generation unit 90. Furthermore, the AD conversion unit 30 outputs the digital signal ado(3) held by the column AD conversion unit 32(3) to the horizontal transfer line 34B in response to the control signal hadr(3) input from the timing generation unit 90. As a result, data with value Da00 and data with value Da02 are output sequentially to the horizontal transfer line 34A, and an invalid signal is output to the horizontal transfer line 34B. That is, only the signal (A signal) based on the amount of charge of the photoelectric conversion unit PDA is output to the horizontal transfer line 34A, and an invalid signal is output to the horizontal transfer line 34B. Subsequently, the next cycles of horizontal scanning are performed sequentially.

[0055] At the following time t7, the horizontal synchronization signal HD output from the timing generation unit 90 transitions again from a low level to a high level, and the operation of the next horizontal period begins. This horizontal period becomes the acquisition period for the image forming signal.

[0056] Also at time t7, the timing generation unit 90 controls the control signal psave from a high level to a low level. This turns on the column AD conversion units 32(1), 32(3), ... Although the horizontal transfer operation that started at time t6 is still in progress at this time, the horizontal transfer operation reads signals held in the memory of the column AD conversion unit 32, so the operations from pixel driving to AD conversion after time t7 can be performed in parallel with this horizontal transfer operation.

[0057] During the period from time t8 to time t9, the vertical scanning unit 20 controls the control signals tx1[0] and tx2[0] of the first row to a high level. This turns on the transfer transistors M1A and M1B of the pixels 12 of the first row, and the charge stored in the photoelectric conversion units PDA and PDB is transferred to the common node FD. As a result, a pixel signal based on the total amount of charge stored in the photoelectric conversion units PDA and PDB is output to the signal output line 16 of each column.

[0058] After time t9, the column AD conversion unit 32 in each column performs AD conversion from analog to digital for the pixel signals read out on the signal output line 16. Then, by time t10, after time t9, the results of the AD conversion in the column AD conversion unit 32 in each column are assumed to be finalized. Here, the value of the digital signal ado(0) output from column AD conversion unit 32(0) is assumed to be Dab00, and the value of the digital signal ado(1) output from column AD conversion unit 32(1) is assumed to be Dab01. Furthermore, the value of the digital signal ado(2) output from column AD conversion unit 32(2) is assumed to be Dab02, and the value of the digital signal ado(3) output from column AD conversion unit 32(3) is assumed to be Dab03. Note that the horizontal transfer operation of the phase difference detection signal, which started at time t6, is assumed to be completed by time t10.

[0059] At the following time t11, the timing generation unit 90 supplies a control signal (horizontal scanning signal) hadr to the AD conversion unit 30 and sequentially transfers the digital signals held by the column AD conversion unit 32 to the subsequent signal processing unit 120, two columns at a time. First, in the first cycle of horizontal scanning, the AD conversion unit 30 outputs the digital signal ado(0) held by the column AD conversion unit 32(0) to the horizontal transfer line 34A in response to the control signal hadr(0) input from the timing generation unit 90. The AD conversion unit 30 also outputs the digital signal ado(1) held by the column AD conversion unit 32(1) to the horizontal transfer line 34B in response to the control signal hadr(1) input from the timing generation unit 90. Next, in the following cycle of horizontal scanning, the AD conversion unit 30 outputs the digital signal ado(2) held by the column AD conversion unit 32(2) to the horizontal transfer line 34A in response to the control signal hadr(2) input from the timing generation unit 90. Furthermore, the AD conversion unit 30 outputs the digital signal ado(3) held by the column AD conversion unit 32(3) to the horizontal transfer line 34B in response to the control signal hadr(3) input from the timing generation unit 90. As a result, data with value Dab00 and data with value Dab02 are output sequentially to the horizontal transfer line 34A, and data with value Dab01 and data with value Dab03 are output sequentially to the horizontal transfer line 34B. In other words, signals (A+B signals) based on the total amount of charge accumulated in the photoelectric conversion units PDA and PDB are output to the horizontal transfer lines 34A and 34B, respectively. Subsequently, the next cycles of horizontal scanning are performed sequentially.

[0060] From time t12 onwards, the phase difference detection signal for the second row's pixel 12 is acquired in the same manner as from time t2. That is, after time t14, the column AD conversion unit 32 for each column performs AD conversion from analog to digital for the pixel signal read out on the signal output line 16. Then, by time t15 after time t14, the results of the AD conversion in the column AD conversion unit 32 for each column are assumed to be finalized. Here, the value of the digital signal ado(0) output from column AD conversion unit 32(0) is assumed to be Da10, and the value of the digital signal ado(2) output from column AD conversion unit 32(2) is assumed to be Da12. From time t16 onwards, data with the value Da10 and data with the value Da12 are output sequentially to the horizontal transfer line 34A, and an invalid signal is output to the horizontal transfer line 34B.

[0061] From time t17 onwards, the image forming signal for the second row of pixels 12 is acquired in the same manner as from time t7. Here, it is assumed that the value of the digital signal ado(0) output from column AD conversion unit 32(0) is Dab10, and the value of the digital signal ado(1) output from column AD conversion unit 32(1) is Dab11. Also, it is assumed that the value of the digital signal ado(2) output from column AD conversion unit 32(2) is Dab12, and the value of the digital signal ado(3) output from column AD conversion unit 32(3) is Dab13. In this case, the data with value Dab10 and the data with value Dab12 are output sequentially to horizontal transfer line 34A, and the data with value Dab11 and the data with value Dab13 are output sequentially to horizontal transfer line 34B.

[0062] Subsequently, the signals of pixels 12 from the third row onward are read out in the same manner as the operations of the first and second rows, completing the operation of one frame.

[0063] In the above driving example, we illustrated the operation of selecting rows one by one and performing a vertical scan, but it is also possible to select multiple rows at a time and perform a vertical scan. For example, in the case of a Bayer array, two rows are selected every other row, and the signals of the pixels 12 in each column belonging to these rows are simultaneously output to a common signal output line 16. By operating in this way, the signals of two pixels 12 of the same color located in the same column can be pseudo-added.

[0064] Next, an example of the configuration and operation of the signal processing unit 120 will be explained using Figure 6. Figure 6 is a block diagram showing an example of the configuration of the signal processing unit 120.

[0065] As shown in Figure 6, the signal processing unit 120 includes nodes N2A and N2B, an image processing unit 122, a memory unit 124, a phase difference data generation unit 126, a peak detection unit 128, and a phase difference detection unit 130. The signal from the horizontal transfer line 34A of the AD conversion unit 30 is input to node N2A via the signal output unit 80. This signal propagation path is the aforementioned channel chA. The signal from the horizontal transfer line 34B of the AD conversion unit 30 is input to node N2B via the signal output unit 80. This signal propagation path is the aforementioned channel chB. Node N2A is connected to the image processing unit 122, the memory unit 124, and the phase difference data generation unit 126. Node N2B is connected to the image processing unit 122. The memory unit 124 is connected to the phase difference data generation unit 126. The phase difference data generation unit 126 is connected to the peak detection unit 128. The peak detection unit 128 is connected to the phase difference detection unit 130.

[0066] The signal processing unit 120 performs phase difference detection processing and image processing. Phase difference detection processing is performed using the signal input from node N2A. Image processing is performed using the signal input from node N2A and the signal input from node N2B.

[0067] During the phase difference detection signal acquisition period, node N2A receives only the signal (A signal) based on the charge accumulated in the photoelectric conversion unit PDA. During the image formation signal acquisition period, node N2A receives the signal (A+B signal) based on the total amount of charge accumulated in the photoelectric conversion units PDA and PDB. In both operations, signals are sequentially input to node N2A in increments of four columns, starting from the leftmost column 1. For example, node N2A receives the signal from column 1, the signal from column 5, the signal from column 9, and so on, in sequence.

[0068] Furthermore, during the acquisition period of the phase difference detection signal, an invalid signal is input to node N2B. Also, during the acquisition period of the image forming signal, a signal (A+B signal) based on the total amount of charge accumulated in the photoelectric conversion units PDA and PDB is input to node N2B. Node N2B is sequentially input the signals from the column two columns to the right of the column from which the signal input to node N2A is output.

[0069] In this embodiment, it is assumed that the output of the photoelectric converter 100 is a parallel output corresponding to channels chA and chB, but the output of the photoelectric converter 100 may also be a serial output.

[0070] Next, the phase difference detection process in the signal processing unit 120 will be explained using Figure 6. The memory unit 124 receives A signals sequentially via node N2A during the acquisition period of the phase difference detection signal. The memory unit 124 holds these A signals that are sequentially input from node N2A. The memory unit 124 does not need to hold the image forming signals that are input via node N2A during the acquisition period of the image forming signals.

[0071] The phase difference data generation unit 126 is configured to read data held by the memory unit 124. The phase difference data generation unit 126 receives the A+B signal sequentially via node N2A during the image formation signal acquisition period. The phase difference data generation unit 126 sequentially reads the A signal of the pixel 12 corresponding to the A+B signal sequentially input from node N2A during the image formation signal acquisition period from the memory unit 124, and sequentially performs a subtraction process to subtract the A signal data from the A+B signal data. This calculates a signal (B signal) corresponding to the signal based on the charge accumulated in the photoelectric conversion unit PDB.

[0072] The peak detection unit 128 receives the A signal read from the memory unit 124 and the B signal calculated by the phase difference data generation unit 126 from the phase difference data generation unit 126. The peak detection unit 128 performs peak detection on each of the received A and B signals.

[0073] The phase difference detection unit 130 receives information regarding the respective peak positions of signal A and signal B from the peak detection unit 128. The phase difference detection unit 130 then compares the peak position of signal A with the peak position of signal B to detect whether the image is in focus, front-pinned, or back-pinned.

[0074] Furthermore, the phase difference data generation unit 126, the peak detection unit 128, and the phase difference detection unit 130 may be turned off in response to a control signal input via a control line (not shown) during the acquisition period of the phase difference detection signal. By doing so, power consumption during the acquisition period of the phase difference detection signal can be reduced.

[0075] Next, the image processing in the signal processing unit 120 will be explained using Figure 6. The image processing unit 122 receives A signals sequentially from node N2A during the phase difference detection signal acquisition period, and A+B signals sequentially from nodes N2A and N2B during the image formation signal acquisition period. The image processing unit 122 processes the A+B signals that are input during the image formation signal acquisition period. The image processing unit 122 performs noise reduction, filtering, RGB processing, etc. on the A+B signal data to perform signal correction suitable for display and recording systems.

[0076] Furthermore, the image processing unit 122 may be turned off in response to a control signal input via a control line (not shown) during the acquisition period of the phase difference detection signal. By doing so, power consumption during the acquisition period of the phase difference detection signal can be reduced.

[0077] Thus, in this embodiment, in the photoelectric converter that performs pupil-splitting focus detection on the imaging plane, the A signal and A+B signal of the first pixel are output, but the B signal of the second signal is not output. Therefore, the occurrence of pairs that cannot be compressed by addition is suppressed, and the number of signals and the amount of signal processing can be reduced. As a result, the circuit size can be reduced and power consumption can be reduced. Furthermore, power consumption can be further reduced by turning off the column AD converter that receives a signal based on the amount of charge of the second photoelectric converter read from the second pixel in response to the first readout operation.

[0078] [Second Embodiment] A photoelectric converter according to a second embodiment of the present invention will be described with reference to Figures 7 to 9. Components similar to those in the photoelectric converter according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted or simplified. Figure 7 is a block diagram showing the schematic configuration of the photoelectric converter according to this embodiment. Figure 8 is a block diagram showing an example of the configuration of the signal conversion unit in the photoelectric converter according to this embodiment. Figure 9 is a diagram showing the operation of the signal conversion unit in the photoelectric converter according to this embodiment.

[0079] As shown in Figure 7, the photoelectric converter 100 according to this embodiment further includes a signal conversion unit 40. The signal conversion unit 40 is connected between the AD conversion unit 30 and the signal output unit 80. Other aspects of the photoelectric converter according to this embodiment are the same as those of the photoelectric converter according to the first embodiment.

[0080] Next, an example of the configuration of the signal conversion unit 40 in the photoelectric converter according to this embodiment will be described with reference to Figure 8. As shown in Figure 8, the signal conversion unit 40 of the photoelectric converter according to this embodiment includes nodes N3A and N3B, line memories MA, MAB, MB, and MBA, selectors 42 and 44, a subtractor 46, and nodes N4A and N4B. Node N3A is connected to node N1A of the AD conversion unit 30. Node N4A is connected to node N2A of the signal processing unit 120 via the signal output unit 80. Node N3B is connected to node N1B of the AD conversion unit 30. Node N4B is connected to node N2B of the signal processing unit 120 via the signal output unit 80.

[0081] Line memory MA and line memory MAB are connected to node N3A. Line memory MB and line memory MBA are connected to node N3B. Line memory MA is connected to one input node of selector 42. Line memory MAB is connected to the other input node of selector 42. Line memory MB is connected to one input node of selector 44. A signal of data 0 (fixed value zero) is input to the other input node of the selector. The output node of selector 44 is connected to one input node of subtractor 46. Line memory MBA is connected to the other input node of subtractor 46. The output node of selector 42 is connected to node N4A. The output node of subtractor 46 is connected to node N4B.

[0082] The signal conversion unit 40 has the function of performing a conversion process on the signal output from the AD conversion unit 30 according to the control signal from the timing generation unit 90, and outputting the converted signal to the signal processing unit 120 via the signal output unit 80. Details of the conversion process in the signal conversion unit 40 will be described later.

[0083] During the phase difference detection signal acquisition period, only the signal (A signal) based on the charge accumulated in the photoelectric conversion unit PDA is sequentially input to node N3A. During the image formation signal acquisition period, the signal (A+B signal) based on the total amount of charge accumulated in the photoelectric conversion units PDA and PDB is sequentially input to node N3A. In both operations, the signal is sequentially input to node N3A every four columns from the leftmost column of the pixel unit 10.

[0084] During the acquisition period for the phase difference detection signal, only the signal based on the charge accumulated in the photoelectric conversion unit PDB (the B signal) is sequentially input to node N3B. During the acquisition period for the image forming signal, the signal based on the total amount of charge accumulated in the photoelectric conversion units PDA and PDB (A+B) is sequentially input to node N3B. In both operations, node N3B is sequentially input the signal from the column two columns to the right of the column from which the signal input to node N3A is output. In this embodiment, unlike the first embodiment, the control signal psave input to the column AD conversion units 32(1), 32(3),... is always set to a low level. Therefore, during the acquisition period for the phase difference detection signal, the B signal is output from the column AD conversion units 32(1), 32(3),...

[0085] Thus, line memory MA holds the A signal data that was input during the acquisition period of the phase difference detection signal from the data sequentially input from node N3A. Line memory MB holds the B signal data that was input during the acquisition period of the phase difference detection signal from the data sequentially input from node N3B. Line memory MAB holds the A+B signal data that was input during the acquisition period of the image forming signal from the data sequentially input from node N3A. Line memory MBA holds the A+B signal data that was input during the acquisition period of the image forming signal from the data sequentially input from node N3B.

[0086] Selectors 42 and 44 select and output one of the two input signals depending on whether the signal output from the signal conversion unit 40 is a phase difference detection signal or an image forming signal. Subtractor 46 subtracts the signal output from selector 44 from the signal output from line memory MBA and outputs the result.

[0087] In other words, when the signal output from the signal conversion unit 40 is a phase difference detection signal, as shown in Figure 9(a), selector 42 selects the output signal of line memory MA, and selector 44 selects the output signal of line memory MB. As a result, node N4A outputs the A signal held in line memory MA. Also, node N4B outputs a signal obtained by subtracting the B signal held in line memory MB from the A+B signal held in line memory MBA, i.e., a signal equivalent to the A signal.

[0088] Furthermore, when the signal output from the signal conversion unit 40 is an image forming signal, as shown in Figure 9(b), selector 42 selects the output signal of line memory MAB, and selector 44 selects the signal of data 0. As a result, node N4A outputs the A+B signal held in line memory MAB. Also, node N4B outputs a signal obtained by subtracting the signal of data 0 from the A+B signal held in line memory MBA, i.e., the A+B signal held in line memory MBA.

[0089] Next, the driving method of the photoelectric converter according to this embodiment will be explained using Figure 10. Figure 10 is a timing diagram showing the driving method of the photoelectric converter according to this embodiment. Figure 10 shows the waveforms of the vertical synchronization signal VD and the horizontal synchronization signal HD, the data values ​​in nodes N3A, N3B, line memories MA, MAB, MB, MBA and nodes N4A, N4B and the selection of selectors 42 and 44. The symbols (0) and (1) appended to line memories MA, MAB, MB, MBA represent the column numbers. Note that the operation at each timing from time t1 to time t11 and time t16 is the same as the operation of the first embodiment explained using Figure 5, so the explanation will be omitted as appropriate.

[0090] At time t6, the timing generation unit 90 supplies a control signal (horizontal scanning signal) hadr to the AD conversion unit 30 and sequentially transfers the digital signals held by the column AD conversion unit 32 to the subsequent signal conversion unit 40 in pairs of two columns. First, in the first cycle of horizontal scanning, the AD conversion unit 30 outputs the digital signal ado(0) held by the column AD conversion unit 32(0) to the horizontal transfer line 34A in response to the control signal hadr(0) input from the timing generation unit 90. The AD conversion unit 30 also outputs the digital signal ado(1) held by the column AD conversion unit 32(1) to the horizontal transfer line 34B in response to the control signal hadr(1) input from the timing generation unit 90. Next, in the following cycle of horizontal scanning, the AD conversion unit 30 outputs the digital signal ado(2) held by the column AD conversion unit 32(2) to the horizontal transfer line 34A in response to the control signal hadr(2) input from the timing generation unit 90. Furthermore, the AD conversion unit 30 outputs the digital signal ado(3) held by the column AD conversion unit 32(3) to the horizontal transfer line 34B in response to the control signal hadr(3) input from the timing generation unit 90.

[0091] In this embodiment, as described above, the control signal psave supplied to the AD conversion unit 30 is fixed at a low level. That is, the column AD conversion units 32(1) and 32(3) are always in the ON state, and the digital signals ado(1) and ado(3) output from the column AD conversion units 32(1) and 32(3) are not invalid signals but signals (B signals) based on the charge stored in the photoelectric conversion unit PDB. Here, the value of the digital signal ado(1) output from the column AD conversion unit 32(1) is assumed to be Db01, and the value of the digital signal ado(3) output from the column AD conversion unit 32(3) is assumed to be Db03.

[0092] In this manner, the digital signals ado(0) and (2) output to the horizontal transfer line 34A are sequentially output to channel chA via node N1A and input to the signal conversion unit 40 via node N3A. Similarly, the digital signals ado(1) and (3) output to the horizontal transfer line 34B are sequentially output to channel chB via node N1B and input to the signal conversion unit 40 via node N3B.

[0093] At the following time t100, line memory MA stores the digital signal ado(0) (value: Da00) input from node N3A in line memory MA(0) in response to the control signal from timing generation unit 90. Line memory MB also stores the digital signal ado(1) (value: Db01) input from node N3B in line memory MB(0) in response to the control signal from timing generation unit 90.

[0094] Next, at time t101, after the digital signals ado(2) and ado(3) have been output to the horizontal transfer lines 34A and 34B, line memories MA and MB hold the digital signals ado(2) and ado(3) input from nodes N3A and N3B. Specifically, line memory MA holds the digital signal ado(2) (value: Da02) input from node N3A in line memory MA(1) in accordance with the control signal from the timing generation unit 90. Line memory MB also holds the digital signal ado(3) (value: Db03) input from node N3B in line memory MB(1) in accordance with the control signal from the timing generation unit 90.

[0095] In this way, during the period up to time t11, the signal conversion unit 40 stores the series of data sequentially input from nodes N3A and N3B in line memories MA and MB. As a result, the line memory MA of the signal conversion unit 40 stores the A signal of the pixel 12 of the row to be read. The line memory MB of the signal conversion unit 40 stores the B signal of the pixel 12 of the row to be read.

[0096] At time t11, the timing generation unit 90 supplies a control signal (horizontal scanning signal) hadr to the AD conversion unit 30 and sequentially transfers the digital signals held by the column AD conversion unit 32 to the subsequent signal conversion unit 40 in pairs of two columns. First, in the first cycle of horizontal scanning, the AD conversion unit 30 outputs the digital signal ado(0) held by the column AD conversion unit 32(0) to the horizontal transfer line 34A in response to the control signal hadr(0) input from the timing generation unit 90. The AD conversion unit 30 also outputs the digital signal ado(1) held by the column AD conversion unit 32(1) to the horizontal transfer line 34B in response to the control signal hadr(1) input from the timing generation unit 90. Next, in the following cycle of horizontal scanning, the AD conversion unit 30 outputs the digital signal ado(2) held by the column AD conversion unit 32(2) to the horizontal transfer line 34A in response to the control signal hadr(2) input from the timing generation unit 90. Furthermore, the AD conversion unit 30 outputs the digital signal ado(3) held by the column AD conversion unit 32(3) to the horizontal transfer line 34B in response to the control signal hadr(3) input from the timing generation unit 90.

[0097] At the following time t102, line memory MAB stores the digital signal ado(0) (value: Dab00) input from node N3A in line memory MAB(0) in response to the control signal from timing generation unit 90. Line memory MBA also stores the digital signal ado(1) (value: Dab01) input from node N3B in line memory MBA(0) in response to the control signal from timing generation unit 90.

[0098] Next, at time t104, after the digital signals ado(2) and ado(3) have been output to the horizontal transfer lines 34A and 34B, line memories MAB and MBA hold the digital signals ado(2) and ado(3) input from nodes N3A and N3B. Specifically, line memory MAB holds the digital signal ado(2) (value: Dab02) input from node N3A in line memory MAB(1) in response to the control signal from timing generation unit 90. Line memory MBA also holds the digital signal ado(3) (value: Dab03) input from node N3B in line memory MBA(1) in response to the control signal from timing generation unit 90.

[0099] In this way, during the period up to time t16, the signal conversion unit 40 stores the series of data sequentially input from nodes N3A and N3B in line memories MAB and MBAD. As a result, the line memories MAB and MBA of the signal conversion unit 40 store the A+B signals of the pixels 12 of the row to be read.

[0100] Meanwhile, from time t102 onward, the signal conversion unit 40 sequentially outputs signals based on the signals held in line memories MA, MAB, MB, and MBA from nodes N4A and N4B in accordance with the control signals from the timing generation unit 90.

[0101] At time 103, between time t102 and time t104, selector 42 selects line memory MA in response to a control signal from timing generation unit 90. As a result, node N4A outputs data with the value Da00 of line memory MA(0). Also, selector 44 selects line memory MB in response to a control signal from timing generation unit 90. As a result, node N4B outputs data with the value Da01', which is obtained by subtracting the value Db01 of line memory MB(0) from the value Dab01 of line memory MBA(0).

[0102] As mentioned above, the value Da00 is a signal (A signal) based on the charge stored in the photoelectric conversion unit PDA, and the data Da01' is a signal corresponding to the signal (A signal) based on the charge stored in the photoelectric conversion unit PDA. Therefore, the signal obtained by adding the value Da00 output from node N4A and the value Da01' output from node N4B is also a signal that can be used for phase difference detection in the signal processing unit 120.

[0103] At time t104, when the value Dab02 is stored in line memory MAB(1) and the value Dab03 is stored in line memory MBA(1), at the following time t105, node N4A outputs the data of the value Dab02 in line memory MA(1). Also, node N4B outputs the data of the value Dab03', which is obtained by subtracting the value Db03 in line memory MB(1) from the value Dab03 in line memory MBA(1).

[0104] In this way, during the period up to time t107, the signal conversion unit 40 sequentially outputs A signals based on the signals held in line memories MA, MAB, MB, and MBA from nodes N4A and N4B.

[0105] At the following time t107, selector 42 selects line memory MAB in response to a control signal from timing generation unit 90. As a result, node N4A outputs data with the value Dab00 from line memory MAB(0). Also, selector 44 selects data 0 in response to a control signal from timing generation unit 90. As a result, node N4B outputs data with the value Dab01, which is obtained by subtracting data 0 from the value Dab01 from line memory MBA(0).

[0106] At the following time t108, the signal conversion unit 40 outputs the data of value Dab02 from line memory MAB(1) from node N4A in response to the control signal from timing generation unit 90. It also outputs the data of value Dab03 from node N4B, which is the value obtained by subtracting data 0 from the value Dab03 from line memory MBA(1).

[0107] In this way, the signal conversion unit 40 sequentially outputs A+B signals based on the signals held in line memories MA, MAB, MB, and MBA from nodes N4A and N4B.

[0108] Thus, according to this embodiment, in a photoelectric converter that performs pupil-splitting focus detection on the imaging plane, it is possible to reduce the number of signals and the amount of signal processing by suppressing the occurrence of pairs that cannot be compressed by addition. This makes it possible to reduce the circuit size and power consumption. Furthermore, in this embodiment, all phase difference detection signals can be used for phase difference detection instead of some of the phase difference detection signals being invalidated, thereby improving the accuracy of phase difference detection.

[0109] In this embodiment, a configuration example was described in which the signal conversion unit 40 has line memories MA, MAB, MB, and MBA, but frame memories may be used instead of line memories. Also, the memory used by the signal conversion unit 40 does not necessarily have to be a memory dedicated to the signal conversion unit 40, but may be another memory provided by the photoelectric converter 100. For example, the memory used by the signal conversion unit 40 may be a memory provided by the AD converter 30.

[0110] Furthermore, in this embodiment, the operation of selecting rows one by one and performing a vertical scan, i.e., a non-additive operation, has been illustrated, but the system may be configured to add the signals of two or more pixels 12. For example, when performing 2-pixel addition in the vertical direction, two rows are selected at a time, alternating between rows, and the signals of the pixels 12 in each column belonging to these rows are simultaneously output to a common signal output line 16. By operating in this manner, the signals of two pixels 12 of the same color located in the same column can be pseudo-added. Also, when performing addition in the horizontal direction, the signals of node N4A and node N4B are digitally added, and the added signal can be input from node N2AB of the signal processing unit 120 configured as shown in Figure 11, for example, and processed. By configuring in this way, it is possible to realize 2-pixel addition in both the vertical and horizontal directions. When signals are added, the effect of reducing the bandwidth of the phase difference signal can be obtained.

[0111] [Third Embodiment] A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figures 12 to 15. Components similar to those in the photoelectric conversion devices of the first and second embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified. Figure 12 is a block diagram showing the schematic configuration of the photoelectric conversion device according to this embodiment. Figure 13 is a circuit diagram showing the connection relationship between the pixel unit, the signal summing unit, and the AD conversion unit in the photoelectric conversion device according to this embodiment. Figures 14 and 15 are diagrams showing the operation of the signal summing unit in the photoelectric conversion device according to this embodiment.

[0112] The photoelectric converter 100 according to this embodiment further includes a signal summing unit 50, as shown in Figure 12. The signal summing unit 50 is connected between the pixel unit 10 and the AD conversion unit 30. The signal summing unit 50 generates an image forming signal based on the signal output from the pixel unit 10, according to a control signal from the timing generation unit 90. The image forming signal generated in the signal summing unit 50 is output to the AD conversion unit 30. Other aspects of the photoelectric converter according to this embodiment are the same as those of the photoelectric converter according to the first or second embodiment.

[0113] Next, an example of the configuration of the signal summing unit 50 in the photoelectric conversion device according to this embodiment will be described with reference to Figure 13. As shown in Figure 13, the signal summing unit 50 of the photoelectric conversion device according to this embodiment has a plurality of adders 52 and a plurality of selectors 54, each corresponding to a plurality of sets, each set formed by two adjacent signal output lines 16. For example, in the configuration example of Figure 12, the first block of the AD conversion unit 30, which is located below the pixel unit 10, is connected to the signal output lines 16 arranged in the odd-numbered columns of the pixel unit 10. In this case, for example, the signal output line 16 of the first column and the signal output line 16 of the third column form one set, and the signal output line 16 of the fifth column and the signal output line 16 of the seventh column form another set.

[0114] One of the two input nodes of the adder 52 is connected to one of the two signal output lines 16 that make up the pair. The other of the two input nodes of the adder 52 is connected to the other of the two signal output lines 16 that make up the pair. One of the two input nodes of the selector 54 is connected to the output node of the adder 52. The other of the two input nodes of the selector 54 is connected to the other of the two signal output lines 16 that make up the pair. The output node of the selector 54 is connected to the column AD converter 32 corresponding to the other of the two signal output lines 16 that make up the pair. The column AD converter 32 corresponding to one of the two signal output lines 16 that make up the pair is connected to one of the two signal output lines 16 that make up the pair.

[0115] For example, focusing on the pair of the first and third columns, the two input nodes of the adder 52 are connected to the signal output line 16 of the first column and the signal output line 16 of the third column. The two input nodes of the selector 54 are connected to the output node of the adder 52 and the signal output line 16 of the third column. The output node of the selector 54 is connected to the column AD converter 32(1) provided corresponding to the third column. The signal output line 16 of the first column is connected to the column AD converter 32(0) provided corresponding to the first column.

[0116] The selector 54 selects one of the signals input to the two input nodes according to the control signal ab_gen supplied from the timing generation unit 90, and outputs it from the output node. For example, the selector 54 selects the output signal of the adder 52 when the control signal ab_gen is at a high level, and selects the other signal of the two signal output lines 16 that make up the pair when the control signal ab_gen is at a low level.

[0117] When the selector 54 selects the output signal of the adder 52, as shown in Figure 14, the signal obtained by adding the signals of the two signal output lines 16 constituting the pair is input to the column AD converter 32 corresponding to the other of the two signal output lines 16 constituting the pair. The signals of the two signal output lines 16 constituting the pair are the signals of pixels 12 that are sensitive to the same color when the color filter is a Bayer array. Therefore, the addition process performed in this way results in horizontal addition of two pixels of the same color. In addition, one of the signals of the two signal output lines 16 constituting the pair is a signal based on the charge accumulated in the photoelectric converter PDA (A signal), and the other is a signal based on the charge accumulated in the photoelectric converter PDB (B signal). Therefore, the signal obtained by the addition process performed in this way is an image forming signal (A+B signal).

[0118] When the selector 54 selects the other signal from the two signal output lines 16 that make up the pair, the selected signal is input to the column AD conversion unit 32 corresponding to the other of the two signal output lines 16 that make up the pair, as shown in Figure 15. Note that if the signal summing unit 50 is connected as shown in Figure 15, the connection between the pixel unit 10 and the AD conversion unit 30 is substantially the same as the connection in Figure 4.

[0119] Next, the driving method of the photoelectric converter according to this embodiment will be explained using Figure 16. Figure 16 is a timing diagram showing the driving method of the photoelectric converter according to this embodiment. Figure 16 shows the waveforms of the vertical synchronization signal VD, the horizontal synchronization signal HD, and the control signals tx1, tx2, res, sel, ab_gen, and psave. Figure 16 also shows the value of the digital signal ado, the column information selected by the control signal hadr, and the data values ​​output to channels chA and chB. The symbols [0] and [1] appended to the control signals tx1, tx2, res, and sel represent the row numbers. Note that the operation similar to that of the first embodiment explained using Figure 5 will be omitted as appropriate.

[0120] At time t2, the timing generation unit 90 transitions the control signal ab_gen from a low level to a high level. As a result, the signal output from the selector 54 becomes the output signal of the adder 52, i.e., the image forming signal. In this drive example, the control signal psave supplied to the AD conversion unit 30 is fixed at a low level.

[0121] At the following time t5, the image forming signal output from the selector 54 is converted into a digital signal by the column AD conversion units 32(1), 32(3), ... Here, the value of the digital signal ado(1) is assumed to be Dab00, and the value of the digital signal ado(3) is assumed to be Dab02.

[0122] The horizontal transfer operation during the period from time t6 to time t11 is the same as in the first embodiment. That is, data with value Da00 and data with value Da02 are sequentially output to channel chA via node N1A. Also, data with value Dab00 and data with value Dab02 are sequentially output to channel chB via node N1B.

[0123] In this way, a phase difference detection signal can be output to channel chA and an image formation signal to channel chB, allowing both the phase difference detection signal and the image formation signal to be acquired during a 1HD period.

[0124] At the following time t7, the vertical scanning unit 20 transitions the control signals res[0] and sel[1] from low level to high level, then transitions the control signals res[1] and sel[0] from high level to low level, and proceeds to processing the next line.

[0125] During the period from time t8 to time t9, the control signal tx1[1] transitions from a low level to a high level, similar to the period from time t3 to time t4, but the control signal tx2[1] remains at a low level. From time t12 onward, the same operation as from time t2 is repeated.

[0126] In this way, the operation is repeated for each 1HD while performing vertical scanning, and the operation of one frame is completed by reading the signals of all pixels 12 of the pixel unit 10.

[0127] In the first embodiment's driving example, channel chA alternately outputs a phase difference detection signal and an image forming signal, while channel chB alternately outputs an invalid signal and an image forming signal. In contrast, in this embodiment's driving example, channel chA sequentially outputs a phase difference detection signal, while channel chB sequentially outputs an image forming signal. Therefore, there is a difference in the order of data output to channels chA and chB between the first embodiment's driving example and the third embodiment's driving example. This difference in data order can be resolved, for example, by changing the configuration of the signal processing unit 120.

[0128] Figure 17 is a block diagram showing an example configuration of a signal processing unit 120 to resolve differences in data arrangement. In the signal processing unit 120 shown in Figure 17, a selector 132 is inserted between the memory unit 124 and the phase difference data generation unit 126. The phase difference data generation unit 126 is configured to receive one of the signals selected by the selector 132 from the output signal of the memory unit 124 and the input signal to node N2B, as well as the input signal to node N2A.

[0129] By configuring the signal processing unit 120 in this way, it becomes possible to select the data to be input to the phase difference data generation unit 126. That is, as shown in Figure 18(a), if the input signal from channel chB is selected by the selector 132, the phase difference detection signal from channel chA and the image formation signal from channel chB are sequentially input to the phase difference data generation unit 126. This makes it possible to achieve the same data sequence as in the first embodiment. Furthermore, as shown in Figure 18(b), if the output signal of the memory unit 124 is selected by the selector 132, the signal processing unit 120 becomes substantially the same as the configuration example in Figure 6. Note that the output signal of the selector 132 can be controlled by a control signal supplied from the timing generation unit 90 or the like.

[0130] Alternatively, the signal output unit 80, which is located before the signal processing unit 120, may perform a process to rearrange the order of signals output to the signal processing unit 120, thereby eliminating the difference in the order of data in channels chA and chB. In this case, the signal processing unit 120 may have the same configuration as in the first embodiment.

[0131] Furthermore, according to the configuration of this embodiment, it is also possible to dynamically switch between the drive of the first embodiment and the drive of this embodiment. In this case, during the period when the drive of the first embodiment is performed, the selector 54 of the signal summing unit 50 is set to the connection state shown in Figure 15, and the selector 132 of the signal processing unit 120 is set to the connection state shown in Figure 18(b). During the period when the drive of the third embodiment is performed, the selector 54 of the signal summing unit 50 is set to the connection state shown in Figure 14, and the selector 132 of the signal processing unit 120 is set to the connection state shown in Figure 18(a).

[0132] Figure 19 is a timing diagram showing an example of a drive when dynamically switching between the drive of the first embodiment and the drive of this embodiment. Figure 19 shows the waveforms of the vertical sync signal VD, the horizontal sync signal HD, and the control signals tx1, tx2, res, sel, ab_gen, and psave. Figure 19 also shows the value of the digital signal ado, the column information selected by the control signal hadr, and the data values ​​output to channels chA and chB. The symbols [0], [1], and [2] appended to the control signals tx1, tx2, res, and sel represent the row numbers. Note that the operation of the first embodiment described using Figure 5 and the operation of this embodiment described using Figure 16 will be omitted from explanation as appropriate.

[0133] The period from time t2 to time t12 is the drive period for performing the operation of the first embodiment. During this period, the selector 54 of the signal summing unit 50 is set to the connection state shown in Figure 15, the selector 132 of the signal processing unit 120 is set to the connection state shown in Figure 18(b), and the control signal ab_gen is set to a low level. In addition, the control signal psave is set to a high level from time t2 to time t7, and to a low level from time t7 onward. Under these settings, the operation is repeated every 2HD while performing vertical scanning.

[0134] The period from time t12 onward is the drive period during which the operation of this embodiment is performed. During this period, the selector 54 of the signal summing unit 50 is set to the connection state shown in Figure 14, and the selector 132 of the signal processing unit 120 is set to the connection state shown in Figure 18(a). Also during this period, the control signal ab_gen is set to a high level, and the control signal psave is set to a low level. Then, under these settings, the operation is repeated every 1HD while performing vertical scanning.

[0135] By performing the above control while reading the signals from all pixels 12 of the pixel unit 10, the operation of one frame can be mixed with the drive of the first embodiment. This makes it possible to improve the frame rate while reducing power consumption during periods when a high frame rate is not required. Furthermore, by setting the signal summing unit 50 to the connection state shown in Figure 15 during the drive period of the first embodiment and setting the signal summing unit 50 to the connection state shown in Figure 14 during the drive period of this embodiment, the order of the data output from channels chA and chB can be aligned.

[0136] Similarly, it is also possible to dynamically switch between the drive of the second embodiment and the drive of this embodiment. This allows for an improved frame rate while increasing the resolution during periods when a high frame rate is not required.

[0137] Thus, according to this embodiment, in a photoelectric converter that performs pupil-splitting focus detection on the imaging plane, it is possible to suppress the occurrence of pairs that cannot be compressed by addition, thereby reducing the number of signals and the amount of signal processing. This makes it possible to reduce the circuit size and power consumption. Furthermore, in this embodiment, since the phase difference detection signal and the image forming signal are output during the 1HD period, the frame rate can be improved compared to the first embodiment.

[0138] Furthermore, in this embodiment, the operation of selecting rows one by one and performing a vertical scan, i.e., a non-additive operation, has been illustrated, but the system may be configured to add the signals of two or more pixels 12. For example, when performing 2-pixel addition in the vertical direction, two rows are selected at a time, alternating between rows, and the signals of the pixels 12 in each column belonging to these rows are simultaneously output to a common signal output line 16. By operating in this manner, the signals of two pixels 12 of the same color located in the same column can be pseudo-added. Also, when performing addition in the horizontal direction, the signals of node N4A and node N4B are digitally added, and the added signal can be input from node N2AB of the signal processing unit 120 configured as shown in Figure 11, for example, and processed. By configuring in this way, it is possible to perform 2-pixel addition in both the vertical and horizontal directions.

[0139] [Fourth Embodiment] A photoelectric conversion system according to a fourth embodiment of the present invention will be described with reference to Figure 20. Figure 20 is a block diagram showing the schematic configuration of the photoelectric conversion system according to this embodiment.

[0140] The photoelectric conversion device 100 described in the first to third embodiments above is applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in photoelectric conversion systems. Figure 20 shows a block diagram of a digital still camera as an example of these.

[0141] The photoelectric conversion system 200 illustrated in Figure 20 includes an imaging device 201, a lens 202 for forming an optical image of a subject onto the imaging device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and the aperture 204 are an optical system that focuses light onto the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to third embodiments, which converts the optical image formed by the lens 202 into image data.

[0142] The photoelectric conversion system 200 also includes a signal processing unit 208 that processes the output signal output from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as needed before outputting the image data. The imaging device 201 may include an AD conversion unit that generates the digital signal processed by the signal processing unit 208. The AD conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or on a semiconductor substrate separate from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed on the same semiconductor substrate as the imaging device 201.

[0143] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading data from the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200 or it may be detachable.

[0144] Furthermore, the photoelectric conversion system 200 includes an overall control and calculation unit 218 that controls various calculations and the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system 200 only needs to include at least an imaging device 201 and a signal processing unit 208 that processes the output signals output from the imaging device 201.

[0145] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0146] Thus, according to this embodiment, a photoelectric conversion system can be realized by applying the photoelectric conversion device 100 according to the first to third embodiments.

[0147] [Fifth Embodiment] A fifth embodiment of the present invention, consisting of a photoelectric conversion system and a mobile body, will be described with reference to Figure 21. Figure 21 is a diagram showing the configuration of the photoelectric conversion system and mobile body according to this embodiment.

[0148] Figure 21(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any of the first to third embodiments above. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging device 310. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0149] The photoelectric conversion system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to a warning device 340 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0150] In this embodiment, the photoelectric conversion system 300 images the area around the vehicle, for example, the front or rear. Figure 21(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0151] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0152] [Sixth Embodiment] A device according to the sixth embodiment of the present invention will be described with reference to Figure 22. Figure 22 is a block diagram showing the schematic configuration of the device according to this embodiment.

[0153] Figure 22 is a schematic diagram showing an instrument EQP including a photoelectric converter APR. The photoelectric converter APR has the functions of any of the first to third embodiments of the photoelectric converter 100. All or part of the photoelectric converter APR is a semiconductor device IC. The photoelectric converter APR in this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometering sensor, or a distance measuring sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0154] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip equipped with multiple photoelectric conversion units and a second semiconductor chip equipped with peripheral circuits. The peripheral circuits on the second semiconductor chip can each be a column circuit corresponding to a pixel row of the first semiconductor chip. Alternatively, the peripheral circuits on the second semiconductor chip can each be a matrix circuit corresponding to a pixel or pixel block of the first semiconductor chip. Connections between the first and second semiconductor chips can be made using through-silicon vias (TSVs), direct bonding of conductors such as copper for inter-chip wiring, microbump connections between chips, or wire bonding.

[0155] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a cover made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0156] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC. The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or liquid crystal display device that displays information (images) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device or semiconductor device that stores information (images) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has movable parts or propulsion parts such as motors and engines. The device EQP displays signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the device EQP. For this purpose, it is preferable that the device EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR.

[0157] The EQP (Equipment Equipment) shown in Figure 22 can be electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices) or cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In cameras, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. Furthermore, the EQP can be transportation equipment (mobile devices) such as vehicles, ships, and aircraft. Additionally, the EQP can be medical equipment such as endoscopes and CT scanners.

[0158] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, or for assisting and / or automating driving (operation) through its imaging function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0159] The photoelectric converter APR according to this embodiment can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Therefore, by installing the photoelectric converter APR in the EQP (Equipment Equipment), the value of the EQP can also be increased. Thus, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP.

[0160] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0161] Furthermore, although the above embodiment shows an RGB array color filter, it may also be a CMY array color filter including a C pixel with a cyan color filter, an M pixel with a magenta color filter, and a Y pixel with a yellow color filter. In addition to color pixels such as RGB and CMY, it may also include pixels that directly detect incident light without color separation (white pixels) and IR pixels equipped with infrared transmission filters that have a transmission wavelength range in the infrared wavelength range. Furthermore, although the above embodiment shows an example of application to a photoelectric converter that acquires color images, it does not necessarily have to be a photoelectric converter for acquiring color images, and it can also be applied to a photoelectric converter that acquires monochrome images.

[0162] In these pixel configurations, the pixel section 10 can be considered to include a first pixel and a second pixel in each row. Here, the first pixel is a pixel 12 to which the charge of the photoelectric conversion unit PDA is transferred to node FD by a first control signal, and the charge of the photoelectric conversion unit PDB is transferred to node FD by a second control signal. The second pixel is a pixel 12 to which the charge of the photoelectric conversion unit PDA is transferred to node FD by a second control signal, and the charge of the photoelectric conversion unit PDB is transferred to node FD by a first control signal.

[0163] The first and second pixels may be adjacent pixels in the row direction that are sensitive to the same color. In the case of a monochrome sensor, the first and second pixels may be located in adjacent columns. When there are multiple first pixels and multiple second pixels in each row, the first and second pixels may be arranged alternately in the row direction. The pixel section 10 may further have third and fourth pixels in each row that are sensitive to colors different from the first and second pixels. In this case, the first, third, second, and fourth pixels may be arranged repeatedly in this order in the row direction.

[0164] Furthermore, the photoelectric conversion systems shown in the fourth and fifth embodiments above are merely examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and the photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 20 and 21(a).

[0165] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0166] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0167] The above-disclosed embodiment includes the following configuration. (Composition 1) A pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a first photoelectric conversion unit and a second photoelectric conversion unit sharing a single microlens, a charge holding unit that holds the charge transferred from the first photoelectric conversion unit and the second photoelectric conversion unit, and an output unit that outputs a signal corresponding to the amount of charge held by the charge holding unit, A control unit that controls the transfer of charge from the first photoelectric conversion unit and the second photoelectric conversion unit to the charge holding unit in the plurality of pixels on a row-by-row basis, It has a signal processing unit that processes the signal output from the pixel unit, Each row of the pixel section includes a first pixel in which the charge of the first photoelectric converter is transferred to the charge holding section by a first control signal, and the charge of the second photoelectric converter is transferred to the charge holding section by a second control signal, and a second pixel in which the charge of the first photoelectric converter is transferred to the charge holding section by a second control signal, and the charge of the second photoelectric converter is transferred to the charge holding section by a first control signal. The control unit performs a first read operation for each row, supplying the first control signal but not the second control signal, and a second read operation for supplying the first control signal and the second control signal. The signal processing unit outputs a first signal based on the amount of charge of the first photoelectric converter read from the first pixel in response to the first readout operation, and a second signal based on the total amount of charge of the first and second photoelectric converters read from the first pixel in response to the second readout operation, but does not output a third signal based on the amount of charge of the second photoelectric converter read from the second pixel in response to the first readout operation. A photoelectric conversion device characterized by the following features. (Configuration 2) The signal processing unit has a plurality of column AD conversion units, each provided in relation to each of the plurality of columns and each connected to the pixel of the corresponding column, When the signal processing unit reads out the second pixel in response to the first read operation, it stops the AD conversion operation in the column AD conversion unit of the column in which the second pixel is located, thereby not outputting the third signal. A photoelectric conversion device according to configuration 1, characterized by the features described above. (Composition 3) The signal processing unit further outputs a fourth signal based on the total amount of charge from the first and second photoelectric converters read from the second pixel in response to the second readout operation. A photoelectric conversion device according to configuration 1 or 2, characterized by the above. (Composition 4) The first signal is a phase difference detection signal, and the second and fourth signals are image forming signals. A photoelectric conversion device according to configuration 3, characterized by the features described above. (Composition 5) The signal processing unit obtains the third signal and a fourth signal based on the total amount of charge of the first and second photoelectric converters read from the second pixel in response to the second readout operation, and generates a fifth signal by subtracting the third signal from the fourth signal. A photoelectric conversion device according to configuration 1, characterized by the features described above. (Composition 6) The signal processing unit includes a first memory for holding the first signal, a second memory for holding the second signal, a third memory for holding the third signal, and a fourth memory for holding the fourth signal. The first signal read from the first memory and the fifth signal obtained by subtracting the third signal read from the third memory from the fourth signal read from the fourth memory are output in parallel. The second signal read from the second memory and the fourth signal read from the fourth memory are output in parallel. The photoelectric conversion device according to configuration 5, characterized by the features described herein. (Composition 7) The first memory, the second memory, the third memory, and the fourth memory are line memories. A photoelectric conversion device according to configuration 6, characterized by the features described above. (Composition 8) The first memory, the second memory, the third memory, and the fourth memory are composed of frame memories. A photoelectric conversion device according to configuration 6, characterized by the features described above. (Composition 9) The first signal and the fifth signal are phase difference detection signals, and the second signal and the fourth signal are image forming signals. A photoelectric conversion device according to any one of configurations 5 to 8, characterized by the above. (Composition 10) The signal processing unit outputs a sixth signal obtained by adding the first signal and the fifth signal, and a seventh signal obtained by adding the second signal and the fourth signal. The photoelectric conversion device according to configuration 5, characterized by the features described herein. (Composition 11) The sixth signal is a phase difference detection signal, and the seventh signal is an image formation signal. A photoelectric conversion device according to configuration 10, characterized by the above. (Composition 12) A pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a first photoelectric conversion unit and a second photoelectric conversion unit sharing a single microlens, a charge holding unit that holds the charge transferred from the first photoelectric conversion unit and the second photoelectric conversion unit, and an output unit that outputs a signal corresponding to the amount of charge held by the charge holding unit, A control unit that controls the transfer of charge from the first photoelectric conversion unit and the second photoelectric conversion unit to the charge holding unit in the plurality of pixels on a row-by-row basis, It has a signal processing unit that processes the signal output from the pixel unit, Each row of the pixel section includes a first pixel in which the charge of the first photoelectric converter is transferred to the charge holding section by a first control signal, and the charge of the second photoelectric converter is transferred to the charge holding section by a second control signal, and a second pixel in which the charge of the first photoelectric converter is transferred to the charge holding section by a second control signal, and the charge of the second photoelectric converter is transferred to the charge holding section by a first control signal. The signal processing unit includes a signal summing unit that adds the signal read from the first pixel and the signal read from the second pixel, The control unit performs a first read operation for each row, supplying the first control signal and not supplying the second control signal. The signal processing unit outputs a first signal based on the amount of charge of the first photoelectric converter read from the first pixel in response to the first readout operation, and an eighth signal obtained by adding the first signal and a third signal based on the amount of charge of the second photoelectric converter read from the second pixel in response to the first readout operation, but does not output the third signal. A photoelectric conversion device characterized by the following features. (Composition 13) The signal processing unit outputs the first signal and the eighth signal in parallel. A photoelectric conversion device according to configuration 12, characterized by the features described above. (Composition 14) The first signal is a phase difference detection signal, and the eighth signal is an image forming signal. A photoelectric conversion device according to configuration 13, characterized by the features described above. (Composition 15) In the first frame, the signal processing unit outputs the first signal and the eighth signal, but does not output the third signal. In a second frame different from the first frame, the control unit performs the first read operation and the second read operation supplying the first and second control signals row by row, and the signal processing unit outputs the first signal and the second signal based on the total amount of charge of the first and second photoelectric converters read from the first pixel in response to the second read operation, and does not output the third signal. A photoelectric conversion device according to any one of configurations 12 to 14, characterized by the above. (Composition 16) The first pixel and the second pixel are pixels that are sensitive to the same color. A photoelectric conversion device according to any one of configurations 1 to 15, characterized by the above. (Composition 17) The pixel section has a plurality of first pixels and a plurality of second pixels in each row, and the first pixels and second pixels are arranged alternately in the row direction. A photoelectric conversion device according to any one of configurations 1 to 16, characterized by the above. (Composition 18) The pixel section further has a plurality of third pixels and a plurality of fourth pixels in each row, which are sensitive to colors different from the first pixel and the second pixel. The first pixel, the third pixel, the second pixel, and the fourth pixel are arranged repeatedly in this order in the row direction. A photoelectric conversion device according to configuration 17, characterized by the features described above. (Composition 19) The microlens directs light incident on the first pupil region of the optical system that forms an image on the pixel portion into the first photoelectric conversion unit, and directs light incident on a second pupil region different from the first pupil region of the optical system into the second photoelectric conversion unit. A photoelectric conversion device according to any one of configurations 1 to 18, characterized by the above. (Composition 20) The control unit simultaneously drives two or more rows in which the first and second pixels are arranged in the same column. A photoelectric conversion device according to any one of configurations 1 to 19, characterized by the above. (Composition 21) A photoelectric conversion device according to any one of configurations 1 to 20, A signal processing device that processes the signal output from the aforementioned photoelectric converter and A photoelectric conversion system characterized by having the following features. (Composition 22) It is a mobile object, A photoelectric conversion device according to any one of configurations 1 to 20, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features. (Composition 23) A photoelectric conversion device according to any one of configurations 1 to 20, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features. [Explanation of Symbols]

[0168] PDA, PDB... Photoelectric conversion unit 10...Pixel area 12... pixels 20…Vertical scanning unit 30…AD conversion unit 32... Column AD conversion section 40... Signal conversion section 50... Signal addition section 90... Timing generation unit 100... Photoelectric converter

Claims

1. A pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a first photoelectric conversion unit and a second photoelectric conversion unit sharing a single microlens, a charge holding unit that holds the charge transferred from the first photoelectric conversion unit and the second photoelectric conversion unit, and an output unit that outputs a signal corresponding to the amount of charge held by the charge holding unit, A control unit that controls the transfer of charge from the first photoelectric conversion unit and the second photoelectric conversion unit to the charge holding unit in the plurality of pixels on a row-by-row basis, It has a signal processing unit that processes the signal output from the pixel unit, Each row of the pixel section includes a first pixel in which the charge of the first photoelectric converter is transferred to the charge holding section by a first control signal, and the charge of the second photoelectric converter is transferred to the charge holding section by a second control signal, and a second pixel in which the charge of the first photoelectric converter is transferred to the charge holding section by a second control signal, and the charge of the second photoelectric converter is transferred to the charge holding section by a first control signal. The control unit performs a first read operation for each row, supplying the first control signal but not the second control signal, and a second read operation for supplying the first control signal and the second control signal. The signal processing unit outputs a first signal based on the amount of charge of the first photoelectric converter read from the first pixel in response to the first readout operation, and a second signal based on the total amount of charge of the first and second photoelectric converters read from the first pixel in response to the second readout operation, but does not output a third signal based on the amount of charge of the second photoelectric converter read from the second pixel in response to the first readout operation. A photoelectric conversion device characterized by the following features.

2. The signal processing unit has a plurality of column AD conversion units, each of which is provided in accordance with each of the plurality of columns and is connected to the pixels of the corresponding column. When the signal processing unit reads out the second pixel in response to the first read operation, it stops the AD conversion operation in the column AD conversion unit of the column in which the second pixel is located, thereby not outputting the third signal. The photoelectric conversion device according to claim 1, characterized by the features described above.

3. The signal processing unit further outputs a fourth signal based on the total amount of charge of the first and second photoelectric converters read from the second pixel in response to the second readout operation. The photoelectric conversion device according to claim 1, characterized by the features described above.

4. The first signal is a phase difference detection signal, and the second and fourth signals are image forming signals. The photoelectric conversion device according to claim 3.

5. The signal processing unit acquires the third signal and a fourth signal based on the total amount of charge of the first and second photoelectric converters read from the second pixel in response to the second readout operation, and generates a fifth signal by subtracting the third signal from the fourth signal. The photoelectric conversion device according to claim 1, characterized by the features described above.

6. The signal processing unit includes a first memory for holding the first signal, a second memory for holding the second signal, a third memory for holding the third signal, and a fourth memory for holding the fourth signal. The first signal read from the first memory and the fifth signal obtained by subtracting the third signal read from the third memory from the fourth signal read from the fourth memory are output in parallel. The second signal read from the second memory and the fourth signal read from the fourth memory are output in parallel. The photoelectric conversion device according to claim 5, characterized in that it is a photoelectric device.

7. The first memory, the second memory, the third memory, and the fourth memory are line memories. The photoelectric conversion device according to claim 6.

8. The first memory, the second memory, the third memory, and the fourth memory are composed of frame memories. The photoelectric conversion device according to claim 6.

9. The first signal and the fifth signal are phase difference detection signals, and the second signal and the fourth signal are image forming signals. The photoelectric conversion device according to claim 5, characterized in that it is a photoelectric device.

10. The signal processing unit outputs a sixth signal obtained by adding the first signal and the fifth signal, and a seventh signal obtained by adding the second signal and the fourth signal. The photoelectric conversion device according to claim 5, characterized in that it is a photoelectric device.

11. The sixth signal is a phase difference detection signal, and the seventh signal is an image forming signal. The photoelectric conversion device according to claim 10, characterized in that it is a photoelectric conversion device.

12. A pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a first photoelectric conversion unit and a second photoelectric conversion unit sharing a single microlens, a charge holding unit that holds the charge transferred from the first photoelectric conversion unit and the second photoelectric conversion unit, and an output unit that outputs a signal corresponding to the amount of charge held by the charge holding unit, A control unit that controls the transfer of charge from the first photoelectric conversion unit and the second photoelectric conversion unit to the charge holding unit in the plurality of pixels on a row-by-row basis, It has a signal processing unit that processes the signal output from the pixel unit, Each row of the pixel section includes a first pixel in which the charge of the first photoelectric converter is transferred to the charge holding section by a first control signal, and the charge of the second photoelectric converter is transferred to the charge holding section by a second control signal, and a second pixel in which the charge of the first photoelectric converter is transferred to the charge holding section by a second control signal, and the charge of the second photoelectric converter is transferred to the charge holding section by a first control signal. The signal processing unit includes a signal summing unit that adds the signal read from the first pixel and the signal read from the second pixel, The control unit performs a first read operation row by row, supplying the first control signal and not supplying the second control signal. The signal processing unit outputs a first signal based on the amount of charge of the first photoelectric converter read from the first pixel in response to the first readout operation, and an eighth signal obtained by adding the first signal and a third signal based on the amount of charge of the second photoelectric converter read from the second pixel in response to the first readout operation, but does not output the third signal. A photoelectric conversion device characterized by the following features.

13. The signal processing unit outputs the first signal and the eighth signal in parallel. The photoelectric conversion device according to claim 12, characterized in that it is a photoelectric conversion device.

14. The first signal is a phase difference detection signal, and the eighth signal is an image forming signal. The photoelectric conversion device according to claim 13, characterized in that it is a photoelectric conversion device.

15. In the first frame, the signal processing unit outputs the first signal and the eighth signal, but does not output the third signal. In a second frame different from the first frame, the control unit performs the first read operation and the second read operation supplying the first and second control signals row by row, and the signal processing unit outputs the first signal and the second signal based on the total amount of charge of the first and second photoelectric converters read from the first pixel in response to the second read operation, and does not output the third signal. The photoelectric conversion device according to claim 12, characterized in that it is a photoelectric conversion device.

16. The first pixel and the second pixel are pixels that are sensitive to the same color. The photoelectric conversion device according to any one of claims 1 to 15.

17. The pixel section has a plurality of first pixels and a plurality of second pixels in each row, and the first pixels and second pixels are arranged alternately in the row direction. The photoelectric conversion device according to any one of claims 1 to 15.

18. The pixel section further has a plurality of third pixels and a plurality of fourth pixels in each row, which are sensitive to colors different from the first pixel and the second pixel. The first pixel, the third pixel, the second pixel, and the fourth pixel are arranged in this order repeatedly in the row direction. The photoelectric conversion device according to claim 17, characterized in that it is a photoelectric conversion device.

19. The microlens directs light incident on the first pupil region of the optical system that forms an image on the pixel portion into the first photoelectric conversion unit, and directs light incident on a second pupil region different from the first pupil region of the optical system into the second photoelectric conversion unit. The photoelectric conversion device according to any one of claims 1 to 15.

20. The control unit simultaneously drives two or more rows in which the first pixel and the second pixel are arranged in the same column. The photoelectric conversion device according to any one of claims 1 to 15.

21. A photoelectric conversion device according to any one of claims 1 to 15, A signal processing device that processes the signal output from the aforementioned photoelectric converter and A photoelectric conversion system characterized by having the following features.

22. It is a mobile object, A photoelectric conversion device according to any one of claims 1 to 15, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features.

23. A photoelectric conversion device according to any one of claims 1 to 15, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features.

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