Semiconductor wafer, method for manufacturing a semiconductor wafer, semiconductor chip, and method for manufacturing a semiconductor chip.

Abstract

The objective is to provide a semiconductor wafer and a method for manufacturing a semiconductor wafer that can suppress deterioration of the visibility of identification parts that allow for the identification of the semiconductor wafer, even when an epitaxial growth layer is formed on the upper surface of a semiconductor substrate. [Solution] The semiconductor wafer according to this disclosure comprises a semiconductor substrate, an epitaxial growth layer provided on the upper surface of the semiconductor substrate, and an identification portion provided inside the semiconductor substrate and not exposed from the upper and lower surfaces of the semiconductor substrate, which is capable of identifying the semiconductor wafer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor wafer, a method for manufacturing a semiconductor wafer, a semiconductor chip, and a method for manufacturing a semiconductor chip.

Background Art

[0002] In a semiconductor wafer, identification information for identifying the semiconductor wafer may be engraved in the form of characters, symbols, etc. The identification information is, for example, a lot number or wafer number that serves as the ID (Identification) of the semiconductor wafer. By checking the identification part on which the identification information is engraved, product management such as lot management is performed.

[0003] Conventionally, as a method for forming an identification part on a semiconductor wafer, a method of forming an identification part on a semiconductor substrate using a laser beam is known. When forming an identification part using the above method or the like, the substrate is shaved, so the crystal structure of the substrate is destroyed.

[0004] Patent Document 1 discloses a semiconductor wafer having a semiconductor substrate, an identification part provided on the lower surface of the semiconductor substrate that can identify the semiconductor wafer, and a transparent deposition layer deposited on the upper surface of the semiconductor substrate. Further, it is disclosed that the epitaxial growth layer corresponds to the transparent deposition layer, and the identification part may be exposed from the lower surface of the semiconductor substrate.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In semiconductor wafers, if the identification portion is exposed from the upper surface of the semiconductor substrate, introducing a raw material gas to form an epitaxial growth layer on the upper surface of the semiconductor substrate in that state may cause crystal growth to occur as the raw material gas reaches the exposed portion of the identification portion on the upper surface of the semiconductor substrate. Furthermore, even in cases where the identification portion is exposed from the lower surface of the semiconductor substrate, as in the semiconductor wafer described in Patent Document 1, introducing a raw material gas to form an epitaxial growth layer on the upper surface of the semiconductor substrate in that state may cause crystal growth to occur as the raw material gas also wraps around to the lower surface of the semiconductor substrate, reaching the exposed portion of the identification portion on the lower surface of the semiconductor substrate. As described above, when the identification portion is exposed from the upper or lower surface of the semiconductor substrate, the crystal structure of the underlying semiconductor substrate is destroyed in the exposed portion of the identification portion. Therefore, when the raw material gas reaches that portion, the crystal grows abnormally in three dimensions. In that state, when the identification portion is detected from above or below the semiconductor wafer, the abnormally grown crystal and the identification portion overlap, resulting in a problem of poor visibility of the identification portion.

[0007] This disclosure is made to solve the above-mentioned problems and aims to provide a semiconductor wafer and a method for manufacturing a semiconductor wafer that can suppress deterioration of the visibility of identification parts that allow for the identification of the semiconductor wafer, even when an epitaxial growth layer is formed on the upper surface of a semiconductor substrate. [Means for solving the problem]

[0008] The semiconductor wafer according to this disclosure comprises a semiconductor substrate, an epitaxial growth layer provided on the upper surface of the semiconductor substrate, and an identification portion provided inside the semiconductor substrate, not exposed from the upper and lower surfaces of the semiconductor substrate, and capable of identifying the semiconductor wafer.

[0009] The semiconductor wafer manufacturing method according to this disclosure comprises: a semiconductor substrate preparation step of preparing a semiconductor substrate; an identification portion formation step of forming an identification portion inside the semiconductor substrate that is not exposed from the top and bottom surfaces of the semiconductor substrate and is capable of identifying the semiconductor wafer; and an epitaxial growth layer formation step performed after the identification portion formation step of forming an epitaxial growth layer on the top surface of the semiconductor substrate. [Effects of the Invention]

[0010] According to the semiconductor wafer and semiconductor wafer manufacturing method described herein, even when an epitaxial growth layer is deposited on the upper surface of a semiconductor substrate, deterioration of the visibility of the identification portion that allows for the identification of the semiconductor wafer can be suppressed. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic plan view of a semiconductor wafer according to Embodiment 1 before the formation of an opaque layer. [Figure 2] This is a schematic plan view of a semiconductor wafer after the formation of an opaque layer according to Embodiment 1. [Figure 3] This is a schematic cross-sectional view of XX in Figure 2 of a semiconductor wafer according to Embodiment 1. [Figure 4] This is a schematic cross-sectional view of a semiconductor wafer relating to the prior art. [Figure 5] This is a schematic cross-sectional view of a semiconductor wafer relating to the prior art. [Figure 6] This is a schematic cross-sectional view showing the identification part formation step of the semiconductor wafer manufacturing method according to Embodiment 1. [Figure 7] This is a schematic cross-sectional view showing the epitaxial growth layer formation process of the semiconductor wafer manufacturing method according to Embodiment 1. [Figure 8] This is a schematic plan view of a semiconductor wafer before the formation of an opaque layer according to Embodiment 2. [Figure 9] This is a schematic plan view of a semiconductor wafer after the formation of an opaque layer according to Embodiment 2. [Figure 10] This is a schematic cross-sectional view of XX in Figure 9 of a semiconductor wafer according to Embodiment 2. [Figure 11]It is a schematic cross-sectional view showing an identification part formation step of a method for manufacturing a semiconductor wafer according to Embodiment 2. [Figure 12] It is a schematic cross-sectional view showing a semiconductor substrate bonding step of a method for manufacturing a semiconductor wafer according to Embodiment 2. [Figure 13] It is a schematic cross-sectional view showing an epitaxial growth layer formation step of a method for manufacturing a semiconductor wafer according to Embodiment 2. [Figure 14] It is a schematic cross-sectional view taken along the line X-X in FIG. 9 of a semiconductor wafer according to Embodiment 3. [Figure 15] It is a schematic cross-sectional view showing a boundary layer formation step of a method for manufacturing a semiconductor wafer according to Embodiment 3. [Figure 16] It is a schematic cross-sectional view showing an identification part formation step of a method for manufacturing a semiconductor wafer according to Embodiment 3. [Figure 17] It is a schematic cross-sectional view showing a semiconductor substrate bonding step of a method for manufacturing a semiconductor wafer according to Embodiment 3. [Figure 18] It is a schematic cross-sectional view showing an epitaxial growth layer formation step of a method for manufacturing a semiconductor wafer according to Embodiment 3.

Embodiments for Carrying Out the Invention

[0012] <First> One side in the direction parallel to the depth direction of the semiconductor device is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0013] Also, the drawings are shown schematically, and the mutual relationships of the sizes and positions of the images shown in different drawings are not necessarily accurately described and can be changed as appropriate. Also, in the following description, the same reference numerals are given to the same components for illustration, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0014] Embodiment 1. Embodiment 1 will be described below with reference to the drawings. Figure 1 is a schematic plan view of the semiconductor wafer 100 according to Embodiment 1 before the formation of the opaque layer 3. Figure 2 is a schematic plan view of the semiconductor wafer 100 according to Embodiment 1 after the formation of the opaque layer 3. Figure 3 is a schematic cross-sectional view of the semiconductor wafer 100 according to Embodiment 1 after the formation of the opaque layer 3. Note that Figure 3 shows a cross-section along the dashed line X-X shown in Figure 2. Note that the identification part 4 is omitted in Figure 2.

[0015] The configuration of the semiconductor wafer 100 will be explained using Figures 1 to 3. As shown in Figure 3, the semiconductor wafer 100 includes a semiconductor substrate 1, an epitaxial growth layer 2, and an identification portion 4.

[0016] As shown in Figures 1 and 3, the semiconductor wafer 100 has an identification portion 4, which will be described later, engraved on it. As shown in Figure 1, the identification portion 4 is engraved, for example, in an engraved area 102 near the orientation flat 101 of the semiconductor wafer 100. In addition to being near the orientation flat 101, the identification portion 4 may also be engraved in an engraved area provided near a notch. As shown in Figure 1, the identification portion 4 can be seen from above and below the semiconductor wafer 100. Furthermore, as shown in Figure 2, the semiconductor wafer 100 may have an opaque layer region 103 on which the opaque layer 3, described later, is provided, and an outer peripheral region 104 on which the opaque layer 3 is not provided. As shown in Figure 2, the outer peripheral region 104 is provided so as to surround the opaque layer region 103. Of the semiconductor wafer 100, the opaque layer region 103 on which the opaque layer 3 is provided is the region used as a semiconductor device. Note that the position where the identification portion 4 is provided is arbitrary, as long as it can be controlled based on the orientation flat 101 or the notch.

[0017] The semiconductor substrate 1 is made of a semiconductor material that transmits almost all or part of the visible light spectrum, allowing visibility into the identification section 4 described later. For example, it may be made of a semiconductor material such as silicon carbide (SiC). Alternatively, the semiconductor substrate 1 may be made of a semiconductor material that transmits light in wavelength bands other than visible light, such as infrared and ultraviolet light, allowing visibility into the identification section 4 described later. For example, it may be made of a semiconductor material such as silicon (Si). In other words, the semiconductor substrate 1 is made of a semiconductor material that transmits the above-mentioned light, allowing visibility into the identification section 4 described later. Furthermore, as shown in Figure 3, the semiconductor substrate 1 has an upper surface 1a and a lower surface 1b. It is preferable that the semiconductor substrate 1 be made of single-crystal SiC. This improves heat resistance, pressure resistance, etc.

[0018] As shown in Figure 3, the epitaxial growth layer 2 is provided on the upper surface 1a of the semiconductor substrate 1. In Figure 3, the epitaxial growth layer 2 is provided over the entire upper surface 1a of the semiconductor substrate 1. However, if the identification portion 4 is provided in the opaque layer region 103, the epitaxial growth layer 2 may be omitted from the upper surface 1a located in the outer peripheral region 104.

[0019] As shown in Figure 3, the opaque layer 3 may be provided on the upper side of the epitaxial growth layer 2. An interlayer insulating film may be provided between the opaque layer 3 and the epitaxial growth layer 2. The opaque layer 3 is a layer that does not transmit visible light and is often a metal layer that functions as, for example, a gate electrode or upper electrode, but it may also be a resin layer. As shown in Figures 2 and 3, the opaque layer 3 is patterned into a predetermined shape and therefore does not cover the entire upper surface of the semiconductor wafer 100.

[0020] As shown in Figure 3, the identification portion 4 is not exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1, but is provided inside the semiconductor substrate 1. The identification portion 4 is a part of the semiconductor substrate 1 on which identification information that can identify the semiconductor wafer 100 is engraved in the form of characters, symbols, etc. Identification information includes, for example, a lot number or wafer number that serves as the ID (Identification) of the semiconductor wafer. By checking the identification portion 4, product management such as lot management can be performed. As identification information, information to ensure the traceability of the semiconductor wafer 100 may be engraved, such as which ingot the semiconductor wafer was sliced ​​from, and how the front and back surfaces of the semiconductor wafer were finished. Also, as identification information, parameters such as film thickness, concentration, defect information, and the presence or absence of a buffer layer may be engraved as epitaxial growth conditions for forming the epitaxial growth layer. Furthermore, as shown in Figures 1 and 3, it is desirable that the identification portion 4 be provided in the outer peripheral region 104 where the opaque layer 3 is not provided. For example, when forming the identification portion 4 in the opaque layer region 103 of the semiconductor substrate 1 using a laser beam, the semiconductor substrate 1 is scraped away during the formation of the identification portion 4, destroying the crystal structure of the semiconductor substrate 1. Therefore, the region where the identification portion 4 is formed cannot be used as a semiconductor device. By placing the identification portion 4 in the outer peripheral region 104 where the opaque layer 3 is not provided, the region of the identification portion 4 can be used as a semiconductor device. The identification portion 4 is the part of the semiconductor substrate 1 where a portion has been scraped away and the crystal structure of the semiconductor substrate 1 has been destroyed.

[0021] Furthermore, a metal layer such as a lower electrode may be provided on the lower surface 1b side of the semiconductor substrate 1, or a resin layer may be provided.

[0022] As described above, the semiconductor wafer 100 of this embodiment is constructed. In this embodiment, the identification portion 4 is not exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1, but is provided inside the semiconductor substrate 1. This configuration suppresses deterioration of the visibility of the identification portion 4 even when an epitaxial growth layer 2 is deposited on the upper surface 1a of the semiconductor substrate 1. The reason for this will be explained below.

[0023] First, for comparison with the semiconductor wafer 100 in this embodiment, a conventional semiconductor device is shown in Figure 4 as Comparative Example 1. As shown in Figure 4, in a conventional semiconductor wafer, the identification portion 4 is provided inside the semiconductor substrate 1 with the identification portion 4 exposed from the upper surface 1a of the semiconductor substrate 1. When a raw material gas is introduced to form an epitaxial growth layer 2 on the upper surface 1a of the semiconductor substrate 1 in this state, the raw material gas may reach the exposed portion of the identification portion 4, causing crystal growth to occur. In the portion of the upper surface 1a of the underlying semiconductor substrate 1 where the identification portion 4 is exposed, the crystal structure is destroyed, resulting in the formation of abnormally grown crystals 6 in three dimensions. When the identification portion 4 is detected from above or below the semiconductor wafer in this state, the abnormally grown crystals 6 and the identification portion 4 overlap, resulting in poor visibility of the identification portion 4.

[0024] Furthermore, a conventional semiconductor device is shown in Figure 5 as Comparative Example 2. As shown in Figure 5, in a conventional semiconductor wafer, the identification portion 4 is provided inside the semiconductor substrate 1 with the identification portion 4 exposed from the lower surface 1b of the semiconductor substrate 1. When a raw material gas is introduced to form an epitaxial growth layer 2 on the upper surface 1a of the semiconductor substrate 1 in this state, the raw material gas also flows to the lower surface 1b of the semiconductor substrate 1, reaching the area where the identification portion 4 is exposed, and crystal growth may occur. In the area of ​​the lower surface 1b of the underlying semiconductor substrate 1 where the identification portion 4 is exposed, the crystal structure is destroyed, and abnormally grown crystals 6 are formed in a three-dimensional manner. When the identification portion 4 is detected from above or below the semiconductor wafer in this state, the abnormally grown crystals 6 and the identification portion 4 overlap, resulting in poor visibility of the identification portion 4.

[0025] In contrast, in this embodiment, the identification portion 4 of the semiconductor wafer 100 is not exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1, but is provided inside the semiconductor substrate 1. Therefore, even if a raw material gas is introduced onto the upper surface 1a to form the epitaxial growth layer 2 on the upper surface 1a of the semiconductor substrate 1, and the raw material gas also flows to the lower surface 1b of the semiconductor substrate 1, the raw material gas does not reach the identification portion 4. The portion where the crystal structure of the underlying semiconductor substrate 1 is destroyed is not exposed from the upper surface 1a and lower surface 1b, but is located inside the semiconductor substrate 1. Therefore, crystal growth by the raw material gas proceeds normally on the upper surface 1a and lower surface 1b of the semiconductor substrate 1. Consequently, even when depositing the epitaxial growth layer 2 on the upper surface of the semiconductor substrate 1, deterioration of the visibility of the identification portion 4 can be suppressed.

[0026] Next, an example of a method for detecting the identification portion 4 of the semiconductor wafer 100 in this embodiment will be described. The detection step of the identification portion 4 using the detection method described below is performed, for example, when detecting defects in the semiconductor wafer 100. Alternatively, the detection step of the identification portion 4 using the detection method described below may be performed before the epitaxial layer formation process described later. By doing so, the identification portion 4 can be detected and suitable epitaxial growth conditions for the semiconductor wafer 100 can be set.

[0027] The identification portion 4 is detected, for example, by observing it from above the semiconductor wafer 100 using an optical microscope or a laser microscope. Methods for detecting the identification portion 4 include, for example, the method of visual detection using an optical microscope as described in Patent Document 1, and the method of detection using a detection device equipped with a camera with an optical or laser microscope. As described above, the semiconductor substrate 1 of the semiconductor wafer 100 in this embodiment is made of a semiconductor material that transmits light and allows the identification portion 4 to be seen through. Therefore, even if the identification portion 4 is not exposed from the upper surface 1a and lower surface 1b, but is provided inside the semiconductor substrate 1, the identification portion 4 can be detected by the above detection method. Furthermore, if the identification portion 4 is provided in the outer peripheral region 104, the identification portion 4 can be detected from both the upper surface 1a and the lower surface 1b of the semiconductor substrate 1 using the above detection method. Also, if the identification portion 4 is provided in the opaque layer region 103, and the identification portion 4 is to be detected after the opaque layer 3 is provided, the identification portion 4 can be detected from the lower surface 1b of the semiconductor substrate 1 using the above detection method. Furthermore, the identification unit 4 may be detected using light other than visible light, such as infrared or ultraviolet light. In this case, even if the semiconductor substrate 1 is made of Si, which does not transmit visible light, the identification unit 4 can be detected because Si transmits near-infrared light.

[0028] Next, a semiconductor chip manufactured from the semiconductor wafer 100 of this embodiment will be described. The semiconductor chip manufactured from the semiconductor wafer 100 comprises a semiconductor substrate 1, an epitaxial growth layer 2 provided on the upper surface 1a of the semiconductor substrate 1, and an opaque layer 3 provided above the epitaxial growth layer 2. In addition to the identification portion 4 that can identify the semiconductor wafer 100, the semiconductor chip may also be provided with an identification portion that is not exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1, but is provided inside the semiconductor substrate 1, and can identify the semiconductor chip. Multiple such identification portions may be provided for each region where a semiconductor chip is formed. In this way, even after the semiconductor wafer 100 has been divided into multiple semiconductor chip units, it is possible to identify which semiconductor wafer each semiconductor chip was divided from. The identification portion 4 that can identify the semiconductor wafer 100 and the identification portion that can identify the semiconductor chip may have the same identification information, or they may have different identification information.

[0029] Next, the manufacturing method of the semiconductor wafer 100 according to this embodiment will be described using Figures 6 and 7. The manufacturing method of the semiconductor wafer 100 according to this embodiment is basically the same as conventional semiconductor wafer manufacturing methods, except for the identification part formation step, so some parts will be omitted from the explanation.

[0030] The method for manufacturing the semiconductor wafer 100 includes a semiconductor substrate preparation step, an identification portion formation step, and an epitaxial growth layer formation step. Figure 6 illustrates the identification portion formation step, and Figure 7 illustrates the epitaxial growth layer formation step.

[0031] First, the semiconductor substrate preparation process will be described. A semiconductor substrate 1 having an upper surface 1a and a lower surface 1b is prepared. In this embodiment, one semiconductor substrate 1 is prepared.

[0032] Next, the identification portion formation process will be described. As shown in Figure 6, an identification portion 4 capable of identifying the semiconductor wafer 100 is formed inside the semiconductor substrate 1, without being exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1. In addition, in the semiconductor substrate preparation process described above, a semiconductor substrate 1 with the identification portion 4 already formed may be prepared.

[0033] As an example of a method for forming the identification portion 4, a method for forming the identification portion 4 on a semiconductor substrate 1 by laser processing will be described. For example, as shown in Figure 6, the laser L is irradiated from the upper surface 1a side of the semiconductor substrate 1 using a laser irradiator 20, and the identification portion 4 is formed by modifying a certain location inside the semiconductor substrate 1 at a position that is not exposed from the upper surface 1a and lower surface 1b side of the semiconductor substrate 1. Alternatively, the identification portion 4 may be formed by irradiating the lower surface 1b side of the semiconductor substrate 1 with the laser L. Note that since the identification portion 4 is formed by removing a part of the semiconductor substrate 1 using the above-mentioned laser beam method, the crystal structure of the semiconductor substrate 1 is destroyed.

[0034] In order to improve the performance of semiconductor devices, the thickness of the semiconductor wafer 100 may be reduced by grinding the lower surface 1b of the semiconductor wafer 100. Depending on the formation position of the identification portion 4, the identification portion 4 formed inside the semiconductor substrate 1 may also be removed when the semiconductor substrate 1 is ground. In that case, the identification portion 4 may be formed again after grinding the lower surface 1b of the semiconductor wafer 100. Alternatively, the formation position of the identification portion 4 may be adjusted appropriately in advance, taking into account the amount of grinding of the semiconductor wafer 100, so that the identification portion 4 formed inside the semiconductor substrate 1 is not removed when the semiconductor substrate 1 is ground.

[0035] Next, the epitaxial growth layer formation process will be described. The epitaxial growth layer formation process is performed after the identification portion formation process, and as shown in Figure 7, an epitaxial growth layer 2 is formed on the upper surface 1a of the semiconductor substrate 1. For example, the epitaxial growth layer 2 is formed on the upper surface 1a of the semiconductor substrate 1 by the CVD method. As mentioned above, the identification portion formation process described above is performed before the epitaxial growth layer formation process. By doing so, the identification portion 4 formed in the identification portion formation process can be detected by the detection method described above, and the epitaxial growth layer 2 can be formed under epitaxial growth conditions suitable for the semiconductor wafer 100.

[0036] The semiconductor wafer 100 is manufactured through the processes described above. As stated above, the manufacturing method of the semiconductor device wafer 100 in this embodiment includes an identification portion formation step, in which an identification portion 4 capable of identifying the semiconductor wafer 100 is formed inside the semiconductor substrate 1, without being exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1. By doing so, even when an epitaxial growth layer 2 is formed on the upper surface of the semiconductor substrate 1 in the epitaxial growth layer formation step performed after the identification portion formation step, deterioration of the visibility of the identification portion 4 can be suppressed.

[0037] Furthermore, in conventional semiconductor wafer manufacturing methods, the identification portion 4 is formed in the identification portion formation process at a position exposed from the upper surface 1a or lower surface 1b of the semiconductor substrate 1. As a result, dust is generated when forming the identification portion 4, and this dust can reach the semiconductor substrate 1, potentially resulting in defective products. In contrast, in the semiconductor wafer 100 of this embodiment, the identification portion 4 is not exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1, but is provided inside the semiconductor substrate 1. Therefore, the generation of dust when forming the identification portion 4 can be suppressed, and the dust can be prevented from reaching the semiconductor substrate 1, thus suppressing the occurrence of defective products.

[0038] Next, the method for manufacturing the semiconductor chip of this embodiment will be described. The method for manufacturing the semiconductor chip of this embodiment includes a dicing step in which a semiconductor wafer 100 is diced to form a plurality of semiconductor chips. In the dicing step, the semiconductor wafer 100 is divided into semiconductor chip units by a method of dividing the semiconductor wafer, such as blade dicing or laser dicing, thereby forming a plurality of semiconductor chips. After the dicing step, conventional semiconductor chip manufacturing steps such as die bonding are performed.

[0039] Furthermore, in the identification portion formation step described above, an identification portion capable of identifying a semiconductor chip may be formed in the opaque layer region 103. Multiple such identification portions may be formed in each region where a semiconductor chip is formed. This allows for the identification of which semiconductor chip was divided from which semiconductor wafer even after the semiconductor wafer 100 has been divided into multiple semiconductor chip units in the dicing step described above.

[0040] Embodiment 2. The semiconductor wafer 200 in Embodiment 2 will be described using Figures 8 to 10. Figure 8 is a schematic plan view of the semiconductor wafer 200 according to Embodiment 2 before the formation of the opaque layer 3. Figure 9 is a schematic plan view of the semiconductor wafer 200 according to Embodiment 2 after the formation of the opaque layer 3. Figure 10 is a schematic cross-sectional view of the semiconductor wafer 200 according to Embodiment 2 after the formation of the opaque layer 3. Note that Figure 10 shows a cross-section along the dashed line X-X shown in Figure 9. Note that the identification part 4 is omitted in Figure 9.

[0041] The semiconductor wafer 200 of Embodiment 2 differs from Embodiment 1 in that, as shown in Figure 10, the semiconductor substrate 1 is composed of a first semiconductor substrate 11 and a second semiconductor substrate 12 provided on the upper surface 11a of the first semiconductor substrate 11. As shown in Figure 10, the first semiconductor substrate 11 and the second semiconductor substrate 12 together constitute the semiconductor substrate 1, with the upper surface 12a of the second semiconductor substrate 12 being the upper surface 1a of semiconductor substrate 1, and the lower surface 11b of the first semiconductor substrate 11 being the lower surface 1b of semiconductor substrate 1. The first semiconductor substrate 11 and the second semiconductor substrate 12 may each be made of single-crystal SiC. Doing so can improve heat resistance. Alternatively, for example, the second semiconductor substrate 12 may be made of single-crystal SiC, and the first semiconductor substrate 11 may be made of polycrystalline SiC, single-crystal Si, polycrystalline Si, sapphire, carbon, etc. By doing so, the manufacturing cost of the semiconductor wafer 200 can be reduced compared to the case where the first semiconductor substrate 11 is made of single-crystal SiC.

[0042] In the semiconductor wafer 200 of Embodiment 2, as shown in Figure 10, the epitaxial growth layer 2 is provided on the upper surface 1a of the semiconductor substrate 1. More specifically, the epitaxial growth layer 2 is provided on the upper surface 12a of the second semiconductor substrate 12.

[0043] Furthermore, in the semiconductor wafer 200 of Embodiment 2, as shown in Figure 10, the identification portion 4 is not exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1, but is provided inside the semiconductor substrate 1. More specifically, the identification portion 4 is not exposed from the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11, but is provided inside the semiconductor substrate 1. Alternatively, the identification portion 4 may be provided on the lower surface 12b of the second semiconductor substrate 12 and the upper surface 11a of the first semiconductor substrate 11 within the interior of the semiconductor substrate 1. The identification portion 4 provided on the upper surface 11a of the first semiconductor substrate 11 is referred to as the first identification portion 41, and the identification portion 4 provided on the lower surface 12b of the second semiconductor substrate 12 is referred to as the second identification portion 42. As shown in Figure 8, it is desirable that the first identification portion 41 and the second identification portion 42 are provided in positions that do not overlap each other when viewed from above. Furthermore, as shown in Figure 10, it is desirable that the first identification portion 41 and the second identification portion 42 be provided in the outer peripheral region 104 where the opaque layer 3 is not provided.

[0044] In Figure 10, the identification unit 4 is provided on both the lower surface 12b of the second semiconductor substrate 12 and the upper surface 11a of the first semiconductor substrate 11. However, it is sufficient if it is provided on at least one of the lower surface 12b of the second semiconductor substrate 12 or the upper surface 11a of the first semiconductor substrate 11. Furthermore, it is desirable that the identification unit 4 be provided only on the lower surface 12b of the second semiconductor substrate 12 and not on the upper surface 11a of the first semiconductor substrate 11.

[0045] The semiconductor wafer 200 of Embodiment 2 is configured as described above.

[0046] In the second embodiment, the semiconductor wafer 200 consists of a semiconductor substrate 1 comprising a first semiconductor substrate 11 and a second semiconductor substrate 12 provided on the upper surface 11a of the first semiconductor substrate 11. The epitaxial growth layer 2 is provided on the upper surface 12a of the second semiconductor substrate 12, and the identification portion 4 is not exposed from the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11, but is provided inside the semiconductor substrate 1. In this way, even if a raw material gas is introduced onto the upper surface 12a of the second semiconductor substrate 12 and the raw material gas also flows to the lower surface 11b of the first semiconductor substrate 11, the identification portion 4 is not exposed from the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11, but is provided inside the semiconductor substrate 1. Therefore, similar to the first embodiment, the raw material gas can be prevented from reaching the identification portion 4. The areas where the crystal structures of the underlying first semiconductor substrate 11 and second semiconductor substrate 12 are destroyed are not exposed from the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11, but are located inside the entire semiconductor substrate 1. Therefore, normal crystal growth occurs on the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11. Consequently, even when the epitaxial growth layer 2 is deposited on the upper surface 12a of the second semiconductor substrate 12, deterioration of the visibility of the identification part 4 can be suppressed.

[0047] Furthermore, in the semiconductor wafer 200 of Embodiment 2, when the identification section 4 is provided on both the second semiconductor substrate 12 and the first semiconductor substrate 11, it is desirable that the first identification section 41 and the second identification section 42 be positioned so that they do not overlap when viewed from above, as described above. By doing so, the identification sections 41 and 42 can be detected separately, and the identification information can be read appropriately. In addition, in the semiconductor wafer 200 of Embodiment 2, by providing the identification section 4 on the second semiconductor substrate 12 and not on the first semiconductor substrate 11, the first semiconductor substrate 11 can be easily reused.

[0048] Next, an example of a method for detecting the identification portion 4 in the semiconductor wafer 200 of Embodiment 2 will be described. For example, if the identification portion 4 is provided on at least one of the lower surface 12b of the second semiconductor substrate 12 or the upper surface 11a of the first semiconductor substrate 11, and the identification portion 4 is detected using only visible light, the identification portion 4 can be detected if at least one of the first semiconductor substrate 11 or the second semiconductor substrate 12 is made of a semiconductor material that transmits visible light.

[0049] Next, the manufacturing method for the semiconductor wafer 200 of Embodiment 2 will be described using Figures 11 to 13. The manufacturing method for the semiconductor wafer 200 of Embodiment 2 includes a semiconductor substrate preparation step, an identification portion formation step, a semiconductor substrate bonding step, and an epitaxial growth layer formation step. The identification portion formation step will be described in Figure 11, the semiconductor substrate bonding step in Figure 12, and the epitaxial growth layer formation step in Figure 13. Note that parts that are the same as those in Embodiment 1 will be omitted from the explanation.

[0050] First, let's explain the semiconductor substrate preparation process. A first semiconductor substrate 11 and a second semiconductor substrate 12 are prepared as semiconductor substrate 1.

[0051] Next, the identification portion formation process will be described. In the identification portion formation process, the identification portion 4 is formed inside the semiconductor substrate 1 without being exposed from the upper surface 12a of the second semiconductor substrate 12 or the lower surface 11b of the first semiconductor substrate 11. As shown in Figure 11(a), in the second semiconductor substrate 12, the second identification portion 42 may be formed on the lower surface 12b of the second semiconductor substrate 12 without being exposed from the upper surface 12a of the second semiconductor substrate 12, and as shown in Figure 11(b), in the first semiconductor substrate 11, the first identification portion 41 may be formed on the upper surface 11a of the first semiconductor substrate 11 without being exposed from the lower surface 11b of the first semiconductor substrate 11. In Embodiment 2, both the first identification portion 41 and the second identification portion 42 are formed, but it is sufficient to form either the first identification portion 41 or the second identification portion 42, and the identification portion 4 may be formed on at least one of the lower surface 12b of the second semiconductor substrate 12 or the upper surface 11a of the first semiconductor substrate 11. Furthermore, in the semiconductor substrate preparation step described above, a semiconductor substrate 1 with the identification portion 4 already formed may be prepared.

[0052] The identification section 4 may be formed by irradiating the first semiconductor substrate 11 and the second semiconductor substrate 12 with a laser L using a laser irradiator 20, as shown in Figure 11, to form identification sections 41 and 42. On the second semiconductor substrate 12, the second identification section 42 is formed by irradiating the second semiconductor substrate 12 with the laser L from the upper surface 12a side and modifying a part of the lower surface 12b side of the second semiconductor substrate 12 so that it is not exposed from the upper surface 12a side of the second semiconductor substrate 12. Alternatively, the laser L may be irradiated from the lower surface 12b side of the second semiconductor substrate 12. On the first semiconductor substrate 11, the first identification section 41 is formed by irradiating the first semiconductor substrate 11 with the laser L from the upper surface 11a side and modifying a part of the upper surface 11a side of the first semiconductor substrate 11 so that it is not exposed from the lower surface 11b side of the first semiconductor substrate 11. Alternatively, the laser L may be irradiated from the lower surface 11b side of the first semiconductor substrate 11.

[0053] Next, the semiconductor substrate bonding process will be described. As shown in Figure 12(a), first, the upper surface 11a of the first semiconductor substrate 11 and the lower surface 12b of the second semiconductor substrate 12 are aligned so that they face each other. Then, as shown in Figure 12(b), the lower surface 12b of the second semiconductor substrate 12 is bonded to the upper surface 11a of the first semiconductor substrate 11. In Embodiment 2, the first semiconductor substrate 11 and the second semiconductor substrate 12 are directly bonded.

[0054] Next, the epitaxial growth layer formation process will be described. The epitaxial growth layer formation process is performed after the identification portion formation process, and as shown in Figure 13, an epitaxial growth layer 2 is formed on the upper surface 12a of the second semiconductor substrate 12. In the above identification portion formation process, if an identification portion 4 is formed on at least one of the lower surface 12b of the second semiconductor substrate 12 or the upper surface 11a of the first semiconductor substrate 11, the epitaxial growth layer formation process is performed after the identification portion formation process and the semiconductor substrate bonding process.

[0055] The semiconductor wafer 200 is manufactured through the process described above. As stated above, the manufacturing method for the semiconductor device wafer 200 of Embodiment 2 includes an identification portion formation step, in which an identification portion 4 capable of identifying the semiconductor wafer 200 is formed inside the semiconductor substrate 1, without being exposed from the upper surface 12a of the second semiconductor substrate 12 or the lower surface 11b of the first semiconductor substrate 11. The method also includes a semiconductor substrate bonding step, in which the lower surface 12b of the second semiconductor substrate 12 is bonded to the upper surface 11a of the first semiconductor substrate 11. By doing so, even when an epitaxial growth layer 2 is formed on the upper surface 12a of the second semiconductor substrate 12 in the epitaxial growth layer formation step performed after the identification portion formation step, deterioration of the visibility of the identification portion 4 can be suppressed.

[0056] Furthermore, in the manufacturing method of the semiconductor device wafer 100 of Embodiment 1, since the semiconductor substrate 1 is composed of only one, in the identification portion formation step, in order to form the identification portion 4 inside the semiconductor substrate 1 without exposing it from the upper surface 1a and lower surface 1b of the semiconductor substrate 1, it is necessary to form the identification portion 4 inside one semiconductor substrate 1. For this reason, the method for forming the identification portion 4 is limited to, for example, a method using a laser. In contrast, in the manufacturing method of the semiconductor device wafer 200 of Embodiment 2, since the semiconductor substrate 1 is composed of two, a first semiconductor substrate 11 and a second semiconductor substrate 12, in the identification portion formation step, the identification portion 4 is formed on at least one of the lower surface 12b of the second semiconductor substrate 12 or the upper surface 11a of the first semiconductor substrate 11, and in the semiconductor substrate bonding step, the lower surface 12b of the second semiconductor substrate 12 is bonded to the upper surface 11a of the first semiconductor substrate 11, thereby allowing the identification portion 4 to be formed inside the semiconductor substrate 1 without exposing it from the upper surface 1a and lower surface 1b of the semiconductor substrate 1. Therefore, compared to the manufacturing method of the semiconductor device wafer 100 in Embodiment 1, the identification portion 4 can be easily formed inside the semiconductor substrate 1 without being exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1. For example, the identification portion 4 can be formed by mechanical methods such as cutting.

[0057] Furthermore, in the semiconductor wafer 200 manufacturing method of Embodiment 2, after the epitaxial growth layer formation step, the semiconductor wafer 200 may be divided into upper and lower halves, and the part of the divided semiconductor substrate 1 that does not have an epitaxial growth layer may be reused in the semiconductor substrate preparation step of another semiconductor wafer manufacturing method. In this case, the divided semiconductor substrate 1 may be reused as the first semiconductor substrate 11 of another semiconductor wafer, or as the second semiconductor substrate 12. In the semiconductor wafer 200 manufacturing process, the thickness of the semiconductor wafer 200 may be reduced by grinding the lower surface 1b side of the semiconductor wafer 200, in which case the portion of the semiconductor substrate 1 located on the lower surface 1b side is removed. In particular, when the semiconductor substrate 1 is composed of single-crystal SiC, since single-crystal SiC is relatively expensive, the manufacturing cost of the semiconductor wafer can be reduced by dividing the semiconductor wafer 200 and reusing the divided semiconductor substrate 1. Furthermore, in the identification portion formation step in the semiconductor wafer 200 manufacturing method, the identification portion 4 may be formed only on the lower surface 12b of the second semiconductor substrate 12 and not on the upper surface 11a of the first semiconductor substrate 11, thereby making it easier to reuse the first semiconductor substrate 11.

[0058] Embodiment 3. The semiconductor wafer 300 in Embodiment 3 will be described with reference to Figure 14. Figure 14 is a schematic cross-sectional view of the semiconductor wafer 300 according to Embodiment 3 after the formation of the opaque layer 3. Note that the schematic plan view of the semiconductor wafer 300 according to Embodiment 3 before the formation of the opaque layer 3 and the schematic plan view after the formation of the opaque layer 3 are the same as in Figures 8 and 9, respectively, and are therefore omitted. Note that Figure 14 shows a cross-section along the dashed line X-X shown in Figure 9.

[0059] The semiconductor wafer 300 of Embodiment 3 differs from Embodiment 1 in that, as shown in Figure 14, the semiconductor substrate 1 is composed of a first semiconductor substrate 11 and a second semiconductor substrate 12 provided on the upper surface 11a of the first semiconductor substrate 11. Furthermore, it differs from Embodiment 2 in that a boundary layer 5, consisting of at least one of organic or inorganic material, is interposed between the upper surface 11a of the first semiconductor substrate 11 and the lower surface 12b of the second semiconductor substrate 12. Note that, as shown in Figure 14, the first semiconductor substrate 11, the second semiconductor substrate 12, and the boundary layer 5 together constitute the semiconductor substrate 1, the upper surface 12a of the second semiconductor substrate 12 is the upper surface 1a of semiconductor substrate 1, and the lower surface 11b of the first semiconductor substrate 11 is the lower surface 1b of semiconductor substrate 1.

[0060] In the semiconductor wafer 300 of Embodiment 3, as shown in Figure 14, the epitaxial growth layer 2 is provided on the upper surface 1a of the semiconductor substrate 1. More specifically, the epitaxial growth layer 2 is provided on the upper surface 12a of the second semiconductor substrate 12.

[0061] Furthermore, in the semiconductor wafer 300 of Embodiment 3, as shown in Figure 14, the identification portion 4 is not exposed from the upper surface 1a and lower surface 1b of the semiconductor substrate 1, but is provided inside the semiconductor substrate 1. More specifically, the identification portion 4 is not exposed from the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11, but is provided inside the semiconductor substrate 1. Also, as shown in Figure 14, the identification portion 4 may be provided inside the semiconductor substrate 1 on the lower surface 12b of the second semiconductor substrate 12 and the upper surface 11a of the first semiconductor substrate 11. The identification portion 4 provided on the upper surface 11a of the first semiconductor substrate 11 is referred to as the first identification portion 41, and the identification portion 4 provided on the lower surface 12b of the second semiconductor substrate 12 is referred to as the second identification portion 42. As shown in Figure 14, it is desirable that the first identification portion 41 and the second identification portion 42 are provided in positions that do not overlap each other when viewed from above. Furthermore, as shown in Figure 14, it is desirable that the first identification section 41 and the second identification section 42 be provided in the outer peripheral region 104 where the opaque layer 3 is not provided.

[0062] Similar to Embodiment 2, the identification unit 4 may be provided on at least one of the lower surface 12b of the second semiconductor substrate 12 or the upper surface 11a of the first semiconductor substrate 11. Furthermore, it is desirable that the identification unit 4 be provided only on the lower surface 12b of the second semiconductor substrate 12 and not on the upper surface 11a of the first semiconductor substrate 11. In addition, the identification unit 4 may be provided on the boundary layer 5.

[0063] The boundary layer 5 is preferably an amorphous layer. Alternatively, the boundary layer 5 may be composed of an intermediate agent such as an adhesive, as long as it facilitates bonding between the first semiconductor substrate 11 and the second semiconductor substrate.

[0064] The semiconductor wafer 300 of Embodiment 3 is configured as described above.

[0065] In the third embodiment, the semiconductor wafer 300 consists of a semiconductor substrate 1 comprising a first semiconductor substrate 11 and a second semiconductor substrate 12 provided on the upper surface 11a of the first semiconductor substrate 11, with an epitaxial growth layer 2 provided on the upper surface 12a of the second semiconductor substrate 12, and the identification portion 4 is not exposed from the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11, but is provided inside the semiconductor substrate 1. In this way, even if a raw material gas is introduced onto the upper surface 12a of the second semiconductor substrate 12 and the raw material gas also flows to the lower surface 11b of the first semiconductor substrate 11, the identification portion 4 is not exposed from the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11, but is provided inside the semiconductor substrate 1, so that, similar to the first embodiment, the raw material gas can not reach the identification portion 4. The areas where the crystal structures of the underlying first semiconductor substrate 11 and second semiconductor substrate 12 are destroyed are not exposed from the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11, but are located inside the entire semiconductor substrate 1. Therefore, normal crystal growth occurs on the upper surface 12a of the second semiconductor substrate 12 and the lower surface 11b of the first semiconductor substrate 11. Consequently, even when the epitaxial growth layer 2 is deposited on the upper surface 12a of the second semiconductor substrate 12, deterioration of the visibility of the identification part 4 can be suppressed.

[0066] Next, the manufacturing method for the semiconductor wafer 300 of Embodiment 3 will be described using Figures 15 to 18. The manufacturing method for the semiconductor wafer 300 of Embodiment 3 includes a semiconductor substrate preparation step, a boundary layer formation step, an identification part formation step, a semiconductor substrate bonding step, and an epitaxial growth layer formation step. The boundary layer formation step is shown in Figure 15, the identification part formation step in Figure 16, the semiconductor substrate bonding step in Figure 17, and the epitaxial growth layer formation step in Figure 18. Note that parts that are the same as those in Embodiment 1 will be omitted from the explanation.

[0067] First, let's explain the semiconductor substrate preparation process. A first semiconductor substrate 11 and a second semiconductor substrate 12 are prepared as semiconductor substrate 1.

[0068] Next, the boundary layer formation process will be described. A boundary layer 5 made of at least one organic or inorganic material is formed between the upper surface 11a of the first semiconductor substrate 11 and the lower surface 12b of the second semiconductor substrate 12. In Embodiment 2, as shown in Figure 15, a boundary layer 5 made of at least one organic or inorganic material is formed on the lower surface 12b of the second semiconductor substrate 12. As described above, it is desirable to form an amorphous layer as the boundary layer 5, and an intermediate agent such as an adhesive may also be formed. Alternatively, the boundary layer 5 made of at least one organic or inorganic material may be formed on the upper surface 11a of the first semiconductor substrate 11. Furthermore, in the semiconductor substrate preparation process described above, a semiconductor substrate 1 with the boundary layer 5 already formed may be prepared.

[0069] Next, the identification portion formation process will be described. In the identification portion formation process, the identification portion 4 is formed inside the semiconductor substrate 1 without being exposed from the upper surface 12a of the second semiconductor substrate 12 or the lower surface 11b of the first semiconductor substrate 11. As shown in Figure 16(a), in the second semiconductor substrate 12, the identification portion 42 may be formed on the lower surface 12b of the second semiconductor substrate 12 without being exposed from the upper surface 12a of the second semiconductor substrate 12, and as shown in Figure 16(b), in the first semiconductor substrate 11, the identification portion 41 may be formed on the upper surface 11a of the first semiconductor substrate 11 without being exposed from the lower surface 11b of the first semiconductor substrate 11. In Embodiment 2, both the first identification portion 41 and the second identification portion 42 are formed, but it is sufficient to form either the first identification portion 41 or the second identification portion 42, and the identification portion 4 may be formed on at least one of the lower surface 12b of the second semiconductor substrate 12 or the upper surface 11a of the first semiconductor substrate 11. Also, in the semiconductor substrate preparation step described above, a semiconductor substrate 1 with the identification portion 4 and boundary layer 5 already formed may be prepared. In Figure 16(a), the identification portion 42 is formed on the second semiconductor substrate 12 with the boundary layer 5 formed, but the identification portion 42 may be formed on the second semiconductor substrate 12 first, and then the boundary layer 5 may be formed on the second semiconductor substrate 12 with the identification portion 42 formed.

[0070] The identification section 4 may be formed by irradiating the first semiconductor substrate 11 and the second semiconductor substrate 12 with a laser L using a laser irradiator 20, as shown in Figure 16, to form the identification sections 41 and 42. On the second semiconductor substrate 12, the second identification section 42 is formed by irradiating the second semiconductor substrate 12 with the laser L from the upper surface 12a side and modifying a part of the lower surface 12b side of the second semiconductor substrate 12 so that it is not exposed from the upper surface 12a side of the second semiconductor substrate 12. Alternatively, the laser L may be irradiated from the lower surface 12b side of the second semiconductor substrate 12. On the first semiconductor substrate 11, the first identification section 41 is formed by irradiating the first semiconductor substrate 11 with the laser L from the upper surface 11a side and modifying a part of the upper surface 11a side of the first semiconductor substrate 11 so that it is not exposed from the lower surface 11b side of the first semiconductor substrate 11. Alternatively, the laser L may be irradiated from the lower surface 11b side of the first semiconductor substrate 11. In Figure 16(a), the second identification portion 42 is formed inside the second semiconductor substrate 12 by irradiating the interior of the second semiconductor substrate 12 with a laser L. However, the second identification portion 42 may also be formed on the boundary layer 5 by irradiating the boundary layer 5 with a laser L. In such a case, the identification portion 4 can be formed inside the semiconductor substrate 1 without being exposed from the upper surface 12a of the second semiconductor substrate 12 or the lower surface 11b of the first semiconductor substrate 11.

[0071] Next, the semiconductor substrate bonding process will be described. As shown in Figure 17(a), first, the upper surface 11a of the first semiconductor substrate 11 and the lower surface 12b of the second semiconductor substrate 12 are aligned so that they face each other. Then, as shown in Figure 17(b), the lower surface 12b of the second semiconductor substrate 12 is bonded to the upper surface 11a of the first semiconductor substrate 11. In Embodiment 3, the first semiconductor substrate 11 and the second semiconductor substrate 12 are indirectly bonded via a boundary layer 5 composed of an intermediate agent such as an adhesive. Note that when the first semiconductor substrate 11 and the second semiconductor substrate 12 are directly bonded, a boundary layer 5 may be interposed between the first semiconductor substrate 11 and the second semiconductor substrate 12. For example, in room temperature bonding, an amorphous layer which is the boundary layer 5 may be formed on at least one of the first semiconductor substrate 11 and the second semiconductor substrate 12. Therefore, the first semiconductor substrate 11 and the second semiconductor substrate 12 may be bonded at room temperature, with an amorphous layer acting as the boundary layer 5 interposed between them.

[0072] Next, the epitaxial growth layer formation process will be described. The epitaxial growth layer formation process is performed after the identification portion formation process, and as shown in Figure 18, an epitaxial growth layer 2 is formed on the upper surface 12a of the second semiconductor substrate 12. In the above identification portion formation process, if the identification portion 4 is formed on at least one of the lower surface 12b of the second semiconductor substrate 12 or the upper surface 11a of the first semiconductor substrate 11, the epitaxial growth layer formation process is performed after the identification portion formation process and the semiconductor substrate bonding process. However, for example, if the identification portion 4 is formed on the lower surface 12b of the second semiconductor substrate 12 in the above identification portion formation process, and the boundary layer 5 is formed on the lower surface 12b of the second semiconductor substrate 12 in the above boundary layer formation process, the identification portion 4 is not exposed on the lower surface 12b of the second semiconductor substrate 12, so this is not the case.

[0073] The semiconductor wafer 300 is manufactured through the process described above. As stated above, the manufacturing method for the semiconductor device wafer 300 of Embodiment 3 includes an identification portion formation step, in which an identification portion 4 capable of identifying the semiconductor wafer 300 is formed inside the semiconductor substrate 1, without being exposed from the upper surface 12a of the second semiconductor substrate 12 or the lower surface 11b of the first semiconductor substrate 11. The method also includes a semiconductor substrate bonding step, in which the lower surface 12b of the second semiconductor substrate 12 is bonded to the upper surface 11a of the first semiconductor substrate 11. By doing so, even when an epitaxial growth layer 2 is formed on the upper surface 12a of the second semiconductor substrate 12 in the epitaxial growth layer formation step performed after the identification portion formation step, deterioration of the visibility of the identification portion 4 can be suppressed.

[0074] Furthermore, as described above, the manufacturing method for the semiconductor wafer 300 of Embodiment 3 includes a boundary layer formation step, in which a boundary layer 5 made of at least one organic or inorganic material is formed between the upper surface 11a of the first semiconductor substrate 11 and the lower surface 12b of the second semiconductor substrate 12. In this way, in the semiconductor substrate bonding step, the first semiconductor substrate 11 and the second semiconductor substrate 12 can be bonded by the boundary layer 5 made of at least one organic or inorganic material, making the bonding of the first semiconductor substrate 11 and the second semiconductor substrate 12 easier than in Embodiment 2.

[0075] As mentioned above, it is desirable to form an amorphous layer as the boundary layer 5 in the boundary layer formation process. By doing so, in the semiconductor substrate bonding process, depending on the materials of the first semiconductor substrate 11 and the second semiconductor substrate 12, it becomes possible to bond the first semiconductor substrate 11 and the second semiconductor substrate 12 at room temperature. For example, if the first semiconductor substrate 11 and the second semiconductor substrate 12 are made of single crystal SiC, they can be bonded at room temperature. When bonding the first semiconductor substrate 11 and the second semiconductor substrate 12 at room temperature, bonding can be performed without using an intermediate agent such as an adhesive, thus suppressing the deterioration of quality due to the aging of the intermediate agent.

[0076] The configurations shown in the embodiments described above are merely examples of the content of this disclosure and can be combined with other known technologies. Furthermore, the embodiments can be combined with each other, as well as with each other, and variations can be combined. Additionally, parts of the configuration can be omitted or modified without departing from the gist of this disclosure.

[0077] The various aspects of this disclosure are summarized below as an appendix.

[0078] (Note 1) Semiconductor substrate and An epitaxial growth layer provided on the upper surface of the semiconductor substrate, A semiconductor wafer comprising an identification portion that is not exposed from the upper and lower surfaces of the semiconductor substrate, but is provided inside the semiconductor substrate and capable of identifying the semiconductor wafer. (Note 2) The semiconductor substrate is composed of a first semiconductor substrate and a second semiconductor substrate provided on the upper surface of the first semiconductor substrate. The epitaxial growth layer is provided on the upper surface of the second semiconductor substrate, The semiconductor wafer as described in Appendix 1, wherein the identification portion is not exposed from the upper surface of the second semiconductor substrate and the lower surface of the first semiconductor substrate, but is provided inside the semiconductor substrate. (Note 3) The semiconductor wafer as described in Appendix 2, wherein the identification portion is provided on at least one of the lower surface of the second semiconductor substrate or the upper surface of the first semiconductor substrate. (Note 4) The identification unit consists of a first identification unit provided on the upper surface of the first semiconductor substrate and a second identification unit provided on the lower surface of the second semiconductor substrate. The semiconductor wafer described in Appendix 2 or Appendix 3, wherein the first identification portion and the second identification portion are provided in positions that do not overlap each other when viewed from above. (Note 5) The semiconductor wafer as described in Appendix 3, wherein the identification portion is provided only on the lower surface of the second semiconductor substrate. (Note 6) A semiconductor wafer according to any one of the appendices 2 to 5, wherein a boundary layer consisting of at least one organic or inorganic material is interposed between the upper surface of the first semiconductor substrate and the lower surface of the second semiconductor substrate. (Note 7) The identification portion is provided in the boundary layer, and is a semiconductor wafer as described in Appendix 6. (Note 8) The semiconductor wafer according to Appendix 6 or Appendix 7, wherein the boundary layer is an amorphous layer. (Note 9) The epitaxial growth layer further comprises an opaque layer provided above it, The semiconductor substrate has an opaque layer region on which the opaque layer is provided, and an outer peripheral region on which the opaque layer is not provided. The identification portion is provided in the outer peripheral region and is a semiconductor wafer as described in any one of Appendix 1 to Appendix 8. (Note 10) The semiconductor substrate is a semiconductor wafer made of SiC, as described in any one of the appendices 1 to 9. (Note 11) Semiconductor substrate and An epitaxial growth layer provided on the upper surface of the semiconductor substrate, An opaque layer provided above the epitaxial growth layer, A semiconductor chip comprising an identification portion that is not exposed from the upper and lower surfaces of the semiconductor substrate, but is provided inside the semiconductor substrate and capable of identifying the semiconductor chip. (Note 12) The semiconductor substrate preparation process involves preparing a semiconductor substrate, An identification portion formation step is to form an identification portion that is not exposed from the upper and lower surfaces of the semiconductor substrate, but is located inside the semiconductor substrate and capable of identifying a semiconductor wafer. A method for manufacturing a semiconductor wafer, comprising: an epitaxial growth layer formation step performed after the identification portion formation step, wherein an epitaxial growth layer is formed on the upper surface of the semiconductor substrate. (Note 13) The method for manufacturing a semiconductor wafer as described in Appendix 12, wherein the identification portion formation step involves modifying the inside of the semiconductor substrate by laser processing to form the identification portion. (Note 14) The semiconductor substrate preparation step involves preparing a first semiconductor substrate and a second semiconductor substrate as the semiconductor substrates. The identification portion formation step is performed such that the identification portion is not exposed from the upper surface of the second semiconductor substrate and the lower surface of the first semiconductor substrate, and is formed inside the semiconductor substrate. The invention further comprises a semiconductor substrate bonding step of bonding the lower surface of a second semiconductor substrate to the upper surface of the first semiconductor substrate, The method for manufacturing a semiconductor wafer according to Appendix 12 or Appendix 13, wherein the epitaxial growth layer formation step is to form an epitaxial growth layer on the upper surface of the second semiconductor substrate. (Note 15) The identification portion formation step involves forming the identification portion on at least one of the lower surface of the second semiconductor substrate or the upper surface of the first semiconductor substrate. The semiconductor wafer described in Appendix 14, wherein the epitaxial growth layer formation step is performed after the identification portion formation step and the semiconductor substrate bonding step. (Note 16) The method for manufacturing a semiconductor wafer according to Appendix 14, further comprising a boundary layer formation step of forming a boundary layer made of at least one organic or inorganic material between the upper surface of the first semiconductor substrate and the lower surface of the second semiconductor substrate. (Note 17) A method for manufacturing a semiconductor chip, comprising a dicing step of dicing a semiconductor wafer manufactured by any one of the semiconductor wafer manufacturing methods described in Appendix 12 to Appendix 16 to form a plurality of semiconductor chips. [Explanation of symbols]

[0079] 1 Semiconductor substrate, 11 First semiconductor substrate, 12 Second semiconductor substrate, 2 Epitaxial growth layer, 3 Opaque layer, 4 Identification area, 41 First identification area, 42 Second identification area, 5 Boundary layer, 100 200 300 Semiconductor wafer, 103 Opaque layer region, 104 Outer periphery region, L Laser

Claims

1. Semiconductor substrate and An epitaxial growth layer provided on the upper surface of the semiconductor substrate, A semiconductor wafer comprising an identification portion that is not exposed from the upper and lower surfaces of the semiconductor substrate, but is provided inside the semiconductor substrate and capable of identifying the semiconductor wafer.

2. The semiconductor substrate is composed of a first semiconductor substrate and a second semiconductor substrate provided on the upper surface of the first semiconductor substrate. The epitaxial growth layer is provided on the upper surface of the second semiconductor substrate, The semiconductor wafer according to claim 1, wherein the identification portion is not exposed from the upper surface of the second semiconductor substrate and the lower surface of the first semiconductor substrate, and is provided inside the semiconductor substrate.

3. The semiconductor wafer according to claim 2, wherein the identification portion is provided on at least one of the lower surface of the second semiconductor substrate or the upper surface of the first semiconductor substrate.

4. The identification unit comprises a first identification unit provided on the upper surface of the first semiconductor substrate and a second identification unit provided on the lower surface of the second semiconductor substrate. The semiconductor wafer according to claim 2, wherein the first identification portion and the second identification portion are provided in positions that do not overlap with each other when viewed from above.

5. The semiconductor wafer according to claim 3, wherein the identification portion is provided only on the lower surface of the second semiconductor substrate.

6. The semiconductor wafer according to claim 2, wherein a boundary layer consisting of at least one organic or inorganic material is interposed between the upper surface of the first semiconductor substrate and the lower surface of the second semiconductor substrate.

7. The semiconductor wafer according to claim 6, wherein the identification portion is provided in the boundary layer.

8. The semiconductor wafer according to claim 6, wherein the boundary layer is an amorphous layer.

9. The epitaxial growth layer further comprises an opaque layer provided above it, The semiconductor substrate has an opaque layer region on which the opaque layer is provided, and an outer peripheral region on which the opaque layer is not provided. The semiconductor wafer according to any one of claims 1 to 8, wherein the identification portion is provided in the outer peripheral region.

10. The semiconductor wafer according to any one of claims 1 to 8, wherein the semiconductor substrate is made of SiC.

11. Semiconductor substrate and An epitaxial growth layer provided on the upper surface of the semiconductor substrate, An opaque layer provided above the epitaxial growth layer, A semiconductor chip comprising an identification portion that is not exposed from the upper and lower surfaces of the semiconductor substrate, but is provided inside the semiconductor substrate and capable of identifying the semiconductor chip.

12. The semiconductor substrate preparation process involves preparing a semiconductor substrate, An identification portion formation step is to form an identification portion that is not exposed from the upper and lower surfaces of the semiconductor substrate, but is located inside the semiconductor substrate and capable of identifying a semiconductor wafer. A method for manufacturing a semiconductor wafer, comprising: an epitaxial growth layer formation step performed after the identification portion formation step, wherein an epitaxial growth layer is formed on the upper surface of the semiconductor substrate.

13. The method for manufacturing a semiconductor wafer according to claim 12, wherein the identification portion formation step involves modifying the inside of the semiconductor substrate by laser processing to form the identification portion.

14. The semiconductor substrate preparation step involves preparing a first semiconductor substrate and a second semiconductor substrate as the semiconductor substrates. The identification portion formation step is performed such that the identification portion is not exposed from the upper surface of the second semiconductor substrate and the lower surface of the first semiconductor substrate, and is formed inside the semiconductor substrate. The process further includes a semiconductor substrate bonding step of bonding the lower surface of a second semiconductor substrate to the upper surface of the first semiconductor substrate, The method for manufacturing a semiconductor wafer according to claim 12, wherein the epitaxial growth layer formation step is to form an epitaxial growth layer on the upper surface of the second semiconductor substrate.

15. The identification portion formation step involves forming the identification portion on at least one of the lower surface of the second semiconductor substrate or the upper surface of the first semiconductor substrate. The method for manufacturing a semiconductor wafer according to claim 14, wherein the epitaxial growth layer formation step is performed after the identification portion formation step and the semiconductor substrate bonding step.

16. The method for manufacturing a semiconductor wafer according to claim 14, further comprising a boundary layer formation step of forming a boundary layer made of at least one organic or inorganic material between the upper surface of the first semiconductor substrate and the lower surface of the second semiconductor substrate.

17. A method for manufacturing a semiconductor chip, comprising a dicing step of dicing a semiconductor wafer manufactured by the semiconductor wafer manufacturing method described in any one of claims 12 to 16 to form a plurality of semiconductor chips.

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