Layout creation method, original plate manufacturing method, and semiconductor device manufacturing method
The layout creation method addresses the challenge of securing process margins in semiconductor manufacturing by simulating and adjusting layout data to meet acceptable ranges, enhancing the reliability and quality of semiconductor devices through optimized CMP and lithography processes.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2024-11-26
- Publication Date
- 2026-06-05
AI Technical Summary
Existing semiconductor manufacturing processes face challenges in appropriately securing process margins, which are crucial for ensuring the quality and reliability of semiconductor devices.
A layout creation method that involves determining and adjusting layout data to ensure process margins by simulating and modifying the layout of each layer to meet acceptable ranges, specifically focusing on Chemical Mechanical Polishing (CMP) and lithography margins, and optimizing pattern arrangements to reduce steps and variations.
The method effectively secures process margins, reducing defects and improving the manufacturing yield and quality of semiconductor devices by ensuring that process conditions fall within acceptable limits.
Smart Images
Figure 2026092564000001_ABST
Abstract
Description
Technical Field
[0001] This embodiment relates to a layout creation method, a master plate manufacturing method, and a semiconductor device manufacturing method.
Background Art
[0002] In the manufacturing process of a semiconductor device, layout data is created in layout design, a pattern according to the created layout data is drawn on a master plate, and the pattern of the master plate is transferred to a substrate, whereby a real pattern is formed on the substrate. In the manufacturing process of a semiconductor device, it is desired to appropriately secure a process margin.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] One embodiment aims to provide a layout creation method, a master plate manufacturing method, and a semiconductor device manufacturing method capable of appropriately securing a process margin.
Means for Solving the Problems
[0005] According to one embodiment, a layout creation method is provided. The layout creation method includes obtaining a process margin of a second layer to be formed next to the first layer using the layout data of the first layer. The layout creation method includes determining whether a condition regarding the process margin of the second layer is within an allowable range. The layout creation method includes changing the layout data of the first layer when the condition is out of the allowable range.
Brief Description of the Drawings
[0006] [Figure 1] A block diagram showing the configuration of a manufacturing system to which the layout creation method according to the first embodiment is applied. [Figure 2] A flowchart illustrating a method for manufacturing a semiconductor device, including a layout creation method according to the first embodiment. [Figure 3] A flowchart illustrating a layout creation method according to the first embodiment. [Figure 4] A flowchart illustrating the layout creation method according to the second embodiment. [Figure 5] A diagram illustrating the concept of CMP margin in the second embodiment. [Figure 6] A flowchart illustrating the procedure for calculating the CMP margin in the second embodiment. [Figure 7] A diagram showing the expansion of the CMP margin in the second embodiment. [Figure 8] A flowchart illustrating a layout creation method according to the third embodiment. [Figure 9] A diagram showing the relative expansion of the lithography margin to the required lithography margin in the third embodiment. [Figure 10] A diagram showing the layout change of the current layer in the third embodiment. [Figure 11] A flowchart illustrating the layout creation method according to the fourth embodiment. [Figure 12] A diagram showing the margin curves for each region in the fourth embodiment. [Modes for carrying out the invention]
[0007] The method for creating the layout according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.
[0008] (First embodiment) The layout creation method according to the first embodiment creates layout data to be used in the manufacture of semiconductor devices, and incorporates measures to appropriately ensure process margins in the manufacture of semiconductor devices.
[0009] The layout creation method may be applied to a manufacturing system 100 as shown in Figure 1. Figure 1 is a block diagram showing the configuration of a manufacturing system 100 to which the layout creation method is applied.
[0010] The manufacturing system 100 includes a circuit design device 101, a layout design device 102, a simulation device 103, a master plate creation device 104, a coating device 105, an exposure device 106, a developing device 107, a processing device 108, and a host controller 109. The circuit design device 101, the layout design device 102, and the simulation device 103 may be implemented by a single computer or by multiple computers connected to each other in a communicative manner. The master plate creation device 104 may be, for example, an electron beam lithography device. The circuit design device 101, the layout design device 102, the simulation device 103, and the master plate creation device 104 may be connected to each other in a communicative manner via a communication line (not shown). The simulation device 103, the coating device 105, the exposure device 106, the developing device 107, the processing device 108, and the host controller 109 may be connected to each other in a communicative manner via a communication line (not shown).
[0011] Furthermore, the manufacturing system 100 operates as shown in Figure 2. Figure 2 is a flowchart of the operation of the manufacturing system 100.
[0012] The circuit design device 101 performs circuit design (S1) based on predetermined design information and / or instructions from the user, generates schematic data, and supplies it to the layout design device 102.
[0013] Since the device according to the schematic data can be realized with a multi-layer structure, the layout design is also performed for multiple layers in the manufacturing order. The layout design device 102 selects the layer to be processed among the multiple layers as the current layer (S2).
[0014] Based on the schematic data and / or an instruction from the user, the layout design device 102 performs layout design while collaborating with the simulation device 103 (S3), and creates the layout of the current layer.
[0015] In S3, layout design as shown in FIG. 3 may be performed. FIG. 3 is a flowchart showing a layout creation method.
[0016] When the layout design device 102 acquires the schematic data from the circuit design device 101 (S11), it performs the layout design of the current layer (S12). The layout design device 102 arranges a plurality of patterns according to the schematic data on the layout drawing of the current layer. Thereby, the layout design device 102 generates the layout data of the current layer and supplies it to the simulation device 103.
[0017] The simulation device 103 executes process simulation using the layout data of the current layer (S13).
[0018] The simulation device 103 may simulate the processed shape of the substrate when a semiconductor process (e.g., coating, transfer, exposure, development, processing, etc.) is applied to the substrate, or may simulate the processing conditions of the substrate when a semiconductor process is applied to the substrate.
[0019] The simulation device 103 may perform verification as to whether the design of the layout drawing matches the design of the schematic drawing, or verification as to whether physical design criteria (design rules) are satisfied (design rule check).
[0020] The simulation device 103 calculates the process margin of the next layer to be formed after the current layer, according to the simulation results and verification results (S14). The simulation device 103 may numerically calculate the process margin of the next layer. The simulation device 103 may numerically calculate the required process margin according to multiple patterns of the next layer. The simulation device 103 supplies the process margin of the next layer or the required process margin of the next layer to the layout design device 102.
[0021] When the process margin for the next layer or the required process margin for the next layer is supplied, the layout design apparatus 102 determines whether the conditions for the process margin of the next layer are within an acceptable range (S15). The layout design apparatus 102 may also determine whether the processed shape of the substrate when a semiconductor process is applied to the substrate satisfies the process margin, or whether the processing conditions of the substrate when a semiconductor process is applied to the substrate satisfies the process margin, or whether the required process margins corresponding to multiple patterns of the next layer satisfies the process margin.
[0022] If the conditions regarding the process margin of the next layer fall outside the acceptable range (No in S15), the layout design device 102 returns to S12, redoes the layout design of the current layer (S12), and modifies the layout data of the current layer. The layout design device 102 then supplies the modified layout data of the current layer to the simulation device 103.
[0023] The simulation device 103 performs process simulation and verification using the modified layout data of the current layer (S13), and calculates the process margin of the next layer to be formed after the current layer again according to the simulation and verification results (S14). The simulation device 103 supplies the process margin of the next layer to the layout design device 102.
[0024] When the process margin for the next layer is supplied, the layout design apparatus 102 determines whether the conditions for the process margin of the next layer are within an acceptable range (S15).
[0025] The loop processing from S12 to S15 is repeated until the conditions regarding the process margin of the next layer fall within an acceptable range (No in S15).
[0026] When the conditions regarding the process margin of the next layer fall within the acceptable range (Yes in S15), and the design rule check confirms that the layout of the current layer satisfies the design rules, the layout design device 102 terminates the layout design of the current layer.
[0027] Once the layout design for the current layer is complete, the layout design device 102 generates drawing data from the layout data of the current layer and supplies it to the master plate creation device 104. The master plate is, for example, a mask, a reticle, etc.
[0028] The master plate creation device 104 creates a master plate by drawing multiple master plate patterns on the master plate substrate according to the drawing data (S4). The created master plate can be set on the master plate stage of the exposure device 105. Subsequently, the circuit board is manufactured (S5).
[0029] For example, the coating apparatus 105 coats a photosensitive material (e.g., resist) onto a substrate (e.g., wafer). The substrate coated with the photosensitive material is transported from the coating apparatus 105 to the exposure apparatus 106 by a transport system (not shown) and placed on the substrate stage of the exposure apparatus 106. The exposure apparatus 106 uses a projection optical system to project exposure light that has been illuminated by an illumination optical system and passed through the master plate, or exposure light that has been reflected by the master plate, onto the substrate, transferring multiple patterns on the master plate to the photosensitive material on the substrate to form a latent image.
[0030] After exposure, the substrate is transported from the exposure apparatus 106 to the developing apparatus 107 by a transport system (not shown). The developing apparatus 107 develops the latent image in the photosensitive material on the substrate. As a result, a pattern corresponding to the design information (drawing data) is developed in each shot area on the substrate.
[0031] After development, the substrate is transported from the developing device 107 to the processing device 108 by a transport system (not shown). The processing device 108 uses the developed photosensitive pattern as a mask to perform predetermined processing on the substrate. This forms a pattern in each shot area on the substrate according to the design information (drawing data).
[0032] System 100 returns processing to S2 if there are other layers to be processed in the multiple layers that should realize a device according to the schematic data (Yes in S6).
[0033] System 100 terminates processing if there are no other layers to process (No in S6).
[0034] As described above, in the first embodiment, the layout creation method involves using the layout data of the current layer to determine the process margin of the next layer, determining whether the conditions for the process margin of the next layer fall within an acceptable range, and if the conditions fall outside the acceptable range, modifying the layout data of the current layer. These processes are repeated until the conditions for the process margin of the next layer fall within an acceptable range. This allows the layout design of the next layer to be carried out in such a way that the process margin is secured. In other words, the process margin can be appropriately secured.
[0035] Note that the determination in S15 shown in Figure 3 may be performed by the simulation device 103. In this case, the simulation device 103 calculates the process margin of the next layer (S14), then determines whether the conditions related to the process margin of the next layer are within an acceptable range (S15), and supplies the determination result to the layout design device 102. The layout creation method itself is the same as in the first embodiment.
[0036] (Second embodiment) Next, we will describe the layout creation method according to the second embodiment. The following description will focus on the differences from the first embodiment.
[0037] In the first embodiment, a process simulation is performed using the layout data of the current layer to determine the process margin of the next layer. In the second embodiment, a process simulation is performed using the layout data of the current layer to determine the CMP (Chemical Mechanical Polishing) margin of the next layer.
[0038] In S3 of Figure 2, a different layout design from the first embodiment may be implemented, as shown in Figure 4. Figure 4 is a flowchart showing the layout creation method in the second embodiment.
[0039] After steps S11 and S12 are performed in the same manner as in the first embodiment, the simulation device 103 performs a CMP simulation using the layout data of the current layer (S21).
[0040] The simulation device 103 has pre-configured library information that experimentally determines polishing conditions according to multiple pattern layouts. The multiple pattern layouts include layouts with different pattern arrangement densities, maximum density differences between patterns, pattern lengths, pattern widths, and pattern perimeters. The polishing conditions include polishing rates, polishing times, polishing amounts, and polishing shapes.
[0041] The simulation device 103 performs a CMP simulation using the layout data of the current layer while referring to library information. The simulation device 103 may also perform a CMP simulation using the layout data of the current layer for multiple different polishing times (or multiple different polishing amounts).
[0042] The simulation device 103 obtains a step map of the next layer as a simulation result (S22). The simulation device 103 may obtain step maps for multiple different polishing times (or multiple different polishing amounts).
[0043] A step map is a three-dimensional map showing the shape of the polished surface of a substrate after CMP (Chemical Polishing) treatment. The step map may be constructed as image data. The step map may also have pixel position and height information associated two-dimensionally with multiple pixels. The step map may also be a map where the height of the polished surface is shown two-dimensionally using shades of gray or color.
[0044] The step map may further show the layout shape of the conductive film, the thickness distribution of the conductive film, the layout shape of the insulating film, and the thickness distribution of the insulating film. The step map may also associate pixel positions and the thickness information of the conductive film and insulating film in two dimensions for multiple pixels.
[0045] The simulation device 103 calculates the CMP margin of the next layer using a step map (S23). The simulation device 103 may also calculate the CMP margin of the next layer using multiple step maps for multiple different polishing times (or multiple different polishing amounts).
[0046] Here, the CMP margin can be defined as shown in Figure 5. Figure 5 is a diagram illustrating the concept of the CMP margin.
[0047] For example, when a substrate is subjected to CMP (Chemical Polishing), if the amount or time of polishing is appropriate, the conductive film pattern and the insulating film pattern will be formed appropriately, and no defects will occur. As shown in Figure 5(a), there is an appropriate range for the amount or time of polishing that will prevent defects from occurring. This appropriate range for the amount or time of polishing that will prevent defects is called the CMP margin.
[0048] If the amount of polishing on the substrate is less than the appropriate range, or if the polishing time on the substrate is shorter than the appropriate range, as shown in Figure 5(b), insufficient polishing by CMP will occur, resulting in remaining polished conductive film and potentially causing short-circuit defects. Short-circuit defects can occur when the conductive film patterns connect in areas where they should not.
[0049] As shown in Figure 5(c), the upper limit of the CMP margin corresponds to the amount or time of polishing at which the insufficient polishing begins to be resolved when the amount or time of polishing is increased from a state of insufficient polishing.
[0050] On the other hand, if the amount of polishing on the substrate is greater than the appropriate range, or if the polishing time on the substrate is longer than the appropriate range, it is considered over-polishing by the CMP process, which can lead to excessive polishing of the conductive film and potentially cause open-circuit defects. Open-circuit defects can occur when the conductive film pattern is broken at a point where it should be connected.
[0051] As shown in Figure 5(d), the lower limit of the CMP margin corresponds to the amount or time of polishing at which overpolishing begins to be eliminated when the amount or time of polishing is reduced from the overpolished state.
[0052] Taking this into consideration, in S23, the next layer's CMP margin may be calculated as shown in Figure 6. Figure 6 is a flowchart showing the procedure for calculating the CMP margin.
[0053] The simulation device 103 uses the multiple step maps acquired in S22 to determine the polishing time PT1 (or polishing amount PA1) that represents the boundary of the remaining polished area (S31).
[0054] For example, suppose that among the multiple step maps acquired in S22, the step map for polishing time PT10 (or polishing amount PA10) shows that there is at least one place in the substrate where polishing remains, and the step map for polishing time PT11 (or polishing amount PA11) shows no place in the substrate where polishing remains. In this case, the simulation device 103 may determine the polishing time PT1 that represents the boundary of the polishing remains using the following formula 1. PT1 = (PT10 + PT11) / 2 ... Formula 1
[0055] The simulation device 103 may determine the polishing amount PA1 that forms the boundary of the remaining polished area using the following equation 2. PA1 = (PA10 + PA11) / 2 ... Formula 2
[0056] The simulation device 103 uses the multiple step maps acquired in S22 to determine the polishing time PT2 (or polishing amount PA2) that marks the boundary of over-polishing (S32).
[0057] For example, suppose that among the multiple step maps acquired in S22, the step map for polishing time PT20 (or polishing amount PA20) shows that overpolishing has occurred at least one location within the substrate, while the step map for polishing time PT21 (or polishing amount PA21) shows no locations within the substrate where overpolishing has occurred. In this case, the simulation device 103 may determine the polishing time PT2 that represents the boundary of overpolishing using the following formula 3. PT2 = (PT20 + PT21) / 2 ... Formula 3
[0058] The simulation device 103 may determine the polishing amount PA2 that marks the boundary of over-polishing using the following formula 4. PA2 = (PA20 + PA21) / 2 ... Formula 4
[0059] The simulation device 103 takes the difference between polishing time PT1 and polishing time PT2 (or the difference between polishing amount PA1 and polishing amount PA2) (S33) and calculates the CMP margin TM (or AM). The simulation device 103 may also calculate the CMP margin TM with respect to polishing time using the following formula 5. TM = PT1 - PT2 ... Formula 5
[0060] The simulation device 103 may determine the CMP margin AM related to the polishing amount using the following formula 6. AM = PA1 - PA2 ... Formula 6
[0061] Once the calculation of the CMP margin for the next layer (S23) is complete, the simulation device 103 supplies the CMP margin for the next layer to the layout design device 102.
[0062] When the CMP margin for the next layer is supplied, the layout design device 102 determines whether or not the CMP margin for the next layer is within the acceptable range (S24).
[0063] If the conditions regarding the process margin of the next layer fall outside the acceptable range (No in S24), the layout design device 102 returns to S12, redoes the layout design of the current layer (S12), and modifies the layout data of the current layer.
[0064] For example, the layout design device 102 may place dummy patterns in the lower-height areas on the layout diagram for multiple locations with large steps on the step map. The layout design device 102 may increase the width and / or size of the patterns in the lower-height areas on the layout diagram for multiple locations with large steps on the step map. The layout design device 102 may change the pattern shape in the lower-height areas on the layout diagram to a more isotropic shape for multiple locations with large steps on the step map.
[0065] The layout design device 102 may make changes to the layout diagram to bring the density of patterns between multiple locations with large steps on the step map closer together. The layout design device 102 may also make changes to the layout diagram to bring the width and / or size of patterns between multiple locations with large steps on the step map closer together. It may also make changes to bring the shapes of patterns between multiple locations closer together on the layout diagram.
[0066] The layout design device 102 supplies the modified layout data of the current layer to the simulation device 103.
[0067] The simulation device 103 performs a CMP simulation using the modified layout data of the current layer (S21), and obtains a step map again as a simulation result (S22). The simulation device 103 may also obtain step maps for multiple different polishing times (or multiple different polishing amounts).
[0068] The simulation device 103 uses the step map to recalculate the CMP margin of the next layer (S23). The simulation device 103 may also use multiple step maps for multiple different polishing times (or multiple different polishing amounts) to calculate the CMP margin of the next layer.
[0069] The simulation device 103 supplies the process margin for the next layer to the layout design device 102.
[0070] When the CMP margin for the next layer is supplied, the layout design device 102 determines again whether the CMP margin for the next layer is within the acceptable range (S24).
[0071] The loop processing from S12 to S24 is repeated until the CMP margin of the next layer falls within the acceptable range (No in S24).
[0072] When the CMP margin of the next layer falls within the acceptable range (Yes in S24) and the design rule check confirms that the layout of the current layer satisfies the design rules, the layout design device 102 terminates the layout design of the current layer.
[0073] In other words, as the loop processing from S12 to S24 is repeated, the pattern of the current layer is repeatedly modified to reduce the CMP step, as shown in Figure 7, thereby reducing the CMP step and expanding the CMP margin. Figure 7 shows the expansion of the CMP margin.
[0074] As described above, in the second embodiment, the layout creation method involves using the layout data of the current layer to determine the CMP margin of the next layer, determining whether the CMP margin of the next layer falls within the acceptable range, and if the CMP margin falls outside the acceptable range, modifying the layout data of the current layer. These processes are repeated until the CMP margin of the next layer falls within the acceptable range. This allows the layout design of the next layer to be carried out in a way that reduces the CMP step and ensures the CMP margin. In other words, the CMP margin can be appropriately ensured.
[0075] (Third embodiment) Next, a method for creating a layout according to the third embodiment will be described. The following description will focus on the differences from the first and second embodiments.
[0076] In the second embodiment, a process for expanding the CMP margin is exemplified, while in the third embodiment, a process for expanding the lithography margin is exemplified.
[0077] In S3 of Figure 2, a different layout design from the second embodiment may be implemented, as shown in Figure 8. Figure 8 is a flowchart showing the layout creation method in the third embodiment.
[0078] After steps S11 to S22 are performed in the same manner as in the second embodiment, the simulation device 103 calculates the process variation (S30). The process variation can be represented by rectangles with the required EL and required DOF as vertices on a scatter plot with exposure amount on the horizontal axis and depth of field on the vertical axis, as shown in the center of Figure 9. The required EL is calculated from the performance of the exposure device and the variation in each process, and the required DOF is calculated from the exposure device component and the step component. The exposure device component is calculated from the performance of the exposure device and is difficult to improve, i.e., to reduce its value, but the step component is caused by the step of the current layer during exposure and can be reduced by reducing the step.
[0079] Once the calculation of process variation (S30) is complete, the simulation device 103 supplies the process variation to the layout design device 102.
[0080] The layout design device 102 performs the layout design for the next layer (S31). The layout design device 102 places multiple patterns corresponding to the schematic data on the layout diagram of the next layer. As a result, the layout design device 102 generates the layout data for the next layer and supplies it to the simulation device 103.
[0081] The simulation device 103 performs a lithography simulation according to the step map and the layout data of the next layer (S32). The simulation device 103 may also determine the pattern imaging properties on the substrate for the master pattern according to the layout data of the next layer. The simulation device 103 may determine the pattern imaging properties on the substrate for the master pattern under multiple different exposure conditions and generate multiple lithography simulation results. The multiple exposure conditions differ from each other in at least one of the exposure amount EL and depth of focus DOF.
[0082] The simulation device 103 calculates the margin curve for each pattern in the layout based on the performance of the exposure device 106 and the layout data (S33). The simulation device 103 can determine the margin curve with exposure amount and depth of field as axes according to the results of multiple lithography simulations. The margin curve varies depending on the pattern and the step conditions of the current layer, and the pattern in which the area enclosed by the solid line curve shown in the center of Figure 9 and the vertical and horizontal axes is smallest is sometimes called the worst pattern.
[0083] As shown in the center of Figure 9, on a scatter plot with exposure on the horizontal axis and depth of field on the vertical axis, the lithography margin is shown as the area enclosed by the solid curve in the worst pattern and the vertical and horizontal axes minus the process variation. Figure 9 shows how the area enclosed by the margin curve and the vertical and horizontal axes (the margin curve area) expands relatively with respect to the process variation, that is, the relative expansion of the lithography margin with respect to the required lithography margin.
[0084] Once the calculation of the margin curve (S33) is complete, the simulation device 103 supplies the margin curve to the layout design device 102.
[0085] When a margin curve is supplied, the layout design apparatus 102 determines whether or not a lithography margin is secured by checking whether or not the amount of process variation falls within the region of the margin curve (S34).
[0086] For example, if the process variation exceeds the margin curve region, as shown by the dotted rectangular area in the center of Figure 9, the layout design apparatus 102 determines that the process variation does not fall within the margin curve region. This indicates that the lithography margin is not secured.
[0087] If the layout design device 102 does not have sufficient lithography margin (No in S34), it returns to process S12, redoes the layout design of the current layer (S12), and modifies the layout data of the current layer. Specifically, it reduces the step component of the required DOF by modifying the layout of the current layer to reduce the step difference.
[0088] For example, the layout design device 102 may place dummy patterns on the lower-height areas of the layout diagram for multiple locations with large steps on the step map.
[0089] Based on the step map, the layout design device 102 identifies the area RG3 with a lower height due to step ST1 relative to the main areas RG1 and RG2 in the next layer, as shown in Figures 10(a) and 10(b). Figure 10 shows a layout change of the current layer. Figure 10(a) is a plan view showing the layout of the current layer before the change, and Figure 10(b) is a cross-sectional view thereof, showing the cross-section of Figure 10(a) cut along line AA.
[0090] The layout design device 102 places a dummy pattern DP in region RG3, as shown in Figures 10(c) and 10(d). Figure 10(c) is a plan view showing the layout of the current layer after the change, and Figure 10(d) is a cross-sectional view thereof, showing the cross-section of Figure 10(c) cut along line BB. By placing the dummy pattern DP, the step difference of region RG3 relative to the main regions RG1 and RG2 can be reduced from ST1 to ST2. Accordingly, it is thought that the CMP step difference can be reduced.
[0091] The layout design device 102 may increase the width and / or size of the pattern at the lower height locations on the layout diagram for multiple locations with large steps on the step map. The layout design device 102 may also change the pattern shape at the lower height locations on the layout diagram for multiple locations with large steps on the step map to a more isotropic shape.
[0092] The layout design device 102 may make changes to the layout diagram to bring the density of patterns between multiple locations with large steps on the step map closer together. The layout design device 102 may also make changes to the layout diagram to bring the width and / or size of patterns between multiple locations with large steps on the step map closer together. It may also make changes to bring the shapes of patterns between multiple locations closer together on the layout diagram.
[0093] The layout design device 102 supplies the modified layout data of the current layer to the simulation device 103.
[0094] The simulation device 103 performs a CMP simulation using the modified layout data of the current layer (S21), and obtains a step map again as a simulation result (S22). The simulation device 103 may also obtain step maps for multiple different polishing times (or multiple different polishing amounts).
[0095] The simulation device 103 calculates the process variation (S30).
[0096] Once the calculation of process variation (S30) is complete, the simulation device 103 supplies the process variation to the layout design device 102.
[0097] The layout design device 102 redesigns the layout of the next layer (S31) and modifies the layout data of the next layer.
[0098] The layout design device 102 supplies the modified layout data for the next layer to the simulation device 103.
[0099] The simulation device 103 performs a lithography simulation according to the layout data of the next layer and calculates the margin curve for each pattern (S32).
[0100] The simulation device 103 recalculates the margin curve according to the lithography simulation results (S33).
[0101] Once the calculation of the margin curve (S33) is complete, the simulation device 103 supplies the margin curve to the layout design device 102.
[0102] Once the margin curve is supplied, the layout design device 102 determines again whether or not the lithography margin is secured (S34).
[0103] The loop processing from S12 to S34 is repeated until the process variation falls within the margin curve region (No in S34).
[0104] For example, if the step component of the required DOF is reduced due to a change in the layout of the current layer, the right-hand side of the process variation amount shifts to the left, as shown by the solid rectangular area in the center of Figure 9. If the process variation amount falls within the area of the margin curve, the layout design apparatus 102 determines that the lithography margin is secured.
[0105] When the process variation falls within the margin curve range (Yes in S34) and the design rule check confirms that the layout of the current layer satisfies the design rules, the layout design device 102 terminates the layout design of the current layer.
[0106] In other words, as the loop processing from S12 to S34 is repeated, the pattern of the current layer is repeatedly modified so that the CMP step is reduced and the step component is reduced, as shown in Figure 9. This reduces the step component, reduces the required DOF so that the process variation amount falls within the margin curve region, and relatively expands the region of the margin curve relative to the process variation amount. Figure 9 shows the relative expansion of the margin curve relative to the process variation amount, that is, the relative expansion of the lithography margin relative to the required lithography margin.
[0107] By relatively expanding the region of the margin curve with respect to process variation, as shown in Figures 10(c) and 10(d), patterns with a relatively narrow line width LW1 can be placed even in region RG3. This reduces the chip area of semiconductor devices manufactured according to the layout data.
[0108] As described above, in the third embodiment, the layout creation method determines the amount of process variation based on the step map of the next layer obtained using the layout data of the current layer and the layout data of the next layer. It is determined whether the amount of process variation falls within the margin curve region, and if the amount of process variation falls outside the margin curve region, the layout data of the current layer is changed. These processes are repeated until the amount of process variation falls within the margin curve region. This makes it possible to design the layout of the next layer in such a way that the CMP step is reduced and the margin curve region is relatively expanded with respect to the amount of process variation. In other words, the lithography margin can be appropriately secured.
[0109] (Fourth embodiment) Next, we will describe the layout creation method according to the fourth embodiment. The following description will focus on the differences from the first to third embodiments.
[0110] In the first to third embodiments, a process for determining a common process margin for a substrate is exemplified, while in the fourth embodiment, a process for determining a process margin for each of multiple regions within the substrate is exemplified.
[0111] In S3 of Figure 2, a different layout design from the first embodiment may be implemented, as shown in Figure 11. Figure 11 is a flowchart showing the layout creation method in the fourth embodiment.
[0112] After steps S11 to S32 are performed in the same manner as in the third embodiment, the simulation device 103 classifies the entire area of the next layer into multiple regions according to the step map obtained in S22. The simulation device 103 may also classify the entire area of the next layer into multiple regions according to the level of the step shown in the step map.
[0113] As shown in Figures 10(a) and 10(b), the simulation device 103 may classify the entire region in the next layer into three main regions RG1 and RG2 with small step differences, region RG3 with a moderate step difference (e.g., step difference of ST1), and regions RG4 and RG5 with large step differences (e.g., step difference of ST3 > ST1).
[0114] The simulation device 103 calculates margin curves for each of the multiple regions in the next layer (S41).
[0115] As a result, the simulation device 103 can determine margin curves for regions RG1, RG2, and RG3, with exposure and depth of field as the axes, as shown by solid lines in Figures 12(a) and 12(b). The curve in Figure 12(a) shows the margin curve for the worst-case pattern in the main regions RG1 and RG2, where the step difference is small. The curve in Figure 12(b) shows the margin curve for the worst-case pattern in region RG3, where the step difference is moderate.
[0116] The simulation device 103 can choose not to calculate margin curves for regions RG4 and RG5 with large step differences, and to leave these regions without patterns.
[0117] The simulation device 103 selects a region to be processed from among multiple regions in the next layer according to the step map, and also selects a process variation amount (S42). Depending on the step map, the simulation device 103 may select a process variation amount corresponding to a relatively small step, i.e., a process variation amount with a small required DOF, for regions with relatively small steps. Depending on the step map, the simulation device 103 may select a process variation amount corresponding to a relatively large step, i.e., a process variation amount with a large required DOF, for regions with relatively large steps.
[0118] For example, if the main regions RG1 and RG2, which have small step differences, are selected as the regions to be processed, the simulation device 103 uses the margin curve for the worst-case pattern of regions RG1 and RG2 as the margin curve for regions RG1 and RG2, as shown in Figure 12(a).
[0119] When region RG3, which has a moderate step difference, is selected as the region to be processed, the simulation device 103 uses the margin curve of the worst-case pattern of region RG3 as the margin curve for region RG3, as shown in Figure 12(b).
[0120] The simulation device 103 determines whether the process variation amount of the selected region falls within the margin curve region of the selected region (S43).
[0121] For example, if the main regions RG1 and RG2, which have small step differences, are selected as the regions to be processed, the simulation device 103 determines that the process variation amount is within the margin curve region, that is, that the lithography margin is secured, if the rectangular region of the process variation amount falls within the margin curve region, as shown in Figure 12(a).
[0122] When region RG3, which has a moderate step difference, is selected as the region to be processed, the simulation device 103 determines that the process variation amount is within the margin curve region, i.e., the lithography margin is secured, if the rectangular region of the process variation amount falls within the margin curve region, as shown in Figure 12(b).
[0123] If areas RG4 and RG5, which have large step differences, are selected as the processing area, it means that patterns are placed in areas where patterns are not normally placed, so the simulation device 103 can determine that lithography margins are not secured.
[0124] If the layout design device 102 does not have a sufficient lithography margin (No in S43), it returns to S30, calculates the process variation for each of the multiple regions in the next layer (S30), redoes the layout design for the next layer (S31), and modifies the layout data for the next layer.
[0125] For example, the layout design device 102 rearranges patterns that are placed in areas RG4 and RG5 with large step differences to main areas RG1 and RG2 with small step differences, or to area RG3 with moderate step differences.
[0126] After steps S32 to S43 are performed again, the layout design device 102 returns to step S42 if there are any unprocessed areas among the multiple areas in the next layer (Yes in S44), or terminates the process if there are no unprocessed areas (No in S44).
[0127] In the loop processing from S42 to S44, if the process variation amount of at least one of the multiple regions in the next layer falls outside the margin curve region for that region, the loop processing from S30 to S43 is triggered, and the layout data of the next layer is modified.
[0128] On the other hand, in the loop processing of S42-S44, if the amount of process variation in any of the multiple regions in the next layer falls within the margin curve region, the loop processing of S30-S43 is not triggered, and the layout data of the next layer is allowed as is. This makes it possible to allow the coexistence of patterns with different line widths across multiple regions.
[0129] As described above, in the fourth embodiment, the layout creation method determines the process variation amount for each of the multiple regions in the next layer, and selects a margin curve for each of the multiple regions. This makes it possible to individually determine whether the process variation amount falls within the margin curve region, taking into account the step height of each of the multiple regions, and to determine whether or not the lithography margin is secured. As a result, the degree of freedom in layout design can be easily improved, such as by mixing patterns with different line widths between multiple regions.
[0130] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]
[0131] 102 Layout design equipment, 103 Simulation equipment.
Claims
1. Using the layout data of the first layer, the process margin of the second layer to be formed after the first layer is determined, To determine whether the conditions regarding the process margin of the second layer are within an acceptable range, If the above conditions fall outside the acceptable range, the layout data of the first layer shall be changed. A method for creating a layout that includes this.
2. Determining the aforementioned process margin is, This includes determining the CMP (Chemical Mechanical Polishing) margin for the flattening process of the second layer. The method for creating a layout according to claim 1.
3. Determining the CMP margin is To determine the first polishing time at which polishing residue occurs, To determine the second polishing time at which over-polishing occurs, The CMP margin is determined according to the first polishing time and the second polishing time, including The method for creating a layout according to claim 2.
4. The aforementioned determination is, This includes determining whether the CMP margin falls within an acceptable range. The method for creating a layout according to claim 2.
5. Determining the aforementioned process margin is, This includes determining the process variation of the second layer. The method for creating a layout according to claim 1.
6. The aforementioned determination is, This includes determining whether the process variation amount of the second layer falls within the region of the margin curve. The method for creating a layout according to claim 5.
7. The second layer formed after the first layer is classified into multiple regions according to the step map of the first layer, Using the layout data of the second layer, the process variation amount for each of the multiple regions is determined, For each of the aforementioned multiple regions, it is determined whether or not the process variation falls within the region of the margin curve, If, for at least one of the aforementioned multiple regions, the process variation falls outside the margin curve region, the layout data of the second layer is changed. A method for creating a layout that includes this.
8. Creating layout data using the layout creation method described in claim 1, Using the layout data created above, a master copy is created. A method for manufacturing the original plate, including the plate itself.
9. Creating layout data using the layout creation method described in claim 7, Using the layout data created above, a master copy is created. A method for manufacturing the original plate, including the plate itself.
10. Creating layout data using the layout creation method described in claim 1, Using the layout data created above, a master copy is created. The process involves transferring the pattern of the aforementioned master plate onto the substrate, A method for manufacturing a semiconductor device containing [a specific component].
11. Creating layout data using the layout creation method described in claim 7, Using the layout data created above, a master copy is created. The process involves transferring the pattern of the aforementioned master plate onto the substrate, A method for manufacturing a semiconductor device containing [a specific component].