Semiconductor devices and recording devices

Abstract

Because OTP (One Time Programmable) memory, which consists of an antifuse element or a fuse element, lacks a write control function, there is a risk of writing incorrect information due to accidental operation or ESD. [Solution] A memory device having first and second semiconductor memory circuits, each containing a memory element that can be written to only once, characterized in that information stored in the second semiconductor memory circuit is written to the memory element of the first semiconductor memory circuit.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory circuit, and more particularly to a storage device using a one-time programmable non-volatile memory (OTP: One Time Programmable memory) having anti-fuse elements, fuse elements, and the like.

Background Art

[0002] In recent years, semiconductor devices have used OTP (One Time Programmable) memories as storage elements that can be written only once in order to record product-specific information such as chip IDs and setting parameters after the completion of the product. Some OTP memories use fuse elements and anti-fuse elements. As conventional techniques using anti-fuse elements and fuse elements, the configurations of Patent Document 1 and Patent Document 2 are shown.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the storage device described in Patent Document 1, since there is no write protection function for the anti-fuse elements, there is a risk of writing incorrect information due to an incorrect operation.

[0005] Further, in the storage device described in Patent Document 2, since there is no protection circuit for preventing adverse effects on the device due to electrostatic discharge (ESD: Electro-Static Discharge), there is a risk of writing incorrect information due to electrostatic discharge.

[0006] The objective of the present invention is to provide a storage device that prevents erroneous writing to OTP memory due to misoperation or electrostatic discharge. [Means for solving the problem]

[0007] The present invention relates to a memory device having first and second semiconductor memory circuits, each including a memory element that can be written to only once, characterized in that information stored in the second semiconductor memory circuit is written to the memory element of the first semiconductor memory circuit. [Effects of the Invention]

[0008] With the above configuration, it becomes possible to prevent accidental writing to a memory element that can only be written to once due to misoperation or electrostatic discharge. Therefore, it becomes possible to protect the information in the memory element that can only be written to once. [Brief explanation of the drawing]

[0009] [Figure 1A] A diagram showing an example of a semiconductor memory circuit in one embodiment. [Figure 1B] A diagram showing an example of a semiconductor memory circuit in one embodiment. [Figure 1C] A diagram showing an example of a semiconductor memory circuit in one embodiment. [Figure 2A] Diagram showing the read / write operation timing in Embodiment 1. [Figure 2B] Diagram showing the read / write operation timing in Embodiment 1. [Figure 2C] Diagram showing the read / write operation timing in Embodiment 1. [Figure 2D] Diagram showing the read / write operation timing in Embodiment 1. [Figure 2E] Diagram showing the read / write operation timing in Embodiment 1. [Figure 3A] Figure showing an example of a semiconductor memory circuit in the second embodiment. [Figure 3B] Figure showing an example of a semiconductor memory circuit in the second embodiment. [Figure 3C]Figure showing an example of a semiconductor memory circuit in the second embodiment [Figure 3D] Figure showing an example of a semiconductor memory circuit in the second embodiment [Figure 3E] Figure showing an example of a semiconductor memory circuit in the second embodiment [Figure 3F] Figure showing an example of a semiconductor memory circuit in the second embodiment [Figure 3G] Figure showing an example of a semiconductor memory circuit in the second embodiment [Figure 3H] Figure showing an example of a semiconductor memory circuit in the second embodiment [Figure 3I] Figure showing an example of a semiconductor memory circuit in the second embodiment [Figure 4A] Figure showing the read / write operation timing in the second embodiment [Figure 4B] Figure showing the read / write operation timing in the second embodiment [Figure 4C] Figure showing the read / write operation timing in the second embodiment [Figure 4D] Figure showing the read / write operation timing in the second embodiment [Figure 4E] Figure showing the read / write operation timing in the second embodiment [Figure 4F] Figure showing the read / write operation timing in the second embodiment [Figure 4G] Figure showing the read / write operation timing in the second embodiment [Figure 4H] Figure showing the read / write operation timing in the second embodiment [Figure 4I] Figure showing the read / write operation timing in the second embodiment [Figure 4J] Figure showing the read / write operation timing in the second embodiment [Figure 4K] Figure showing the read / write operation timing in the second embodiment [Figure 4L] Figure showing the read / write operation timing in the second embodiment [Figure 4M]Diagram showing the read / write operation timing in the second embodiment. [Figure 5] Figure showing an example of a semiconductor memory circuit in Embodiment 3. [Figure 6] Figure showing an example of a semiconductor memory circuit in Embodiment 4. [Figure 7] Figure showing an example of a semiconductor memory circuit in Embodiment 5. [Figure 8] Figure showing an example of a semiconductor memory circuit in Embodiment 6. [Figure 9] Diagram showing an example of a recording head configuration. [Figure 10] Diagram showing an example of the configuration of a recording device. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described in detail below with reference to the figures.

[0011] (First Embodiment) The first embodiment of the present invention shows a basic circuit configuration in which a fuse element, which is an OTP memory, is used as a memory element that can be written only once, in both the main memory unit and the write protection control unit to the main memory unit. The following explanation will be given with reference to Figures 1A to 1C and Figures 2A to 2E.

[0012] Figures 1A to 1C show the circuit configuration of the first semiconductor device 1, which is a first embodiment of the present invention, and illustrate the change in state when information is written to the fuse element.

[0013] The first semiconductor device 1 of this embodiment includes a first semiconductor memory circuit consisting of a main memory unit 10 having a main memory transistor TN1, a main memory fuse element Fa, a drive voltage conversion element 15 that generates a drive voltage for the main memory transistor TN1, and a node C, and a second semiconductor memory circuit consisting of a protection control unit 18 having a protection control transistor TN2, a protection control fuse element Fb, a drive voltage conversion element 16 that generates a drive voltage for the protection control transistor TN2, and a node D.

[0014] Furthermore, the main memory unit 10 includes a read power terminal VR1, a read power generation circuit 14, a voltage detection node A, a first write voltage terminal VP1, a write control transistor TP1, a transistor control circuit 17 that generates the drive voltage for the write control transistor TP1, and an output voltage detection node E of the transistor control circuit 17. The protection control unit 18 also includes a read power terminal VR2, a read power generation circuit 12, a voltage detection node B, and a write voltage terminal VP2.

[0015] Furthermore, it includes a shift register 13 that generates drive signals for the main memory unit 10 and the protection control unit 18, signals LT, DATA, and CLK that control the shift register, and a ground wire GND.

[0016] In the first semiconductor device 1, which uses a fuse element as memory, information is recorded depending on whether the fuse element is conducting or not, with the conducting state being recorded as unwritten and the non-conducting state as recorded.

[0017] Figures 2A to 2E are time charts showing the operation of each component of the first semiconductor device 1 in chronological order.

[0018] The horizontal axis represents the passage of time, and the vertical axis represents the state of the voltage signal of each element.

[0019] S_Fa indicates whether fuse element Fa is written or not, S_Fb indicates whether fuse element Fb is written or not, the voltage applied to the read power terminal VR1, the voltage applied to the read power terminal VR2, the voltage applied to the first write voltage terminal VP1, the voltage applied to the write voltage terminal VP2, the voltage at node A, the voltage at node B, the voltage at node C, the voltage at node D, the voltage at node E, the ON / OFF state of transistor TN1, the ON / OFF state of transistor TN2, and the ON / OFF state of transistor TP1.

[0020] When fuse elements Fa1 and Fa2 are short-circuited and unwritten, S_Fa1 and S_Fa2 are shown as Low, and when they are open-circuited and written, S_Fa1 and S_Fa2 are shown as High.

[0021] Next, we will explain each operation.

[0022] (1) Reading operation part 1: Initial reading The read operation of fuse element Fa when S_Fa and S_Fb, which have not been written to fuse elements Fa and Fb, are Low will be explained using Figures 1A and 2A.

[0023] First, a read voltage is applied to the read power terminal VR1 of the main memory unit 10. This causes the voltage at node A to go high. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13, setting the output voltage of the drive voltage conversion element 15, which generates the drive voltage for the main memory transistor TN1, to high. This causes the output voltage at node C to also go high. When node C goes high, the main memory transistor TN1 switches ON, and because the fuse element Fa is conducting, the voltage at node A goes low. Then, the voltage at node A is read by a voltage reading circuit (not shown). If the voltage at node A is low, it is determined that it is not written; if it is high, it is determined that it has been written. The fuse element Fa is then determined to be unwritten. After reading the fuse element Fa, signals LT, DATA, and CLK are manipulated to control the shift register 13, setting the output voltage of the drive voltage conversion element 15 to low. This switches transistor TN1 to the OFF state, and the voltage at the read power terminal VR1 is turned OFF.

[0024] In this operation, the write state of the fuse element Fb does not affect the read operation.

[0025] (2) Read operation part 2 Fa written The read operation of fuse element Fa when fuse element Fa is written and S_Fa is High, and fuse element Fb is not written and S_Fb is Low, will be explained using Figures 1B and 2B.

[0026] First, a read voltage is applied to the read power terminal VR1 of the main memory unit 10. This causes the voltage at node A to go high. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13, setting the output voltage of the drive voltage conversion element 15, which generates the drive voltage for the main memory transistor TN1, to high. This also causes the output voltage at node C to go high. When node C goes high, the main memory transistor TN1 switches ON, but because the fuse element Fa is not conducting, the voltage at node A remains high. The voltage at node A is then read by a voltage reading circuit (not shown), and it is determined that the fuse element Fa has been written. After reading the fuse element Fa, signals LT, DATA, and CLK are manipulated to control the shift register 13, setting the output voltage of the drive voltage conversion element 15 to low, turning transistor TN1 OFF, and also turning OFF the voltage at the read power terminal VR1.

[0027] (3) Write operation 1: No write protection The writing operation of fuse element Fa when fuse elements Fa and Fb are unwritten and S_Fa and S_Fb are Low will be explained using Figures 1A and 2C.

[0028] First, the signals LT, DATA, and CLK are manipulated to control the shift register 13, and the output voltage of the drive voltage conversion element 16, which generates the drive voltage for the protection control transistor TN2, is set to High, making the output voltage of node D High, and the read voltage is applied to the read power terminal VR2 of the protection control unit 18. As a result, transistor TN2 turns ON, and because the fuse element Fb is conducting, the voltage at node B remains Low, and node E also remains Low, causing transistor TP1 to switch ON. Next, when the write voltage for the fuse element Fa is applied to the first write voltage terminal VP1, the voltage of the first write voltage terminal VP1 is applied to node A. Then, the signals LT, DATA, and CLK are manipulated to control the shift register 13, and the output voltage of the drive voltage conversion element 15 is set to High, that is, the voltage at node C becomes High, and transistor TN1 turns ON. When transistor TN1 turns ON, a current of 70[mA] or more flows through the fuse element Fa, and the voltage at node A drops to 0[V]. At this time, the fuse element Fa generates heat and eventually melts. Once the fuse element Fa melts and enters the open state (written), current stops flowing through the fuse element Fa and the voltage at node A rises to the voltage at the first write voltage terminal VP1. At this point, S_Fa becomes High when the fuse element Fa is written. After the fuse element Fa is written, the signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 15 to Low, thereby setting the voltage at node C to Low and turning off transistor TN1, thus eliminating the voltage applied to the fuse element Fa. Then, the voltage applied to the read power terminal VR2 and the write voltage terminal VP1 is turned OFF, and transistors TN2 and TP1 are turned OFF.

[0029] By performing this writing operation, the circuit changes from the state shown in Figure 1A to the state shown in Figure 1B, where the fuse element Fa has been programmed.

[0030] (4) Writing operation part 2: Write protection enabled The writing operation of fuse element Fa when fuse element Fa is unwritten and S_Fa is Low, and fuse element Fb is written and S_Fb is High, will be explained using Figures 1C and 2D.

[0031] First, the signals LT, DATA, and CLK are manipulated to control the shift register 13, and the output voltage of the drive voltage conversion element 16, which generates the drive voltage for the protection control transistor TN2, is set to High, making the output voltage of node D High, and the read voltage is applied to the read power terminal VR2 of the protection control unit 18. As a result, transistor TN2 turns ON, and since the fuse element Fb is open, the voltage at node B becomes High, and node E also becomes High, so transistor TP1 switches to the OFF state.

[0032] Subsequently, even if the fuse element write voltage is applied to the write voltage terminal VP1, and signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 15 to High, thereby setting the output voltage of node C to High and turning on transistor TN1, the fuse element Fa cannot be written to because the write voltage is not applied to it. Then, signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 15 to Low, thereby setting the voltage of node C to Low, which turns off transistors TN1 and TN2, and also turns off the application of voltage to the read power supply terminal VR2 and the write voltage terminal VP1.

[0033] Thus, when fuse element Fb is already programmed, no programming voltage is applied to fuse element Fa, thus protecting against programming of fuse element Fa.

[0034] (5) Protected memory write operation The writing operation of fuse element Fb when fuse elements Fa and Fb are unwritten and S_Fa and S_Fb are Low will be explained using Figures 1A and 2E.

[0035] First, when the fuse element writing voltage is applied to the write voltage terminal VP2, the voltage of the write voltage terminal VP2 is applied to node B. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 16 to High, thereby setting the output voltage of node D to High. This turns on transistor TN2. When transistor TN2 turns on, a current of 70[mA] or more flows through the fuse element Fb, and the voltage at node B drops to 0[V]. At this time, the fuse element Fb also heats up and eventually melts. When the fuse element Fb melts and becomes open (written), current stops flowing through the fuse element Fb, and the voltage at node B rises to the voltage of the write voltage terminal VP2. Since the fuse element Fb is now written, S_Fb is set to High. Then, after the fuse element Fb has been written, the signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 16 to Low. As a result, the voltage at node D becomes Low, transistor TN2 turns OFF, and the voltage applied to the fuse element Fb is removed. Then, the voltage applied to the write voltage terminal VP2 is turned OFF.

[0036] By performing this writing operation, the circuit changes from the state shown in Figure 1A to the state shown in Figure 1C, where the fuse element Fb has been written to it.

[0037] As a result, it becomes possible to control the writing of OTP memory in hardware, protecting the written information in OTP memory from accidental operation or ESD-induced writing errors.

[0038] (Second Embodiment) A second embodiment of the present invention shows a basic circuit configuration in which multiple OTP memory fuse elements or antifuse elements are used as memory elements that can be written to only once, in both the main memory unit and the write protection control unit for the main memory unit, and which are controlled to be rewritable. By configuring a rewritable main memory unit using multiple OTP memories in this embodiment, it becomes possible to realize a semiconductor device having a main memory unit in which the write protection control unit can switch between write protection and release protection multiple times, and in which the information can be rewritten.

[0039] A second embodiment of the present invention will be described using Figures 3A to 3I and Figures 4A to 4M.

[0040] Figures 3A to 3I show the circuit configuration of a second semiconductor device 2, which is a second embodiment of the present invention, and illustrate the change in the state in which information is written to the fuse element.

[0041] The second semiconductor device 2 of this embodiment includes a first semiconductor memory circuit comprising a main memory unit 20 having a main memory transistor TN1, a first fuse element Fa1 of the main memory, a second fuse element Fa2 of the main memory, an antifuse element Ca of the main memory, a drive voltage conversion element 15 that generates a drive voltage for the main memory transistor TN1, and a node C, and a second semiconductor memory circuit comprising a write protection control unit 21 having a protection control transistor TN2, a first fuse element Fb1 for protection control, a second fuse element Fb2 for protection control, an antifuse element Cb for protection control, a drive voltage conversion element 16 that generates a drive voltage for the protection control transistor TN2, and a node D.

[0042] Furthermore, the main memory unit 20 includes a read power terminal VR1, a read power generation circuit 14, a voltage detection node A, a first write voltage terminal VP1, a write control transistor TP1, a transistor control circuit 17 that generates the drive voltage for transistor TP1, and an output voltage detection node E of the transistor control circuit 17. The protection control unit 21 also includes a read power terminal VR2, a read power generation circuit 12, a voltage detection node B, and a write voltage terminal VP2.

[0043] Furthermore, it has a shift register 13 that generates drive signals for the main memory unit 20 and the protection control unit 21, signals LT, DATA, and CLK that control the shift register, and a ground wire GND.

[0044] In the second semiconductor device 2, which uses a fuse element as memory, information is recorded depending on whether the fuse element is conducting or not, with the conducting state being marked as unwritten and the non-conducting state being marked as written. Similarly, the antifuse element also records information depending on whether it is conducting or not, with the conducting state being marked as written and the non-conducting state being marked as unwritten.

[0045] Figures 4A to 4M are time charts showing the operation of each component of the second semiconductor device 2 in chronological order.

[0046] The horizontal axis represents the passage of time, and the vertical axis represents the state of the voltage signal of each element.

[0047] S_Fa1 indicates the writing status of fuse element Fa1, S_Fa2 indicates the writing status of fuse element Fa2, S_Fb1 indicates the writing status of fuse element Fb1, S_Fb2 indicates the writing status of fuse element Fb2, S_Ca indicates the writing status of antifuse element Ca, S_Cb indicates the writing status of antifuse element Cb, the voltage applied to the read power terminal VR1, the voltage applied to the read power terminal VR2, the voltage applied to the write voltage terminal VP1, the voltage applied to the write voltage terminal VP2, the voltage at node A, the voltage at node B, the voltage at node C, the voltage at node D, the voltage at node E, the ON / OFF status of transistor TN1, the ON / OFF status of transistor TN2, and the ON / OFF status of transistor TP1.

[0048] When the fuse elements Fa1·Fa2·Fb1·Fb2·Fc1·Fc2 are short-circuited and unwritten, S_Fa1·S_Fa2·S_Fb1·S_Fb2·S_Fc1·S_Fc2 are shown as Low, and when they are open-circuited and written, S_Fa1·S_Fa2·S_Fb1·S_Fb2·S_Fc1·S_Fc2 are shown as High.

[0049] When the antifuse element Ca·Cb is in an open state and not programmed, S_Ca·S_Cb is shown as Low, and when it is in a short-circuit state and programmed, S_Ca·S_Cb is shown as High.

[0050] Next, we will explain each operation.

[0051] (1) Reading operation part 1: Initial reading The read operation of the main memory unit 20 when S_Fa1·S_Fa2·S_Fb1·S_Fb2·S_Ca·S_Cb, which does not contain fuse elements Fa1·Fa2·Fb1·Fb2 and antifuse elements Ca·Cb, is Low will be explained using Figures 3A and 4A.

[0052] First, a read voltage is applied to the read power terminal VR1. This causes the voltage at node A to go high. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 15 to high, causing the output voltage at node C to also go high. When node C goes high, transistor TN1 turns ON, and since fuse element Fa1 is conducting, the voltage at node A goes low. Then, the voltage at node A is read by a voltage reading circuit (not shown). If the voltage at node A is low, it is determined that it has not been written; if it is high, it is determined that it has been written. The main memory unit 20 then determines that it has not been written. After reading by the main memory unit 20, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 15 to low, turning transistor TN1 OFF and turning the voltage at the read power terminal VR1 OFF.

[0053] Note that the write status of the write protection control unit 21 does not affect the read operation of the main memory unit 20, therefore, the fuse elements Fb1 and Fb2 and the antifuse element Cb in Figure 4A are shown with dotted lines.

[0054] (2) Read operation part 2: Fuse element Fa1 has been written The read operation of the main memory unit 20 when fuse element Fa1 is written and S_Fa1 is High, and fuse elements Fa2·Fb1·Fb2 and antifuse elements Ca·Cb are not written and S_Fa2·S_Fb1·S_Fb2·S_Ca·S_Cb are Low will be explained using Figures 3C and 4B.

[0055] First, a read voltage is applied to the read power terminal VR1. This causes the voltage at node A to go high. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 15 to high, causing the output voltage at node C to also go high. When node C goes high, transistor TN1 turns ON, and since fuse element Fa1 is in a non-conductive state, the voltage at node A goes high. Then, the voltage at node A is read by a voltage reading circuit (not shown), and since the voltage at node A is high, it is determined that the data has been written, and the main memory unit 20 determines that the data has been written. After the main memory unit 20 reads the data, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 15 to low, turning transistor TN1 OFF and turning the voltage at the read power terminal VR1 OFF.

[0056] Furthermore, since the write status of the write protection control unit 21 does not affect the read operation of the main memory unit 20, the fuse elements Fb1 and Fb2 and the antifuse element Cb in Figure 4B are shown with dotted lines.

[0057] (3) Read operation part 3: Fuse element Fa1 and antifuse element Ca have been written. The read operation of the main memory unit 20 when fuse element Fa1 and antifuse element Ca have been written to the memory, resulting in S_Fa1·S_Ca being High, and fuse elements Fa2·Fb1·Fb2 and antifuse element Cb have not been written to the memory, resulting in S_Fa2·S_Fb1·S_Fb2·S_Cb being Low, will be explained using Figures 3D and 4C.

[0058] First, a read voltage is applied to the read power terminal VR1. This causes the voltage at node A to go high. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 15 to high, causing the output voltage at node C to also go high. When node C goes high, transistor TN1 turns ON, and because the fuse element Fa2 and antifuse element Ca are conducting, the voltage at node A goes low. Then, the voltage at node A is read by a voltage reading circuit (not shown), and since the voltage at node A is low, the main memory unit 20 determines that the data has been written. After reading from the main memory unit 20, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 15 to low, turning transistor TN1 OFF and turning the voltage at the read power terminal VR1 OFF.

[0059] Note that the write status of the write protection control unit 21 does not affect the read operation of the main memory unit 20, therefore, the fuse elements Fb1 and Fb2 and the antifuse element Cb in Figure 4C are shown with dotted lines.

[0060] (4) Read operation part 4: Fuse elements Fa1 and Fa2 and antifuse element Ca have been written. The read operation of the main memory unit 20 when fuse elements Fa1 and Fa2 and antifuse element Ca have been written to the memory, and S_Fa1, S_Fa2, and S_Ca are High, and fuse elements Fb1 and Fb2 and antifuse element Cb have not been written to the memory, and S_Fb1, S_Fb2, and S_Cb are Low, will be explained using Figures 3F and 4D.

[0061] First, a read voltage is applied to the read power terminal VR1. This causes the voltage at node A to go high. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 15 to high, causing the output voltage at node C to also go high. When node C goes high, transistor TN1 turns ON, and since fuse elements Fa1 and Fa2 are non-conductive, the voltage at node A goes high. Then, the voltage at node A is read by a voltage reading circuit (not shown), and because the voltage at node A is high, the main memory unit 20 determines that the data has been written. After reading by the main memory unit 20, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 15 to low, turning transistor TN1 OFF and turning the voltage at the read power terminal VR1 OFF.

[0062] Note that the write status of the write protection control unit 21 does not affect the read operation of the main memory unit 20, therefore, the fuse elements Fb1 and Fb2 and the antifuse element Cb in Figure 4D are shown with dotted lines.

[0063] (5) Writing operation 1 Fa1 write No write protection With fuse elements Fa1·Fa2·Fb1·Fb2 and antifuse elements Ca·Cb unwritten, and S_Fa1·S_Fa2·S_Fb1·S_Fb2·S_Ca·S_Cb Low, the writing operation of fuse element Fa1 will be explained using Figures 3A and 4E.

[0064] First, the signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 16 to High, making the output voltage of node D High and applying the read voltage to the read power terminal VR2. As a result, transistor TN2 turns ON, and since fuse element Fb1 is conducting, the voltage at node B remains Low, and node E also remains Low, causing transistor TP1 to switch ON. Next, when the fuse element write voltage is applied to the first write voltage terminal VP1, the voltage of the first write voltage terminal VP1 is applied to node A. Then, the signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 15 to High, that is, the voltage at node C becomes High, and transistor TN1 turns ON. When transistor TN1 turns ON, a current of 70[mA] or more flows through fuse element Fa1, and the voltage at node A drops to 0[V]. At this time, fuse element Fa1 also heats up and eventually melts. When fuse element Fa1 melts and enters the open state after being written, S_Fa is set to High, current stops flowing through fuse element Fa1, and the voltage at node A rises to the voltage of the first write voltage terminal VP1. After fuse element Fa1 is written, signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 15 to Low, setting the voltage at node C to Low, which turns off transistor TN1, thus eliminating the voltage applied to fuse element Fa1. Then, the voltage applied to the read power terminal VR2 and the write voltage terminal VP1 is turned off, and transistors TN2 and TP1 are turned off. By performing this writing operation, the circuit changes from the state in Figure 3A to the state in Figure 3C, where fuse element Fa1 has been written.

[0065] (6) Writing operation part 2 Ca writing No write protection The writing operation of antifuse element Ca will be explained using Figures 3C and 4F, assuming that fuse element Fa1 is already written and S_Fa1 is High, and fuse elements Fa2, Fb1, Fb2 and antifuse elements Ca, Cb are not yet written and S_Fa2, S_Fb1, S_Fb2, S_Ca, S_Cb are Low.

[0066] First, signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 16 to High, making the output voltage of node D High and applying the read voltage to the read power terminal VR2. As a result, transistor TN2 turns ON, and because the fuse element Fb1 is conducting, the voltage at node B remains Low, and node E also remains Low, causing transistor TP1 to turn ON. Next, when the antifuse element write voltage is applied to the first write voltage terminal VP1, the voltage of the first write voltage terminal VP1 is applied to node A. Then, signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 15 to High, that is, the voltage at node C to High, causing transistor TN1 to turn ON. When transistor TN1 turns ON, the write voltage terminal VP1 voltage is applied to the antifuse element Ca. Furthermore, signals LT, DATA, and CLK are manipulated to control the shift register 13, setting the output voltage of the drive voltage conversion element 15 to Low, i.e., the voltage at node C to Low, turning off transistor TN1 and releasing the voltage applied to the antifuse element Ca. During antifuse element writing, the operation of applying voltage to the antifuse element for a certain period of time and then releasing the applied voltage is performed at a frequency of approximately 6 MHz, for example, until the antifuse element undergoes a hard breakdown. When the antifuse element Ca undergoes a hard breakdown, a current of approximately 10-30 mA flows, node A drops to the potential of GND, and the writing of the antifuse element Ca is completed. At this time, S_Ca is set to High. After a certain period of time has elapsed, signals LT, DATA, and CLK are manipulated to control the shift register 13, manipulating the output voltages of the drive voltage conversion elements 15 and 16 to Low, turning off transistors TN1 and TN2, and further releasing the voltage applied to the write voltage terminal VP1 and the read power terminal VR2.

[0067] By performing this writing operation, the circuit changes from the state shown in Figure 3C to the state shown in Figure 3D, where the fuse element Fa1 and the antifuse element Ca have been programmed.

[0068] (7) Writing operation 3 Fa2 writing No write protection The writing operation for the antifuse element will be explained using Figures 3D and 4G, assuming that fuse element Fa1 and antifuse element Ca are already programmed, with S_Fa·S_Ca being High, and fuse elements Fa2·Fb1·Fb2 and antifuse element Cb are not programmed, with S_Fa2·S_Fb1·S_Fb2·S_Cb being Low.

[0069] First, the signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 16 to High, making the output voltage of node D High and applying the read voltage to the read power terminal VR2. As a result, transistor TN2 turns ON, and since the fuse element Fb1 is conducting, the voltage at node B remains Low, and node E also remains Low, causing transistor TP1 to switch ON. Next, when the fuse element write voltage is applied to the first write voltage terminal VP1, the voltage of the first write voltage terminal VP1 is applied to node A. Then, the signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 15 to High, that is, the voltage at node C becomes High, and transistor TN1 turns ON. When transistor TN1 turns ON, a current of 70[mA] or more flows through the fuse element Fa2, and the voltage at node A subsequently drops to 0[V]. At this time, the fuse element Fa2 heats up and eventually melts. When the fuse element Fa2 melts and becomes open (written), current stops flowing to the fuse element Fa and the voltage at node A rises to the voltage at the first write voltage terminal VP1. At this time, S_Fa2 is set to High. After the fuse element Fa2 is written, the signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 15 to Low, setting the voltage at node C to Low and turning off transistor TN1, thereby eliminating the voltage applied to the fuse element Fa2. Then, the voltage applied to the read power terminal VR2 and the write voltage terminal VP1 is turned off, and transistors TN2 and TP1 are turned off. By performing this writing operation, the circuit changes from the state shown in Figure 3D to the state shown in Figure 3F, where the fuse element Fa2 has been written.

[0070] (8) Writing operation part 4 Fa1 writing Write protection enabled Figure 4H will explain the writing operation of fuse element Fa1 in the following cases: Figure 3B, where fuse elements Fa1, Fa2, and Fb2 and antifuse elements Ca and Cb are unwritten, with S_Fa1, S_Fa2, S_Fb2, S_Ca, and S_Cb being Low, and only fuse element Fb1 is written, with S_Fb1 being High; or Figure 3G, where fuse elements Fa1 and Fa2 and antifuse element Ca are unwritten, with S_Fa1, S_Fa2, and S_Ca being Low, and fuse elements Fb1, Fb2, and antifuse element Cb are written, with S_Fb1, S_Fb2, and S_Cb being High.

[0071] First, signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 16 to High, thereby setting the output voltage of node D to High and applying the read voltage to the read power terminal VR2. As a result, transistor TN2 turns ON, and since fuse elements Fb1 or Fb2 are in a non-conductive state, the voltage at node B is High, and node E is also High, so transistor TP1 remains OFF and does not switch to the ON state. Therefore, even if the fuse element write voltage is applied to the write voltage terminal VP1, signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 15 to High and switches transistor TN1 ON, the write voltage cannot be applied to the main memory unit 20, and therefore the fuse element Fa1 is not written. Then, by manipulating signals LT, DATA, and CLK, the shift register 13 is controlled to lower the output voltage of the drive voltage conversion elements 15 and 16, thereby lowering the voltage of nodes C and D, which turns off transistors TN1 and TN2, and also turns off the voltage applied to the read power terminal VR2 and the write voltage terminal VP1.

[0072] Thus, if fuse element Fb1 is already programmed as shown in Figure 3B, or if fuse elements Fb1 and Fb2 are already programmed as shown in Figure 3G, then fuse element Fa1 becomes unprogrammable, thus protecting the information.

[0073] (9) Writing operation part 5 Ca writing Write protection enabled In the case of Figure 3H, where fuse elements Fa2·Fb2 and antifuse elements Ca·Cb are unwritten, S_Fa2·S_Fb2·S_Ca·S_Cb are Low, and fuse elements Fa1·Fb1 are written, S_Fa1·S_Fb1 are High, the writing operation of fuse element Fa1 will be explained using Figure 4I.

[0074] First, signals LT, DATA, and CLK are manipulated to control the shift register 13, which changes the output voltage of the drive voltage conversion element 16 to High, thereby setting the output voltage of node D to High and applying the read voltage to the read power terminal VR2. As a result, transistor TN2 turns ON, and since fuse element Fb1 is in a non-conductive state, the voltage at node B becomes High, and node E also becomes High, preventing transistor TP1 from switching from the OFF state to the ON state. Therefore, even if the fuse element write voltage is applied to the write voltage terminal VP1, the write voltage cannot be applied to the main memory unit 20. Consequently, even if signals LT, DATA, and CLK are manipulated to control the shift register 13 and periodically change the output voltage of the drive voltage conversion element 15 from High to Low, thereby changing transistor TN1 from ON to OFF, it is not possible to write to the anti-fuse element Ca. Then, by manipulating signals LT, DATA, and CLK, the shift register 13 is controlled to lower the output voltage of the drive voltage conversion elements 15 and 16, thereby lowering the voltage of nodes C and D, which turns off transistors TN1 and TN2, and also turns off the voltage applied to the read power terminal VR2 and the write voltage terminal VP1.

[0075] In this way, when the fuse element Fb1 is already written to, the antifuse element Ca becomes unwriteable, thus protecting the information.

[0076] Furthermore, even when writing is performed to the fuse elements Fb1 and Fb2 (not shown) and the antifuse element Cb, the write voltage cannot be applied to the main memory unit 20, thus protecting the antifuse element Ca from being written.

[0077] (10) Writing operation 6 Fa2 writing Write protection enabled In the case shown in Figure 3I, where fuse elements Fa2 and Fb2 and antifuse element Cb are unwritten and S_Fa1, Fb1, and S_Cb are Low, and only fuse elements Fa1 and Fb1 are written and S_Fa1 and S_Fb1 are High, the writing operation of fuse element Fa2 will be explained using Figure 4J.

[0078] First, signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 16 to High, making the output voltage of node D High, and applying the read voltage to the read power terminal VR2. As a result, transistor TN2 turns ON, and since fuse element Fb1 is in a non-conductive state, the voltage at node B is High, and node E is also High, so transistor TP1 remains OFF and does not switch to the ON state. Therefore, even if the fuse element write voltage is applied to the write voltage terminal VP1, signals LT, DATA, and CLK are manipulated to control the shift register 13, which sets the output voltage of the drive voltage conversion element 15 to High, and transistor TN1 is turned ON, the write voltage cannot be applied to the main memory unit 20, and therefore the fuse element Fa2 is not written. Then, by manipulating signals LT, DATA, and CLK, the shift register 13 is controlled to lower the output voltage of the drive voltage conversion elements 15 and 16, thereby lowering the voltage of nodes C and D, which turns off transistors TN1 and TN2, and also turns off the voltage applied to the read power terminal VR2 and the write voltage terminal VP1.

[0079] In this way, if fuse element Fb1 is already written to, fuse element Fa2 becomes unwriteable, thus protecting the information.

[0080] Furthermore, even when writing is performed to the fuse elements Fb1 and Fb2 (not shown) and the antifuse element Cb, a write voltage cannot be applied to the main memory unit 20, making it impossible to write to the fuse element Fb2, thereby protecting the information.

[0081] (11) Protected memory writing operation part 1: Fb1 writing The writing operation of fuse element Fb1 when fuse elements Fa1·Fa2·Fb1·Fb2 and antifuse elements Ca·Cb are unwritten and S_Fa1·S_Fa2·S_Fb1·S_Fb2·S_Ca·S_Cb are Low will be explained using Figures 3A and 4K.

[0082] First, when the fuse element writing voltage is applied to the write voltage terminal VP2, the voltage of the write voltage terminal VP2 is applied to node B. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 16 to High, thereby setting the output voltage of node D to High. This turns on transistor TN2. When transistor TN2 turns on, a current of 70[mA] or more flows through the fuse element Fb1, causing the voltage at node B to drop to 0[V]. At this time, the fuse element Fb1 also heats up and eventually melts. Once the fuse element Fb1 melts and becomes open (written), current stops flowing through the fuse element Fb1, and the voltage at node B rises to the voltage of the write voltage terminal VP2. After the fuse element Fb1 is written, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 16 to Low. At this point, S_Fb1 becomes High because the fuse element Fb1 has been written to. As a result, the voltage at node D becomes Low, transistor TN2 turns OFF, and the voltage applied to fuse element Fb1 is removed. Then, the voltage applied to the write voltage terminal VP2 is also turned OFF.

[0083] By performing this writing operation, the circuit changes from the state shown in Figure 3A to the state shown in Figure 3B, where the fuse element Fb1 has been written to.

[0084] In this way, by writing the fuse element Fb1, the transistor TP1 will not turn ON, the voltage at the write voltage terminal VP1 will not be applied to the main memory unit 20, the main memory unit 20 will become unwriteable, and the information can be protected.

[0085] (12) Protected memory writing operation part 2: Cb writing The writing operation of fuse element Cb when fuse elements Fa1·Fa2·Fb2 and antifuse elements Ca·Cb are unwritten and S_Fa1·S_Fa2·S_Fb2·S_Ca·S_Cb are Low will be explained using Figures 3B and 4L.

[0086] First, when the antifuse element write voltage is applied to the write voltage terminal VP2, the write voltage of the write voltage terminal VP2 is applied to node B. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 16 to High, thereby setting the output voltage of node D to High. This turns on transistor TN2. When transistor TN2 turns on, the voltage of the write voltage terminal VP2 is applied to the antifuse element Cb. Furthermore, signals LT, DATA, and CLK are manipulated to control the shift register 13 and set the output voltage of the drive voltage conversion element 16 to Low, that is, the voltage at node D to Low, turning off transistor TN2 and releasing the voltage applied to the antifuse element Cb. In writing to the antifuse element, the operation of applying voltage to the antifuse element for a certain period of time and then releasing the applied voltage is performed at a frequency of, for example, about 6 [MHz] until the antifuse element hard breaks down. When the antifuse element Cb hard-breaks down, a current of about 10-30 mA flows, the potential of node B drops to GND, and the writing of the antifuse element Cb is completed. With the antifuse element Cb written, S_Cb becomes High. After a certain period of time has elapsed, the signals LT, DATA, and CLK are manipulated to control the shift register 13, which lowers the output voltage of the drive voltage conversion element 16 to Low, turning off transistor TN2, and further releasing the voltage applied to the write voltage terminal VP2.

[0087] By performing this writing operation, the circuit changes from the state shown in Figure 3B to the state shown in Figure 3E, where the antifuse element Cb has been written to it.

[0088] By programming the fuse element Fb1 and the antifuse element Cb, the transistor TP1 turns ON, the voltage of the write voltage terminal VP1 is applied to the main memory unit 20, and writing to the main memory unit 20 becomes possible.

[0089] (13) Protected memory writing operation part 3: Fb2 writing The writing operation of the antifuse element Cb when the fuse elements Fa1·Fa2·Fb1·Fb2 and the antifuse element Ca are unwritten and S_Fa1·S_Fa2·S_Fb1·S_Fb2·S_Ca are Low will be explained using Figures 3E and 4M.

[0090] First, when the fuse element writing voltage is applied to the write voltage terminal VP2, the voltage of the write voltage terminal VP2 is applied to node B. Next, signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 16 to High, thereby making the output voltage of node D High. Then, transistor TN2 turns ON. When transistor TN2 turns ON, a current of 70[mA] or more flows through the fuse element Fb1, and the voltage at node B drops to 0[V]. At this time, the fuse element Fb2 also heats up and eventually melts. When the fuse element Fb2 melts and becomes open (written), current stops flowing through the fuse element Fb2, and the voltage at node B rises to the voltage of the write voltage terminal VP2. Because the fuse element Fb2 is now written, S_Fb2 becomes High. Then, after the fuse element Fb2 has been written, the signals LT, DATA, and CLK are manipulated to control the shift register 13 and manipulate the output voltage of the drive voltage conversion element 16 to Low. As a result, the voltage at node D becomes Low, transistor TN2 turns OFF, and the voltage applied to the fuse element Fb2 is removed. Then, the voltage applied to the write voltage terminal VP2 is turned OFF.

[0091] By performing this writing operation, the circuit changes from the state shown in Figure 3E to the state shown in Figure 3G, where the fuse element Fb2 has been written to.

[0092] By writing the fuse elements Fb1 and Fb2 and the antifuse element Cb, and setting S_Fb1, Fb2, and S_Cb to High, the transistor TP1 will not switch ON, the voltage at the write voltage terminal VP1 will not be applied to the main memory unit 20, making the main memory unit 20 unwriteable and protecting the information.

[0093] In this embodiment, the main memory unit 20 and the write protection control unit 21 are configured with one antifuse element and two fuse elements. However, if you want to change the number of rewrite cycles or the number of rewrite protection cycles, you can change the number of antifuse elements and fuse elements in the main memory unit 20 and the write protection control unit 21.

[0094] As a result, it becomes possible to control the writing of OTP memory in hardware, making it impossible to write to the OTP memory due to accidental operation or ESD, thereby protecting the information.

[0095] (Third embodiment) A third embodiment of the present invention shows a basic circuit configuration in which one antifuse element, which is an OTP memory, is used as a memory element that can be written to only once in the main memory unit, and one fuse element, which is also an OTP memory, is used in the write protection control unit.

[0096] A third embodiment of the present invention will be described below with reference to Figure 5.

[0097] Figure 5 shows the circuit configuration of a third semiconductor device 3, which is a third embodiment of the present invention, and illustrates the state before information is written to the antifuse element and fuse element.

[0098] The semiconductor device 3 of this embodiment includes a first semiconductor memory circuit consisting of a main memory unit 30 having a transistor TN1, an antifuse element Ca, a drive voltage conversion element 15 that generates a drive voltage for transistor TN1, and a node C, and a second semiconductor memory circuit consisting of a protection control unit 18 having a transistor TN2, a fuse element Fb, a drive voltage conversion element 16 that generates a drive voltage for transistor TN2, and a node D.

[0099] Furthermore, the main memory unit 30 has a read power terminal VR1, a read power generation circuit 14, a voltage detection node A, a write voltage terminal VP1, a write control transistor TP1, a transistor control circuit 17 that generates the drive voltage for transistor TP1, and a voltage output detection node E of the transistor control circuit 17. Furthermore, the protection control unit 18 has a read power terminal VR2, a read power generation circuit 12, a voltage detection node B, a write voltage terminal VP2, a shift register 13 that generates drive signals for the memory unit 30 and the protection control unit 18, signals LT, DATA, and CLK that control the shift register, and a ground wire GND.

[0100] In the fourth semiconductor device 4, which uses an antifuse element as memory, information is recorded depending on whether the antifuse element is conductive or non-conductive. If it is non-conductive, it is considered unwritten, and if it is conductive, it is considered written.

[0101] In this embodiment, if the fuse element Fb1 is already programmed, it is possible to protect against writing to the antifuse element Ca.

[0102] As a result, it becomes possible to control the writing of OTP memory in hardware, protecting the written information in OTP memory from accidental operation or ESD-induced writing errors.

[0103] (Fourth embodiment) A fourth embodiment of the present invention shows a basic circuit configuration in which one antifuse element, which is an OTP memory, is used in both the main memory unit and the write protection control unit to the main memory unit, as a memory element that can be written only once.

[0104] A fourth embodiment of the present invention will be described below with reference to Figure 6.

[0105] Figure 6 shows the circuit configuration of the fourth semiconductor device 4, which is a fourth embodiment of the present invention, and illustrates the change in state before information is written to the antifuse element.

[0106] The fourth semiconductor device 4 of this embodiment includes a first semiconductor memory circuit consisting of a transistor TN1, an antifuse element Ca·Cb, a drive voltage conversion element 15 that generates a drive voltage for transistor TN1, and a memory unit 30 having node C; and a second semiconductor memory circuit consisting of a transistor TN2, a fuse element Fb, a drive voltage conversion element 16 that generates a drive voltage for transistor TN2, and a protection control unit 31 having node D.

[0107] Furthermore, the main memory unit 10 includes a read power terminal VR1, a read power generation circuit 14, a voltage detection node A for the main memory unit 10, a write voltage terminal VP1 for the main memory unit 10, a write control transistor TP1 for the main memory unit 10, a drive voltage conversion element 33 that generates a drive voltage for transistor TP1, a voltage output detection node E for the drive voltage conversion element 33, a read power terminal VR2 for the protection control unit 31, a read power generation circuit 12 for the protection control unit 31, and a voltage detection node B for the protection control unit 31.

[0108] Furthermore, the protection control unit 18 has a write voltage terminal VP2, a shift register 13 that generates drive signals for the memory unit 30 and the protection control unit 18, signals LT, DATA, and CLK that control the shift register, and a ground wire GND.

[0109] In the fourth semiconductor device 4, which uses an antifuse element as memory, information is recorded depending on whether the antifuse element is conductive or non-conductive. If it is non-conductive, it is considered unwritten, and if it is conductive, it is considered written.

[0110] In this embodiment, if the antifuse element Cb is already programmed, it is possible to protect against writing to the antifuse element Ca.

[0111] (Fifth embodiment) A fifth embodiment of the present invention shows a basic circuit configuration comprising a plurality of main memory units, each having both a region with write protection functionality and a region without write protection functionality.

[0112] The above write protection function is implemented by a write protection control unit configured to be rewritable, that is, to allow multiple switching between write protection and protection release, using multiple fuse elements or antifuse elements, which are OTP memories, as memory elements that can be written to only once.

[0113] The main memory unit is configured to be rewritable, meaning that the stored information can also be rewritten, by using multiple fuse elements or antifuse elements, which are also OTP memories.

[0114] By providing a main memory area with write protection and a main memory area without write protection, it becomes possible to limit the main memory area that requires write protection, thereby preventing cost increases due to the increased circuit size of the semiconductor device.

[0115] A fifth embodiment of the present invention is illustrated in Figure 7.

[0116] Figure 7 shows the circuit configuration of the fifth semiconductor device 5, which is the fifth embodiment of the present invention, and illustrates the state before information is written to the fuse element and the antifuse element.

[0117] The fifth semiconductor device 5 of this embodiment includes a transistor TN1, a fuse element Fa1, a fuse element Fa2, an antifuse element Ca, a drive voltage conversion element 15 that generates a drive voltage for transistor TN1, and a plurality of main memory units 20 having nodes C. A write protection control unit 21 having a transistor TN2, a fuse element Fb1, a fuse element Fb2, a drive voltage conversion element 16 that generates a drive voltage for transistor TN2, and a node D. A transistor TN3, a fuse element Fc1, a fuse element Fc2, an antifuse element Cc, a drive voltage conversion element 19 that generates a drive voltage for transistor TN3, and multiple memory units 22 having node F, The main memory unit 20's read power terminal VR1, the main memory unit 20's read power generation circuit 14, the main memory unit 20's voltage detection node A, the main memory unit 20's write voltage terminal VP1, the main memory unit 20's write control transistor TP1, the transistor control circuit 17 that generates the drive voltage for transistor TP1, the transistor control circuit 17's output voltage detection node E, the write protection control unit 21's read power terminal VR2, the write protection control unit 21's read power generation circuit 12, the write protection control unit 21's voltage detection node B, the write protection control unit 21's write voltage terminal VP2, The read power terminal VR3 of the memory unit 22, the read power generation circuit 25 of the memory unit 22, the voltage detection node G of the memory unit 22, the write voltage terminal VP3 of the memory unit 22, The fifth semiconductor device 5 has a shift register 13 that generates drive signals for the main memory unit 20, the write protection control unit 21, and the memory unit 22, as well as signals LT, DATA, and CLK that control the shift register, and a ground wire GND. In the fifth semiconductor device 5, which uses fuse elements and antifuse elements as memory, information is recorded depending on whether the fuse elements and antifuse elements are conducting or not. For the fuse elements, the conducting state is considered unwritten, and the non-conducting state is considered written. For the antifuse elements, the conducting state is considered written, and the non-conducting state is considered unwritten.

[0118] In this embodiment, the main memory unit 20 has a write protection function that stores information on whether or not to protect writing based on the state of the write protection control unit 21, while the memory unit 22 does not have a write protection function.

[0119] As a result, it becomes possible to control the writing of OTP memory in hardware, protecting the written information in OTP memory from accidental operation or ESD-induced writing errors.

[0120] (Sixth embodiment) In this embodiment, as an example of applying the semiconductor devices 1 to 5 described in Embodiments 1 to 5, an example in which the fifth semiconductor device 5 is applied to a recording device will be described.

[0121] Figure 8 shows an example of a control circuit of a recording device 900, which consists of a circuit configuration of a liquid ejection recording element substrate 100 having the fifth semiconductor device 5 described in the fifth embodiment, a circuit configuration of a recording device control board 930 that controls the liquid ejection recording element substrate 100, and a carriage substrate 922 that transfers power and signals from the recording device control board 930 to the liquid ejection recording element substrate 100.

[0122] The recording device control board 930 includes a power generation circuit 931, a recording device control circuit 932, a VDD control element 933, a VH control element 934, a VHT control element 935, a VR1 control element 936, a VP1 control element 937, a VR2 control element 938, a VP2 control element 939, a VR3 control element 940, and a VP3 control element 941.

[0123] The power generation circuit 931 provides the following necessary for operating the recording device 900: a first power supply voltage VDD, a second power supply voltage VH, a third power supply voltage VHT, a fourth power supply voltage VR1, a fifth power supply voltage VP1, a sixth power supply voltage VR2, a seventh power supply voltage VP2, an eighth power supply voltage VR3, a ninth power supply voltage VP3, and a ground potential GND.

[0124] The recording device control circuit 932 is a control circuit that controls the recording device 900, and controls the clock signal CLK, image data signal DATA, latch signal LT, and recording element control signal HE that control the liquid ejection recording element substrate 100, the VDD control element 933 that controls the output of the first power supply voltage VDD, the VH control element 934 that controls the output of the second power supply voltage VH, the VHT control element 935 that controls the output of the third power supply voltage VHT, the VR1 control element 936 that controls the output of the fourth power supply voltage VR1, the VP1 control element 937 that controls the output of the fifth power supply voltage VP1, the VR2 control element 938 that controls the output of the sixth power supply voltage VR2, the VP2 control element 939 that controls the output of the seventh power supply voltage VP2, the VR3 control element 940 that controls the output of the eighth power supply voltage VR3, and the VP3 control element 941 that controls the output of the ninth power supply voltage VP3.

[0125] The carriage substrate 922 is a substrate that electrically connects signals and power between the liquid ejection recording element substrate 100 and the recording device control substrate 930.

[0126] The liquid ejection recording element substrate 100 includes a recording unit 101, a recording element control circuit 103a, a memory control circuit 103b, a step-down circuit 107, a memory unit 112, a write protection control unit 113, a memory unit 114, a first power supply voltage VDD input terminal and wiring circuit VDD, a second power supply voltage VH input terminal and wiring circuit VH, a third power supply voltage VHT input terminal and wiring circuit VHT, a fourth power supply voltage VR1 input terminal and wiring, a read power generation circuit 14 that generates a read power supply based on the fourth power supply voltage VR1, a fifth power supply voltage VP1 input terminal and wiring, and a sixth power supply voltage VR2 input terminal and wiring. The unit includes a read power generation circuit 12 that generates a read power supply based on the sixth power supply voltage VR2, a seventh power supply voltage VP2 input terminal and wiring, an eighth power supply voltage VR3 input terminal and wiring, a read power generation circuit 25 that generates a read power supply based on the eighth power supply voltage VR3, a ninth power supply voltage VP3 input terminal and wiring, a transistor TP1 that controls the application of the fifth power supply voltage VP1 to the memory unit 112, a transistor control circuit 17 that controls the transistor TP1 in the state of the write protection control unit 113, node A, node B, a ground wiring GND connection terminal and ground wiring GND.

[0127] The step-down circuit 107 is a power supply circuit that reduces the voltage of the third power supply voltage VHT to generate the tenth power supply voltage VHTM.

[0128] The memory unit 112 includes a transistor TN1, a logical AND circuit 109 for driving transistor TN1, fuse elements Fa1 and Fa2, an antifuse element Ca, and a node C. In this embodiment, the case with three memory units 112 is shown, but it is also possible to use three or more.

[0129] It includes a transistor TN2, a logical AND circuit 109 for driving transistor TN2, fuse elements Fb1 and Fb2, an antifuse element Cb, and node D. In this embodiment, the case where there is one write protection control unit 113 is shown, but it is also possible to provide multiple units.

[0130] The write protection control unit 113 includes a transistor TN3, a logical AND circuit 109 for driving transistor TN3, fuse elements Fc1 and Fc2, an antifuse element Cc, and a node F. In this embodiment, the case of three write protection control units 113 is shown, but it is also possible to use three or more units.

[0131] Furthermore, the recording unit 101 includes a recording element (electric thermal conversion element, heater, piezoelectric element) Rh and a drive unit (for example, a transistor TN4 and a logical AND circuit) that drives the recording element Rh. By driving the recording element Rh, that is, by energizing the recording element Rh and generating heat, the recording material is ejected from the ejection port, and recording can be performed. In this embodiment, the case of four recording units 101 is shown, but it is also possible to use four or more units.

[0132] The recording element control circuit 103a and the memory control circuit 103b can be configured, for example, by a shift register or latch circuit (not shown). The recording element control circuit 103a and the memory control circuit 103b may receive a clock signal CLK, image data signal DATA, latch signal LT, and heater control signal HE from the recording device control circuit 932 via a host PC (not shown). In addition, a tenth power supply voltage VHTM (e.g., 3-5V) is supplied to the logical AND gates 108 and 109, as well as the recording element control circuit 103a and the memory control circuit 103b, as the power supply voltage for driving the transistors. Thus, the recording element Rh of the recording unit 101 and the memory unit 102 (semiconductor device) are electrically connected to the recording element control circuit 103a, respectively.

[0133] Here, the recording element control circuit 103a can, for example, perform time-division driving to drive the recording element Rh by controlling the operation of the recording units 101 for each of m groups, each having n recording units 101. Time-division driving can be performed by the recording element control circuit 103a outputting an m-bit block selection signal 104 and an n-bit time-division selection signal 105.

[0134] The AND gate 108 receives the corresponding block selection signal 104 and time-division selection signal 105, which in turn cause transistor TN4 to conduct, driving the recording element Rh connected in series with transistor TN4. Here, the recording unit 101 is supplied with a second power supply voltage VH (e.g., 24V) as the power supply voltage for driving the recording element, and the ground potential is set to GND.

[0135] The AND gate 109 receives the control signal 106 and the time-division selection signal 105 as inputs, and the corresponding signals are output to transistors TN1, TN2, and TN3, switching between the conduction and non-conduction states of transistors TN1, TN2, and TN3.

[0136] The liquid ejection recording element substrate 100 includes a fourth power supply voltage VR1 (for example, 3.3V) for reading information from the memory unit 112, and a read power supply generation circuit 14 that generates a read power supply for the memory unit 112 based on the power supply voltage VR1. A sixth power supply voltage VR2 (e.g., 3.3V) for reading information from the write protection control unit 113, and a read power supply generation circuit 12 that generates a read power supply for the write protection control unit 113 based on the power supply voltage VR2, An eighth power supply voltage VR3 (for example, 3.3V) for reading information from the memory unit 114, and a read power supply generation circuit 25 that generates a read power supply for the memory unit 114 based on the power supply voltage VR3, A fifth power supply voltage VP1 (e.g., 24.0V) for writing information to the memory unit 112, a seventh power supply voltage VP2 (e.g., 24.0V) for writing information to the write protection control unit 113, and a ninth power supply voltage VP3 (e.g., 24.0V) for writing information to the memory unit 114 are supplied, and the ground potential is set to GND.

[0137] Figure 9 is a perspective view of a liquid ejection recording head 810, which can be mounted on a recording device as a liquid ejection head unit. The recording element substrate 813, which serves as the liquid ejection head on the liquid ejection recording head 810, is electrically connected to a contact pad 815 that connects to the recording device via a flexible film wiring substrate 814. In Figure 9, the liquid ejection recording head 810 has a configuration in which the recording element substrate 813 and the ink tank 812 are integrated, but it can also be a separate type in which the ink tank can be separated.

[0138] The liquid ejection recording head 810 receives electrical signals from the carriage substrate 922 mounted on the carriage 920 (Figure 10) via a contact pad 815, and ejects ink according to the electrical signals to perform the recording described above. The ink tank 812 has, for example, a fibrous or porous ink retaining material (not shown), and can hold ink with this ink retaining material.

[0139] Figure 10 shows a bird's-eye view of the recording device 900. The liquid ejection recording head 810 is the liquid ejection recording head partially shown in Figure 9 and can be mounted on the carriage 920. The carriage 920 can be attached to a lead screw 904 having a helical groove 921. By rotating the lead screw 904, the liquid ejection recording head 810 can move along the guide 919 in the direction of arrow a or arrow b together with the carriage 920. The rotation of the lead screw 904 is linked to the rotation of the drive motor 901 via drive force transmission gears 902 and 903.

[0140] The recording paper P, which is the recording medium, can be transported onto the platen 906 by a transport unit (not shown). The paper press plate 905 can press the recording paper P against the platen 906 along the carriage movement direction. The recording device 900 can check the position of levers provided on the carriage 920 via photocouplers 907 and 908 and switch the rotation direction of the drive motor 901, etc. The support member 910 can support cap members 911 that cap each nozzle of the liquid ejection recording head 810. The suction means 912 can suck the inside of the cap member 911 and perform a suction recovery process of the liquid ejection recording head 810 through the cap opening 913.

[0141] A well-known cleaning blade is used for the cleaning blade 914, and a moving member 915 can move the cleaning blade 914 in the front-rear direction. A main body support plate 916 can support the moving member 915 and the cleaning blade 914. A lever 917 may be provided to start the suction recovery process.

[0142] As the cam 918, which engages with the carriage 920, moves, the lever 917 moves. The driving force from the drive motor 901 can be controlled by known transmission means such as clutch switching. The recording device 900 is provided with a recording control unit (not shown), and the recording device 900 can control the drive of each mechanism according to electrical signals such as recording data from an external source. The recording device 900 can complete recording on the recording paper P by repeatedly moving the liquid ejection recording head 810 back and forth and transporting the recording paper P by a transport unit (not shown).

[0143] As a result, it becomes possible to control the writing of OTP memory in hardware, protecting the written information in OTP memory from accidental operation or ESD-induced writing errors. [Explanation of Symbols]

[0144] 1. First Semiconductor Device 10 Main memory units 17. Drive voltage conversion element 18 Write Protection Control Unit 100 Liquid Discharge Recording Element Substrate 810 Liquid Discharge Recording Head 900 Recording device VP1 Main memory unit write voltage terminal VP2 Protection Control Unit Write Voltage Terminal VR1 Main memory unit read power terminal VR2 Protection Control Unit Read Power Terminal

Claims

1. A memory device having first and second semiconductor memory circuits including a memory element that can be written to only once, A memory device characterized by writing information stored in the second semiconductor memory circuit to a memory element of the first semiconductor memory circuit.

2. A first write voltage terminal for applying a write voltage to the first semiconductor memory circuit, A transistor that controls the application of the write voltage, connecting the first semiconductor memory circuit and the first write voltage terminal, A transistor control circuit that writes to the memory elements of the first semiconductor memory circuit by switching between a conductive state and a non-conductive state between the first semiconductor memory circuit and the first write voltage terminal based on the information stored in the second semiconductor memory circuit, The storage device according to claim 1, characterized by comprising:

3. The memory device according to claim 2, characterized in that it protects the information stored in the first semiconductor memory circuit by making it unwriteable based on the information stored in the second semiconductor memory circuit.

4. The storage device according to claim 2, characterized in that the first semiconductor memory circuit is a main memory unit that mainly holds information to be stored, and the second semiconductor memory circuit is a write protection control unit for the main memory unit that changes the state of the main memory unit to make the information writable or unwritable.

5. The memory device according to claim 2, wherein the first semiconductor memory circuit includes a plurality of memory elements, and the information stored in the first semiconductor memory circuit is rewritable.

6. The memory device according to claim 2, wherein the second semiconductor memory circuit includes a plurality of memory elements, and the information stored in the second semiconductor memory circuit is rewritable.

7. The memory device according to any one of claims 1 to 6, characterized in that the memory element that can be written to only once is a fuse element or an antifuse element.

8. In the second semiconductor memory circuit, the plurality of memory elements include first and second fuse elements and one antifuse element. The memory device according to claim 6, characterized in that by writing to the first fuse element, the antifuse element, and the second fuse element in that order, the information stored in the second semiconductor memory circuit is rewritten, and the information stored in the first semiconductor memory circuit is made rewritable or protected from being rewritten.

9. The memory device according to claim 1, characterized by comprising a plurality of the first or second semiconductor memory circuits.

10. Based on the information stored in the second semiconductor memory circuit, the first semiconductor memory circuit protects the stored information so that it can be rewritten or not rewritten, The first semiconductor memory circuit writes to the memory element without relying on the information stored in the second semiconductor memory circuit, The storage device according to claim 9, characterized by comprising:

11. A liquid ejection recording element substrate comprising a storage device as described in claim 1 and a recording element that ejects liquid.

12. A liquid ejection recording head characterized by comprising a recording element substrate as described in claim 10 and an ejection port for ejecting liquid.

13. A recording device comprising a liquid discharge recording head as described in claim 11 and a mechanism for transporting a recording medium.

Images