Digital-to-analog converter
The DAC enhances linearity by using conversion and compensation current units with amplification and current mirroring to address impedance variations, achieving improved performance at reduced costs.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- GLOBAL UNICHIP CORPORATION
- Filing Date
- 2025-01-08
- Publication Date
- 2026-06-05
AI Technical Summary
Digital-to-analog converters (DACs) suffer from deteriorating linearity due to varying equivalent output impedance, which affects their performance.
The DAC incorporates a plurality of conversion current units, a compensation current unit, a first amplification circuit, and a current source circuit, utilizing differential switch pairs, multilayer transistors, and current source transistors to enhance output impedance and improve linearity through gain boosting and current mirroring.
The solution effectively increases output impedance at a lower cost, thereby improving the linearity of the digital-to-analog converter.
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Figure 2026092637000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter having a compensation current unit.
Background Art
[0002] A digital-to-analog converter (DAC) is a device that converts a digital signal into an analog signal so that the digital signal can be externally identified. In this digital age, it can be said that a DAC is one of the essential components of various electronic devices. However, since a digital-to-analog converter is affected by the varying equivalent output impedance of its output terminal, there is a risk that its linearity deteriorates.
Summary of the Invention
[0003] The embodiment of the present disclosure is a digital-to-analog converter. The digital-to-analog converter includes a plurality of conversion current units, a compensation current unit, a first amplification circuit, and a current source circuit. Each conversion current unit includes a first differential switch pair, a first multilayer transistor, and a first current source transistor. The first differential switch pair is controlled by a first control signal and a first inverse control signal. The first multilayer transistor and the first current source transistor are connected in series with each other and are connected to the first differential switch pair. The compensation current unit includes a second differential switch pair, a second multilayer transistor, and a second current source transistor. The second differential switch pair is controlled by a second control signal. The second multilayer transistor and the second current source transistor are connected in series with each other and are connected to the second differential switch pair, the gate of the second current source transistor being connected to the gate electrode of the first current source transistor. The input terminal of the first amplifier circuit is connected to the source of the second multilayer transistor, and the output terminal of the first amplifier circuit is connected to the gate of the second multilayer transistor and the gate of the first multilayer transistor, respectively. The current source circuit is connected to the second current source transistor to form a current mirror, and is also connected to the first current source transistor to form a current mirror. [Brief explanation of the drawing]
[0004] The contents of this disclosure can be better understood by referring to the following drawings and reading the detailed description of the following embodiments. [Figure 1A] This is a schematic circuit diagram of a digital-to-analog converter based on several embodiments of the present disclosure. [Figure 1B] This is a schematic circuit diagram of a digital-to-analog converter based on several embodiments of the present disclosure. [Figure 1C] This is a schematic circuit diagram of a single-sided output structure within a portion of a digital-to-analog converter based on several embodiments of the present disclosure. [Figure 2A] This is a schematic circuit diagram of a digital-to-analog converter based on several embodiments of the present disclosure. [Figure 2B] This is a schematic circuit diagram of a digital-to-analog converter based on several embodiments of the present disclosure. [Modes for carrying out the invention]
[0005] The following provides a detailed explanation combining examples and drawings. However, the specific examples described are for interpretation purposes only and do not limit this disclosure. Furthermore, descriptions of structure and operation do not restrict the order of their execution. Any device having equivalent effects resulting from a rearrangement of any of the elements is covered by this disclosure.
[0006] Unless otherwise specified, the terms used in the entire specification and in the claims generally have their general meanings as used in this art, the content disclosed herein, and the specific content.
[0007] As used in this text, "connection" or "linking" can refer to two or more elements making direct physical or electrical contact with each other, or to two or more elements making indirect physical or electrical contact with each other, or to two or more elements operating or acting on each other.
[0008] Referring to Figure 1A, Figure 1A is a schematic circuit diagram of a digital-to-analog converter 100A based on several embodiments of the present disclosure. As shown in Figure 1A, the digital-to-analog converter 100A includes a plurality of conversion current units 110, a compensation current unit 120, an amplification circuit 131, a front-end processor 130, a digital controller 150, and a current source circuit 140.
[0009] In some embodiments, the digital controller 150 is used to generate the digital signal DS. The front-end processor 130 uses the digital signal DS to generate multiple control signals.
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[0010] Referring to Figure 1A, each of the multiple conversion current units 110 includes a differential switch pair 111, a multilayer transistor M3, and a current source transistor M4. For simplicity, Figure 1A shows only the detailed arrangement of a single conversion current unit 110. In the following text, unless otherwise specified, please understand that the arrangement of the single conversion current unit 110 described applies to each of the multiple conversion current units 110. Of these, the differential switch pair 111 includes switches M1 and M2, which are controlled by a control signal (Qj) and an inverse control signal (Qj-), respectively. More specifically, switch M1 is controlled by one of the control signal (Qj) and the inverse control signal (Qj-), and switch M2 is controlled by the other of the control signal (Qj) and the inverse control signal (Qj-).
[0011] Furthermore, the control signal (Qj) and the inverse control signal (Qj-) are related to the digital signal DS. In other words, the digital signal DS is converted into the control signal (Qj) and the inverse control signal (Qj-) through the front-end processor 130, and then the digital-to-analog converter 100A generates an analog signal based on the control signal (Qj) and the inverse control signal (Qj-). Since the control signal (Qj) and the inverse control signal (Qj-) are in opposite directions, when one of switches M1 and M2 is turned on, the other switch M1 and M2 is turned off.
[0012] In some embodiments, the 'j' in the control signal (Qj) and the inverse control signal (Qj-) can represent a plurality of positive integers, and the plurality of conversion current units 110 each receive the corresponding control signal (Qj) and the inverse control signal (Qj-). For example, switches M1 and M2 in the first conversion current unit 110 receive the control signal
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[0013] As shown in FIG. 1A, switch M1 in the conversion current unit 110 is connected between the output terminal n1 and node n3, and switch M2 is connected between the output terminal n2 and node n3. The stacked transistor M3 and the current source transistor M4 are connected in series with each other between node n3 and node n4. Among them, for switch M1, switch M2, stacked transistor M3, and current source transistor M4, NMOS transistors will be taken as examples for explanation. More specifically, the sources of switch M1 and switch M2 are connected at node n3, the drain of switch M1 is connected to the output terminal n1, and the drain of switch M2 is connected to the output terminal n2. The source of the stacked transistor M3 is connected to the drain of the current source transistor M4. The drain of the stacked transistor M3 is connected to node n3, and the source of the current source transistor M4 is connected to node n4. In some embodiments, node n4 is the ground terminal.
[0014] Referring to FIG. 1A again. Similar to the conversion current unit 110, the compensation current unit 120 includes a differential switch pair 121, a stacked transistor M7, and a current source transistor M8. Among them, the differential switch pair 121 is controlled by a control signal
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[0015] More specifically, the differential switch pair 121 includes switches M5 and M6. Switch M5 is controlled by the control signal (B). In some embodiments, switch M6 can be controlled by an inverse control signal
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[0016] In some embodiments, the control signal (B) and the reverse control signal (B-) are a fixed differential signal pair. Compared to the control signal (Qj) and the reverse control signal (Qj-) received by the conversion current unit 110, the control signal (B) and the reverse control signal (B-) remain unchanged, while the control signal (Qj) and the reverse control signal (Qj-) change in accordance with the digital signal DS.
[0017] In other words, in some embodiments, switch M5 holds the ON position and switch M6 holds the OFF position. In some variations, switch M5 is controlled by an inverse control signal (B-) and switch M6 is controlled by a control signal (B). In other words, switch M5 holds the OFF position and switch M6 holds the ON position.
[0018] As shown in Figure 1A, switch M5 in the compensation current unit 120 is connected between output terminal n1 and node n5, and switch M6 is connected between output terminal n2 and node n5. The multilayer transistor M7 and the current source transistor M8 are connected in series with each other between node n5 and node n4. Of these, switches M5, M6, multilayer transistor M7, and current source transistor M8 will be described using NMOS transistors as examples. More specifically, the source of switch M5 and the source of switch M6 are connected at node n5, the drain of switch M5 is connected to output terminal n1, and the drain of switch M6 is connected to output terminal n2. The source of multilayer transistor M7 is connected to the drain of current source transistor M8. The drain of multilayer transistor M7 is connected to node n5, and the source of current source transistor M8 is connected to node n4.
[0019] Refer again to Figure 1A. The amplifier circuit 131 is connected between the gate and source of the multilayer transistor M7. More specifically, the amplifier circuit 131 may include an operational amplifier OPA, of which the inverting input terminal of the operational amplifier OPA is connected to the source of the multilayer transistor M7, the non-inverting input terminal of the operational amplifier OPA is connected to the bias signal Vb, and the output terminal of the operational amplifier OPA is connected to the gate of the multilayer transistor M7. In Figure 1A, the inverting input terminal is represented by the sign -, and the non-inverting input terminal is represented by the sign +. In this configuration, a regulated loop L1 is formed between the gate and source of the multilayer transistor M7.
[0020] Furthermore, the gate of the multilayer transistor M7 is connected to the gates of each multilayer transistor M3 in the multiple conversion current units 110. Correspondingly, the amplifier circuit 131 can supply a voltage signal Vsh to the gates of the multilayer transistor M3 and the gates of the multilayer transistor M7. For simplicity, Figure 1A only shows the connection method between the multilayer transistor M7 and a single conversion current unit 110, but please understand that the other conversion current units 110 are connected to the multilayer transistor M7 in the same way. In the above configuration, the output terminal of the amplifier circuit 131 is connected to the gate of the multilayer transistor M7, and further connected to the gates of each multilayer transistor M3 in the multiple conversion current units 110 via the gate of the multilayer transistor M7. In this way, the amplifier circuit 131 increases the total impedance of the multilayer transistor M3 and the current source transistor M4, and the total impedance of the multilayer transistor M7 and the current source transistor M8, respectively, by providing gain, and correspondingly increases the output impedance of the conversion current unit 110 and the compensation current unit 120.
[0021] Looking at Figure 1A again, in some embodiments, the gate of the current source transistor M8 is further connected to the gate of each current source transistor M4 in multiple conversion current units 110. Here, for simplicity, Figure 1A only shows the connection method between the current source transistor M8 and a single conversion current unit 110, but please understand that the other conversion current units 110 are also connected to the current source transistor M8 in the same connection method.
[0022] As shown in Figure 1A, the current source circuit 140 is connected to the current source transistor M8 to form a current mirror. In this way, the current source transistor M8 can generate a mirror current by turning on the current source circuit 140. At the same time, the current source circuit 140 can also be connected to each current source transistor M4 in the multiple conversion current units 110 to form a current mirror. In this way, each current source transistor M4 can generate a mirror current by turning on the current source circuit 140.
[0023] In some embodiments, the current source circuit 140 may include a current source 141 and a gate bias circuit 142. One end of the current source 141 is used to receive the power supply voltage VDD, and the other end of the current source 141 is connected to the gate bias circuit 142. The gate bias circuit 142 is connected to the ground terminal and is used to provide gate bias to the gates of the current source transistors M4 and M8.
[0024] In some embodiments, the gate bias circuit 142 can be implemented by a transistor (not shown). The gate of this transistor is connected to the gates of current source transistors M4 and M8. The drain of this transistor is connected to its gate and the current source 141. The source of this transistor is connected to the ground terminal.
[0025] In various embodiments, the digital-to-analog converter 100A can output analog signals from output terminals n1 and n2 in various ways. For example, the digital-to-analog converter 100A can be implemented with a one-sided output structure. Figure 1C is a schematic circuit diagram of a portion of a digital-to-analog converter based on some embodiments of the present disclosure, within a one-sided output structure. As shown in Figure 1C, in the one-sided output structure, the digital-to-analog converter 100A further includes an operational amplifier 131C and an output resistor RF. The inverting input terminal of the operational amplifier 131C is connected to output terminal n1. The non-inverting input terminal of the operational amplifier 131C is connected to the ground terminal. The output resistor RF is connected between output terminal n1 and the output terminal of the operational amplifier 131C.
[0026] In the example above, multiple conversion current units 110 are used to generate multiple output currents I1 flowing through switch M1 and multiple currents I2 flowing through switch M2. The sum of the output currents I1 is determined by the number of times switch M1 is turned on and the switch M5 that remains turned on. The sum of the currents I2 is determined by the number of times switch M2 is turned on and the switch M6. In this way, the digital-to-analog converter 100A can generate an output voltage, of which the output voltage is equal to the sum of the output currents I1 multiplied by the output resistance RF.
[0027] Another example is that the digital-to-analog converter 100A can be implemented with a double-sided output structure. In a double-sided output structure, the digital-to-analog converter 100A may further include a load resistor (not shown). The load resistor may include resistors R1 and R2 (not shown). More specifically, resistor R1 is connected to multiple conversion current units 110 at output terminal n1, and resistor R2 is connected to multiple conversion current units 110 at output terminal n2. In some embodiments, resistors R1 and R2 have the same resistance value. Furthermore, in another embodiment, the load resistor may include only resistor R1, in which case resistor R1 is connected to output terminal n1, and output terminal n2 is changed to a ground terminal.
[0028] In the example above, multiple conversion current units 110 are used to generate multiple output currents I1 flowing through switch M1 and multiple currents I2 flowing through switch M2. The sum of the output currents I1 is determined by the number of times switch M1 is turned on and the switch M5 that remains turned on. The sum of the output currents I2 is determined by the number of times switch M2 is turned on and the switch M6. The sum of the output currents I1 and the sum of the output currents I2 flow through resistors R1 and R2, respectively, resulting in an output voltage difference between output terminals n1 and n2.
[0029] Please refer to Figure 1B. Figure 1B is a schematic circuit diagram of a digital-to-analog converter 100B based on several embodiments of the present disclosure. Compared to the digital-to-analog converter 100A in Figure 1A, the main difference is that the amplification circuit 131 of the digital-to-analog converter 100B includes transistor M13 and current source IS. Of these, transistor M13, switches M1-M2, switches M5-M6, multilayer transistor M3, multilayer transistor M7, current source transistor M4 and current source transistor M8 will be described using NMOS transistors as examples. More specifically, the drain of transistor M13 is connected to the gate of current source IS and multilayer transistor M7. The gate of transistor M13 is connected to the source of multilayer transistor M7. In this way, the amplification circuit 131 increases the total impedance of multilayer transistor M3 and current source transistor M4 and the total impedance of multilayer transistor M7 and current source transistor M8, respectively, by providing gain, and correspondingly increases the output impedance of the conversion current unit 110 and compensation current unit 120.
[0030] Please refer to Figure 2A. Figure 2A is a schematic circuit diagram of a digital-to-analog converter 200A based on several embodiments of this disclosure. Referring to Figures 1A and 2A, the digital-to-analog converter 200A is a type of modification of the digital-to-analog converter 100A. The elements of the digital-to-analog converter 200A follow the coding scheme of the digital-to-analog converter 100A. For the sake of brevity, we will focus our discussion on the differences between the digital-to-analog converter 200A and the digital-to-analog converter 100A, rather than the similarities.
[0031] In the embodiment corresponding to Figure 2A, the sources of current source transistor M4 and current source transistor M8 are connected to the power supply voltage VDD at node n6. The drains of switch M2 and switch M6 are connected to the ground terminal at output terminal n2. Of these, switches M1-M2, switches M5-M6, multilayer transistor M3, multilayer transistor M7, current source transistor M4, and current source transistor M8 will be described using PMOS transistors as examples.
[0032] Please refer to Figure 2B. Figure 2B is a schematic circuit diagram of a digital-to-analog converter 200B based on several embodiments of the present disclosure. Compared to the digital-to-analog converter 200A in Figure 2A, the main difference is that the amplification circuit 131 of the digital-to-analog converter 200B includes transistor M13 and current source IS. Of these, transistor M13, switches M1-M2, switches M5-M6, multilayer transistor M3, multilayer transistor M7, current source transistor M4 and current source transistor M8 will be described using PMOS transistors as examples. More specifically, the drain of transistor M13 is connected to the current source IS and the gate of multilayer transistor M7. The gate of transistor M13 is connected to the source of multilayer transistor M7. In this way, the amplification circuit 131 increases the total impedance of multilayer transistor M3 and current source transistor M4 and the total impedance of multilayer transistor M7 and current source transistor M8, respectively, by providing gain, and correspondingly increases the output impedance of the conversion current unit 110 and the compensation current unit 120.
[0033] In the embodiment shown in Figure 2B, one end of the current source 141 is connected to a ground terminal, and the other end of the current source 141 is connected to a gate bias circuit 142. The gate bias circuit 142 is used to receive the power supply voltage VDD and to supply the gate bias voltage to the gates of the current source transistors M4 and M8.
[0034] As described above, the technical method of this disclosure can increase the output impedance of a digital-to-analog converter at a lower cost and can help improve the linearity of the digital-to-analog converter.
[0035] Although the embodiments described above are presented in this disclosure, they are not intended to limit the disclosure. Those skilled in the art can make various modifications and alterations without departing from the spirit and scope of this disclosure, and the scope of protection of this disclosure shall be determined based on the appended claims. [Explanation of Symbols]
[0036] 100A~100B Digital-to-Analog Converter 110 Conversion Current Unit 111, 121 Differential Switch Pair 120 Compensation Current Unit 130 Front-end processors 140 Current source circuit 150 Digital Controllers (Qj), (B) Control signals (Qj-), (B-) Reverse control signals M3, M7 Multilayer Transistors M4, M8 Current Source Transistors M1, M2, M5, M6 switches M13 Transistor Vb bias signal 131 Amplifier Circuit 131C Operational Amplifier Vsh voltage signal DS Digital Signal 141, IS current source 142 Gate bias circuit 200A~200B Digital-to-Analog Converter n1, n2 output terminals Nodes n3~n6 L1 Adjustment Loop VDD power supply voltage RF output resistance
Claims
1. Multiple conversion current units, each of the conversion current units is A first differential switch pair controlled by a first control signal and a first inverse control signal, A plurality of conversion current units, each including a first stacked transistor and a first current source transistor connected in series with each other and connected to the first differential switch pair, A compensating current unit, A second differential switch pair controlled by a second control signal, A compensation current unit comprising a second stacked transistor and a second current source transistor connected in series with each other and connected to the second differential switch pair, wherein the gate of the second current source transistor is connected to the gate of the first current source transistor, A first amplifier circuit, wherein the input terminal of the first amplifier circuit is connected to the source of the second multilayer transistor, and the output terminal of the first amplifier circuit is connected to the gate of the second multilayer transistor and the gate of the first multilayer transistor, The current source circuit includes a current source circuit which is connected to the second current source transistor to form a current mirror, and is also connected to the first current source transistor to form a current mirror, Digital-to-analog converter.
2. The first amplification circuit described above, An operational amplifier, wherein the inverting input terminal of the operational amplifier is connected to the source of the second stacked transistor, the non-inverting input terminal of the operational amplifier is connected to a bias signal, and the output terminal of the operational amplifier is connected to the gate of the second stacked transistor and the gate of the first stacked transistor, respectively. The digital-to-analog converter according to claim 1.
3. The first amplification circuit described above, A first transistor wherein the drain of the first transistor is connected to the gate of the second stacked transistor and the gate of the first stacked transistor, and the gate of the first transistor is connected to the source of the second stacked transistor, A first current source connected to the drain of the first transistor, The digital-to-analog converter according to claim 1.
4. The first differential switch pair, A first switch, wherein the first terminal of the first switch is connected to a first output terminal, and the second terminal of the first switch is connected to the first multilayer transistor at a first node, A second switch, wherein the first terminal of the second switch is connected to a second output terminal, and the second terminal of the second switch is connected to the first node, The digital-to-analog converter according to claim 1.
5. The second differential switch pair, A third switch, which is controlled by the second control signal, the first terminal of the third switch is connected to the first output terminal, and the second terminal of the third switch is connected to the second multilayer transistor at a second node, A fourth switch, which is controlled by a second inverse control signal and connected to the second node, is included. Of these, the second control signal and the second inverse control signal are kept constant. The digital-to-analog converter according to claim 4.
6. Operational amplifier and The output resistor and, further, Of these, the inverting input terminal of the operational amplifier is connected to the first output terminal, the non-inverting input terminal of the operational amplifier is connected to the ground terminal, and The output resistor is connected between the first output terminal and the output terminal of the operational amplifier. The digital-to-analog converter according to claim 4.
7. It further includes a load resistor, and the load resistor is Including a first resistor connected to the first output terminal, The digital-to-analog converter according to claim 4.
8. The aforementioned load resistance further, Including a second resistor connected to the second output terminal, The digital-to-analog converter according to claim 7.
9. The digital-to-analog converter according to claim 1, wherein the first current source transistor is connected to a ground terminal.
10. The digital-to-analog converter according to claim 1, wherein the first current source transistor is used to receive the power supply voltage.