Semiconductor device and method for manufacturing a semiconductor device
The semiconductor device addresses RDSon and Vth instability in SiC planar MOSFETs by employing a controlled doping structure and precise manufacturing steps to prevent well region contact, achieving stable performance and reduced hot carrier injection.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- EPISIL TECH INC
- Filing Date
- 2025-04-21
- Publication Date
- 2026-06-05
AI Technical Summary
Conventional SiC planar MOSFETs face issues such as increased drain-source on-resistance (RDSon), unstable threshold voltage (Vth), and susceptibility to signal noise due to reduced cell pitch, which leads to misalignment and limitations in metal filling, causing hot carrier injection and short-channel effects.
A semiconductor device design with a silicon carbide epitaxial substrate featuring well regions, junction field-effect transistor regions, source regions, and controlled doping layers, along with precise manufacturing steps to form low- and high-concentration doped regions, ensuring the junction field-effect transistor region does not contact well regions, and using oblique ion implantation to create specific doping layers.
The solution effectively suppresses hot carrier injection and short-channel effects, maintaining stable threshold voltage and reducing RDSon without adversely affecting electrical properties, thereby enhancing the reliability and performance of the semiconductor device.
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Abstract
Description
[Technical Field]
[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices and methods for manufacturing the same. [Background technology]
[0002] Silicon carbide (SiC) has many advantages, such as resistance to high pressure and high temperature, and is currently widely used in electronic components where such properties are required. For example, Patent Document 1 discloses a SiC semiconductor device and a method for manufacturing a SiC semiconductor device.
[0003] Conventionally, in order to reduce the drain-source on-resistance (RDSon) of a SiC planar metal oxide semiconductor field-effect transistor (SiC planar MOSFET) and thereby reduce power consumption, it was necessary to reduce the cell pitch of the SiC planar MOSFET.
[0004] However, reducing the cell pitch can introduce various technical bottlenecks (such as misalignment and limitations on the metal filling capacity of the source contact pad), which can affect the electrical properties of SiC planar MOSFETs and cause them to deviate from standard characteristics.
[0005] More specifically, the cell pitch of a SiC planar MOSFET is the junction field-effect transistor region (J FET It can be narrowed by reducing the width of the region.
[0006] However, this also shortens the channel length, which can lead to an unstable threshold voltage (Vth) due to the short-channel effect, potentially causing a higher electric field within the channel and leading to hot carrier injection.
[0007] This could affect the reliability of SiC planar MOSFETs.
[0008] Furthermore, when the width of the J FET region is narrowed, the electrical resistance of the J FET region (hereinafter abbreviated as "R JFET ") increases, and as a result, RDSon increases.
[0009] By narrowing the width of the J region of the SiC planar MOSFET, in order to avoid an increase in the R FET of the SiC planar MOSFET, the J JEFT region is doped (JF implant) at a higher doping concentration (doped at a higher concentration) to offset the increase in R FET . JFET
[0010] However, due to the bottleneck of the current process technology, when manufacturing a conventional semiconductor device, the J FET region partially overlaps with the well region, and the doping concentration of the well region decreases due to the highly doped J FET region, resulting in a decrease in the threshold voltage (Vth) of the semiconductor device.
[0011] A conventional semiconductor device is more susceptible to signal noise when the threshold voltage (Vth) is too low.
Prior Art Documents
Patent Documents
[0012]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0013] Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that can reduce at least one of the drawbacks of the prior art.
Means for Solving the Problems
[0014] The present invention includes a silicon carbide epitaxial substrate, two well regions, a junction field-effect transistor region, two source regions, two low-concentration doped regions, two high-concentration doped regions, a gate terminal, a drain terminal, and The silicon carbide epitaxial substrate has a top surface and a bottom surface which is the opposite surface of the top surface. The two well regions are spaced apart from each other, each extending downward from the top surface of the silicon carbide epitaxial substrate, and are doped with a second type dopant. The junction field-effect transistor region extends downward from the top surface of the silicon carbide epitaxial substrate, is located between the two well regions, and is doped with a first-type dopant. The two source regions extend downward from the top surface of the silicon carbide epitaxial substrate and are each located in each of the two well regions. Each of the two low-concentration doped regions comprises a first low-concentration doped layer, each positioned in each of the two well regions and extending downward from the top surface of the silicon carbide epitaxial substrate so as to be parallel to the upper part of the boundary edge of the corresponding source region, and a second low-concentration doped layer, extending downward from the first low-concentration doped layer so as to be parallel to the lower part of the boundary edge of the corresponding source region and further extending downward so as to lie below the corresponding source region. The first low-concentration doped layer is doped with a type 1 dopant. The second low-concentration doped layer is doped with a type 2 dopant and has a width greater than the width of the first low-concentration doped layer. Each of the two high-concentration doped regions is formed below the corresponding source region without extending beyond the bottom surface of the corresponding well region, and is doped with a second type of dopant. The gate terminal is located on the top surface of the silicon carbide epitaxial substrate between the two source regions and has two opposing outer ends, each overlapping the two source regions. The drain terminal provides a semiconductor device that is located on the bottom surface of the silicon carbide epitaxial substrate.
[0015] Also, a silicon carbide epitaxial substrate, two well regions, a junction field effect transistor region, two source regions, a gate terminal, and a drain terminal are included. The silicon carbide epitaxial substrate has a top surface and a bottom surface that is opposite to the top surface. The two well regions are spaced apart from each other, each extending downward from the top surface of the silicon carbide epitaxial substrate, and being doped with a second-type dopant. The junction field effect transistor region extends downward from the top surface of the silicon carbide epitaxial substrate, is located between the two well regions, and is doped with a first-type dopant. Also, the junction field effect transistor region has a width smaller than the distance between the two well regions and does not contact either of the two well regions. The two source regions extend downward from the top surface of the silicon carbide epitaxial substrate, and each is located in each of the two well regions. The gate terminal is located on the top surface of the silicon carbide epitaxial substrate between the two source regions and has two opposite outer ends that each overlap the two source regions. The drain terminal provides a semiconductor device that is located on the bottom surface of the silicon carbide epitaxial substrate.
[0016] Also, the present invention includes step A of forming a first hard mask unit on the top surface of a silicon carbide epitaxial substrate, where the first hard mask unit has a first hard mask layer, a second hard mask layer, and a third hard mask layer that are stacked in order from the top surface of the silicon carbide epitaxial substrate upward. Step B involves etching the first hard mask unit from the third hard mask layer to the first hard mask layer in a photolithography process to form a plurality of first openings that are spaced apart from each other, Step C involves doping the silicon carbide epitaxial substrate with a second type dopant by ion implantation through each of the first openings, thereby forming a plurality of well regions that are spaced apart from each other. Step D: After forming the etched first hard mask unit and the first mask film covering each of the first openings, remove the third hard mask layer and the first mask film covering each of the first openings such that each of the remaining thickness portions of the first mask film remaining at the boundary of each of the first openings defines a second opening having a size smaller than the size of each of the first openings. Step E is a step of performing a first ion implantation through each of the second openings to form a first low-concentration doped layer, and then performing a second ion implantation through each of the second openings to form a second low-concentration doped layer that is located below the first low-concentration doped layer and has a width wider than the width of the first low-concentration doped layer, wherein the first low-concentration doped layer is doped with a first type dopant, and the second low-concentration doped layer is doped with a second type dopant. Step F involves forming a fourth hard mask layer that covers the third hard mask layer, the first mask film, and the first hard mask layer exposed through the second opening, and then forming a second mask film that covers the fourth hard mask layer, and then removing a portion of the second mask film corresponding to the position of the third hard mask layer and the position of each second opening such that each of the remaining thickness portions of the second mask film remaining at the boundary of each second opening defines a third opening having a diameter smaller than the diameter of each second opening. A method for manufacturing a semiconductor device is provided, comprising step G, which is a step of performing ion implantation through each of the third openings to form a plurality of source regions extending downward from the top surface of the silicon carbide epitaxial substrate, wherein each of the source regions is doped with a first type dopant and has a doping concentration greater than the doping concentration of the first low-concentration doped layer and the doping concentration of the second low-concentration doped layer, and each of the source regions has a bottom end located at a depth between the depth of the bottom end of the first low-concentration doped layer and the depth of the bottom end of the second low-concentration doped layer. [Effects of the Invention]
[0017] The semiconductor device of the present invention, by carefully controlling the manufacturing process, forms a first low-concentration doping layer 31 in the source region S that is doped with a first-type dopant, and then forms a second low-concentration doping layer 32 that has a width greater than the width of the first low-concentration doping layer 31 and is doped with a second-type dopant, thereby suppressing hot carrier injection and avoiding the short-channel effect caused by miniaturization of the semiconductor device. [Brief explanation of the drawing]
[0018] [Figure 1] This is a cross-sectional view showing an embodiment of the semiconductor device of the present invention. [Figure 2] This is a cross-sectional flow diagram showing steps A to C of an embodiment of a semiconductor device manufacturing method. [Figure 3] This is a cross-sectional flowchart showing steps D to E of the above embodiment. [Figure 4] This is a cross-sectional flow diagram showing steps F to G of the above embodiment. [Figure 5] This is a cross-sectional flowchart showing steps H to I of the above embodiment. [Figure 6] This is a cross-sectional flow diagram showing steps J to K of the above embodiment. [Modes for carrying out the invention]
[0019] The present invention will be described in detail below.
[0020] As shown in Figure 1, an embodiment of the semiconductor device of the present invention comprises a silicon carbide (SiC) epitaxial substrate 2, two well regions W, and a junction field-effect transistor region J. FET It includes two source regions S, two low-concentration doped regions 3, two high-concentration doped regions HW, a gate terminal G, a drain terminal D, an insulating layer 4, a conductive unit 5, a protective unit 6, and an electrical connection unit 7.
[0021] The silicon carbide epitaxial substrate 2 is doped with a type 1 dopant and has a silicon carbide substrate material 21, a silicon carbide epitaxial film 22 located on the silicon carbide substrate material 21, a top surface 23, and a bottom surface 24 which is the opposite surface of the top surface 23.
[0022] The first type dopant used to dope the silicon carbide epitaxial substrate 2 has first type electrical conductivity, and the second type dopant used to dope the well region W described below has second type electrical conductivity opposite to that of the first type.
[0023] For example, a Type 1 dopant is an N-type dopant, and a Type 2 dopant is a P-type dopant.
[0024] As another example, a Type 1 dopant can be a Type P dopant, and a Type 2 dopant can be an Type N dopant.
[0025] In this embodiment, the semiconductor device is a planar metal oxide semiconductor (MOS), the first type dopant is an N-type dopant, the N-type dopant can be nitrogen (N) or phosphorus (P), and the P-type dopant can be aluminum (Al).
[0026] As shown in Figure 1, the two well regions W are spaced apart from each other, each extending downward from the top surface 23 of the silicon carbide epitaxial substrate 2 and located within the silicon carbide epitaxial film 22.
[0027] In this embodiment, each of the two well regions W is doped with a type 2 dopant (type P dopant).
[0028] Junction field-effect transistor region J FET As shown in Figure 1, it extends downward from the top surface 23 of the silicon carbide epitaxial substrate 2 and is formed to be located between the two well regions W.
[0029] In this embodiment, the junction field-effect transistor region J FET It is located between the two well regions W without touching the two well regions W.
[0030] Junction field-effect transistor region J FET It has a width smaller than the distance between the two well regions W, and therefore does not come into contact with either of the two well regions W.
[0031] In this embodiment, the junction field-effect transistor region J FET The individual is doped with a Type 1 dopant (Type N dopant).
[0032] As shown in Figure 1, the two source regions S each extend downward from the top surface 23 of the silicon carbide epitaxial substrate 2 and are located in the respective two well regions W.
[0033] The two low-concentration doped regions 3 are each located in one of the two well regions W, as shown in Figure 1, and each has a first low-concentration doped layer 31 extending downward from the top surface 23 of the silicon carbide epitaxial 2 so as to be parallel to the upper part of the boundary edge of the corresponding source region S, and a second low-concentration doped layer 32 extending downward from the first low-concentration doped layer 31 so as to be parallel to the lower part of the boundary edge of the corresponding source region S, and further extending downward so as to lie at the bottom below the corresponding source region S. That is, each source region S has a bottom end at a depth between the depth of the bottom end of the first low-concentration doped layer 31 and the depth of the bottom end of the second low-concentration doped layer 32.
[0034] In this embodiment, the first low-concentration doping layer 31 is doped with a type 1 dopant (type N dopant), and the second low-concentration doping layer 32 is doped with a type 2 dopant (type P dopant).
[0035] The second low-concentration doped layer 32 has a width greater than the width of the first low-concentration doped layer 31.
[0036] More specifically, the width between the edge of the first low-concentration doped layer 31 and the edges of each source region S defines a channel.
[0037] The second low-concentration doping layer 32 is located below the first low-concentration doping layer 31, and the horizontal distance from the edge of the second low-concentration doping layer 32 to the edge of each well region W is smaller than the horizontal distance from the edge of the first low-concentration doping layer 31 to the edge of each well region W.
[0038] Therefore, the edges of the second low-concentration doping layer 32 of each low-concentration doping region 3 are closer to the edges of the well region W than the edges of the first low-concentration doping layer 31 of the low-concentration doping region 3, and the second low-concentration doping layer 32 has a width greater than the width of the first low-concentration doping layer 31.
[0039] Furthermore, the second low-concentration doping layer 32 has a doping concentration lower than the doping concentration of the well region W.
[0040] The two highly doped regions HW are formed below their respective source regions S, without extending beyond the bottom surface of the corresponding well region W, as shown in Figure 1.
[0041] The second low-concentration doping layer 32 of each low-concentration doping region 3 extends downward from the bottom of the corresponding source region S, runs parallel to the boundary wall of the high-concentration doping region HW, and its bottom edge is connected to the side edge of the corresponding high-concentration doping region HW.
[0042] The two high-concentration doped regions HW are doped with the same type of dopant (type 2 dopant) as the well region W. Furthermore, the high-concentration doped regions HW have a higher doping concentration than the well region W.
[0043] The gate terminal G is located on the top surface 23 of the silicon carbide epitaxial substrate 2 between two adjacent source regions S, as shown in Figure 1. The gate terminal G has two opposing outer ends, each overlapping the two source regions S.
[0044] As shown in Figure 1, the insulating layer 4 comprises a first insulating layer 41 made of an oxide material that covers the top surface 23 of the silicon carbide epitaxial substrate 2, and a second insulating layer 42 located above the first insulating layer 41, made of a dielectric insulating material, and covering the gate terminal G.
[0045] The gate terminal G is located on the surface above the first insulating layer 41.
[0046] In other words, the second insulating layer 42 covers the first insulating layer 41 and the gate terminal G.
[0047] As shown in Figure 1, the conductive unit 5 has an ohmic contact layer 51 that is electrically connected to the source region S, and a source electrode 52 that is electrically connected to the ohmic contact layer 51.
[0048] The protective unit 6 is made of insulating material and, as shown in Figure 1, is located on the second insulating layer 42 and covers the source electrode 52. That is, the protective unit 6 covers the second insulating layer 42 and the source electrode 52.
[0049] As shown in Figure 1, the electrical connection unit 7 has a plurality of conductive structures 71 that penetrate the protective unit 6 and the second insulating layer 42 and are electrically connected to the gate terminal G, source electrode 52 and source region S, and a conductor 72 for electrically connecting the plurality of conductive structures 71 to the outside.
[0050] The conductor 72 is electrically connected to the conductive structure 71, located on the protective unit 6, and electrically connected to the source region S and gate terminal G, and electrically connected to the outside by 3D wiring (Figure 1 only shows that the conductive structure 71 is connected to the source region S and conductor 72). The ohmic contact layer 51 of the conductive unit 5 can be made of a metal silicide, such as nickel silicide (Ni silicide).
[0051] The source electrode 52 can be made of a metal or alloy such as titanium (Ti), titanium nitride (TiN), or aluminum-copper alloy (AlCu).
[0052] The protective unit 6 can be made of an insulating material such as an oxide or nitride, and may have a single-layer or multi-layer structure.
[0053] The conductor 72 can be made of a metal or alloy such as titanium (Ti), titanium nitride (TiN), or aluminum-copper alloy (AlCu), and may have a single-layer or multi-layer structure.
[0054] The drain terminal D is located on the bottom surface 24 of the silicon carbide epitaxial substrate 2.
[0055] Furthermore, the drain terminal D includes a metallic silicon layer D11 formed on the bottom surface 24 of the silicon carbide epitaxial substrate 2, and a metallic conductive layer D12 formed on the surface of the metallic silicon layer D11.
[0056] The metallic conductive layer D12 can be composed of a metal or alloy such as titanium, titanium nitride, or aluminum-copper alloy.
[0057] The metallic silicon layer D11 can be composed of a metallic silicide, such as nickel silicide.
[0058] An embodiment of the method for manufacturing a semiconductor device of the present invention includes steps A to O.
[0059] Figure 2 is a cross-sectional flow diagram showing steps A to C of an embodiment of a semiconductor device manufacturing method.
[0060] As shown in Figures 1 and 2, in step A, a silicon carbide epitaxial substrate 2 is prepared, and a first hard mask unit 20 is formed on the top surface 23 of the silicon carbide epitaxial substrate 2 (which may be the surface of the silicon carbide epitaxial film 22 in the embodiment of a semiconductor device).
[0061] The first hard mask unit 20 has a first hard mask layer HM1, a second hard mask layer HM2, and a third hard mask layer HM3, which are stacked in order from the top surface 23 of the silicon carbide epitaxial substrate 2 upwards.
[0062] More specifically, the first hard mask unit 20 can be formed by sequentially performing chemical vapor deposition (CVD) to form a first hard mask layer HM1, a second hard mask layer HM2, and a third hard mask layer HM3.
[0063] The first hard mask unit 20 can be made from materials such as nitrides, oxides, or polycrystalline silicon.
[0064] Furthermore, the high etching selectivity ratio between the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 is advantageous for forming an etching stop layer.
[0065] Then, in step B, a photoresist is formed on the surface of the third hard mask layer HM3, and a plurality of spaced-apart openings are formed in the photoresist by a photolithography process, and the first hard mask unit 20 is etched through these openings from the third hard mask layer HM3 to the first hard mask layer HM1 by a photolithography process to form a plurality of spaced-apart first openings OP1.
[0066] Then, the photoresist is removed.
[0067] Subsequently, in step C, the silicon carbide epitaxial substrate 2 is doped through each first opening OP1 by ion implantation, thereby forming multiple well regions W in the silicon carbide epitaxial film 22 that are doped with a type 2 dopant and are spaced apart from each other.
[0068] In this embodiment, the second type dopant is a P-type dopant.
[0069] Figure 3 is a cross-sectional flow diagram showing steps D to E of the above embodiment.
[0070] After step C is performed, in step D, as shown in Figure 3, a third hard mask layer HM3 and a first mask film SPA1 covering each first opening OP1 are formed on the surface of the etched first hard mask unit 20.
[0071] The first mask film SPA1 can be made of an oxide material or a nitride material.
[0072] Furthermore, the first hard mask layer HM1 and the third hard mask layer HM3 have a high etching selectivity ratio compared to the first mask film SPA1.
[0073] Then, by an etching back process, the surface of the third hard mask layer HM3 and the first mask film SPA1 covering each of the first openings OP1 are removed such that each remaining thickness portion of the first mask film SPA1 at the boundary of each first opening OP1 defines a second opening OP2 having a size smaller than that of each first opening OP1.
[0074] Subsequently, in step E, a first ion implantation is performed through each second opening OP2 to form a first low-concentration doped layer 31 extending downward from the top surface 23 of the silicon carbide epitaxial substrate 2. Then, a second ion implantation is performed through each second opening OP2 to form a second low-concentration doped layer 32 located below the first low-concentration doped layer 31 and having a wider width than the first low-concentration doped layer 31.
[0075] The first low-concentration doping layer 31 is doped with a type 1 dopant, and the second low-concentration doping layer 32 is doped with a type 2 dopant.
[0076] In this embodiment, the first low-concentration doped layer 31 is doped with an N-type dopant, and the second low-concentration doped layer 32 is doped with a P-type dopant.
[0077] Furthermore, when performing a second ion implantation, the second ion implantation can be controlled to implant ions at an oblique angle.
[0078] Furthermore, in some embodiments, as long as the width of the second low-concentration doped layer 32 is greater than the width of the first low-concentration doped layer 31, the first ion implantation can be controlled to implant ions at an oblique angle.
[0079] Figure 4 is a cross-sectional flow diagram showing steps F to G of the above embodiment.
[0080] As shown in Figure 4, in step F, a fourth hard mask layer HM4 is formed by vapor deposition, covering the surface of the third hard mask layer HM3, the surface of the first mask film SPA1, and the surface of the first hard mask layer HM1 exposed through the second opening OP2, and a second mask film SPA2 is formed covering the fourth hard mask layer HM4.
[0081] The second mask film SPA2 is manufactured from an oxide or nitride material and has a high etching selectivity ratio with respect to the fourth hard mask layer HM4.
[0082] Subsequently, portions of the second mask film SPA2 corresponding to the top surface of the third hard mask layer HM3 and the bottom surface of the second opening OP2 are removed by an etch-back process so that each of the remaining thickness portions of the second mask film SPA2 remaining at the boundary of the second opening OP2 defines a third opening OP3 having a diameter smaller than the diameter of each second opening OP2.
[0083] Subsequently, in step G, ion implantation is performed through each third opening OP3 to extend downward from the top surface 23 of the silicon carbide epitaxial substrate 2, forming multiple source regions S doped with the first type of dopant, each source region S having a doping concentration higher than the doping concentration of the first low-concentration doping layer 31 and the doping concentration of the second low-concentration doping layer 32.
[0084] Furthermore, each source region S has a bottom end located at a depth between the depth of the bottom end of the first low-concentration doped layer 31 and the depth of the bottom end of the second low-concentration doped layer 32.
[0085] In this embodiment, the source region S is doped with an N-type dopant.
[0086] Figure 5 is a cross-sectional flow diagram showing steps H to I of the above embodiment.
[0087] As shown in Figure 5, in step H, the first hard mask layer HM1 to the fourth hard mask layer HM4 and the first mask film SPA1 to the second mask film SPA2 (see Figures 2 and 4) are removed using an acid (e.g., HF).
[0088] A photoresist layer (not shown) is formed on the top surface 23 of the silicon carbide epitaxial substrate 2, and then a patterned photoresist layer is formed by photolithography.
[0089] The patterned photoresist layer defines at least two doping openings (not shown) corresponding to each source region S, each having a width smaller than the width of the source region S.
[0090] High-concentration ion implantation is performed through each of the multiple doping openings to form high-concentration doped regions HW at the bottom of the source region S, each doped with a type 2 dopant.
[0091] Subsequently, the patterned photoresist layer is removed.
[0092] Then, in step I, a second hard mask unit 30 is formed having a fifth hard mask layer HM5, a sixth hard mask layer HM6, and a seventh hard mask layer HM7 that are stacked sequentially from the top surface 23 of the silicon carbide epitaxial substrate 2 upwards.
[0093] The material selection for the second hard mask unit 30 is the same as for the first hard mask unit 20, and is based on the high etching selectivity ratio between the fifth hard mask layer HM5, the sixth hard mask layer HM6, and the seventh hard mask layer HM7, thereby forming an etching stop layer. Then, a photoresist (not shown) is formed on the second hard mask unit 30 and patterned by photolithography to form a patterned photoresist having a photoresist opening located between two well regions W.
[0094] Subsequently, the seventh hard mask layer HM7, the sixth hard mask layer HM6, and the fifth hard mask layer HM5 are etched through each photoresist opening until the depth reaches the fifth hard mask layer HM5, thereby forming an opening OP between two adjacent well regions W.
[0095] Afterward, the patterned photoresist is removed.
[0096] Figure 6 is a cross-sectional flow diagram showing steps J to K of the above embodiment.
[0097] After step I is performed, in step J, as shown in Figure 6, a third mask film SPA3 is formed by CVD to cover the surface of the etched second hard mask unit 30.
[0098] The third mask film SPA3 is made of an oxide or nitride material, and the fifth hard mask layer HM5 and the seventh hard mask layer HM7 have a high etching selectivity ratio compared to the third mask film SPA3.
[0099] Then, the remaining thickness portion of the third mask film SPA3 that remains in the opening OP is removed by an etch-back process, with the portion corresponding to the top surface of the seventh hard mask layer HM7 and the bottom surface of the opening OP, so as to define a fourth opening OP4 having a diameter smaller than the diameter of the opening OP and smaller than the minimum distance between two adjacent well regions W.
[0100] Then, in step K, ion implantation is performed through the fourth opening OP4 to extend downward from the top surface 23 of the silicon carbide epitaxial substrate 2, and a junction field-effect transistor region J is doped with a type 1 dopant and is located between two well regions W without contact with adjacent well regions W. FET It forms.
[0101] In this embodiment, the junction field-effect transistor region J FET This is an extension of a silicon carbide epitaxial substrate 2, extending downward from the top surface 23, and doped with an N-type dopant.
[0102] Subsequently, the remaining portions of the third mask film SPA3 and the second hard mask unit 30 are removed to expose the top surface 23 of the silicon carbide epitaxial substrate 2.
[0103] Subsequently, as shown in Figures 1 and 6, an insulating layer 4 is formed in step L.
[0104] The insulating layer 4 comprises a first insulating layer 41 covering the top surface 23 of the silicon carbide epitaxial substrate 2, a polycrystalline silicon layer (not shown) formed on the first insulating layer 41, and a second insulating layer 42 located on the first insulating layer 41. That is, the insulating layer 4 comprises the first insulating layer 41, the polycrystalline silicon layer, and the second insulating layer 42, which are stacked in order from the top surface 23 of the silicon carbide epitaxial substrate 2 upwards (see Figure 1).
[0105] The first insulating layer 41 and the second insulating layer 42 can be made of an oxide material or a nitride material.
[0106] The polycrystalline silicon layer can be subjected to a later process to form gate terminals G.
[0107] The first insulating layer 41 and the second insulating layer 42 can be formed by thermal oxidation or vapor deposition when they are made from oxide materials.
[0108] The first insulating layer 41 and the second insulating layer 42 can be formed by CVD when they are made from nitride materials.
[0109] Since oxide and nitride materials and methods for forming them are well known in the art, further details will be omitted for brevity.
[0110] Then, through multiple photolithography processes, the polycrystalline silicon layer is etched downward from the second insulating layer 42 to the corresponding source region S, defining the gate terminal G shown in Figure 1, and forming recessed cells that extend through each source region S to the highly doped region HW.
[0111] The gate terminal G is located on the first insulating layer 41 and is formed to cover the second insulating layer 42.
[0112] An ohmic contact layer 51 made of metal silicide and a source electrode 52 covering the ohmic contact layer 51 are formed in each of the recessed grooves in sequence.
[0113] This forms a conductive unit 5 that is connected to the source region S.
[0114] Specifically, the conductive unit 5 has an ohmic contact layer 51 formed by vapor deposition in a highly doped region HW, and a source electrode 52 formed by vapor deposition on the ohmic contact layer 51.
[0115] In step M, a protective unit 6 is formed to cover the source electrode 52 with an insulating material such as an oxide or nitride.
[0116] In step N, an electrical connection unit 7 is formed which penetrates the protective unit 6 and is electrically connected to the gate terminal G and the source electrode 52, and is also electrically connected to the outside.
[0117] The electrical connection unit 7 has multiple conductive structures 71 that penetrate the protective unit 6 and are electrically connected to the corresponding gate terminal G, source electrode 52, and source region S, and a conductor 72 that is electrically connected to each conductive structure 71, is located on the protective unit 6, and is electrically connected to the source region S and gate terminal G and electrically connected to the outside by 3D wiring (in Figure 1, only the fact that the conductive structure 71 is connected to the source region S and conductor 72 is shown).
[0118] In step O, a drain terminal D is formed by sequentially stacking a metallic silicon layer D11 and a metallic conductive layer D12 from the bottom surface 24 of the silicon carbide epitaxial substrate 2 downwards. This allows for the manufacture of the semiconductor device shown in Figure 1.
[0119] The manufacturing parameters, parameter controls, and manufacturing materials used in steps L through O are well known in the relevant technical field, so for the sake of brevity, further details will be omitted.
[0120] In miniaturizing semiconductor devices, such as transistors, by reducing their dimensions, the length of the transistor channel is reduced. Therefore, the semiconductor device of the present invention provides a first low-concentration doping layer 31 which is doped with a first type dopant and is located on the side of the source region S closer to the channel, and a second low-concentration doping layer 32 located below the first low-concentration doping layer 31.
[0121] Furthermore, the second low-concentration doped layer 32 extends laterally toward the boundary of each well region W and has a width longer than the width of the first low-concentration doped layer 31.
[0122] This reduces the negative effects of shortening the channel length.
[0123] The first low-concentration doped layer 31 and the second low-concentration doped layer 32 help suppress short-channel effects in semiconductor devices and reduce hot carrier injection.
[0124] Furthermore, reducing the dimensions of semiconductor devices leads to a reduction in the distance between well regions W.
[0125] However, conventional photolithography cannot accurately etch narrow apertures.
[0126] Therefore, when a semiconductor device is miniaturized, the opening in the mask used to form the junction field-effect transistor region, which is used for doping in conventional technology, overlaps with the underlying well region, causing the thus formed junction field-effect transistor region to come into contact with the well region.
[0127] Conventionally, when miniaturizing semiconductor devices, the doping concentration of the junction field-effect transistor region is increased to reduce the drain-source on-resistance (RDSon). However, if the junction field-effect transistor region comes into contact with the well region due to miniaturization, the electrical properties of the well region are adversely affected by the highly doped junction field-effect transistor region, and the threshold voltage (Vth) decreases, potentially leading to semiconductor device failure.
[0128] Therefore, in steps I, J, and K of the present invention, a larger diameter aperture OP (see Figure 5) is first formed using a conventional photolithography process, and the third mask film SPA3 is etched by an etch-back process, leaving a residual thickness portion at the boundary of the aperture OP to define a smaller fourth aperture OP4 (see Figure 5).
[0129] The thickness of the third mask film SPA3 and the parameters of the etch-back process are carefully controlled and precisely managed to form the fourth opening OP4, which has a narrower profile (higher depth-to-width ratio) by carefully controlling the remaining thickness portion of the third mask film SPA3.
[0130] Thus, a small-diameter fourth aperture OP4 with high precision is formed, and a junction field-effect transistor region J is formed through the fourth aperture OP4. FET This can be precisely controlled to avoid contact with adjacent well regions W. Therefore, the junction field-effect transistor region J in the semiconductor device of the present invention FET This can be doped at high concentrations to reduce RDSon without affecting the threshold voltage (Vth) of the semiconductor device, while ensuring the normal functioning of the semiconductor device.
[0131] Based on the above, the semiconductor device of the present invention, by carefully controlling the manufacturing process, forms a first low-concentration doped layer 31 stretched in the channel direction and doped with a first-type dopant by ion implantation through a second aperture OP2, and then forms a second low-concentration doped layer 32 having a width greater than the width of the first low-concentration doped layer 31 and doped with a second-type dopant, thereby suppressing hot carrier implantation and avoiding the short-channel effect caused by miniaturization of the semiconductor device.
[0132] Furthermore, by carefully controlling the manufacturing process, the junction field-effect transistor region J FET This avoids contact with either of the two well regions W, thereby mitigating the adverse effects on electrical characteristics caused by the highly doped junction field-effect transistor region.
[0133] In this way, the semiconductor device of the present invention has a reduced possibility of failure, and the objectives of the present invention can be achieved.
[0134] The above embodiments are illustrative in illustrating the principles and effects of the present invention and do not limit it. Those skilled in the art can make some modifications and alterations to the above embodiments, provided they do not deviate from the spirit and scope of the invention. Therefore, all modifications and alterations made by those skilled in the art, provided they do not deviate from the spirit of the invention, should also be considered to fall within the scope of protection of the present invention. [Explanation of Symbols]
[0135] 2. Silicon Carbide Epitaxial Substrate 21 Silicon Carbide Substrate Material 22 Silicon Carbide Epitaxial Film 23 Top surface 24 Bottom W Well Area J FET Junction field-effect transistor region S Source Area 3. Low-concentration doped area 31. First low-concentration doping layer 32. Second low-concentration doping layer HW High-concentration doped area G gate terminal 4. Insulating layer 41 First insulating layer 42 Second insulating layer 5 Conductive Units 51 Ohm Contact Layer 52 Source electrodes 6. Protective Unit 7. Electrical connection unit 71 Conductive structure 72 Conductors D drain terminal D11 Metallic Silicon Layer D12 Metal conductive layer 20. First hard mask unit 30 Second hard mask unit HM1~HM7: First hard mask layer to seventh hard mask layer SPA1~SPA3 First Mask Film~Third Mask Film OP1~OP3 First opening~Third opening OP opening
Claims
1. A silicon carbide epitaxial substrate, two well regions, a junction field-effect transistor region, two source regions, two low-concentration doped regions, two high-concentration doped regions, a gate terminal, a drain terminal, and other components are included. The silicon carbide epitaxial substrate has a top surface and a bottom surface which is the opposite surface of the top surface. The two well regions are spaced apart from each other, each extending downward from the top surface of the silicon carbide epitaxial substrate, and are doped with the second type of dopant. The junction field-effect transistor region extends downward from the top surface of the silicon carbide epitaxial substrate, is located between the two well regions, and is doped with a first-type dopant. The two source regions extend downward from the top surface of the silicon carbide epitaxial substrate and are each located in each of the two well regions. Each of the two low-concentration doped regions comprises a first low-concentration doped layer, each positioned in each of the two well regions and extending downward from the top surface of the silicon carbide epitaxial substrate so as to be parallel to the upper part of the boundary edge of the corresponding source region, and a second low-concentration doped layer, extending downward from the first low-concentration doped layer so as to be parallel to the lower part of the boundary edge of the corresponding source region and further extending downward so as to lie below the corresponding source region. The first low-concentration doped layer is doped with a type 1 dopant. The second low-concentration doped layer is doped with a type 2 dopant and has a width greater than the width of the first low-concentration doped layer. Each of the two high-concentration doped regions is formed below the corresponding source region without extending beyond the bottom surface of the corresponding well region, and is doped with a second type of dopant. The gate terminal is located on the top surface of the silicon carbide epitaxial substrate between the two source regions, and has two opposing outer ends, each overlapping the two source regions. The drain terminal is a semiconductor device located on the bottom surface of the silicon carbide epitaxial substrate.
2. The semiconductor device according to claim 1, wherein the junction field-effect transistor region has a width smaller than the distance between the two well regions and is not in contact with either of the two well regions.
3. The second low-concentration doping layer has a doping concentration lower than the doping concentration in the well region. The semiconductor device according to claim 1, wherein the high-concentration doped region has a doping concentration greater than the doping concentration of the well region.
4. The semiconductor device according to claim 1, wherein the second low-concentration doping layer of each low-concentration doping region extends downward from the bottom of the corresponding source region and is parallel to the boundary wall of the high-concentration doping region.
5. It further includes an insulating layer, a conductive unit, and a protective unit. The insulating layer includes a first insulating layer covering the top surface of the silicon carbide epitaxial substrate and a second insulating layer. The gate terminal is located above the first insulating layer, The second insulating layer is located above the first insulating layer and covers the gate terminal. The conductive unit comprises an ohmic contact layer electrically connected to the source region and a source electrode electrically connected to the ohmic contact layer. The semiconductor device according to claim 1, wherein the protective unit is made of an insulating material and covers the source electrode and the second insulating layer.
6. Further including an electrical connection unit, The semiconductor device according to claim 5, wherein the electrical connection unit comprises a plurality of conductive structures that penetrate the protective unit and the second insulating layer and are each electrically connected to the source electrode and the gate terminal, and a conductor for electrically connecting the plurality of conductive structures to the outside.
7. A silicon carbide epitaxial substrate, two well regions, a junction field-effect transistor region, two source regions, a gate terminal, a drain terminal, and other components are included. The silicon carbide epitaxial substrate has a top surface and a bottom surface which is the opposite surface of the top surface. The two well regions are spaced apart from each other, each extending downward from the top surface of the silicon carbide epitaxial substrate, and are doped with the second type of dopant. The junction field-effect transistor region extends downward from the top surface of the silicon carbide epitaxial substrate, is located between the two well regions, and is doped with a first-type dopant. Furthermore, the junction field-effect transistor region has a width smaller than the distance between the two well regions and does not contact either of the two well regions. The two source regions extend downward from the top surface of the silicon carbide epitaxial substrate and are each located in each of the two well regions. The gate terminal is located on the top surface of the silicon carbide epitaxial substrate between the two source regions, and has two opposing outer ends, each overlapping the two source regions. The drain terminal is a semiconductor device located on the bottom surface of the silicon carbide epitaxial substrate.
8. Step A, comprising the step of forming a first hard mask unit on the top surface of a silicon carbide epitaxial substrate, wherein the first hard mask unit has a first hard mask layer, a second hard mask layer, and a third hard mask layer stacked in order from the top surface of the silicon carbide epitaxial substrate upwards, Step B of the photolithography process involves etching the first hard mask unit from the third hard mask layer to the first hard mask layer to form a plurality of first openings that are spaced apart from each other, Step C involves doping the silicon carbide epitaxial substrate with a second type dopant by ion implantation through each of the first openings, thereby forming a plurality of well regions that are spaced apart from each other. Step D: After forming the etched first hard mask unit and the first mask film covering each of the first openings, remove the third hard mask layer and the first mask film covering each of the first openings such that each of the remaining thickness portions of the first mask film remaining at the boundary of each of the first openings defines a second opening having a size smaller than the size of each of the first openings. Step E is a step of performing a first ion implantation through each of the second openings to form a first low-concentration doped layer, and then performing a second ion implantation through each of the second openings to form a second low-concentration doped layer that is located below the first low-concentration doped layer and has a width wider than the width of the first low-concentration doped layer, wherein the first low-concentration doped layer is doped with a first type dopant, and the second low-concentration doped layer is doped with a second type dopant. Step F involves forming a fourth hard mask layer that covers the third hard mask layer, the first mask film, and the first hard mask layer exposed from the second opening, and then forming a second mask film that covers the fourth hard mask layer, and then removing a portion of the second mask film corresponding to the position of the third hard mask layer and the position of each second opening such that each of the remaining thickness portions of the second mask film remaining at the boundary of each second opening defines a third opening having a diameter smaller than the diameter of each second opening. A method for manufacturing a semiconductor device, comprising step G: ion implantation through each of the third openings to form a plurality of source regions extending downward from the top surface of the silicon carbide epitaxial substrate, wherein each of the source regions is doped with a first type dopant and has a doping concentration greater than the doping concentration of the first low-concentration doped layer and the doping concentration of the second low-concentration doped layer, and each of the source regions has a bottom end located at a depth between the depth of the bottom end of the first low-concentration doped layer and the depth of the bottom end of the second low-concentration doped layer.
9. A method for manufacturing a semiconductor device according to claim 8, further comprising step H: removing the first hard mask layer, the second hard mask layer, the third hard mask layer, the fourth hard mask layer, the first mask film and the second mask film; forming a patterned photoresist layer on the top surface of the silicon carbide epitaxial substrate by photolithography; defining a plurality of doping openings having a width smaller than the width of the source region; performing high-concentration ion implantation through each of the plurality of doping openings to form a high-concentration doped region doped with a type 2 dopant; and then removing the patterned photoresist layer.
10. Step I involves forming a second hard mask unit having a fifth hard mask layer, a sixth hard mask layer, and a seventh hard mask layer stacked sequentially from the top surface upward of the silicon carbide epitaxial substrate, and etching the seventh hard mask layer, the sixth hard mask layer, and the fifth hard mask layer until the depth reaches the fifth hard mask layer to form an opening between the two well regions. Step J involves removing a portion of the third mask film corresponding to the position of the top surface of the seventh hard mask layer and a portion of the bottom of the opening, such that a third mask film is formed to cover the etched second hard mask unit, and the remaining thickness of the third mask film in the opening of the second hard mask unit defines a fourth opening having a diameter smaller than the diameter of the opening and smaller than the minimum distance between two adjacent well regions. A method for manufacturing a semiconductor device according to claim 8 or 9, further comprising step K: performing ion implantation through a fourth opening to form a junction field-effect transistor region that is located between the two well regions without contact with the two well regions, extends downward from the top surface of the silicon carbide epitaxial substrate, and is doped with a first type dopant; and then removing the residual portion of the third mask film and the residual portion of the second hard mask unit.
11. Step L involves first forming a first insulating layer, a polycrystalline silicon layer, and a second insulating layer stacked sequentially from the top surface upward of the silicon carbide epitaxial substrate, then etching downward from the second insulating layer to the corresponding source region position using multiple photolithography processes to define the polycrystalline silicon layer as a gate terminal, forming recesses in each source region, and then sequentially forming an ohmic contact layer and a source electrode in each recess. Step M involves forming a protective unit that covers the source electrode, A method for manufacturing a semiconductor device according to claim 8, further comprising step N of forming an electrical connection unit that penetrates the protective unit and is electrically connected to the gate terminal and the source electrode, and is also electrically connected to the outside.
12. A method for manufacturing a semiconductor device according to claim 11, further comprising step O, forming a drain terminal by forming a metallic silicon layer and a metallic conductive layer stacked sequentially from the bottom surface downwards of the silicon carbide epitaxial substrate 2.