Concave glass via structure for glass substrates

Abstract

The present invention provides an apparatus equipped with a concave glass via structure for glass substrates. [Solution] Embodiments disclosed herein relate to an apparatus including a glass substrate having a first surface and a second surface opposite to the first surface. In the embodiment, an opening is provided through the thickness of the substrate, and a first via is provided in the opening. In the embodiment, a first layer is on the first surface, and the first layer fills a first portion of the opening adjacent to the first via. In the embodiment, a second via penetrates the first layer in the opening, and the second via is electrically coupled to the first via. In the embodiment, a second layer is on the second surface, and the second layer fills a second portion of the opening adjacent to the first via. In the embodiment, a third via penetrates the second layer in the opening, and the third via is electrically coupled to the first via.

Description

[Background technology]

[0001] Glass cores for packaging substrates are an attractive option because they offer improved rigidity, flatness, and wiring density compared to existing organic cores. However, glass is brittle, which presents several challenges in manufacturing. One problem with glass cores is the high stress generated by through-glass vias (TGVs) formed through the core. Conventional plating involves creating a seed layer along the sidewall of the via opening and then forming the via from the sidewall through plating. This ensures a strong mechanical bond between the via and the glass core. However, during thermal cycling tests, the via expands more than the glass core, generating high stress on the glass core. This high stress can lead to defects such as cracks, which significantly impact the reliability of the glass core. [Brief explanation of the drawing]

[0002] [Figure 1] This is a cross-sectional view of a portion of a glass core and a glass through via (TGV) according to the embodiment, showing a high-stress region at the corner interface between the glass core and the TGV. [Figure 2A] This is a cross-sectional view showing a part of a TGV having a recessed structure in which a buffer layer covers the glass core and the corner interface between the glass core and the TGV, according to an embodiment. [Figure 2B] This is a cross-sectional view of the glass core of Figure 2A, representing the entire TGV according to the embodiment. [Figure 2C] This is a cross-sectional view of a glass core with a via opening having an hourglass-shaped profile, according to the embodiment. [Figure 3A] This is a cross-sectional view showing a process for forming a TGV by a sintering process in a package substrate, in which a dielectric layer is provided on the corner interface between the glass core and the TGV, according to an embodiment. [Figure 3B]This is a cross-sectional view showing a process for forming a TGV by a sintering process in a package substrate, in which a dielectric layer is provided on the corner interface between the glass core and the TGV, according to an embodiment. [Figure 3C] This is a cross-sectional view showing a process for forming a TGV by a sintering process in a package substrate, in which a dielectric layer is provided on the corner interface between the glass core and the TGV, according to an embodiment. [Figure 3D] This is a cross-sectional view showing a process for forming a TGV by a sintering process in a package substrate, in which a dielectric layer is provided on the corner interface between the glass core and the TGV, according to an embodiment. [Figure 3E] This is a cross-sectional view showing a process for forming a TGV by a sintering process in a package substrate, in which a dielectric layer is provided on the corner interface between the glass core and the TGV, according to an embodiment. [Figure 3F] This is a cross-sectional view showing a process for forming a TGV by a sintering process in a package substrate, in which a dielectric layer is provided on the corner interface between the glass core and the TGV, according to an embodiment. [Figure 3G] This is a cross-sectional view showing a process for forming a TGV by a sintering process in a package substrate, in which a dielectric layer is provided on the corner interface between the glass core and the TGV, according to an embodiment. [Figure 4A] This is a cross-sectional view showing a repeating sintering process for forming a TGV according to an embodiment. [Figure 4B] This is a cross-sectional view showing a repeating sintering process for forming a TGV according to an embodiment. [Figure 4C] This is a cross-sectional view showing a repeating sintering process for forming a TGV according to an embodiment. [Figure 5] This is a flowchart of the process for forming TGV in a glass core by a sintering process according to the embodiment. [Figure 6] This is a cross-sectional view of an electronic system having a package substrate with a glass core including a TGV formed by a sintering process, according to an embodiment. [Figure 7]This is a schematic diagram of a computing device configured according to an embodiment. [Modes for carrying out the invention]

[0003] This specification describes glass substrates having through-glass vias (TGVs) formed by a sintering process, according to various embodiments. In the following description, various aspects of the embodiments are described using terminology commonly used by those skilled in the art, so as to convey the essence of their research to others skilled in the art. However, as will be obvious to those skilled in the art, this disclosure may be carried out by only some of the aspects described. For illustrative purposes, specific numbers, materials and configurations are given so as to provide a complete understanding of the embodiments. However, as will be obvious to those skilled in the art, this disclosure may be carried out without specific details. In other instances, well-known features are omitted or simplified so as not to obscure the embodiments.

[0004] While various aspects are described as multiple separate actions, that is, in the manner most helpful in understanding this disclosure, the order in which they are described should not be interpreted as indicating that these actions necessarily depend on the order in which they are presented. In particular, these actions do not need to be performed in the order in which they are presented.

[0005] Various embodiments or aspects of the present disclosure are described in the specification. In some implementations, different embodiments are implemented separately. However, embodiments are not limited to those that are implemented separately. For example, two or more different embodiments may be combined to be implemented as a single device, process, structure, etc. In some cases, the whole of various embodiments may be combined. In other cases, a part of the first embodiment may be combined with a part of one or more different embodiments. For example, a part of the first embodiment may be combined with a part of the second embodiment, or a part of the first embodiment may be combined with parts of the second and third embodiments.

[0006] As mentioned above, existing glass cores offer improved rigidity, flatness, and wiring density compared to organic cores. However, the strong mechanical bond between the through-glass vias (TGVs) and the glass core generates high stress in the glass core during thermal cycling. As a result, defects such as cracks can occur in the glass core. This negatively impacts the reliability of such vias. Furthermore, the high aspect ratio of TGVs makes it difficult to form void-free TGVs cost-effectively. For example, the TGV sidewalls can be seeded using an atomic layer deposition process, followed by electroplating with delicate engineering focusing on the TGV geometry and plating dynamics at various points during the plating stage. However, atomic layer deposition is a time-consuming and costly process, and such processes may be difficult to implement in mass production environments. When the aspect ratio (height:diameter) of the TGV exceeds approximately 10:1, sidewall-driven electroplating becomes difficult. Moreover, process quality is highly sensitive to the TGV sidewall profile.

[0007] The stress applied to the glass core is highest at the sharp edges between the TGV and the glass core. For example, the corners of the glass core at the edges of the opening where the TGV is formed often cause defects such as cracks in the glass core. An example of such a TGV is shown in Figure 1.

[0008] Referring now to Figure 1, a cross-sectional view of the glass core 110 including a portion of the TGV120 (i.e., the upper half of the TGV120) is shown according to an embodiment. As shown, the TGV120 may extend through an opening in the glass core 110 defined by a side wall 113. A buffer layer 107 may be provided on the upper surface of the glass core 110. The TGV120 may penetrate the buffer layer 107 to contact the top covering pad 125. As indicated by the dashed circle, a corner region 103 is an interface where multiple different materials come into contact with each other at a single point. For example, in Figure 1, the glass core 110, the TGV120, and the buffer layer 107 meet at a corner region 103. The different materials have different coefficients of thermal expansion (CTE). This results in significant stress during thermal cycling because the expansions of the three materials are not equal. Unequal expansion in sharp corner regions 103 can cause high stress concentrations within the glass core 110. High stress concentrations can lead to defects such as cracks within the glass core 110. In other cases, the overlay pad 125 may also be in direct contact with the glass core 110. That is, the buffer layer 107 surrounds the overlay pad 125. In such embodiments, the stress induced in corner regions 103 becomes even more severe.

[0009] Accordingly, embodiments disclosed herein may include the formation of a TGV including a concave surface that allows a buffer layer to be positioned in the corner region of an opening penetrating a glass core. For example, a first portion of the via is formed by a sintering process that allows for a volume reduction of the first portion of the via within the via opening. A buffer layer (e.g., an organic dielectric material) fills the remainder of the via opening, and a second portion of the via is formed through the thickness of the buffer layer. An example of such a TGV is shown in Figure 2A.

[0010] Referring now to Figure 2A, a partial cross-sectional view of the glass core 210 is shown according to the embodiment. In the embodiment, the via opening defined by the side wall 213 is provided through the thickness of the glass core 210. The via opening can be formed by any suitable process. For example, in some embodiments, a laser-assisted etching process may be used to form the via opening. In the embodiment, the via opening may be a via opening with a high aspect ratio. For example, the aspect ratio (height:diameter) of the via opening may be 5:1 or greater, 10:1 or greater, or 20:1 or greater. The embodiment may also be used for via openings with smaller aspect ratios.

[0011] In embodiments, the glass core 210 may be substantially entirely glass. The glass core 210 may be a solid mass containing a glass material having an amorphous crystalline structure, and the solid glass core may also include various structures filled with one or more other materials (e.g., metals, metal alloys, dielectric materials, etc.), such as vias, cavities, channels, or other features. Thus, the glass core 210 can be distinguished from, for example, the “prepreg” or “FR4” core of a printed circuit board (PCB) substrate, which typically contains glass fibers embedded in a resin-organic material such as epoxy.

[0012] The glass core 210 can have any suitable dimensions. In certain embodiments, the glass core 210 can have a thickness that is about 50 μm or greater. For example, the thickness of the glass core 210 can be between about 50 μm and about 1.4 mm. Note that smaller or larger thicknesses may also be used. The glass core 210 can have an edge dimension (e.g., length, width, etc.) that is about 10 mm or greater. For example, the edge dimension can be between about 10 mm and about 250 mm. Note that larger or smaller edge dimensions may also be used. More generally, the area dimensions of the glass core 210 (from a top view) can be between about 10 mm × 10 mm and about 250 mm × 250 mm. In an embodiment, the glass core 210 can have a first side that is perpendicular or orthogonal to a second side. In a more general embodiment, the glass core 210 can have a rectangular prism volume with sections (e.g., vias) removed and filled with another material (e.g., metal, etc.).

[0013] The glass core 210 can have a single monolithic layer of glass. In other embodiments, the glass core 210 may have two or more individual glass layers stacked on top of each other. The individual glass layers may be provided in direct contact with each other, or the individual glass layers may be mechanically bonded to each other by an adhesive or the like. The individual glass layers in the glass core 210 can each have a thickness that is less than about 50 μm. For example, the individual glass layers in the glass core 210 can have a thickness between about 25 μm and about 50 μm. Note that the individual glass layers may have larger or smaller thicknesses in some embodiments. As used herein, "about" can refer to a range of values within 10% of the stated value. For example, 50 μm can refer to a range between 45 μm and 55 μm.

[0014] The glass core 210 may be any suitable glass formulation having the required mechanical robustness and compatibility with the processes of manufacturing and assembling the semiconductor package. For example, the glass core 210 may have aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, fused silica, etc. In some embodiments, the glass core 210 may include one or more additives such as, but not limited to, Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, or Zn. More generally, the glass core 210 may include any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc in addition to silicon and oxygen. In an embodiment, the glass core 210 may include at least 23% silicon (by weight) and at least 26% oxygen (by weight). In some embodiments, the glass core 210 may further include at least 5% aluminum (by weight).

[0015] In FIG. 2A, a part of the TGV (i.e., the upper part) is shown according to an embodiment. In an embodiment, the TGV may have a first via portion 231 and a second via portion 232. The first via portion 231 may have a surface 204 recessed below the upper surface 211. The first via portion 231 may be entirely within the via opening. The second via portion 232 may penetrate the buffer layer 207 above the upper surface 211 of the glass core 210, and the second via portion 232 may extend within the via opening. The second via portion 232 may be electrically coupled to the first via portion 231. For example, in FIG. 2A, the first via portion 231 is in direct contact with the second via portion 232. As will be described in more detail herein, a seed layer or other intervening conductive layer may be provided between the first via portion 231 and the second via portion 232.

[0016] In this embodiment, the buffer layer 207 may also fill a portion of the via opening. The second via portion 232 may penetrate the portion of the buffer layer 207 within the via opening. That is, the second via portion 232 may be surrounded by the buffer layer 207 such that the second via portion 232 is separated from the side wall 213 of the via opening by the buffer layer 207. In contrast, the first via portion 231 may be in direct contact with the side wall 213 of the via opening. In other words, the first via portion 231 may be in direct contact with the glass core 210, while the second via portion 232 may be separated from the glass core 210 by the buffer layer 207.

[0017] In an embodiment, the side wall 236 of the second via portion 232 may be inclined with respect to the upper surface 211 of the glass core 210. In an embodiment, the slope of the side wall 236 may be the result of a patterning process used to form an opening through the buffer layer 207. For example, an opening through the buffer layer 207 may be formed using a laser ablation process. In an embodiment, a pad 225 may be provided on the buffer layer 207 and electrically coupled to the second via portion 232.

[0018] As shown in the figure, the corner region 203 of the glass core 210 where the side wall 213 of the via opening contacts the upper surface 211 of the glass core 210 is covered by a buffer layer 207. This allows the second via portion 232 to be separated from the corner region 203. The buffer layer 207 may have a polymer material, a polymer-based composite material, etc. In the embodiment, the buffer layer 207 may have a lower mechanical modulus compared to the mechanical modulus of the first via portion 231 and / or the second via portion 232. It can absorb stress induced by the second via portion 232. Thus, stress concentration in the corner region 203 is reduced. This improves the mechanical robustness of the glass core 210, as it reduces the likelihood of the glass core 210 cracking during thermal cycling.

[0019] In this embodiment, the first via portion 231 may have a first porosity, and the second via portion 232 may have a second porosity different from the first porosity. For example, the porosity of the first via portion 231 may be higher than that of the second via portion 232. The difference in porosity may be the result of different processes used to form the first via portion 231 and the second via portion 232. For example, the first via portion 231 may be formed by a sintering process, and the second via portion 232 may be formed by an electroplating process. The porosity of a material can be defined as the area of ​​the cross-section containing solid material relative to the area of ​​the cross-section containing space, gaps (voids), etc. In this embodiment, the first via portion 231 may have a porosity of about 20% or less (i.e., about 20% or less of the cross-sectional area consists of space or gaps, and about 80% or more of the cross-sectional area consists of solid material). The embodiment may include a first via portion 231 having a porosity of about 10% or less, about 5% or less, or about 1% or less. The second via portion 232 may have a porosity of about 5% or less, about 1% or less, or about 0.5% or less.

[0020] Referring now to Figure 2B, a cross-sectional view of the glass core 210 is shown according to an embodiment. The glass core 210 in Figure 2B may be similar to the glass core 210 described in relation to Figure 2A. However, the overall height of the TGV is shown in Figure 2B. As shown, the glass core 210 may have a bottom surface 212, and the first via portion 231 may have a surface 205 recessed from the bottom surface 212 of the glass core 210. Similar to the top surface of the TGV, the buffer layer 208 may partially fill a portion of the via opening, and the third via portion 233 may penetrate the buffer layer 208. That is, the buffer layer 208 may separate the third via portion 233 from the glass core 210 in order to reduce stress in the glass core 210.

[0021] In some embodiments, the first via portion 231 may have a height (between surfaces 204 and 205) smaller than the thickness of the glass core 210 between the top surface 211 and the bottom surface 212. In some embodiments, the first via portion 231 may have a midpoint between surfaces 204 and 205, and the glass core 210 may have a midpoint between the top surface 211 and the bottom surface 212. In some embodiments, the line connecting the midpoint of the first via portion 231 to the glass core 210 may be substantially parallel to the top surface 211 of the glass core.

[0022] In the embodiments shown, the side walls 213 of the via opening are substantially vertical (i.e., perpendicular to the top surface 211 and bottom surface 212 of the glass core 210). The embodiments may also include side walls 213 that are tapered or have any other profile, as will be described in further detail herein. In the embodiments, the width of the first via portion 231 may be wider than the widths of the second via portion 232 and the third via portion 233.

[0023] In Figure 2B, seed layers 228 are shown between the second via portion 232 and the buffer layer 207, and between the third via portion 233 and the buffer layer 208. Seed layers 228 can be used to plate the second via portion 232, pad 225, third via portion 233, and pad 226. For example, the second via portion 232, pad 225, third via portion 233, and pad 226 can be plated using an electroplating process. In some embodiments, a portion of the seed layer 228 can separate the first via portion 231 from the second via portion 232, and a portion of the seed layer 228 can separate the first via portion 231 from the third via portion 233. Furthermore, seed layers 228 can separate the second via portion 232 from the buffer layer 207, and seed layers 228 can separate the third via portion 233 from the buffer layer 208. The use of the plating process results in both the second via portion 232 and the third via portion 233 having lower porosity than the first via portion 231 (which may be formed by the sintering process).

[0024] Referring now to Figure 2C, a cross-section of the glass core 210 is shown according to a further embodiment. The glass core 210 in Figure 2C may be similar to the glass core 210 in Figure 2B, except for the profile of the side wall 213. For example, the side wall 213 in Figure 2C may be inclined with respect to the top surface 211 and / or bottom surface 212 of the glass core 210. In the specific embodiment shown in Figure 2C, the side wall 213 may form an hourglass-shaped via opening profile. In other embodiments, the side wall 213 may form a via opening with a single taper (for example, the via opening is wider on the top surface of the glass core 210 than on the bottom surface 212 of the glass core 210). In some embodiments, the first via portion 231 may have a non-uniform diameter over the height of the first via portion 231.

[0025] Referring now to Figures 3A to 3G, a series of cross-sectional views are shown illustrating a process for forming a package substrate having a glass core including a TGV formed by a sintering process, according to the embodiment.

[0026] Referring now to Figure 3A, a cross-sectional view of the glass core 310 is shown according to an embodiment. In the embodiment, the glass core 310 may be similar to either a glass core or a glass substrate, which are described in more detail herein. In the embodiment shown, a single unit of glass core 310 is shown. Of course, a glass panel or glass substrate having multiple units of glass core 310 may be used according to a similar embodiment. In the embodiment, the glass core 310 may have a top surface 311 and a bottom surface 312. Multiple via openings 316 may be formed through the thickness of the glass core 310. In the embodiment shown, the side walls 313 of the via openings 316 are substantially vertical. Of course, in some embodiments, the side walls 313 may be inclined with respect to the top surface 311 or the bottom surface 312. The via openings 316 may be formed by any suitable plating process, such as a laser-assisted etching process. In the embodiment, the via openings 316 may have an aspect ratio (height:diameter) of about 5:1 or more, about 10:1 or more, or about 20:1 or more. Furthermore, via openings 316 having a smaller aspect ratio may also be advantageous from the embodiments described herein.

[0027] Referring now to Figure 3B, a cross-sectional view of the glass core 310 after conductive nanopaste 338 has been applied to the via opening is shown according to the embodiment. In the embodiment, the nanopaste 338 may have a copper-based nanopaste material. The nanopaste 338 may be applied to the via opening 316 by a printing process (e.g., a screen printing process, a stencil printing process, etc.). In the embodiment, the nanopaste 338 may substantially fill the via opening 316.

[0028] Referring now to Figure 3C, a cross-sectional view of the glass core 310 after the nanopaste 338 has been sintered to form a first via portion 331 is shown according to the embodiment. As shown, the sintering process can reduce the volume of the nanopaste 338 so that the solid first via portion 331 has an upper surface 304 recessed from the upper surface 311 of the glass core 310 and a lower surface 305 recessed from the lower surface 312 of the glass core 310. That is, the upper and lower via openings 316 of the first via portion 331 are empty.

[0029] In some embodiments, the sintering process may be designed to reduce the porosity of the first via portion 331. For example, the temperature of the sintering process may be about 250°C or higher, or about 350°C or higher. In some embodiments, the sintering process may be carried out in a reducing environment (e.g., an environment exposed to hydrogen, formic acid, etc.). In some embodiments, the first via portion 331 may have a porosity of about 10% or less, about 5% or less, or about 1% or less.

[0030] Referring to Figure 3D, a cross-sectional view of the glass core 310 after the buffer layer 307 has been applied to the top surface 311 and the buffer layer 308 has been applied to the bottom surface 312 is shown according to the embodiment. In the embodiment, the buffer layers 307 and 308 may have an organic dielectric material such as an organic build-up material. The buffer layers 307 and 308 may be applied by a liquid process, a film lamination process, or the like.

[0031] As shown, buffer layers 307 and 308 may fill portions of the via opening 316 above and below the first via portion 331. That is, in some embodiments, buffer layers 307 and 308 may be in direct contact with the first via portion 331. However, naturally, there may be no buffer layer (or other intervening layer) between the side wall of the first via portion 331 and the side wall 313 of the glass core 310. That is, in some embodiments, the first via portion 331 may be in direct contact with the glass core 310.

[0032] Referring now to Figure 3E, a cross-sectional view of the glass core 310 after the buffer layer opening 319 has been formed through the buffer layers 307 and 308 is shown according to the embodiment. The buffer layer opening 319 may be formed by a laser ablation process or other suitable subtractive patterning process. The formation of the buffer layer opening 319 does not require the removal of the entire buffer layers 307 and 308 from the via opening 316. That is, the buffer layer opening 319 may be narrower than the via opening 316.

[0033] Referring now to Figure 3F, a cross-sectional view of the glass core 310 after the second via portion 332, pad 325, third via portion 333, and pad 326 have been formed is shown according to the embodiment. In the embodiment, the second via portion 332, pad 325, third via portion 333, and pad 326 may be formed by a plating process such as an electroplating process. Although not shown, a seed layer may be formed on the buffer layers 307 and 308 to enable plating. For example, a seed layer similar to the seed layer 228 described above may be used for the plating process. By using a plating process, the second via portion 332 and the third via portion 333 may have a lower porosity than the first via portion 331. Furthermore, although shown in Figure 3F as having different shading, the first via portion 331, the second via portion 332, and the third via portion 333 may, of course, have substantially the same composition. For example, the first via portion 331, the second via portion 332, and the third via portion 333 may be substantially made of copper in some embodiments.

[0034] Referring now to Figure 3G, a cross-sectional view of a package substrate having a glass core 310 is shown according to an embodiment. In an embodiment, the glass core 310 may be covered by an upper build-up layer 351 over a buffer layer 307 and by a bottom build-up layer 352 over a buffer layer 308. In an embodiment, the upper build-up layer 351 and the bottom build-up layer 352 may each have multiple laminated organic layers (e.g., build-up film layers). In some embodiments, the upper build-up layer 351 and the bottom build-up layer 352 may have the same material as the buffer layers 307 and 308. In an embodiment, electrically conductive wiring (not shown) in the upper build-up layer 351 can electrically couple pads 325 to first-level interconnects (FLI) 354, and electrically conductive wiring (not shown) in the bottom build-up layer 352 can electrically couple pads 326 to second-level interconnects (SLI) 353. Electrically conductive wiring may include pads, traces, vias, etc. In some embodiments, one or more dies 355 may be electrically coupled to the upper build-up layer 351 by the FLI 354. In some embodiments, a bridge substrate (not shown) embedded in or provided on the upper build-up layer 351 may electrically couple two or more dies 355 together.

[0035] Referring now to Figures 4A to 4C, a series of cross-sectional views illustrating an alternative process for forming the first via portion of the TGV within the glass core are shown according to the embodiment.

[0036] Referring now to Figure 4A, the first via portion 431 sintered within the via opening 416 A A cross-sectional view of the glass core 410 having the first via portion 431 is shown according to the embodiment. Figure 4A shows the glass core 410 and the first via portion 431 A is the first via section 431 A Except for the height, it can be similar to the glass core 310 and the first via portion 331 in Figure 3C. For example, the sintering process is similar to the first via portion 431 Acan result in a greater volume reduction. In such embodiments, the empty portion of the via opening 416 may become too large. Therefore, an iterative sintering process may be used.

[0037] Referring now to FIG. 4B, a cross-sectional view of the glass core 410 after the conductive nanopaste 438 has been applied within the via opening 416 over the first via portion 431A is shown in accordance with an embodiment. The nanopaste 438 can be applied by a screen printing process, a stencil printing process, or the like.

[0038] Referring now to FIG. 4C, a cross-sectional view of the glass core 410 after a sintering process has been used to form the first via portion 431 A above and below the first via portion 431 B is shown in accordance with an embodiment. The sintering process of FIG. 4C can be similar to any of the sintering processes described in more detail herein. Due to the volume reduction of the first via portion 431 B , a desired recess with respect to above and below the via opening 416 is obtained. In other embodiments, more than two nanopaste deposition and sintering cycles may be used. In embodiments including multiple sintering cycles, as shown in FIG. 4C, seams may become visible within the first via portion (i.e., the first via portions 431 A and 431 B ).

[0039] Referring now to FIG. 5, a flow diagram representing a process 560 for forming TGVs in a glass core by a sintering process is shown in accordance with an embodiment. In an embodiment, the process 560 can be similar to any of the sintering processes described in more detail. For example, the TGV can have a sintered region with a recessed top and bottom surface and a plating region penetrating the buffer layer.

[0040] In embodiments, process 560 may begin with operation 561, which includes forming a first opening through a substrate containing a glass layer. In embodiments, the substrate may be similar to any of the glass cores described in further detail herein. In embodiments, the first opening may be considered a via opening. The first opening may be formed by any suitable plating process, such as a laser-assisted etching process.

[0041] In an embodiment, process 560 may be followed by operation 562, which includes filling the first opening with conductive nanopaste. In an embodiment, the conductive nanopaste may have copper nanoparticles or the like. The conductive nanopaste may be applied to the first opening by a screen printing process, a stencil printing process, or the like.

[0042] In some embodiments, process 560 may be followed by operation 563, which includes sintering a conductive nanopaste to form a first via at the first opening. In some embodiments, the sintering process may result in the formation of a first via recessed from above and below the first opening. The sintering process may be similar to any of the sintering processes described in further detail herein. For example, the sintering temperature may be about 250 degrees or higher, or about 350 degrees or higher. In some embodiments, the sintering process may be carried out in a reducing environment (e.g., an environment exposed to hydrogen, formic acid, etc.).

[0043] In the embodiment, operations 562 and 563 may be repeated any number of times to provide a first via of the desired dimensions within the first opening. For example, as in the embodiment described with respect to Figures 4A-4C, the cyclic nanopaste extrusion and sintering process can be repeated multiple times.

[0044] In an embodiment, process 560 may be followed by operation 564, which includes forming a buffer layer on the substrate. In an embodiment, the buffer layer fills a portion of the first opening on the first via. The buffer layer may have an organic dielectric material or the like. The buffer layer may be applied by a liquid process, a lamination process, or the like.

[0045] In an embodiment, process 560 may be followed by operation 565, which includes forming a second opening by penetrating the buffer layer to expose a first via. In an embodiment, the second opening may be formed by a laser drilling process or any other suitable substrate patterning process. In an embodiment, the width of the second opening may be narrower than the width of the first opening. As such, a portion of the buffer layer may remain in the first opening after the second opening has been formed.

[0046] In an embodiment, process 560 may be followed by operation 566, which includes forming a second via at the second opening. In an embodiment, the second via is electrically coupled to the first via. In an embodiment, the second via may be formed by an electroplating process, for example. For example, a seed layer may be formed on the buffer layer for plating the second via. The porosity of the first and second vias may differ depending on the different processes used to form them. For example, the first via may have a higher porosity than the second via.

[0047] In some embodiments, the resulting substrate can then be integrated onto a package substrate by a typical build-up layer manufacturing process. For example, multiple stacked layers are patterned to form electrical wiring. In some embodiments, the electrical wiring in the build-up layer may electrically couple second vias to a die bonded to the package substrate.

[0048] Referring now to Figure 6, a cross-sectional view of the electronic system 690 is shown according to an embodiment. In an embodiment, the electronic system 690 may have a board 691 such as a printed circuit board (PCB), motherboard, etc. In an embodiment, the board 691 may be coupled to a package substrate 650 by an SLI 653. In an embodiment, the SLI 653 may have solder balls, sockets, etc.

[0049] In embodiments, the package substrate 650 may be similar to any of the package substrates described in further detail herein. In embodiments, the package substrate 650 may have a glass core 610 including a TGV. In embodiments, the TGV may have a first via portion 631, a second via portion 632 above the first via portion 631, and a third via portion 633 below the first via portion 631. The second via portion 632 and the third via portion 633 may be separated from the glass core 610 by parts of buffer layers 607 and 608, respectively. The TGV structure of the glass core 610 may be similar to any of the TGV structures described in further detail herein.

[0050] In some embodiments, the package substrate 650 may also have build-up layers 651 and 652 provided above and below the glass core 610. The build-up layer 651 may include electrical wiring (not shown) that electrically connects the pads to the FLI 654, and the build-up layer 652 may include electrical wiring (not shown) that electrically connects the pads 626 to the SLI 653.

[0051] In embodiments, one or more dies 655 may be coupled to the build-up layer 651 by an FLI 654. The FLI 654 may be any suitable FLI architecture, such as solder balls, copper bumps, or a hybrid bonding interface. In embodiments, one or more dies 655 may be any type of die (e.g., processor dies (e.g., central processing unit (CPU), graphics processing unit (GPU), XPU), memory dies, communication dies, power management dies, and / or similar). In embodiments, two or more dies 655 may be electrically coupled together by a bridge (not shown) embedded in or provided on the build-up layer 651.

[0052] Figure 7 shows a computing device 700 according to one embodiment of the present disclosure. The computing device 700 houses a board 702. The board 702 may include, but is not limited to, a number of components including a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some embodiments, at least one communication chip 706 is also physically and electrically coupled to the board 702. In further embodiments, the communication chip 706 is part of the processor 704.

[0053] Other such components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, crypto processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0054] The communication chip 706 enables wireless communication for the transfer of data to and from the computing device 700. The term “wireless” and its derivatives are sometimes used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the devices in question do not contain any wires, although in some embodiments they may not contain wires. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long-Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth®, and their derivatives, as well as any other wireless protocols designed as 3G, 4G, 5G, and later. The computing device 700 may include multiple communication chips 706. For example, a first communication chip 706 may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth, and a second communication chip 706 may be dedicated to longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0055] The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some embodiments of this disclosure, the integrated circuit die of the processor may be a portion of a package substrate having a glass core including a TGV formed by a sintering process, according to embodiments described herein. The term “processor” can mean any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory.

[0056] The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In another embodiment of this disclosure, the integrated circuit die of the communication chip may be a portion of a package substrate having a glass core including a TGV formed by a sintering process, according to the embodiments described herein.

[0057] In embodiments, the computing device 700 may be a part of any device. For example, the computing device may be a part of a personal computer, server, mobile device, tablet, automobile, etc. That is, the computing device 700 is not limited to being used in any particular type of system, and may be included in any device that may benefit from computing capabilities.

[0058] The foregoing description of the manifested practices of this disclosure, including that contained in the abstract, is not intended to be exhaustive or to limit the disclosure to the exact form disclosed. While specific practices of this disclosure and examples of the disclosure are described herein for illustrative purposes only, various equivalent modifications are possible within the scope of this disclosure, as a person skilled in the art would recognize.

[0059] These changes may be made to this disclosure in light of the detailed description above. The terms used in the subsequent claims should not be construed as limiting this disclosure to the specific practices disclosed in the specification and claims. Rather, the scope of this disclosure should be determined as a whole by the subsequent claims, which should be construed in accordance with established principles of claim interpretation.

[0060] Example 1: A substrate having a first surface and a second surface opposite to the first surface, and including a glass layer, An opening that penetrates the thickness of the aforementioned substrate, A first via having a third surface and a fourth surface opposite to the third surface within the opening, A first layer located on the first surface and filling the first portion of the opening adjacent to the third surface of the first via, In the opening, a second via penetrates the first layer and is electrically coupled to the first via, A second layer located on the second surface and filling the second portion of the opening adjacent to the fourth surface of the first via, In the opening, a third via penetrates the second layer and is electrically coupled to the first via. A device having.

[0061] Example 2: The first via has a first porosity, the second via has a second porosity, the third via has a third porosity, and the first porosity is greater than the second and third porosities. The apparatus described in Example 1.

[0062] Example 3: The first via has sintered metal, The apparatus described in Example 1 or Example 2.

[0063] Example 4: The first layer covers the corner of the substrate at the edge portion of the opening, The apparatus described in Examples 1-3.

[0064] Example 5: The side wall of the opening is inclined with respect to the first surface. The apparatus described in Examples 1-4.

[0065] Example 6: The first layer is in contact with the first via, and the second layer is in contact with the first via. The apparatus described in Examples 1-5.

[0066] Example 7: The first via is in direct contact with the substrate. The apparatus described in Examples 1-6.

[0067] Example 8: The first layer separates the second via from the substrate. The apparatus described in Examples 1-7.

[0068] Example 9: The second via and the first layer further have a seed layer, The apparatus described in Examples 1-8.

[0069] Example 10: The aforementioned substrate is the core of the package substrate. The apparatus described in Examples 1-9.

[0070] Example 11: A substrate having a thickness between the first and second surfaces and including a glass layer, An opening that penetrates the aforementioned substrate, A first via located within the opening and having a height lower than the thickness of the substrate, A layer located on the first surface of the substrate, filling a portion of the opening and in contact with the first via, A second via penetrates the aforementioned layer and is electrically coupled to the first via. A device having.

[0071] Example 12: The first via has a first porosity, the second via has a second porosity, and the first porosity is greater than the first porosity. The apparatus described in Example 11.

[0072] Example 13: The first via has sintered metal, The apparatus described in Example 12.

[0073] Example 14: The first via has a third surface and a fourth surface opposite to the third surface, The third surface is recessed from the first surface of the substrate. The fourth surface is recessed from the second surface of the substrate. The apparatus described in Examples 11-13.

[0074] Example 15: The first midpoint between the first and second surfaces, and the second midpoint between the third and fourth surfaces, are both located along a line substantially parallel to the first surface. The apparatus described in Example 14.

[0075] Example 16: The second via makes direct contact with the first via. The apparatus described in Examples 11-15.

[0076] Example 17: Board and, A package substrate coupled to the aforementioned board, The package substrate comprises a die bonded to the package substrate, The aforementioned package substrate is A core containing a glass layer, It has an opening that penetrates the core, A first via, a second via electrically coupled to the first via, and a layer surrounding the second via are located within the opening. Device.

[0077] Example 18: The first via has a first porosity, the second via has a second porosity, and the first porosity is greater than the second porosity. The apparatus described in Example 17.

[0078] Example 19: A third via electrically coupled to the first via and a second layer surrounding the third via are located within the opening. The apparatus described in Example 17 or Example 18.

[0079] Example 20: The layer covers the corner of the core at the edge portion of the opening. The apparatus described in Examples 17-19. [Explanation of Symbols]

[0080] 103,203 Corner area 107,207,208,307,308,607,608 buffer layers 110, 210, 310, 410, 610 glass core 113,213,313 side wall 120 TGV 228 seed layers 231,331,431 A ,431 B ,631 First via section 232,332,632 Second via section 233,333,633 Third via section 316,416 via openings 338,438 Conductive Nanopaste 351 Upper build-up layer 352 Bottom build-up layer 650 Package Substrates 690 Electronic Systems 691,702 boards 700 Computing Devices 704 Processor 706 Communication Chip

Claims

1. A substrate having a first surface and a second surface opposite to the first surface, and including a glass layer, An opening that penetrates the thickness of the aforementioned substrate, A first via having a third surface and a fourth surface opposite to the third surface within the opening, A first layer located on the first surface and filling the first portion of the opening adjacent to the third surface of the first via, In the opening, a second via penetrates the first layer and is electrically coupled to the first via, A second layer located on the second surface and filling the second portion of the opening adjacent to the fourth surface of the first via, In the opening, a third via penetrates the second layer and is electrically coupled to the first via. A device having.

2. The first via has a first porosity, the second via has a second porosity, the third via has a third porosity, and the first porosity is greater than the second and third porosities. The apparatus according to claim 1.

3. The first via has sintered metal, The apparatus according to claim 1 or 2.

4. The first layer covers the corner of the substrate at the edge portion of the opening. The apparatus according to claim 1 or 2.

5. The side wall of the opening is inclined with respect to the first surface. The apparatus according to claim 1 or 2.

6. The first layer is in contact with the first via, and the second layer is in contact with the first via. The apparatus according to claim 1 or 2.

7. The first via is in direct contact with the substrate. The apparatus according to claim 1 or 2.

8. The first layer separates the second via from the substrate. The apparatus according to claim 1 or 2.

9. The second via and the first layer further have a seed layer, The apparatus according to claim 1 or 2.

10. The aforementioned substrate is the core of the package substrate. The apparatus according to claim 1 or 2.

11. A substrate having a thickness between the first and second surfaces and including a glass layer, An opening that penetrates the aforementioned substrate, A first via located within the opening and having a height lower than the thickness of the substrate, A layer located on the first surface of the substrate, filling a portion of the opening and in contact with the first via, A second via penetrates the aforementioned layer and is electrically coupled to the first via. A device having.

12. The first via has a first porosity, the second via has a second porosity, and the first porosity is greater than the first porosity. The apparatus according to claim 11.

13. The first via has sintered metal, The apparatus according to claim 12.

14. The first via has a third surface and a fourth surface opposite to the third surface. The third surface is recessed from the first surface of the substrate. The fourth surface is recessed from the second surface of the substrate. The apparatus according to claim 11 or 12.

15. The first midpoint between the first and second surfaces, and the second midpoint between the third and fourth surfaces, are both located along a line substantially parallel to the first surface. The apparatus according to claim 14.

16. The second via is in direct contact with the first via. The apparatus according to claim 11 or 12.

17. Board and, A package substrate coupled to the aforementioned board, The package substrate comprises a die bonded to the package substrate, The aforementioned package substrate is A core containing a glass layer, It has an opening that penetrates the core, A first via, a second via electrically coupled to the first via, and a layer surrounding the second via are located within the opening. Device.

18. The first via has a first porosity, the second via has a second porosity, and the first porosity is greater than the second porosity. The apparatus according to claim 17.

19. A third via electrically coupled to the first via and a second layer surrounding the third via are located within the opening. The apparatus according to claim 17 or 18.

20. The layer covers the corner of the core at the edge portion of the opening. The apparatus according to claim 17 or 18.

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