Electronic component embedded substrate, and method for manufacturing an electronic component embedded substrate

Abstract

Improving the quality of circuit boards with embedded electronic components. [Solution] The electronic component embedded substrate of the embodiment has a core substrate having a first surface and a second surface opposite to the first surface, and having openings that open to the first surface and the second surface; an electronic component housed in the opening; a first surface side resin layer including a first surface side lower layer that covers the electronic component and the first surface on the first surface side, and a first surface side upper layer laminated on the first surface side lower layer; a second surface side resin layer including a filling resin that fills the opening on the second surface side, covers the electronic component and reaches the first surface side lower layer, a second surface side lower layer that is integral with the filling resin and covers the second surface, and a second surface side upper layer laminated on the second surface side lower layer.

Description

【Technical Field】 【0001】 The technology disclosed herein relates to a substrate with built-in electronic components and a method for manufacturing a substrate with built-in electronic components. 【Background Art】 【0002】 Patent Document 1 describes a wiring board having a core portion having an opening penetrating between a first surface and a second surface, a wiring layer formed on an outer surface of the core portion, a chip capacitor, and an insulating layer that fills the opening so as to cover a part of a side surface of the chip capacitor and covers the second surface of the core portion. This wiring board has an interlayer insulating layer covering the second surface of the insulating layer and an interlayer insulating layer covering the first surface of the core portion and the chip capacitor exposed from the insulating layer. Further, this wiring board has a wiring layer connected to the chip capacitor via a via wiring penetrating the interlayer insulating layer and a wiring layer connected to the wiring layer via a via wiring penetrating the interlayer insulating layer and the insulating layer. 【Prior Art Documents】 【Patent Documents】 【0003】 【Patent Document 1】 Japanese Unexamined Patent Application Publication No. 2014-239186 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0004】 In a substrate with built-in electronic components in which an electronic component is housed in an opening, it is desirable to suppress warping of the substrate with built-in electronic components. 【Means for Solving the Problems】 【0005】 The electronic component embedded substrate of this disclosure has a core substrate having a first surface and a second surface opposite to the first surface, and having openings opening to the first surface and the second surface; an electronic component housed in the opening; a first surface side resin layer including a first surface side lower layer covering the electronic component and the first surface on the first surface side, and a first surface side upper layer laminated on the first surface side lower layer; a second surface side resin layer including a filling resin filling the opening on the second surface side, covering the electronic component and reaching the first surface side lower layer, a second surface side lower layer integral with the filling resin and covering the second surface, and a second surface side upper layer laminated on the second surface side lower layer. 【0006】 The present disclosure is a method for manufacturing an electronic component embedded substrate, comprising: forming an opening in the first surface and the second surface of a core substrate having a first surface and a second surface opposite to the first surface; housing an electronic component in the opening; filling the opening with resin from the second surface side to form a filling resin that covers the electronic component, while providing a second surface lower layer that covers the second surface with the resin; providing a first surface lower layer that covers the electronic component and the first surface from the first surface side with the resin; laminating a second surface upper layer on the second surface lower layer with resin; and laminating a first surface upper layer on the first surface lower layer with resin. 【0007】 According to embodiments of this disclosure, warping of an electronic component-embedded substrate in which an electronic component is housed in an opening can be suppressed. [Brief explanation of the drawing] 【0008】 [Figure 1] This is a cross-sectional view showing an electronic component embedded substrate according to a first embodiment of the present disclosure. [Figure 2] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 3] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 4] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 5]This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 6] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 7] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 8] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 9] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 10] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 11] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 12] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 13] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Figure 14] This is a cross-sectional view showing an example of the manufacturing process for an electronic component embedded substrate according to the first embodiment of the present disclosure. [Modes for carrying out the invention] 【0009】 Hereinafter, an example of an embodiment of this disclosure will be described in detail with reference to the drawings. 【0010】 Components indicated by the same reference numeral in each drawing are considered to be the same or similar components. In the embodiments described below, redundant descriptions and reference numerals may be omitted. The drawings used in the following description are all schematic. The dimensional relationships and ratios of each element shown in the drawings do not necessarily correspond to reality. The dimensional relationships and ratios of each element do not necessarily correspond between multiple drawings. 【0011】 [First Embodiment] FIG. 1 is a cross-sectional view showing the electronic component-embedded substrate 10 of the embodiment. The electronic component-embedded substrate 10 has a core substrate 11. The core substrate 11 has a first surface 11F on the front side and a second surface 11S on the back side, that is, on the side opposite to the first surface 11F. The electronic component-embedded substrate 10 further has a first surface-side resin layer 50, a second surface-side resin layer 60, a resin insulating layer 21, and conductor patterns 12 and 22. The first surface-side resin layer 50 is formed on the first surface 11F of the core substrate 11. The second surface-side resin layer 60 is formed on the second surface 11S of the core substrate 11. 【0012】 The first surface-side resin layer 50 has a first surface-side lower layer 52 and a first surface-side upper layer 54. The second surface-side resin layer 60 has a second surface-side lower layer 62 and a second surface-side upper layer 64. 【0013】 The resin insulating layer 21 is laminated on the first surface-side upper layer 54 and on the second surface-side upper layer 64. In the example shown in FIG. 1, on both sides of the first surface 11F side and the second surface 11S side, the resin insulating layer 21 is a single layer. The resin insulating layer 21 may be a plurality of layers on both sides of the first surface 11F side and the second surface 11S side. 【0014】 The core substrate 11 has an insulating base material 13K. In the example shown in FIG. 1, the insulating base material 13K is a single layer. A plurality of insulating base materials 13K may be arranged in layers. 【0015】 On the outer surface in the thickness direction of the core substrate 11, the conductor pattern 12 is formed on the insulating base material 13K. In the example shown in FIG. 1, the thickness of the conductor pattern 12 on the first surface 11F side is about the same as the thickness of the conductor pattern 12 on the second surface 11S side. The thickness of the conductor pattern 12 on the first surface 11F side and the thickness of the conductor pattern 12 on the second surface 11S side may be different. 【0016】 The core substrate 11 includes the insulating base material 13K, the conductor pattern 12 on the first surface 11F side, and the conductor pattern 12 on the second surface side. 【0017】 The conductor pattern 22 is formed on the resin insulating layer 21. In the example shown in Figure 1, the thickness of the conductor pattern 22 on the first surface 11F side and the thickness of the conductor pattern 22 on the second surface 11S side are approximately the same. However, the thickness of the conductor pattern 22 on the first surface 11F side and the thickness of the conductor pattern 22 on the second surface 11S side may be different. 【0018】 A solder resist layer 26 is formed on top of the outermost conductor pattern 22. 【0019】 An opening 11A is formed in the core substrate 11. The opening 11A penetrates the core substrate 11 in the thickness direction. The opening 11A is open to the first surface 11F and the second surface 11S. 【0020】 An electronic component 80 is housed in the opening 11A. The type of electronic component 80 is not particularly limited. The electronic component 80 is, for example, a chip capacitor. 【0021】 The side of the electronic component 80 that is positioned on the first surface 11F side is defined as the first component surface 80F of the electronic component 80. The side of the electronic component 80 that is positioned on the second surface 11S side is defined as the second component surface 80S of the electronic component 80. 【0022】 The first component side 80F of the electronic component 80 is provided with terminal 81F. The second component side 80S of the electronic component 80 is provided with terminal 81S. 【0023】 The external height L1 of the electronic component 80 is shorter than the thickness T2 of the core substrate 11. The external height L1 of the electronic component 80 is the length from the outer surface of terminal 81F to the outer surface of terminal 81S. The thickness T2 of the core substrate 11 is the length from the conductor pattern 12 on the first surface 11F to the conductor pattern 12 on the second surface 11S. 【0024】 The external width W1 of the electronic component 80 is shorter than the opening width W2 of the opening 11A. The external width W1 of the electronic component 80 is the length between the sides 80G of the electronic component 80. The sides 80G of the electronic component 80 are spaced apart from the inner surface 11N of the opening 11A. 【0025】 On the first surface 11F side of the core substrate 11, the first component surface 80F of the electronic component 80 is substantially the same surface as the first surface 11F of the core substrate 11. The lower layer 52 on the first surface side covers the electronic component 80 and the first surface 11F on the first surface 11F side. 【0026】 The upper layer 54 on the first side is laminated onto the lower layer 52 on the first side. The surface of the lower layer 52 on the first side is the interface with the upper layer 54 on the first side. The surface of the lower layer 52 on the first side is roughened. Due to the roughening, the surface of the lower layer 52 on the first side has a surface roughness suitable for adhesion with the upper layer 54 on the first side. 【0027】 The resin material constituting the lower layer 52 on the first surface side may have the same composition as the resin material constituting the upper layer 54 on the first surface side, or it may have a different composition. 【0028】 On the second surface 11S side of the core substrate 11, the second component surface 80S of the electronic component 80 is positioned further inward in the thickness direction of the core substrate 11 than the second surface 11S of the core substrate 11. 【0029】 The gap between the electronic component 80 and the inner surface 11N of the opening 11A is filled with filler resin 30. The filler resin 30 is formed when the resin constituting the second surface lower layer 62 is also filled into the opening 11A. In other words, a part of the second surface lower layer 62 is filled into the opening 11A on the second surface 11S side to form the filler resin 30. The filler resin 30 covers the electronic component 80. The presence of the filler resin 30 between the electronic component 80 and the opening 11A fixes the electronic component 80 within the opening 11A. The filler resin 30 extends from the gap between the electronic component 80 and the inner surface 11N of the opening 11A to the first surface lower layer 52. 【0030】 The lower layer 62 on the second surface side covers the second surface 11S. The lower layer 62 on the second surface side is integral with the filler resin 30. There is no boundary between the filler resin 30 and the lower layer 62 on the second surface side. 【0031】 The upper layer 64 on the second side is laminated onto the lower layer 62 on the second side. The surface of the lower layer 62 on the second side is the interface with the upper layer 64 on the second side. The surface of the lower layer 62 on the second side is roughened. Due to the roughening, the surface of the lower layer 62 on the second side has a surface roughness suitable for adhesion with the upper layer 64 on the second side. 【0032】 The resin material constituting the lower layer 62 on the second surface side may have the same composition as the resin material constituting the upper layer 64 on the second surface side, or it may have a different composition. 【0033】 In the example shown in Figure 1, the resin material constituting the lower layer 62 on the second side has the same composition as the resin material constituting the lower layer 52 on the first side. Furthermore, the resin material constituting the upper layer 64 on the second side has the same composition as the resin material constituting the upper layer 54 on the first side. 【0034】 The thickness of the lower layer 52 on the first side and the thickness of the lower layer 62 on the second side are approximately the same. The thickness of the upper layer 54 on the first side and the thickness of the upper layer 64 on the second side are approximately the same. Therefore, the thickness of the resin layer 50 on the first side and the thickness of the resin layer 60 on the second side are also approximately the same. The layer configuration and material configuration of the resin layers adjacent to the core substrate 11 on the first side 11F and the second side 11S are symmetrical with respect to the core substrate 11. 【0035】 The resin insulating layer 21 on the first surface 11F side covers the conductor pattern 22 of the upper layer 54 on the first surface side, and the upper layer 54 on the first surface side where there is no conductor pattern 22. In the upper layer 54 on the first surface side, the resin material that makes up the resin insulating layer 21 is filled between the conductor pattern 22. 【0036】 The resin insulating layer 21 on the second surface 11S side covers the conductor pattern 22 of the upper layer 64 on the second surface side, and the upper layer 64 on the second surface side where there is no conductor pattern 22. In the upper layer 64 on the second surface side, the resin material constituting the resin insulating layer 21 is filled between the conductor patterns 22. 【0037】 The first side resin layer 50, the second side resin layer 60, and the resin insulating layer 21 have via holes 23 that penetrate through the first side resin layer 50, the second side resin layer 60, and the resin insulating layer 21 in the thickness direction. Via conductors 24 are formed in the via holes 23 by filling them with plating. The terminal 81F on the first side 11F of the electronic component 80 is connected to the conductor pattern 22 via the via conductors 24 formed in the first side resin layer 50. 【0038】 Through-holes 15 are formed in the core substrate 11. The through-holes 15 penetrate the insulating substrate 13K of the core substrate 11 in the thickness direction. Through-hole conductors 16 are formed on the inner wall of the through-holes 15. Parts of the through-hole conductors 16 are exposed on the first surface 11F side and the second surface 11S side of the core substrate 11. Hole-filling resin 17 is filled inside the through-hole conductors 16. Parts of the conductor pattern 12 on the first surface 11F side and part of the conductor pattern 12 on the second surface 11S side of the electronic component embedded substrate 10 are connected by the through-hole conductors 16. 【0039】 The conductor pattern 12 on the first surface 11F side of the core substrate 11 is connected to the conductor pattern 22 on the first surface 11F side via via conductors 24 formed in the first surface side resin layer 50. Furthermore, the conductor pattern 12 on the second surface 11S side of the core substrate 11 is connected to the conductor pattern 22 on the second surface 11S side via via conductors 24 formed in the second surface side resin layer 60. 【0040】 In the electronic component-embedded substrate 10, a semiconductor element mounting area 27 is formed on the surface facing the first surface 11F. The semiconductor element mounting area 27 is, for example, the area where a semiconductor element is mounted on the electronic component-embedded substrate 10. The semiconductor element mounting area 27 is formed, for example, in a position that overlaps with the electronic component 80 when viewed in the direction normal to the first surface 11F. Conductive bumps are formed in the solder resist layer 26, for example, that are in contact with via conductors 24. The semiconductor element is then mounted on the semiconductor element mounting area 27 through the bumps and connected to the electronic component-embedded substrate 10. 【0041】 Next, the manufacturing method of the electronic component embedded substrate 10 will be described. The electronic component embedded substrate 10 is manufactured as follows. 【0042】 (1) As shown in Figure 2, a core substrate 11 is prepared. Through-holes 15 are formed in the insulating substrate 13K of this core substrate 11. Through-hole conductors 16 are formed on the inner walls of the through-holes 15. Hole-filling resin 17 is filled inside the through-hole conductors 16. Conductor patterns 12 are formed on the first surface 11F and the second surface 11S on the insulating substrate 13K. A portion of the conductor pattern 12 on the first surface 11F and a portion of the conductor pattern 12 on the second surface 11S are connected by the through-hole conductors 16. 【0043】 The core substrate 11 does not yet have an opening 11A formed in it. The insulating substrate 13K included in the core substrate 11 is, for example, made by impregnating glass cloth with BT (bismaleimide triazine) resin or epoxy resin and curing it. 【0044】 (2) As shown in Figure 3, an opening 11A is formed in the core substrate 11, for example by router processing. The opening 11A penetrates the core substrate 11 in the thickness direction. The opening 11A is open to the first surface 11F and the second surface 11S. The opening 11A has an inner surface 11N. The inner surface 11N is the surface that is separated from and opposite the side surface 80G of the electronic component 80 when the electronic component 80 is housed in the opening 11A. 【0045】 (3) As shown in Figure 4, the core substrate 11 is placed on the adhesive tape 40. The first surface 11F of the core substrate 11 faces the adhesive tape 40. The first surface 11F side of the opening 11A of the core substrate 11 is covered with the adhesive tape 40. 【0046】 (4) As shown in Figure 5, the electronic component 80 is housed within the opening 11A. The side of the electronic component 80 that is positioned on the first surface 11F side is referred to as the first component surface 80F of the electronic component 80. The side of the electronic component 80 that is positioned on the second surface 11S side is referred to as the second component surface 80S of the electronic component 80. The first component surface 80F is in contact with the adhesive tape 40. The first component surface 80F is on approximately the same plane as the first surface 11F of the core substrate 11. The second component surface 80S is located inward in the thickness direction of the core substrate 11 from the second surface 11S of the core substrate 11. The first component surface 80F is provided with terminal 81F. The second component surface 80S is provided with terminal 81S. 【0047】 (5) As shown in Figure 6, a second surface lower layer 62 is formed on the second surface 11S side. A portion of the resin material constituting the second surface lower layer 62 is filled as a filler resin 30 between the electronic component 80 and the opening 11A. This resin material covers the conductor pattern 12 on the second surface 11S side and the insulating substrate 13K in the portion where the conductor pattern 12 is not formed. On the first surface 11F side, the filler resin 30 contacts the adhesive tape 40 from between the electronic component 80 and the opening 11A. 【0048】 As the resin material constituting the lower layer 62 on the second surface side, a resin material with a lower elastic modulus and thermal expansion coefficient than at least the resin material constituting the insulating substrate 13K of the core substrate 11 is effective. Specifically, epoxy resins with silica particles as fillers can be used. In particular, since a portion of the resin material constituting the lower layer 62 on the second surface side fills the space between the electronic component 80 and the opening 11A, a resin material suitable for filling is effective. 【0049】 (6) As shown in Figure 7, the adhesive tape 40 is peeled off. 【0050】 (7) As shown in Figure 8, the first surface lower layer 52 is formed on the first surface 11F side. The resin material constituting the first surface lower layer 52 covers the conductor pattern 12 on the first surface 11F side and the insulating substrate 13K in the areas where the conductor pattern 12 is not formed. The resin material is also filled between the side surface 80G of the electronic component 80 and the inner surface 11N of the opening 11A. 【0051】 The resin material constituting the lower layer 52 on the first side is the same as the resin material constituting the lower layer 62 on the second side. 【0052】 (8) The resin material constituting the lower layer 52 on the first surface and the resin material constituting the lower layer 62 on the second surface are subjected to a heat-curing treatment. The heat-curing treatment hardens the resin material constituting the lower layer 52 on the first surface and the resin material constituting the lower layer 62 on the second surface. The degree of hardening is set to a level suitable for polishing these resin materials in a subsequent process. 【0053】 (9) As shown in Figure 9, the lower layer 52 on the first surface is polished. The thickness of the lower layer 52 on the first surface is reduced. This polishing does not reach the conductor pattern 12 on the first surface 11F side. The conductor pattern 12 on the first surface 11F side is not thinned by the polishing and maintains its thickness. The conductor pattern 12 on the first surface 11F side is maintained in a state where it is covered by the lower layer 52 on the first surface. 【0054】 Similarly, the lower layer 62 on the second surface is polished. The thickness of the lower layer 62 on the second surface is reduced. This polishing does not reach the conductor pattern 12 on the second surface 11S side. The conductor pattern 12 on the second surface 11S side is not thinned by the polishing and maintains its thickness. The conductor pattern 12 on the second surface 11S side remains covered by the lower layer 62 on the second surface. 【0055】 The thickness of the lower layer 52 on the first surface after polishing and the thickness of the lower layer 62 on the second surface after polishing are approximately the same. The order of polishing the lower layer 52 on the first surface and the lower layer 62 on the second surface does not matter; they may be done simultaneously. 【0056】 (10) The lower layer 52 on the first surface is desmeared. The residue generated when polishing the lower layer 52 on the first surface is removed by desmearing. The lower layer 62 on the second surface is also desmeared. The residue generated when polishing the lower layer 62 on the second surface is removed by desmearing. These desmearing processes can be performed using, for example, wet desmearing with an alkaline permanganate solution, or dry desmearing using a gas such as plasma. 【0057】 The surface of the lower layer 52 on the first side is roughened to a surface roughness suitable for bonding and adhering the upper layer 54 on the first side in a subsequent process. The surface of the lower layer 62 on the second side is roughened to a surface roughness suitable for bonding and adhering the upper layer 64 on the second side in a subsequent process. 【0058】 (11) As shown in Figure 10, the resin material of the first surface upper layer 54 is attached to and laminated to the first surface lower layer 52. The first surface resin layer 50 is formed by the first surface lower layer 52 and the first surface upper layer 54. The resin material constituting the first surface upper layer 54 may be the same as or different from the resin material constituting the first surface lower layer 52. In the disclosed art, the resin material constituting the first surface upper layer 54 is the same as the resin material constituting the first surface lower layer 52. 【0059】 The resin material of the second surface upper layer 64 is attached to and laminated onto the second surface lower layer 62. The second surface lower layer 62 and the second surface upper layer 64 constitute the second surface resin layer 60. The resin material constituting the second surface upper layer 64 may be the same as or different from the resin material constituting the second surface lower layer 62. In the disclosed art, the resin material constituting the second surface upper layer 64 is the same as the resin material constituting the second surface lower layer 62. In the disclosed art, the resin material constituting the second surface upper layer 64 is the same as the resin material constituting the first surface upper layer 54. The thickness of the second surface upper layer 64 is approximately the same as the thickness of the first surface upper layer 54. 【0060】 The order in which the resin material of the upper layer 54 on the first side is laminated onto the lower layer 52 on the first side, and the resin material of the upper layer 64 on the second side is laminated onto the lower layer 62 on the second side, does not matter and may be done simultaneously. 【0061】 A heat-curing treatment is performed on the resin material constituting the first surface resin layer 50 and the resin material constituting the second surface resin layer 60. The heat-curing treatment hardens the resin material constituting the first surface resin layer 50 and the resin material constituting the second surface resin layer 60. In the first surface resin layer 50, the heat-curing treatment is performed for the first upper layer 54 and for the second lower layer 52. In the second surface resin layer 60, the heat-curing treatment is performed for the first upper layer 64 and for the second lower layer 62. 【0062】 (12) As shown in Figure 11, via holes 23 are formed in the first surface resin layer 50 and the second surface resin layer 60, for example by laser processing. In the first surface resin layer 50, the via holes 23 are formed by penetrating the first surface upper layer 54 and the first surface lower layer 52. In the second surface resin layer 60, the via holes 23 are formed by penetrating the second surface upper layer 64 and the second surface lower layer 62. 【0063】 (13) On the first surface side resin layer 50, electroless plating is performed, and an electroless plating film 33 is formed on the first surface side resin layer 50 and on the via hole 23. Inside the via hole 23, the electroless plating film 33 is in contact with the terminal 81F of the electronic component 80, or a part of the conductor pattern 12 on the first surface 11F side. 【0064】 On the second side resin layer 60, electroless plating is performed, and an electroless plating film 33 is formed on the second side resin layer 60 and on the via hole 23. Inside the via hole 23, the electroless plating film 33 is in contact with a part of the conductor pattern 12 on the second side 11S. 【0065】 (14) As shown in Figure 12, a plating resist 34 with a predetermined pattern is formed on the electroless plating film 33. 【0066】 (15) Electroplating is performed, and as shown in Figure 13, the electroplating fills the via holes 23 to form via conductors 24. 【0067】 (16) The plating resist 34 is peeled off, and the electroless plating film 33 beneath the plating resist 34 is removed. Then, the remaining electroless plating film 33 forms the conductive pattern 22 on the first side resin layer 50 and the second side resin layer 60. 【0068】 (17) As shown in Figure 14, on the first surface 11F, a resin insulating layer 21 is formed on the conductor pattern 22 and on the first surface side resin layer 50 in the portion where the conductor pattern 22 is not formed. On the second surface 11S, a resin insulating layer 21 is formed on the conductor pattern 22 and on the second surface side resin layer 60 in the portion where the conductor pattern 22 is not formed. The resin insulating layer 21 is composed of, for example, a resin film that does not contain a core material and contains an inorganic filler. In the example shown in Figure 14, the resin material constituting the resin insulating layer 21 is a different resin material from the resin material constituting the filler resin 30. The resin material constituting the resin insulating layer 21 is subjected to a heat-curing treatment. At this time, the first surface side resin layer 50 and the second surface side resin layer 60 located below the resin insulating layer 21 are also heat-cured. 【0069】 From (18) onward, via holes 23 are formed in the resin insulating layer 21 by laser processing, similar to how via holes 23 are formed in the first side resin layer 50 and the second side resin layer 60. Electroless plating is performed, and an electroless plating film 33 is formed on the resin insulating layer 21 and in the via holes 23 of the resin insulating layer 21. Within the via holes 23, the electroless plating film 33 is in contact with the conductor pattern 22 of the resin insulating layer 21 located beneath it. 【0070】 A predetermined pattern of plating resist 34 is formed on the electroless plating film 33. Electroplating is performed, and the electroplating fills the via holes 23 to form via conductors 24. The plating resist 34 is peeled off, and the electroless plating film 33 beneath the plating resist 34 is removed. Then, the remaining electroless plating film 33 forms a conductor pattern 22. 【0071】 (19) The same process as described in (17) to (18) above is performed on the resin insulating layer 21 formed in this manner, and on the resin insulating layer 21 on which the conductor pattern 22 is not formed, so that one layer of resin insulating layer 21 and one layer of conductor pattern 22 are formed on both the front and back surfaces. Furthermore, a solder resist layer 26 is formed on both the front and back surfaces. With the above steps completed, the electronic component embedded substrate 10 shown in Figure 1 is completed. 【0072】 The resin insulating layer 21 may also be made of a prepreg. A prepreg is a resin sheet made by impregnating a core material with a resin containing an inorganic filler. The resin that makes up the prepreg is thermosetting and is in a semi-cured state. In this case, copper foil is laminated on the resin insulating layer 21. Furthermore, the conductor pattern 22 is formed by electroless plating and electrolytic plating. 【0073】 In the manufacturing method of the electronic component embedded substrate 10 of this embodiment, a filler resin 30 is filled between the electronic component 80 housed in the opening 11A of the core substrate 11 and the opening 11A. The filler resin 30 is formed by filling the opening 11A with the resin of the second surface lower layer 62 that constitutes the second surface resin layer 60. When filling the opening 11A with the resin material that constitutes the resin insulating layer 21, the amount of resin may be insufficient. In this embodiment, by using the resin material that constitutes the second surface lower layer 62, a sufficient amount of resin can be filled into the opening 11A as the filler resin 30. 【0074】 In the manufacturing method of the electronic component embedded substrate 10 of this embodiment, the polishing of the lower layer 52 on the first surface and the lower layer 62 on the second surface is performed to the extent that it does not reach the conductor pattern 12 on the first surface 11F and the conductor pattern 12 on the second surface 11S. The conductor pattern 12 on the first surface 11F and the conductor pattern 12 on the second surface 11S are not thinned by polishing and their thickness is maintained. In addition, the conductor pattern 12 on the first surface 11F is maintained in a state where it is covered by the lower layer 52 on the first surface, and the conductor pattern 12 on the second surface 11S is maintained in a state where it is covered by the lower layer 62 on the second surface. 【0075】 In the manufacturing method of the electronic component embedded substrate 10 of this embodiment, polishing and desmearing the first surface lower layer 52 and the second surface lower layer 62 results in surface roughness suitable for bonding the first surface upper layer 54 and the second surface resin layer 60. Compared to a configuration in which the surface roughness of the first surface lower layer 52 and the second surface lower layer 62 is not as described, the first surface upper layer 54 can be strongly bonded to the first surface lower layer 52, and the second surface upper layer 64 can be strongly bonded to the second surface lower layer 62. 【0076】 In the electronic component embedded substrate 10 of this embodiment, the layer structure and material composition of the resin layer 50 on the first side and the resin layer 60 on the second side are the same. Therefore, compared to electronic component embedded substrates in which the layer structure or material composition of the resin layer differs between the first side 11F and the second side 11S, warping is less likely to occur. 【0077】 [Other embodiments] (1) The circuit board 10 containing electronic components may have multiple electronic components 80 with different heights L1. In this case, multiple electronic components 80 may be housed in one opening 11A. Alternatively, multiple openings 11A may be formed in the core circuit board 11, and one electronic component 80 may be housed in each of the openings 11A. 【0078】 (2) In the above embodiment, the core substrate 11 may be a single-layer core comprising only one insulating substrate 13K. 【0079】 (3) The electronic component 80 may be a passive component such as a resistor or a coil, or it may be an active component such as an IC chip including a semiconductor element. 【0080】 (4) In the method for manufacturing the electronic component embedded substrate 10, a support plate may be prepared, and adhesive tape 40 (see Figures 4 to 6) may be provided on both sides of the support plate, so that the electronic component embedded substrate 10 can be manufactured in parallel on both sides of the support plate. 【0081】 (5) In the above embodiment, the electronic component 80 may be placed on the adhesive tape 40, and then the core substrate 11 may be placed on the adhesive tape 40 so that the electronic component 80 fits inside the opening 11A. 【0082】 Furthermore, the electronic component embedded substrates of the technology of this disclosure are not limited to the structures illustrated in each drawing, nor to the structures, shapes, and materials illustrated herein. As stated above, the electronic component embedded substrates of the embodiments may have any laminated structure. The electronic component embedded substrates of the embodiments may include any number of conductive and insulating layers. 【0083】 The method for manufacturing an electronic component embedded substrate of the technology disclosed herein is not limited to the method described with reference to the drawings. Furthermore, each insulating layer may be formed using any form of resin, not limited to a film-like resin. In addition to the steps described above, any additional steps may be added to the electronic component embedded substrate manufacturing method of the embodiment, and some of the steps described above may be omitted. [Explanation of symbols] 【0084】 10. Circuit board with embedded electronic components 11 Core board 11F Front page 11S second side 11A opening 11N Inner surface of the opening 12 Conductor Patterns 13 Resin layer 13K insulating substrate 15 Through Holes 16 Through-hole conductors 17. Hole-filling resin 21 Resin insulating layer 22 Conductor Patterns 23 Beer Hall 24 via conductors 26 Solder Resist Layers 30 Filling resin 33 Electroless Plating Film 34 Resist 40 Adhesive Tapes 50 First side resin layer 52 First side lower layer 54 First side upper layer 60 Second side resin layer 62 Second side lower layer 64 Second side upper layer 80 Electronic Components 80F First Parts 80s Part 2 81F, 81S terminals

Claims

[Claim 1] A core substrate having a first surface and a second surface opposite to the first surface, and having openings that open to the first surface and the second surface, The electronic components housed in the aforementioned opening, A first-side resin layer comprising a first-side lower layer covering the electronic component and the first surface on the first-side, and a first-side upper layer laminated on the first-side lower layer, The filling resin that fills the opening on the second surface side, covering the electronic component and reaching the lower layer on the first surface side, A second surface resin layer comprising a second surface side lower layer which is integral with the filling resin and covers the second surface, and a second surface side upper layer which is laminated on the second surface side lower layer, A circuit board with embedded electronic components. [Claim 2] The electronic component embedded substrate according to claim 1, The lower layer on the first side and the lower layer on the second side are made of the same resin material. The upper layer on the first side and the upper layer on the second side are made of the same resin material. [Claim 3] The electronic component embedded substrate according to claim 1, The interface between the first surface lower layer and the first surface upper layer, and the interface between the second surface lower layer and the second surface upper layer, are roughened. [Claim 4] The electronic component embedded substrate according to claim 1, It has a via conductor that penetrates the first surface resin layer and contacts the terminal of the electronic component. [Claim 5] A core substrate having a first surface and a second surface opposite to the first surface, to which openings are formed on the first surface and the second surface, To house electronic components in the aforementioned opening, The process involves filling the opening with resin from the second surface side to form a filling resin that covers the electronic component, while simultaneously providing a lower layer on the second surface side that covers the second surface with the resin, A lower layer on the first surface side is provided, which covers the electronic component and the first surface from the first surface side using resin, The upper layer on the second surface is laminated onto the lower layer on the second surface using resin, The upper layer on the first surface is laminated onto the lower layer on the first surface using resin, A method for manufacturing a circuit board containing electronic components. [Claim 6] A method for manufacturing an electronic component embedded substrate according to claim 5, The lower layer on the first side and the lower layer on the second side are made of the same resin material. The upper layer on the first surface and the upper layer on the second surface are made of the same resin material. [Claim 7] A method for manufacturing an electronic component embedded substrate according to claim 5, After roughening the surface of the lower layer on the second side, the upper layer on the second side is laminated. After roughening the surface of the lower layer on the first side, the upper layer on the first side is laminated.

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