Package substrate with components enclosed within a glass core cavity

Abstract

The present invention provides a package substrate in which components are contained within a cavity of a glass core. [Solution] One example of a device includes a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. The example of the device further includes a conductive material adjacent to the first wall of the first opening and a dielectric material adjacent to the second wall of the second opening.

Description

Background Art

[0001] Integrated circuit (IC) chips and / or semiconductor dies are typically connected via a package substrate to a larger circuit board such as, for example, a motherboard and other types of printed circuit boards (PCBs). As the size of IC chips and / or dies shrinks and the interconnect density increases, alternatives to traditional substrate layers have been developed to provide stable transmission of high-frequency data signals and / or increased power delivery between different circuits. One option being pursued is the implementation of package substrates having a glass core.

Brief Description of the Drawings

[0002] [Figure 1] An example of an integrated circuit (IC) package constructed in accordance with the teachings disclosed herein is shown. [Figure 2A] An example of a glass core assembly that may be implemented within the example package substrate of FIG. 1 is shown. [Figure 2B] An enlarged view corresponding to the dashed box shown in FIG. 2A, representing an example of the outer surface structure of an example glass through via (TGV) with respect to the inner surface of an associated through hole. [Figure 2C] An enlarged view corresponding to the dashed box shown in FIG. 2A, representing another example of the outer surface structure of another TGV with respect to the inner surface of an associated through hole. [Figure 2D] A cross-sectional view taken from above another example of a TGV shown in FIG. 2A. [Figure 2E] A cross-sectional view taken from above another example of a TGV shown in FIG. 2A. [Figure 3A] Another example of a glass core assembly that may be implemented within the example package substrate of FIG. 1 is shown. [Figure 3B] An enlarged view corresponding to the dashed box shown in FIG. 3A, representing an example of the outer surface structure of an example glass through via (TGV) with respect to the inner surface of an associated through hole. [Figure 3C]This is an enlarged view corresponding to the dashed box shown in Figure 3A, representing another structural example of the outer surface of another TGV example relative to the inner surface of the related through-hole. [Figure 3D] Figure 3A is a top-down cross-sectional view of another TGV example. [Figure 3E] Figure 3A is a top-down cross-sectional view of another TGV example. [Figure 4] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 5] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 6] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 7] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 8] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 9] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 10] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 11] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 12] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 13]Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 14] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 15] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 16] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 17] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 18] Figures 4-18 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 2A and / or Figure 3A. [Figure 19] Figure 1 shows other examples of glass core assemblies that can be mounted within the example package substrate. [Figure 20] Figure 1 shows other examples of glass core assemblies that can be mounted within the example package substrate. [Figure 21] Figures 21-27 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 19 and / or Figure 20. [Figure 22] Figures 21-27 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 19 and / or Figure 20. [Figure 23] Figures 21-27 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 19 and / or Figure 20. [Figure 24] Figures 21-27 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 19 and / or Figure 20. [Figure 25] Figures 21-27 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 19 and / or 20. [Figure 26] Figures 21-27 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 19 and / or 20. [Figure 27] Figures 21-27 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 19 and / or 20. [Figure 28] Other example glass core assemblies that can be implemented within the example package substrate of FIG. 1 are shown. [Figure 29] Other example glass core assemblies that can be implemented within the example package substrate of FIG. 1 are shown. [Figure 30] Figures 30-36 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 28 and / or 29. [Figure 31] Figures 30-36 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 28 and / or 29. [Figure 32] Figures 30-36 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 28 and / or 29. [Figure 33] Figures 30-36 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 28 and / or 29. [Figure 34] Figures 30-36 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 28 and / or 29. [Figure 35] Figures 30-36 show various stages in an example manufacturing process for manufacturing an example glass core assembly of FIGS. 28 and / or 29. [Figure 36]Figures 30-36 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 28 and / or Figure 29. [Figure 37] Figure 1 shows other examples of glass core assemblies that can be mounted within the example package substrate. [Figure 38] Figure 1 shows other examples of glass core assemblies that can be mounted within the example package substrate. [Figure 39] Figures 39-44 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 37 and / or Figure 38. [Figure 40] Figures 39-44 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 37 and / or Figure 38. [Figure 41] Figures 39-44 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 37 and / or Figure 38. [Figure 42] Figures 39-44 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 37 and / or Figure 38. [Figure 43] Figures 39-44 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 37 and / or Figure 38. [Figure 44] Figures 39-44 show various steps in an example manufacturing process for producing the glass core assembly example shown in Figure 37 and / or Figure 38. [Figure 45] Examples of glass panels that can be processed according to the teachings disclosed herein are shown for the manufacture of any of the glass core assembly examples in Figures 2A, 3A, 19, 20, 28, 29, 37, and / or 38. [Figure 46] The frame example shows a reconstructed panel example that includes the glass panel example shown in Figure 45. [Figure 47A]Figures 47A, 47B, 48, and 49 are flowcharts illustrating an example method for manufacturing one of the glass core assembly examples shown in Figures 2A, 3A, 19, 20, 28, 29, 37, and / or 38, which may be implemented in the IC package example 100 of Figure 1. [Figure 47B] Figures 47A, 47B, 48, and 49 are flowcharts illustrating an example method for manufacturing one of the glass core assembly examples shown in Figures 2A, 3A, 19, 20, 28, 29, 37, and / or 38, which may be implemented in the IC package example 100 of Figure 1. [Figure 48] Figures 47A, 47B, 48, and 49 are flowcharts illustrating an example method for manufacturing one of the glass core assembly examples shown in Figures 2A, 3A, 19, 20, 28, 29, 37, and / or 38, which may be implemented in the IC package example 100 of Figure 1. [Figure 49] Figures 47A, 47B, 48, and 49 are flowcharts illustrating an example method for manufacturing one of the glass core assembly examples shown in Figures 2A, 3A, 19, 20, 28, 29, 37, and / or 38, which may be implemented in the IC package example 100 of Figure 1. [Figure 50] This is a top view of a wafer containing a die that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 51] This is a side cross-sectional view of an IC device that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 52] This is a side cross-sectional view of an IC device assembly that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 53] This is a block diagram of an example of electrical equipment that may be included in an IC package constructed according to the teachings disclosed herein.

[0003] Generally, throughout the drawings and accompanying descriptions, the same or similar parts are referred to using the same reference numerals. Drawings are not necessarily to scale. Rather, the thickness of layers or areas may be enlarged in the drawings. Drawings show layers and areas with clear lines and boundaries, but some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be unobservable, blended, and / or uneven. [Modes for carrying out the invention]

[0004] Figure 1 shows an example integrated circuit (IC) package 100 constructed according to the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to a substrate 102 located below it via an array of contacts 104 on the package mounting surface 106 (e.g., bottom, outer surface) of the package. In some examples, the substrate 102 may be mounted by a printed circuit board (PCB) or a package substrate (e.g., the IC package 100 is part of another larger package). In the illustrated example, the contacts 104 are represented as pads or lands. However, in some examples, the IC package 100 may include, in addition to or instead of, the pads or lands shown, balls, pins, and / or any other type of contacts to enable the electrical coupling of the IC package 100 to the substrate 102. In this example, the package 100 includes two semiconductor dies 108, 110 (e.g., silicon dies), which may also be referred to as chips or chiplets, mounted on a package substrate 112 and surrounded by a package lid 114 (e.g., a mold compound, integrated heat spreader, IHS). Thus, the package substrate 112 is an example of means for supporting the semiconductor dies. In some examples, the package lid 114 is omitted, thereby leaving the semiconductor dies 108, 110 exposed or bare.

[0005] The IC package example 100 in Figure 1 includes two dies 108 and 110, but in other examples, the IC package 100 may have only one die or three or more dies. In some examples, one of the dies 108 and 110 (or separate dies) is embedded in the package substrate 112. The dies 108 and 110 can provide any preferred type of function (e.g., data processing, memory storage, etc.). In some examples, one or both of the dies 108 and 110 are mounted by a die package that includes multiple dies arranged in a stacked configuration. For example, die 110 may include a stack of dynamic random access memory (DRAM) dies placed on top of a memory controller die to form a memory die stack.

[0006] As shown in the illustrated example, each of the dies 108, 110 is electrically and mechanically coupled to the package substrate 112 via a corresponding array of interconnects 116. In Figure 1, the interconnects are shown as bumps. In some examples, the interconnects 116 may include solder joints, microbumps, combinations of metal (e.g., copper) pillars and solder, etc. In other examples, the interconnects 116 may include directly bonded or "hybrid bonded" metal interconnects. In other examples, the interconnects 116 may be any other type of electrical connection (e.g., balls, pins, pads, pillars, wire bonding, etc.) in addition to, or instead of, the bumps shown. The electrical connection between the dies 108, 110 and the package substrate 112 (e.g., the interconnects 116) may be referred to as first-level interconnects. In contrast, the electrical connections (e.g., contacts 104) between the IC package 100 and the substrate 102 may be referred to as a second-level interconnect. In some examples, one or both of the dies 108, 110 may be stacked on top of one or more other dies and / or interposers. In such examples, the dies 108, 110 may be coupled to the underlying dies and / or interposers via a first set of first-level interconnects, and the underlying dies and / or interposers may be connected to the package substrate 112 via another set of first-level interconnects associated with those underlying dies and / or interposers. Thus, as used herein, a first-level interconnect refers to an interconnect (e.g., balls, bumps, pins, pads, wire bonding, etc.) between a die and the package substrate, or between a die and the underlying dies and / or interposers.

[0007] As shown in Figure 1, the interconnect 116 of the first level interconnect includes two different types of bumps corresponding to core bumps 118 and bridge bumps 120. When used here, the core bump 118 is a bump on the dies 108, 110 through which electrical signals pass between the dies 108, 110 and external components of the IC package 100. More specifically, as shown in the illustrated example, when the dies 108, 110 are mounted on the package substrate 112, the core bump 118 is physically connected and electrically coupled to contact pads 122 on the die mounting surface 124 (e.g., top surface, apex surface, etc.) of the package substrate 112. The contact pads 122 on the die mounting surface 124 of the package substrate 112 are electrically coupled to the contacts 104 on the package mounting surface 106 of the package substrate 112 (e.g., the bottom, outer surface) (e.g., the surface opposite to the die mounting surface 124) via an internal interconnect 126 within the package substrate 112. As a result, a continuous electrical signal path exists between the core bumps 118 of the dies 108, 110 and the contacts 104 mounted on the substrate 102, through the contact pads 122 and interconnect 126 provided between them. As shown in the figure, the package mounting surface 106 and the die mounting surface 124 define the opposite outer surfaces of the package substrate 112. Although both surfaces are outer surfaces of the package substrate, the die mounting surface 124 may be referred to here as an internal or inner surface relative to the entire IC package 100. In contrast, in this example, the package mounting surface 106 is an outer or outer surface of the IC package 100.

[0008] When used here, the bridge bump 120 is a bump on dies 108, 110 through which electrical signals pass between different dies 108, 110 within the IC package 100. Thus, as shown in the illustrated example, the bridge bump 120 of the first die 108 is electrically coupled to the bridge bump 120 of the second die 110 via an interconnect bridge 128 (e.g., a silicon-based interconnect bridge, interconnect die, or embedded interconnect bridge (EMIB)) embedded in the package substrate 112. As shown in Figure 1, the core bump 118 is typically larger than the bridge bump 120. In some examples, the interconnect bridge 128 and its associated bridge bump 120 are omitted.

[0009] In some examples, underfill material 130 is provided between the dies 108, 110 and the package substrate 112, around and / or between the first level interconnect 116 (for example, around and / or between the core bump 118 and / or bridge bump 120). In the illustrated example, only the first die 108 is accompanied by underfill material 130. However, in other examples, both dies 108 and 110 are accompanied by underfill material 130. In other examples, the underfill material 130 is omitted. In some examples, the mold compound used for the package lid 114 is used as the underfill material surrounding the first level interconnect 116.

[0010] In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and / or inductors, which are located on the package mounting surface 106 and / or the die mounting surface 124 of the package substrate 112.

[0011] In Figure 1, the substrate 112 of IC package example 100 includes a glass core 132 (e.g., a glass substrate, glass layer, etc.) between two separate build-up layers or regions 134, 136 (e.g., a first build-up region 134 and a second build-up region 136, which are also referred to here as redistribution layers or regions). In some examples, the glass core 132 includes at least one of aluminosilicate, borosilicate, aluminoborosilicate, silica, and / or fused silica. In some examples, the glass core 132 contains one or more additives, including aluminum oxide (Al2O3), boron trioxide (B2O3), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon oxide (SrO), barium oxide (BaO), tin oxide (SnO2), nickel alloy (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium (Ti), and / or zinc (Zn). In some examples, the glass core 132 contains silicon and oxygen. In some examples, the glass core 132 contains silicon, oxygen, and / or one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, the glass core 132 comprises at least 23 weight percent silicon and at least 26 weight percent oxygen. In some examples, the glass core is a layer of glass comprising silicon, oxygen, and aluminum. In some examples, the glass core 132 comprises at least 23 weight percent silicon, at least 26 weight percent oxygen, and at least 5 weight percent aluminum.

[0012] In some examples, the glass core 132 is an amorphous solid glass layer. In some examples, the glass core 132 is a layer of glass that does not contain organic adhesives or organic materials. In some examples, the glass core 132 is a solid layer of glass that has a rectangular shape in plan view. In some examples, the glass core 132 includes at least one glass layer as a glass substrate, does not contain epoxy, and does not contain glass fibers (e.g., does not contain an epoxy prepreg layer having glass cloth). In some examples, the glass core 132 corresponds to a single piece of glass extending across the entire height / thickness of the core.

[0013] In some examples, the glass core 132 has a rectangular shape with substantially the same extent as the layers above and / or below the core in a plan view. In some examples, the glass core 132 has a thickness ranging from about 50 micrometers (μm) to about 1.4 millimeters (mm). In some examples, the glass core 132 can be a multilayer glass substrate (e.g., a coreless substrate), where the glass layers have a thickness ranging from about 25 μm to about 50 μm. In some examples, the glass core 132 can have dimensions ranging from about 10 mm to about 250 mm on each side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some examples, the glass core 132 corresponds to a rectangular prism volume from which sections (e.g., vias) have been removed and filled with other materials (e.g., metal). In particular, glass cores are advantageous over epoxy-based cores because glass is harder and therefore provides greater mechanical support or strength to the package substrate. Therefore, the glass core 132 serves as an example of a means for strengthening the package substrate.

[0014] The first and second build-up regions 134, 136 are represented in Figure 1 as lumps / blocks having internal interconnects 126 extending linearly through the build-up regions 134, 136 (and the glass core 132). However, Figure 1 is simplified for clarity and explanatory purposes. In reality, the interconnects are not necessarily linear. More specifically, in some examples, the build-up regions 134, 136 are defined by alternating layers of dielectric material and layers of conductive material (e.g., metal such as copper). The conductive (metal) layers serve as the basis for the internal interconnects 126, which are represented in a simplified linear form as shown in Figure 1. In some examples, the metal layers are patterned to define electrical wiring or conductive traces that are electrically coupled between different metal layers by conductive (e.g., metal) vias extending through the intervening dielectric layers. Furthermore, electrical wiring or traces on either side of the glass core 132 may be electrically coupled by through-glass vias (TGVs) (e.g., copper-plated vias) extending through the glass core 132.

[0015] Using glass as the starting core material (e.g., glass core 132 in Figure 1) offers mechanical, electrical, and design flexibility advantages over using traditional organic core materials (e.g., epoxy prepregs). In particular, glass cores are more advantageous than epoxy cores because glass is harder and therefore provides greater mechanical support or strength to the package substrate. Thus, glass core 132 is an example of a means for strengthening the package substrate. In addition to the mechanical advantages, glass cores also offer other benefits, including higher plated through-hole (PTH) density, lower signal loss, and lower overall thickness variation. However, glass cores also present challenges due to the brittle (e.g., brittle) nature of glass, the potential for defects to develop into cracks propagating through the glass, and associated limitations in the methods that can be used to manufacture and / or process glass cores.

[0016] For example, in epoxy-based organic cores, cavities, holes, and / or openings can be mechanically drilled, but such a process is not suitable for glass cores. Instead, cavities, holes, and / or openings within the glass layer are created by a laser-induced etching (LIDE) process. Specifically, in the LIDE process, a laser is concentrated on specific areas of a glass piece (e.g., a glass core 132) to modify the chemical properties of the glass core 132 in those areas. The change in chemical properties increases the etching sensitivity of the glass core 132 in the laser-exposed areas, and as a result, those areas can be removed in a subsequent etching process. This etching process exposes the entire glass core 132 to an etching solution. This presents challenges when different cavities, holes, and / or openings are added to the glass core 132 at different times. For example, glass associated with a first opening created during a first LIDE process may be adversely affected by exposure to an etching solution associated with a second LIDE process performed to generate a second (subsequent) opening. Furthermore, repeated exposure to the etching solution may affect other parts or features of the glass core 132, regardless of whether the glass associated with the first opening is affected. In many known manufacturing processes for organic cores, such concerns do not exist because the first opening can be generated by a first machining process (e.g., drilling), and the second opening can be added at any later point by a second machining process without affecting the first opening or other areas of the core.

[0017] Examples disclosed herein overcome one or more of the above challenges based on a process flow in which multiple different types of cavities, holes, and / or openings are generated within a glass core in a single LIDE process. More specifically, in some examples, the different types of openings include a through-hole for the TGV associated with the interconnect 126 and at least one larger cavity 138 that is large enough to accommodate some other electronic component 140 placed inside. The electronic component 140 can be any suitable electronic component such as a coaxial magnetic inductor loop (CMIL), a deep trench capacitor (DTC), or another semiconductor device (e.g., a semiconductor die). In the example shown in Figure 1, the electronic component 140 is entirely contained within the cavity 138. However, in some examples, at least a portion of the electronic component 140 extends beyond the cavity 138. In some examples, two or more electronic components 140 (whether of the same or different types) can be positioned within a given cavity 138 (e.g., in the X, Y, and / or Z directions). In addition, or instead, the glass core 132 may contain two or more cavities 138, each of which contains one or more electronic components 140. Manufacturing through-holes for the TGV within the glass core 132 simultaneously with (e.g., in parallel with) a larger cavity 138 avoids concerns about multiple etching processes that could adversely affect the glass core 132 (e.g., the structural integrity of the glass core 132 and / or one or more structural features of the glass core 132).

[0018] Furthermore, the examples disclosed herein ensure that mechanisms and / or structures provided within different types of openings can be manufactured without affecting each other. For example, in some examples, after fabricating the through-hole and cavity 138, the cavity 138 is subsequently filled with a dielectric material before the through-hole is filled with a conductive material (e.g., a metal such as copper) to define the TGV. By first filling the cavity 138 with the dielectric material, a plating process that adds the conductive material to generate the TGV does not result in the conductive material entering the cavity 138. Also, in some examples, the dielectric material in the cavity can be processed using methods unsuitable for glass. For example, a machining process (e.g., drilling) can be performed in a manner similar to known processes involved in organic cores to remove part of the dielectric material and create space for (one or more) electronic components 140.

[0019] Figure 2A shows an example glass core assembly 200 that can be mounted within the package substrate example 112 of Figure 1. In the illustrated example of Figure 2, the glass core assembly 200 includes a glass core 202 which may correspond to the glass core 132 described above in relation to Figure 1. Thus, the description of the glass core 132 described above in relation to Figure 1 also applies to the glass core 202 of Figure 2. As shown in Figure 2A, the glass core 202 includes a plurality of through-glass vias (TGVs) 204 defined by a first conductive material 206 that substantially fills the associated through-holes 208 (e.g., holes, cavities, openings, etc.) extending through the glass core 202. As used herein, “substantially filling” or “substantially packed” means that it is filled to at least 95%. In some examples, the first conductive material 206 includes any preferred metal, such as copper. In some cases, TGV204 in Figure 2 corresponds to a portion of the internal interconnect 126 that extends through the package substrate 112 in Figure 1.

[0020] As shown in the illustrated example, the glass core 202 includes a cavity 210 corresponding to cavity 138 in Figure 1. Thus, as shown in Figure 2A, an electronic component 212 (corresponding to electronic component 140 in Figure 1) is placed within the cavity 210. In this example, electronic component 212 is a coaxial magnetic inductor loop (CMIL). For illustrative purposes, electronic component 212 will be referred to as CMIL212 below. That said, one or more additional and / or (one or more) other types of (one or more) electronic components may be used. As shown, the CMIL example 212 extends through the glass core assembly 200, including through the first and second buffer layers 214, 216 (e.g., adhesive layer, dielectric layer) on the first and second surfaces 218, 220 of the glass core 202, respectively. Therefore, in this example, CMIL212 penetrates the cavity 210 and extends beyond it (for example, above and / or below the first and second surfaces 218, 220). In some examples, the buffer layers 214, 216 are composed of dielectric material. More specifically, in some examples, the buffer layers 214, 216 include organic laminate dielectrics (e.g., epoxy build-up dielectrics).

[0021] In the illustrated example in Figure 2A, the CMIL 212 includes first and second portions 222, 224 defined by two plated through-holes in the dielectric material 226 within the cavity 210. More specifically, as shown in Figure 2A, the dielectric material 226 substantially fills one or more gaps within the cavity 210 that are not occupied by the structure of the CMIL 212. In some examples, the dielectric material 226 fills the space between the CMIL 212 and the sidewall 227 of the cavity 210 (e.g., an inward-facing surface, a wall, etc.), separating the CMIL 212 from the glass core 202. Furthermore, in some such examples, the dielectric material 226 fills the space between different portions 222, 224 of the CMIL 212.

[0022] In the illustrated examples, each of the first and second portions 222, 224 of CMIL212 includes a non-magnetic plug 228 (e.g., a non-magnetic core) that defines the central region of each portion 222, 224, surrounded by a second conductive material 230, which itself is surrounded by a magnetic material 232 (e.g., a magnetic lining). That is, in some examples, the magnetic material 232 defines the magnetic outer covering for each portion 222, 224 of CMIL212, and the conductive material 230 defines the conductive core of each portion 222, 224 of CMIL212. In some examples, the portions of the non-magnetic plug 228, conductive material 230, and magnetic material 232 of CMIL212 generally have a cylindrical shape. In some examples, the non-magnetic plug 228 includes a dielectric material (e.g., epoxy). In some examples, the non-magnetic plug 228 is omitted, and the central region of each section 222, 224 is filled with a solid mass of the second conductive material 230. That is, in some examples, the second conductive material 230 extends continuously across the space inside the magnetic material 232. In some examples, the second conductive material 230 contains the same metal as the first conductive material 206 (e.g., copper) in the TGV 204. In other examples, the second conductive material 230 may contain any other suitable conductive material (e.g., metal). In some examples, the magnetic material 232 may contain any suitable material having magnetic properties (e.g., iron, iron-containing alloys (e.g., silicon steel), ferrite materials (e.g., nickel-zinc ferrite (e.g., Ni a Zn (1-a) Fe2O4), manganese ferrite (e.g., Mn a Zn (1-a) It includes Fe2O4, cobalt ferrite (e.g., CoFe2O4, CoO·Fe2O3), other ferromagnetic particles or elements, etc.

[0023] In the illustrated example in Figure 2A, the first and second portions 222, 224 of CMIL212 are capped at each end by their respective conductive pads 234 (e.g., contact pads). In some examples, the conductive pads 234 contain the same material as the second conductive material 230 (e.g., copper) that extends along the axial length of the two portions 222, 224 of CMIL212. In some examples, the conductive pads 234 accompanying portions 222, 224 of CMIL212 are in the same metal layer as a further conductive pad 235 electrically coupled to TGV204.

[0024] In Figure 2A, the first and second buffer layers 214 and 216 are represented as materials different from the dielectric material 226 that fills the (one or more) gaps in the cavity 210 surrounding the CMIL 212. More specifically, as described above, in some examples the first and second buffer layers 214 and 216 include organic laminate dielectrics (e.g., epoxy build-up dielectrics), while the dielectric material 226 includes a liquid-dispensable dielectric. In other examples the first and second buffer layers 214 and 216 include the same material as the dielectric material 226 in the cavity 210.

[0025] As described above, in this example, the first and second buffer layers 214, 216 are located on the first and second surfaces 218, 220 opposite the glass core 202. Thus, in this example, the first and second buffer layers 214, 216 define the first and second outer surfaces 236, 238 of the entire glass core assembly 200. However, in some examples, the first and second buffer layers 214, 216 shown in Figure 2A may be omitted and / or correspond to the first layer of the build-up region on each side of the glass core assembly 200 (e.g., the build-up regions 134, 136 in Figure 1). In such examples, the first and second surfaces of the glass core 202 define the first and second outer surfaces 236, 238 of the entire glass core assembly 200.

[0026] Figure 2B is an enlarged view corresponding to the dashed box 240 shown in Figure 2A, illustrating an example of the structure of the outer surface 242 (e.g., outward-facing surface) of the first conductive material 206 defining the TGV 204 relative to the inner surface 244 (e.g., inward-facing surface, wall, side wall, etc.) of the through-hole 208. Figure 2C is an enlarged view corresponding to the dashed box 240 shown in Figure 2A, illustrating another example of the structure of the outer surface 242 of the first conductive material 206 facing the inner surface 244 of the through-hole 208. In the example of Figure 2B, multiple open spaces 246 (e.g., gaps, voids, etc.) are defined between the opposing surfaces 242, 244. That is, the open spaces 246 separate at least a portion of the outer surface 242 of the conductive material 206 from the inner surface 244 of the through-hole 208. In some examples, the open spaces 246 are empty and / or do not contain solid material. In some examples, the open space 246 is defined by notches, cracks, and / or defects on one or both of the opposing surfaces 242, 244 of the TGV 204 and the glass core 202. In addition, or instead, in some examples, the opposing surfaces 242, 244 are relatively smooth (e.g., substantially free of notches, cracks, and / or defects) but are slightly spaced apart, defining a gap and / or open space 246 between them. Such a gap and / or open space 246 may be relatively long, as shown in the illustrated example in Figure 2C, compared to the shorter open space 246 shown in Figure 2B. In other examples, the (one or more) gaps and / or (one or more) open spaces 246 can be of any other size.

[0027] The (one or more) open spaces 246 between the glass core 202 and TGV204 can vary in size. For example, in some examples, the open space has a width 248 measured radially (e.g., perpendicularly) with respect to the longitudinal axis 250 of the through-hole 208 (shown in Figure 2A) (e.g., the longitudinal axis of TGV204), which is at most about 250 nanometers (nm), but sometimes significantly smaller (e.g., less than or equal to about 200 nm, less than or equal to about 150 nm, less than or equal to about 100 nm, less than or equal to about 50 nm, less than or equal to about 25 nm, etc.). In contrast, as shown in Figure 2B, example open spaces 246 can be significantly larger than the width 248 (e.g., at least twice the width 248, at least three times the width 248, at least five times the width 248, at least ten times the width 248, etc.), and have a length 252 measured parallel to the longitudinal axis 250. In some examples, the length 252 of a given open space 246 extends over a considerable distance of the total length of the through-hole 208 or TGV 204 (e.g., at least 5%, at least 10%, at least 25%, at least 50%, at least 75%, at least 90%). In some examples, a single open space 246 can extend over the entire length of the through-hole 208. In other examples, there are multiple open spaces 246 (which may or may not be connected).

[0028] In some examples, the open spaces 246 (one or more) extend not only partially and / or completely longitudinally along the length of the through-hole 208, but also partially and / or completely circumferentially along the inner surface 244 of the through-hole 208 (for example, along the outer periphery of the cross-section of the first conductive material 206), as shown in Figures 2D and 2E. Specifically, Figure 2D is a top-down cross-sectional view of the TGV example 204 shown in Figure 2A (e.g., the same TGV204 in Figure 2B, the same TGV204 in Figure 2C, or a different TGV). Figure 2E is a top-down cross-sectional view of another TGV example 204 shown in Figure 2A (e.g., the same TGV204 in Figure 2B, the same TGV204 in Figure 2C, or a different TGV). The example in Figure 2D differs from the example in Figure 2E in that Figure 2D shows multiple open spaces 246 extending around the TGV 204 at different circumferential lengths, whereas Figure 2E shows a single open space 246 extending around the TGV 204 over the entire perimeter. There may be two or more open spaces 246 within the same perimeter plane. Thus, as shown, one or more open spaces 246 can extend around the TGV 204 by any preferred circumferential distance (e.g., at least 5%, at least 10%, at least 25%, at least 50%, at least 75%, at least 90%, etc.). One or more open spaces 246 may exist between the conductive material 206 of TGV204 and the inner surface 244 (e.g., sidewall) of the associated through-hole 208, but in some examples, the dielectric material 226 in the cavity 210 is in direct contact (e.g., abuts) with the sidewall 227 of the cavity 210 in all and / or most areas.

[0029] In some examples, the (one or more) open spaces 246 are created based on a method in which a first conductive material 206 is plated into a through-hole 208 to produce a TGV 204. Known TGVs are often manufactured by first depositing a seed layer on the surface of a glass core (e.g., along the inner surface of the through-hole 208) using an electroless plating process. Then, the bulk first conductive material 206 is deposited on the seed layer using an electroplating process in which the seed layer acts as an electrode. The use of a seed layer facilitates relatively strong adhesion between the inner wall of the through-hole to be plated and the conductive material. Unlike this known approach, in some examples, the TGV 204 is deposited using a bottom-up plating process without a seed layer. That is, the conductive material is positioned at the base or bottom of the through-hole 208 to act as an electrode in the electroplating process, and the first conductive material 206 is deposited through the electroplating process until it is built up along the entire length (or substantially the entire length (e.g., at least 90%)) of the through-hole 208.

[0030] In such an example, since there is no seed layer along the walls of the through-hole 208 (e.g., inner surface 244), the conductive material on which the first conductive material 206 will be plated is the base beneath the electrode, on which portions of the first conductive material 206 are gradually deposited during the plating process. As a result, no strong adhesion occurs between the first conductive material 206 and the glass core 202, which results in one or more open spaces 246 as described above. The lack of adhesion between the first conductive material 206 and the glass core 202, and the accompanying (one or more) open spaces 246 between them, is advantageous because it reduces the stress resulting from the mismatch in the coefficients of thermal expansion (CTE) of these two different materials. That is, the (one or more) open spaces 246 can provide some space for the first conductive material 206 to expand and / or contract radially without significantly affecting the glass core 202. Furthermore, the relatively low adhesion and the associated (one or more) open spaces 246 allow the first conductive material 206 to expand longitudinally, enabling a longitudinal shift of the material relative to the glass core 202 without generating excessive stress on the glass core 202. As a result, the examples disclosed herein reduce stress in the glass core 202, thereby suppressing the occurrence of cracks and / or other failures known to occur in known glass core applications.

[0031] Figure 3A shows another example glass core assembly 300 that can be mounted within the package substrate example 112 of Figure 1. The glass core assembly example 300 in Figure 3A is substantially the same as the glass core assembly example 200 in Figure 2A, except as described below and / or otherwise evident from the context. Thus, features shown in Figure 3A that are the same or similar as the corresponding features in Figure 2A are identified by the same reference numerals. Also, the descriptions of such features described above in relation to Figure 2A apply similarly to the corresponding features in Figure 3A. Specifically, the glass core assembly example 300 includes a glass core 202, which includes a TGV 204 extending through it and a cavity 210 in which a CMIL 212 is placed.

[0032] The example in Figure 3A differs from the example in Figure 2A based on the inclusion of a thin film dielectric 302 (e.g., a dielectric layer) covering the outer surface of the glass core 202. That is, as shown in Figure 3A, the thin film dielectric 302 extends along the first and second surfaces 218, 220 opposite to the glass core 202, and along the sidewalls of the through-hole 208 and cavity 210. In some examples, the thin film dielectric 302 includes the same dielectric material used in the first and second buffer layers 214, 216 and / or the same dielectric material used in the dielectric material 226 filling the cavity 210. In other examples, the thin film dielectric 302 is different from the material used in the first and second buffer layers 214, 216 and different from the dielectric material 226 filling the cavity 210. More specifically, in some examples, the thin film dielectric 302 comprises at least one of silicon nitride, silicon oxide, silicon carbide, carbon-doped oxide (CDO), polyimide, parylene, and / or any other suitable dielectric material. In some examples, the thin film dielectric 302 is referred to as a repair layer because it “repairs” the underlying glass by filling in notches, cracks, and / or fissures on the surface of the glass core, thereby reducing the adverse effects of such cracks and fissures.

[0033] Figures 3B and 3C are enlarged views corresponding to the dashed box 304 shown in Figure 3A, illustrating different structural examples of the outer surface 242 of the first conductive material 206 facing the inner surface 244 of the through-hole 208. Figures 3E and 3F are top-down cross-sectional views of different TGV examples 204 shown in Figure 3A. Figures 3B-3E are substantially the same as Figures 2B-2E, except as described below and / or as otherwise evident from the context. More specifically, Figures 3B-3E show that the thin film dielectric 302 covers (e.g., contacts, abuts) the inner surface of the through-hole 208 of the glass core 202. As illustrated, in these examples, there is still (one or more) open space 246 between the inner surface 244 of the through-hole 208 and the outer surface 242 of the first conductive material 206 (e.g., TGV 204). However, in these examples, the thin film dielectric 302 is located between the glass core 202 and (one or more) open spaces 246. While (one or more) open spaces 246 may exist between the conductive material 206 of the TGV 204 and the inner surface 244 of the associated through-hole 208, in some examples, the dielectric material 226 in the cavity 210 is in direct contact (e.g., abuts) with the thin film dielectric 302 abutting against the side wall 227 of the cavity 210.

[0034] Figures 4-18 show various stages in an example manufacturing process for producing the glass core assembly example 200 of Figure 2A and / or the glass core assembly example 300 of Figure 3A. Figure 4 represents the glass panel 400 corresponding to the initial state of the glass core 202. In some examples, the glass panel 400 is manufactured to a thickness corresponding to the final thickness of the glass core 202. However, in some examples, the glass panel 400 is initially slightly larger than the final thickness of the glass core 202 to allow some amount of glass to be removed during subsequent polishing or planarization processes, which will be described further later.

[0035] Figure 5 shows the manufacturing stage after the glass core 202 has been exposed to a laser, as part of the laser-induced deep etching (LIDE) process. The laser is focused on defined regions 502 of the glass core 202, modifying the optical and / or chemical properties of the glass core 202 in those regions 502. Figure 6 shows the manufacturing stage after the chemical etching process, which removes the material within the modified regions 502 of the glass core 202 shown in Figure 5 to define the through-hole 208 for TGV 204 and the cavity 210 associated with the location of CMIL 212. In this example, both the through-hole 208 and the cavity 210 have cross-sectional profiles that generally correspond to an hourglass shape, and the width (e.g., diameter) of the opening narrows near the midpoint of the opening between the first and second surfaces 218, 220 on both sides of the glass core 202. In other examples, one or more of the through-hole 208 and / or the cavity 210 may have different cross-sectional shapes. For example, in some examples, one or more of the through-holes 208 and / or cavities 210 may be generally conical or tapered in shape, with the width (e.g., diameter) being smallest on one of the two surfaces 218, 220 of the glass core 202 and the width (e.g., diameter) being largest on the opposite surface 218, 220. In other examples, the width (e.g., diameter) of one or more of the through-holes 208 and / or cavities 210 is substantially constant along the entire length of the opening between the two surfaces 218, 220 of the glass core 202.

[0036] As shown in Figure 6, the through-hole 208 has a first width 602 that is smaller than the second width 604 of the cavity 210. In some examples, the second width 604 is significantly larger than the first width 602 (e.g., at least twice as large, at least three times as large, at least five times as large, at least ten times as large, etc.). Although the widths are different, the through-hole 208 and the cavity 210 have the same height 606 (e.g., length) defined by the thickness of the glass core (e.g., the distance between the first and second surfaces 218, 220). Thus, in the illustrated example, the through-hole 208 has a first height-to-width aspect ratio that is larger than the second height-to-width aspect ratio of the cavity.

[0037] In some examples, the manufacturing process following the steps shown in Figure 6 (and preceding Figure 7) involves depositing a thin film dielectric 302 on all external (e.g., exposed) surfaces of the glass core 202, as described above in relation to Figures 3A-3E. In some such examples, the thin film dielectric 302 is deposited using conformal coating processes (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.). In other examples, the thin film dielectric 302 is deposited using directional deposition processes (e.g., physical vapor deposition (PVD), etc.).

[0038] Figure 7 shows the manufacturing stage after the glass core 202 has been attached to the conductive carrier 702. In this example, the conductive carrier includes a conductive layer 704 (e.g., a copper layer) and a release layer 706 (e.g., an adhesive dielectric layer). Figure 8 shows the manufacturing stage after the cavity 210 within the glass core 202 has been filled with dielectric material 226. In some examples, the dielectric material 226 is dispensed into the opening as a liquid or paste (e.g., a liquid-dispensable dielectric) and then cured. In some examples, excess dielectric material 226 extending beyond the first surface 218 of the glass core 202 is removed by a polishing process (e.g., chemical mechanical planarization (CMP)). In some examples, this polishing process slightly thins the glass core 202.

[0039] Figure 9 shows the manufacturing stage after the application of a mask 902 (e.g., by photolithography) to cover the assembly except for the through-holes 208 of the glass core. The manufacturing stage shown in Figure 9 is also after an etching process (e.g., plasma etching, dry etching) to remove the portion of the delamination layer 706 exposed within the through-holes 208 of the glass core 202, thereby exposing the underlying conductive layer 704. The mask 902 protects the dielectric material 226 during the etching process.

[0040] Figure 10 illustrates the manufacturing steps after the removal (e.g., peeling) of the mask 902 and the subsequent plating of the conductive material 206 (e.g., copper) in the through-hole 208 to define the TGV 204 extending through the glass core 202. In this example, the TGV 204 is plated from the exposed portion of the conductive layer 704 upwards (e.g., bottom-up plating). Therefore, in this example, there is no seed layer deposited along the walls of the through-hole 208 prior to the plating process. However, in other examples, a seed layer may be used to facilitate the plating of the TGV 204. The manufacturing steps shown in Figure 10 are also after a subsequent polishing process (e.g., a CMP process) to remove excess copper extending over the first surface 218 of the glass core 202. Therefore, in some examples, the outer surfaces (e.g., edges) of both the dielectric material 226 and the TGV 204 are substantially coplanar and / or substantially parallel to the first surface 218. When used herein, two surfaces are substantially coplanar if there is an offset of 100 nm or less between them. Also, when used herein, two surfaces are substantially parallel if they are within 3 degrees of strictly parallel.

[0041] Figure 11 shows the manufacturing stage after the removal of the conductive carrier 702, which includes both the conductive layer 704 and the release layer 706. In some examples, the second surface 220 of the glass core 202 undergoes a polishing process (e.g., a CMP process) to make both the dielectric material 226 and TGV 204 substantially coplanar with the second surface 220. In some examples, this assembly also undergoes a cleaning process to remove residual material.

[0042] Figure 12 illustrates the manufacturing stage after the application (e.g., lamination) of the first and second buffer layers 214, 216 onto the first and second surfaces 218, 220 of the glass core 202, respectively, and across the outer surface of the dielectric material 226 within the cavity 210. Figure 12 also illustrates the result of adding conductive vias 1202 that penetrate the buffer layers 214, 216 to electrically couple the underlying TGV 204 to the outer layer 1204 of the conductive material. More specifically, holes (e.g., vias) are drilled through the buffer layers 214, 216 to expose the ends of the TGV 204, and then these holes are filled to define the material of the conductive vias 1206 and generate the outer layer 1204 of the conductive material. In some examples, the outer layer 1204 of the conductive material serves as a basis for the subsequent creation of the conductive pad 235 of the TGV 204, as described in relation to Figure 2A.

[0043] Figure 13 shows the manufacturing stage after drilling the holes 1302 that penetrate the outer layer 1204 of the conductive material, the buffer layers 214 and 216, and the dielectric material 226. Thus, the holes 1302 in Figure 13 extend through the cavity 210 in the glass core 202 and the outer layer 1204 of the conductive material. In this example, the holes 1302 define the outer extent of the first and second portions 222 and 224 of the CMIL 212 shown in Figure 2A. Unlike the through-holes 208 and cavity 210 in the glass core 202 which are produced through the LIDE process, the holes 1302 that penetrate the dielectric material 226 can be directly machined (e.g., drilled). Thus, in some examples, the holes 1302 are round holes with straight (e.g., substantially parallel along the entire length of the round hole 1302) opposing side walls. In contrast, as shown in the illustrated example, the side walls of cavity 210 are not straight (for example, they are not parallel along the entire length of the cavity wall).

[0044] Figure 14 shows the manufacturing stage after the holes 1302 have been filled with the magnetic material 232 used in CMIL212. In some examples, the magnetic material 232 is deposited into the holes 1302 as a paste or resin that is later cured. A grinding and / or polishing process (e.g., a CMP process) may then be used on both sides of this assembly to remove excess material.

[0045] Figure 15 shows the manufacturing stage after drilling the inner through-hole 1402 that penetrates the center of different parts of the magnetic material 232.

[0046] Figure 16 illustrates the manufacturing stage after the deposition of conductive material 230 onto the walls of the inner through-hole 1402 (e.g., electroplating) (e.g., the inner walls of the magnetic material 232 are plated with conductive material 230). In some examples, this is achieved by a bottom-up plating process. In other examples, this is achieved by direct plating onto the magnetic material 232 and / or a seed layer on top of the magnetic material 232. As shown in Figure 16, the remaining central region of the inner through-hole 1402 (inside the conductive material 230) is filled with a non-magnetic plug 228. In some examples, the non-magnetic plug 228 is deposited within the central region of the conductive material 230 as a paste or resin that is subsequently cured. A grinding and / or polishing process (e.g., a CMP process) may then be used on both sides of this assembly to remove excess material.

[0047] Figure 17 shows the manufacturing stage after the deposition (e.g., plating) of additional conductive material 1702 on the outer layer 1204 of conductive material added at the stage shown in Figure 12. As shown in Figure 17, the additional conductive material 1702 extends across the CMIL 212.

[0048] Figure 18 shows the manufacturing stage after selective removal (e.g., via photolithography) of a portion of the additional conductive material 1702 (and the pre-deposited outer layer of conductive material 1204) to provide the conductive pad 235 attached to the TGV 204 and the conductive pads 234 capping the ends of the first and second portions 222 and 224 of the CMIL 212. The structure of the example glass core assembly shown in Figure 18 corresponds to the structure of the example glass core assembly 200 shown in Figure 2A, and therefore represents the completion of the manufacturing process.

[0049] Figure 19 shows another example glass core assembly 1900 that can be mounted within the package substrate example 112 of Figure 1. The glass core assembly example 1900 in Figure 19 is substantially the same as the glass core assembly example 200 in Figures 2A-2E, except as described below and / or otherwise evident from the context. Thus, features shown in Figure 19 that are the same as or similar to the corresponding features in Figures 2A-2E (and related Figures 4-18) are identified by the same reference numerals. Furthermore, the descriptions of such features described above in relation to Figures 2A-2E (and related Figures 4-18) also apply similarly to the corresponding features in Figure 19.

[0050] The example in Figure 19 differs from the example in Figure 2A in the construction of the CMIL example 1902 (e.g., an electronic component) embedded in the cavity 210 of the glass core 202. Specifically, in Figure 2A, the central region of the two parts 222, 224 of CMIL 212 is defined by a non-magnetic plug 228. In contrast, in the example in Figure 19 shown, there is no non-magnetic plug in the first and second parts 1904, 1906 of CMIL 1902. Instead, the central region of the two parts 1904, 1906 is defined by a conductive material 230 (e.g., copper) that fills the entire space inside the magnetic material 232. That is, the conductive material 230 in the first and second parts 1904, 1906 is a solid mass that extends continuously from the inner surface of the magnetic material 232 to the center of the longitudinal length of parts 1904, 1906 (e.g., the central axis). In other words, in the illustrated example in Figure 19, each portion 1904, 1906 includes a solid metal core that extends continuously across the cross-section of the metal core.

[0051] Another difference between the example in Figure 2A and the example in Figure 19 is the thickness of the magnetic material 232. That is, as shown in the illustrated example, the magnetic material 232 is thicker in the example in Figure 19 than in the example in Figure 2A. In other examples (based on either Figure 2A or Figure 19), the thickness of the magnetic material 232 may differ from that shown. In addition, in the example in Figure 19, the upper and lower ends of the magnetic material 232 have the same extension as the dielectric material 226 in the cavity 210. That is, in this example, the edges (e.g., outer surfaces) of the magnetic material 232 (and dielectric material 226) are substantially coplanar with the first and second surfaces 218, 220 (e.g., outer surfaces) opposite the glass core 202. This is different from the example in Figure 2A, where the magnetic material extends beyond the dielectric material 226 and the opposite surfaces of the glass core 202.

[0052] Figure 20 shows another example glass core assembly 2000 that can be mounted within the package substrate example 112 of Figure 1. The glass core assembly example 2000 in Figure 20 is substantially the same as the glass core assembly example 1900 in Figure 19, except as described below and / or as otherwise evident from the context. Therefore, features shown in Figure 20 that are the same as or similar to the corresponding features in Figure 19 are identified by the same reference numerals. Furthermore, the descriptions of such features described above in relation to Figure 19 also apply similarly to the corresponding features in Figure 20.

[0053] The example in Figure 20 differs from the example in Figure 19 based on the inclusion of a thin film dielectric 2002 (e.g., a dielectric layer) covering the outer surface of the glass core 202. In some examples, the thin film dielectric 2002 is substantially the same as the thin film dielectric 302 in Figure 3A. Therefore, the description of the thin film dielectric 302 described above in relation to Figure 3A (and related Figures 3B-3E) also applies similarly to the thin film dielectric 2002 in Figure 20.

[0054] The process for manufacturing the glass core assembly examples 1900 and 2000 in Figures 19 and 20 can follow the same or similar process as described above in relation to the various manufacturing stages shown in Figures 4-8 in relation to the glass core assembly examples 200 and 300 in Figures 2A and 3A. However, the subsequent processes after the manufacturing stage shown in Figure 8 may differ. Figures 21-27 show the various stages in the subsequent process flow for manufacturing the glass core assembly examples 1900 and 2000 in Figures 19 and 20.

[0055] Figure 21 shows the manufacturing stage after the application of a mask 2102 (e.g., by photolithography) to cover the assembly containing the through-hole 208 and dielectric material 226 within the cavity 210 of the glass core 202. The manufacturing stage shown in Figure 21 is after the holes 2104 that penetrate the mask 2102 and the dielectric material 226 have been drilled. In this example, the holes 2104 define the outer extent of the first and second portions 1904 and 1906 of the CMIL 1902 shown in Figure 19. Thus, in this example, the holes 2104 are equivalent to the holes 1302 provided in Figure 13. Therefore, the description of the holes 1302 in Figure 13 also applies to the holes 2104 in Figure 21.

[0056] Figure 22 illustrates the manufacturing stage after the holes 2104 have been filled with the magnetic material 232 used in CMIL 212. In some examples, the magnetic material 232 is deposited in the holes 2104 as a paste or resin that is later cured. Subsequently, grinding and / or polishing processes (e.g., CMP processes) may be used on both sides of this assembly to remove excess material. In some examples, the grinding and / or polishing process is also used to remove the mask 2102, as shown in Figure 22. Alternatively, in some examples, the mask 2102 can be removed by peeling, and then a subsequent polishing and / or grinding process can be performed to remove any residue and ensure that the outer surface of the magnetic material 232 is substantially coplanar with the first surface 218 of the glass core 202.

[0057] Figure 23 shows the manufacturing stage after drilling the inner through-hole 2302 that penetrates the center of different parts of the magnetic material 232.

[0058] Figure 24 shows the manufacturing stage after the application of another mask 2402 (e.g., by photolithography) to cover the assembly except for the through-hole 208 in the glass core 202 and the inner through-hole 2302 in the magnetic material 232. The manufacturing stage shown in Figure 24 is also after an etching process (e.g., plasma etching, dry etching) to remove the portion of the delamination layer 706 exposed in the through-holes 208, 2302, thereby exposing the underlying conductive layer 704. As described above in relation to Figure 9, the mask 2402 protects the dielectric material 226 during the etching process.

[0059] Figure 25 illustrates the manufacturing steps after the removal (e.g., peeling) of the mask 2402 and the subsequent plating of conductive material 206, 230 (e.g., copper) within through-holes 208, 2302 to define the TGV 204 extending through the glass core 202 and the central region of the different parts 1904, 1906 of CMIL 1902. In this example, the through-holes 208, 2302 are plated from the exposed portion of the conductive layer 704 upwards (e.g., bottom-up plating). Therefore, in this example, there is no seed layer deposited along the walls of the through-holes 208, 2302 prior to the plating process. As a result, as described above in relation to Figures 2B-2E, (one or more) open spaces 246 (e.g., (one or more) gaps, (one or more) voids, etc.) may be located between the conductive material 206 of the TGV 204 and the sidewall (e.g., inner surface 244) of the through-hole 208. Furthermore, since the inner through-hole 2302 is plated simultaneously with the through-hole 208 in the same bottom-up plating process (for example, without a seed layer), a similar open space 246 (e.g., a gap, void, etc.) may exist between the conductive material 230 in the inner through-hole 2302 and the sidewall of the inner through-hole 2302. In other examples, a seed layer may be used to facilitate the plating of the through-holes 208 and 2302.

[0060] The manufacturing stage shown in Figure 25 is also after a subsequent polishing process (e.g., a CMP process) to remove excess copper extending over the first surface 218 of the glass core 202. Thus, in some examples, both the dielectric material 226 and TGV204 are substantially coplanar with the first surface 218. Figure 25 also shows the manufacturing stage after the application (e.g., lamination) of the first buffer layer 214 on the first surface 218 of the glass core 202, as well as across the outer surface of the dielectric material 226 and the upper edge of CMIL1902.

[0061] Figure 26 shows the manufacturing stage after the removal of the conductive carrier 702, which includes both the conductive layer 704 and the release layer 706. In some examples, the second surface 220 of the glass core 202 undergoes a polishing process (e.g., a CMP process) to make both the dielectric material 226 and TGV204 substantially coplanar with the second surface 220. In some examples, this assembly also undergoes a cleaning process to remove residual material. Figure 26 also shows the manufacturing stage after the application (e.g., lamination) of the second buffer layer 216 on the second surface 220 of the glass core 202, as well as across the outer surface of the dielectric material 226 and the lower end of CMIL1902.

[0062] Figure 27 shows the result of adding conductive pads 235 to buffer layers 214 and 216 for TGV204 and electrically coupling TGV204 to conductive pads 235 using conductive vias 2702 extending through buffer layers 214 and 216. Also, Figure 27 shows adding conductive pads 234 to buffer layers 214 and 216 for CMIL1902 and electrically coupling the conductive material 230 in CMIL1902 to conductive pads 234 using conductive vias 2704 extending through buffer layers 214 and 216. More specifically, in some examples, openings (e.g., vias) are provided (e.g., perforated) through the buffer layers and then filled (e.g., via plating) to define conductive vias 2702, and the positions of the defined conductive pads 234 and 235 are defined through a photolithography process. The structure of the example glass core assembly shown in Figure 27 corresponds to the structure of example glass core assembly 1900 shown in Figure 19, and therefore represents the completion of the manufacturing process.

[0063] Figure 28 shows another example glass core assembly 2800 that can be mounted within the package substrate example 112 of Figure 1. The glass core assembly example 2800 in Figure 28 is substantially the same as the glass core assembly example 1900 in Figure 19, except as described below and / or as otherwise evident from the context. Therefore, features shown in Figure 28 that are the same as or similar to the corresponding features in Figure 19 are identified by the same reference numerals. Furthermore, the descriptions of such features described above in relation to Figure 19 also apply similarly to the corresponding features in Figure 28.

[0064] The example in Figure 28 differs from the example in Figure 19 in the construction of a CMIL example 2802 (e.g., an electronic component) embedded within the cavity 210 of the glass core 202. Specifically, in Figure 19, two separate portions 1904 and 1906 of CMIL 1902 are defined by two separate regions of magnetic material 232. That is, in the illustrated example in Figure 19, different regions of magnetic material 232 are separated by a portion of dielectric material 226. In contrast, in the illustrated example in Figure 28, the magnetic material 232 associated with the first and second portions 2804 and 2806 of CMIL 2802 is defined by a single continuous mass of magnetic material 232. In other words, in the illustrated example of Figure 28, the first part 2804 of CMIL 2802 includes a first part of conductive material 230 and a first part of magnetic material 232 surrounding the first part of conductive material, and the first part of magnetic material 232 is a continuous extension of the second part of magnetic material 232 associated with the second part 2806 of CMIL 2802.

[0065] Figure 29 shows another example glass core assembly 2900 that can be mounted within the package substrate example 112 of Figure 1. The glass core assembly example 2900 in Figure 29 is substantially the same as the glass core assembly example 2800 in Figure 28, except as described below and / or as otherwise evident from the context. Thus, features shown in Figure 29 that are the same as or similar to the corresponding features in Figure 28 are identified by the same reference numerals. Furthermore, the descriptions of such features described above in relation to Figure 28 also apply similarly to the corresponding features in Figure 29.

[0066] The example in Figure 29 differs from the example in Figure 28 based on the inclusion of a thin-film dielectric 2902 (e.g., a dielectric layer) covering the outer surface of the glass core 202. In some examples, the thin-film dielectric 2902 is substantially the same as the thin-film dielectric 302 in Figure 3A. Therefore, the description of the thin-film dielectric 2002 described above in relation to Figure 20 also applies to the thin-film dielectric 2902 in Figure 29.

[0067] The process for manufacturing the glass core assembly examples 2800 and 2900 in Figures 28 and 29 can follow the same or similar processes described above in relation to the various manufacturing stages for the glass core assembly examples 1900 and 2000 in Figures 19 and 20. Figures 30–36 show the various stages in the process flow for manufacturing the glass core assembly examples 2800 and 2900 in Figures 28 and 29. As can be seen from the figures, Figures 30–36 generally correspond to Figures 21–27, respectively. Therefore, the same reference numerals are used to refer to the same or similar features, and the details provided above in relation to the description of Figures 21–27 also apply to Figures 30–36.

[0068] The main difference between the process flows shown in Figures 21-27 and the example process flows shown in Figures 30-36 arises in the manufacturing stage shown in Figure 30 (which roughly corresponds to Figure 21). Specifically, as shown in Figure 21, two separate holes 2104 are created (e.g., by machining, drilling, etc.) through the mask 2102 and the dielectric material 226 in the cavity 210 of the glass core 202. In contrast, in Figure 30, one (larger) hole 3002 is created (e.g., by machining, drilling, etc.) through the mask 2102 and the dielectric material 226 in the cavity 210 of the glass core 202. In this example, the hole 3002 in Figure 30 corresponds to the combined region of the two holes 2104 in Figure 21 plus the region between the two holes 2104. In other examples, the hole 3002 produced in the manufacturing stage shown in Figure 30 can be larger or smaller than shown.

[0069] The manufacturing stages shown in Figures 31-36 largely correspond to those described above in relation to Figures 22-27, with the main difference being the single hole 3002 produced in Figure 30 instead of the two separate holes 2104 described above in relation to Figure 21. Thus, Figure 31, as described above in Figure 22, represents the manufacturing stage after filling the single hole 3002 in the magnetic material 232 used for CMIL 212, and then the removal of the mask 2102. Figure 32, as described above in relation to Figure 23, represents the manufacturing stage after drilling the inner through-hole 2302 that penetrates the magnetic material 232. However, the through-hole 2302 is drilled through the same (single) block of magnetic material 232 within the same (single) hole 3002, rather than through different parts of the magnetic material 232 (as in Figure 23). Figure 33, as described above in relation to Figure 24, shows the manufacturing steps after the application of another mask 2402 and the subsequent etching process to remove a portion of the delamination layer 706. Figure 34, as described above in relation to Figure 25, shows the manufacturing steps after the removal of the mask 2402, the subsequent plating of the conductive material 206 in the through-holes 208, 2302, and the application of the first buffer layer 214. Figure 35, as described above in relation to Figure 26, shows the manufacturing steps after the removal of the conductive carrier 702 and the subsequent application of the second buffer layer 216. Finally, Figure 36, as described above in relation to Figure 27, shows the result after the addition of conductive pads 234, 235 and the associated vias 2702, 2704. The structure of the example glass core assembly shown in Figure 36 corresponds to the structure of the example glass core assembly 2800 shown in Figure 28, and therefore represents the completion of the manufacturing process.

[0070] Figure 37 shows another example glass core assembly 3700 that can be mounted within the package substrate example 112 of Figure 1. The glass core assembly example 3700 in Figure 37 is substantially the same as the glass core assembly example 200 in Figures 2A-2E, except as described below and / or as otherwise evident from the context. Thus, features shown in Figure 37 that are the same as or similar to the corresponding features in Figures 2A-2E (and related Figures 4-18) are identified by the same reference numerals. Furthermore, the descriptions of such features described above in relation to Figures 2A-2E (and related Figures 4-18) also apply similarly to the corresponding features in Figure 37.

[0071] The example in Figure 37 differs from the example in Figure 2A in the type of electronic component embedded in the cavity 210 of the glass core 202. Specifically, in Figure 2A, CMIL example 212 is embedded in the cavity 210. In contrast, in the illustrated example in Figure 37, a capacitor 3702 (e.g., a deep trench capacitor) is embedded in the cavity 210. In this example, capacitor 3702 is a deep trench capacitor mounted on a semiconductor (e.g., silicon) substrate. That is, in this example, capacitor 3702 is a semiconductor die (e.g., similar to semiconductor dies 108 and 110 in Figure 1).

[0072] In some examples, the capacitor 3702 includes a first surface 3704 (e.g., the top surface) and a second surface 3706 (e.g., the bottom surface) opposite to the first surface 3704, defining the thickness of the capacitor 3702. In some examples, as shown in Figure 37, the thickness of the capacitor 3702 is less than the thickness of the glass core 202. In other examples, the thickness of the capacitor 3702 is approximately equal to the thickness of the glass core 202.

[0073] As shown in the illustrated example in Figure 37, the capacitor 3702 is surrounded by the dielectric material 226 (e.g., encased, surrounded by it). Thus, in some examples, the dielectric material 226 separates the capacitor 3702 from the sidewalls 227 of the cavity 210 of the glass core 202. In some examples, at least one (both in the illustrated example) of the first or second surface 3704, 3706 of the capacitor 3702 is inserted into or recessed into adjacent outer surfaces 218, 220 of the glass core 202. In such examples, the (one or more) inserted surfaces 3704, 3706 are covered by the dielectric material 226. That is, as shown in the illustrated example, the dielectric material 226 separates the capacitor 3702 from the buffer layers 214, 216. In other examples, at least one of the first or second surface of the capacitor 3702 is substantially coplanar with adjacent outer surfaces 218, 220 of the glass core 202. In some such examples, the associated (one or more) buffer layers 214, 216 can be in direct contact with the (one or more) surfaces 3704, 3706 of the capacitor 3702.

[0074] In this example, the capacitor 3702 includes two contact pads 3708 on the first surface 3704, the contact pads 3708 being electrically coupled to a conductive pad 3710 on the first buffer layer 214 by conductive vias extending through the first buffer layer 214. In this example, the contact pads 3708 protrude outward from the first surface 3704 of the capacitor 3702, resulting in the first surface 3704 being recessed or inserted into the outer surface 218 of the glass core 202. In other examples, the contact pads 3708 of the capacitor 3702 may be embedded within the first surface 3704 of the capacitor 3702 and coplanar with the first surface 3704.

[0075] Figure 38 shows another example glass core assembly 3800 that can be mounted within the package substrate example 112 of Figure 1. The glass core assembly example 3800 in Figure 38 is substantially the same as the glass core assembly example 3700 in Figure 37, except as described below and / or as otherwise evident from the context. Therefore, features shown in Figure 38 that are the same as or similar to the corresponding features in Figure 37 are identified by the same reference numerals. Furthermore, the descriptions of such features described above in relation to Figure 37 also apply similarly to the corresponding features in Figure 38.

[0076] The example in Figure 38 differs from the example in Figure 37 based on the inclusion of a thin film dielectric 3802 (e.g., a dielectric layer) covering the outer surface of the glass core 202. In some examples, the thin film dielectric 3802 is substantially the same as the thin film dielectric 302 in Figure 3A. Therefore, the description of the thin film dielectric 302 described above in relation to Figure 3A (and related Figures 3B-3E) also applies similarly to the thin film dielectric 3802 in Figure 38.

[0077] The process for manufacturing the glass core assembly examples 3700 and 3800 in Figures 37 and 38 can follow the same or similar process as described above in relation to the various manufacturing stages shown in Figures 4-7 in relation to the glass core assembly examples 200 and 300 in Figures 2A and 3A. However, the subsequent processes after the manufacturing stage shown in Figure 7 may differ. Figures 39-44 show the various stages in the subsequent process flow for manufacturing the glass core assembly examples 3700 and 3800 in Figures 37 and 38.

[0078] Figure 39 shows the manufacturing stage after the capacitor 3702 has been placed on the conductive carrier 702 within the cavity 210 of the glass core 202. In some examples, the capacitor 3702 is placed upside down (for example, with the first (top) surface 3704 facing downwards toward the conductive carrier 702). In some such examples, the glass core 202 is also placed upside down (for example, with the first surface 218 facing downwards toward the conductive carrier 702). In other examples, the capacitor 3702 remains face up when placed within the cavity 210.

[0079] The manufacturing stages shown in Figures 40-43 largely correspond to the process flow described above in relation to Figures 8-11, except for the presence of the capacitor 3702 in the cavity. Thus, the explanations provided above for Figures 8-11 also apply to the manufacturing stages shown in Figures 40-43, except for what is described below and / or otherwise evident from the context. Specifically, Figure 40 represents the manufacturing stage after the cavity 210 in the glass core 202 has been filled with dielectric material 226, similar to what was described above in relation to Figure 8. In this example, the dielectric material 226 is dispensed around the capacitor 3702 already placed in the cavity 210. Thus, the dielectric material 226 surrounds (e.g., encapsulates, wraps around, etc.) the capacitor 3702. Figure 41 represents the manufacturing stage after the application of the mask 902 and the subsequent etching process to remove part of the delamination layer 706, similar to what was described above in relation to Figure 9. Figure 42, similar to that described above in relation to Figure 10, shows the manufacturing steps after the removal of the mask 902 and the subsequent plating of the conductive material 206 in the through-hole 208 to define the TGV 204. Figure 43, similar to that described above in relation to Figure 11, shows the manufacturing steps after the removal of the conductive carrier 702.

[0080] Figure 44 shows the manufacturing stage after the application (e.g., lamination) of the first and second buffer layers 214, 216 on the outer surfaces 218, 220 of the glass core 202 and the outer surface of the dielectric material 226 in the cavity 210. Figure 44 also shows the result of adding conductive vias 1202 through the buffer layers 214, 216 to electrically couple the underlying TGV 204 to the corresponding conductive pad 235 and the contact pad 3708 of the capacitor 3702 to the corresponding conductive pad 3710. More specifically, holes (e.g., vias) are drilled through the buffer layers 214, 216 to expose the ends of the TGV 204 and the contact pad 3708 of the capacitor 3702. The holes are then filled to define the material for the conductive vias 1206 and to generate the conductive pads 235, 3710. Figure 44 also shows the entire assembly being inverted or flipped over so that the capacitor 3702 has its front side facing up. The structure of the example glass core assembly shown in Figure 44 corresponds to the structure of the example glass core assembly 3700 shown in Figure 37, and therefore represents the completion of the manufacturing process.

[0081] The above-mentioned examples of glass core assemblies 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800 teach or suggest different features. Each of the glass core assemblies 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800 disclosed above has certain features, but it should be understood that certain features of one example are not necessarily used exclusively with that example. Instead, any of the features described above and / or shown in the drawings can be combined with any of those examples, in addition to or substituting for any of the other features of those examples. Features of one example are not mutually exclusive with features of another example. Instead, the scope of this disclosure encompasses any combination of any features among the features. Therefore, for example, two or more different CMIL structures, such as those shown in Figures 2A, 3A, 19, 20, 28, and 29, can be mounted within the same glass core (for example, within the same cavity or different cavities within the glass core). Also, the capacitor 3702 in Figures 37 and 38 can be mounted within the same glass core as any of the CMIL structures in Figures 2A, 3A, 19, 20, 28, and 29 (for example, within the same cavity or different cavities within the glass core).

[0082] Figure 45 shows a glass panel example 4500 that can be processed according to the teachings disclosed herein to manufacture any of the glass core assembly examples 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800 of Figures 2A, 3A, 19, 20, 28, 29, 37, and 38. In the illustrated example, the glass panel 4500 defines separate active areas 4502, 4504, 4506, and 4508 corresponding to areas related to a particular glass core (e.g., glass core 132 in Figure 1) for a particular package substrate (e.g., package substrate 112 in Figure 1). That is, in a subsequent manufacturing step, the glass panel example 4500 of Figure 45 is cut or pieced into four separate pieces that serve as the basis for four separate package substrates. The area outside of the active areas 4502, 4504, 4506, and 4508 is referred to as the Keep Out Zone (KOZ) 4510.

[0083] As shown in Figure 45, the KOZ4510 of the glass panel 4500 includes one or more tooling holes 4512. The tooling holes can facilitate the handling and / or positioning of the glass panel 4500 and / or the alignment of manufacturing tools to the glass panel 4500 at various stages of manufacturing. That is, in some examples, the tooling holes 4512 function as reference markers used for alignment purposes. Four tooling holes 4512 are shown in the KOZ4510, but in other examples, a different number of tooling holes 4512 may be implemented. In some examples, the tooling holes 4512 are omitted. Furthermore, while tooling holes 4512 are most commonly implemented within KOZ 4510 (so as not to occupy space within active areas 4502, 4504, 4506, and 4508), some examples include one or more additional tooling holes 4514 within one or more of the active areas 4502, 4504, 4506, and 4508. In this example, one additional tooling hole 4514 is included within one of the active areas (e.g., the first active area 4502). In other examples, two or more of the active areas 4502, 4504, 4506, and 4508 (e.g., all of them) include one or more tooling holes 4514. In other examples, none of the active areas 4502, 4504, 4506, and 4508 include any tooling holes 4514.

[0084] In some examples, the tooling holes 4512 and 4514 are manufactured during the same manufacturing process used to produce the through-hole 208 for TGV204 and the cavity 210 for housing electronic components (e.g., one or more of CMIL212, 1902, 2802, and / or capacitor 3702). That is, in some examples, the tooling holes 4512 and 4514 are manufactured during the LIDE process described above in relation to Figures 5 and 6. In the illustrated example of Figure 45, the through-hole 208 and cavity 210 are not shown for simplicity. Also, the tooling holes 4512 and 4514 can typically be much larger than the through-hole 208 and much larger than the cavity 210.

[0085] Since the tooling holes 4512 and 4514 are fabricated simultaneously with the through-holes 208 and the cavity 210, in examples including the thin-film dielectrics 302, 2002, 2902, and 3802, the inner sidewalls of the tooling holes 4512 and 4514 are lined or covered with the thin-film dielectrics 302, 2002, 2902, and 3802. However, due to the larger size of the tooling holes 4512 and 4514 compared to other openings in the glass panel 4500 (e.g., the through-holes 208 and the cavity 210), the tooling holes 4512 and 4514 are not filled with the conductive material 206 during the bottom-up plating process performed to form the TGV 204 (as described above in relation to Figures 9 and 10). That is, even after the plating process that produces the TGV 204, the tooling holes 4512 and 4514 remain empty. As a result, in some examples, the tooling holes 4512 and 4514 are filled with different materials applied during a later manufacturing process. More specifically, in some examples, the tooling holes 4512 and 4514 are filled with magnetic material 232. As described above in relation to Figure 14, in some examples, the magnetic material 232 is deposited as a paste or resin that is later cured. More specifically, in some examples, the magnetic material 232 is applied as a paste over the entire surface of the glass panel 4500, thereby resulting in the tooling holes 4512 and 4514 being filled with magnetic material 232, as shown in Figure 46.

[0086] Figure 46 shows a reconfigured panel example 4600 containing the glass panel example 4500 of Figure 45 within a frame example 4602. Frame example 4602 allows for compatibility with manufacturing tools specifically designed for organic cores rather than glass cores. That is, frame example 4602 allows the glass panel 4500 to be processed using manufacturing techniques typically intended for organic cores, while protecting the glass panel 4500 from damage. As shown in Figure 46, the tooling holes 4512, 4514 are filled with magnetic material 232, and the magnetic material also extends around the outer periphery of the glass panel 4500. In some examples, the magnetic material 232 still fills the tooling holes 4512, 4514, and different materials extend along the outer periphery of the glass panel 4500. Thus, the presence of magnetic material 232 in the tooling holes 4512, 4514 indicates that the process example disclosed herein was followed when manufacturing the glass panel 4500 of Figure 45.

[0087] Figures 47A–49 are flowcharts illustrating example methods for manufacturing one of the glass core assembly examples 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800 shown in Figures 2A, 3A, 19, 20, 28, 29, 37, and 38, which can be implemented in the IC package example 100 of Figure 1. In some examples, some or all of the operations outlined in the example methods of Figures 47A–49 are performed automatically by manufacturing equipment programmed to perform those operations. That is, in some examples, the example method or part thereof may be implemented and / or controlled by one or more processor circuits executing instructions based on data from sensors and / or user input. The example manufacturing method is described with reference to the flowcharts shown in Figures 47A–49, but numerous other methods may be used instead. For example, the execution order of blocks can be changed, and / or parts of the described blocks can be combined, split, rearranged, omitted, removed, and / or performed in some other way. Also, in some examples, additional processing operations may be performed before, between, and / or after any of the blocks shown in the illustrated examples.

[0088] The process example begins in block 4702 by providing an opening through a glass core (e.g., glass core 202). In some examples, the glass core 202 in this manufacturing stage is part of a glass panel, such as glass panel example 4500 in Figure 45. In some examples, the opening provided in the glass core 202 includes a through-hole 208 for TGV 204, a cavity 210 for housing electronic components, and / or tooling holes 4512, 4514. In some examples, the opening is provided by the LIDE process as described above in relation to Figures 5 and 6.

[0089] In block 4704, the process example includes determining whether to add a thin dielectric layer. If so, the process proceeds to block 4706, where the exposed surface of the glass core is covered with a thin dielectric (e.g., thin dielectrics 302, 2002, 2902, 3802). The process then proceeds to block 4708. If no thin dielectric layer is added (as determined in block 4704), the process proceeds directly to block 4708.

[0090] In block 4708, the process example includes mounting the glass core onto a conductive carrier (e.g., the conductive carrier 702 as described above in relation to Figure 7). In block 4710, the process example includes determining whether at least one opening contains at least one semiconductor device (e.g., capacitor 3702 and / or any other suitable semiconductor device). If so, the process proceeds to block 4712, where (one or more) semiconductor devices are placed within (one or more) openings (e.g., capacitor 3702 is placed within cavity 210 as described above in relation to Figure 39). The process then proceeds to block 4714. If no semiconductor devices are included (as determined in block 4710), the process proceeds directly to block 4714.

[0091] In block 4714, the process example includes depositing a dielectric material (e.g., dielectric material 226) in any other (one or more) openings (e.g., other cavities 210) which should include (one or more) openings (e.g., cavities 210) containing (one or more) semiconductor elements and / or at least one CMIL (e.g., at least one of CMIL 212, 1902, 2802).

[0092] In block 4716, the process example includes determining whether at least one CMIL contains a conductive material (e.g., conductive material 230) that is deposited simultaneously (e.g., in parallel) with the conductive material (e.g., conductive material 206) that is deposited for TGV204. If so, the process proceeds to block 4718, in which the CMIL structure is manufactured to be plated simultaneously with TGV204. Further details regarding the implementation of block 4718 are provided below in relation to Figure 48. The process then proceeds to block 4720. If none of the CMILs contain conductive materials deposited simultaneously with the conductive materials for TGV (as determined in block 4716), the process proceeds directly to block 4720.

[0093] In block 4720, the process example involves applying a mask (for example, one of the masks 902, 2402 described above in relation to Figures 9, 24, 33, and 41) that exposes the openings to be plated. In some examples, these openings include through-holes 208 for TGV204, while the cavity 210 is covered as illustrated and described in relation to Figures 9 and 41. In some examples, these openings also include inner through-holes 2302 in the magnetic material 232 inside the cavity 210, as illustrated and described in relation to Figures 23 and 32. The process then proceeds to block 4722, shown at the top of Figure 47B.

[0094] In block 4722, the process example includes depositing a conductive material within an exposed opening. In the example where only the through-hole 208 for TGV204 is exposed, the conductive material corresponds to the conductive material 206 described above in relation to Figures 10 and 42. In the example where the inner through-hole 2302 within the magnetic material 232 is also exposed, the conductive material corresponds to both the conductive material 206 and the conductive material 230 within CMIL1902 and 2802 described above in relation to Figures 25 and 34.

[0095] In block 4724, the process example includes removing masks 902 and 2402 from the glass core 202. In block 4726, the process example includes removing conductive carriers 702 from the glass core 202. In block 4728, the process example includes depositing buffer layers (e.g., buffer layers 214 and 216) on the outer surfaces 218 and 220 of the glass core 202. In some examples, the first buffer layer 214 may be added before the conductive carriers 702 are removed (as shown in Figures 25 and 26 or Figures 34 and 35). In other examples, the conductive carriers 702 are removed before either buffer layer 214 or 216 is added (as shown in Figures 11 and 12 or Figures 43 and 44).

[0096] In block 4730, the process example includes adding conductive vias (e.g., conductive vias 1202, 2702, 2704 as described above in relation to Figures 12, 27, 36, and 44) ​​that penetrate the buffer layers 214, 216. In some examples, the conductive vias connect to the contact pad 3708 of the underlying TGV 204, the underlying CMIL copper core, and / or the underlying capacitor 3702.

[0097] In block 4732, the process example includes determining whether at least one CMIL contains a conductive material (e.g., conductive material 230) deposited separately from the TGV 204. If so, the process proceeds to block 4734, where one or more CMILs are manufactured using the conductive material deposited separately from the TGV 204. In some examples, the use of separate plating of the CMILs makes it possible to include a non-magnetic plug (e.g., non-magnetic plug 228). Further details regarding the implementation of block 4734 are provided below in relation to Figure 49. The process then proceeds to block 4736. If none of the CMILs contain a conductive material deposited separately from the TGV (as determined in block 4732), the process proceeds directly to block 4736.

[0098] In block 4736, the process example includes adding conductive pads that are electrically coupled to the conductive vias (added in block 4730) and / or to the cap ends of (one or more) CMILs (as described in relation to Figures 17 and 18). The process examples in Figures 47A and 47B then end.

[0099] Figure 48 is a flowchart illustrating an example process for carrying out block 4718 of Figure 47A. This example process begins in block 4802, where a mask (e.g., the mask 2102 mentioned above in relation to Figures 21 and 30) is applied to cover the opening for TGV204 (e.g., through-hole 208). In block 4804, the example process involves drilling (one or more) holes through the dielectric material extending through the opening in the glass core 202. In some examples, these (one or more) holes also penetrate the mask 2102. In some examples, multiple holes (e.g., hole 2104 in Figure 21) are drilled to define different parts of a given CMIL (e.g., different parts 1904, 1906 of CMIL 1902). In another example, a hole (e.g., hole 3002 in Figure 30) is made to define the area of ​​all parts of a given CMIL (e.g., both parts 2804 and 2806 of CMIL 2802).

[0100] In block 4806, the process example includes filling the (one or more) holes with a magnetic material (e.g., the magnetic material 232 described above in relation to Figures 22 and 31). As described above, in some examples, the magnetic material 232 is added as a paste covering the entire assembly located below. Thus, in some examples, the magnetic material 232 also fills the tooling holes 4512, 4514. The magnetic material 232 in the tooling holes 4512, 4514 is not intended to serve a purpose and is a result of the manufacturing process disclosed herein.

[0101] In block 4808, the process example includes removing the mask 2102 from the glass core 202. In block 4810, the process example includes drilling an inner through-hole (e.g., the inner through-hole 2302 described above in relation to Figures 23 and 32) through the magnetic material 232. The process example in Figure 48 is then completed, and the process returns to complete the process examples in Figures 47A and 47B.

[0102] Figure 49 is a flowchart illustrating an example process for carrying out block 4734 of Figure 47B. This example process begins in block 4902 by adding an outer layer of conductive material (e.g., the outer layer 1204 of conductive material described above in relation to Figure 12) on top of the buffer layers 214, 216. In block 4904, the example process involves drilling (one or more) holes through the dielectric material that extends through the openings in the glass core 202. In some examples, these (one or more) holes also penetrate the outer layer 1204 of conductive material and the buffer layers 214, 216. In some examples, multiple holes (e.g., hole 1302 in Figure 13) are drilled to define different parts of a given CMIL (e.g., different parts 222, 224 of CMIL 212). In other examples, a single hole is made to define the area of ​​all parts of a given CMIL (e.g., both parts 2804 and 2806 of CMIL 2802) (for example, as shown above for CMIL 2802 in relation to Figures 28-36).

[0103] In block 4906, the process example includes filling the (one or more) holes with a magnetic material (e.g., the magnetic material 232 described above in relation to Figure 14). In block 4908, the process example includes creating an inner through-hole (e.g., the inner through-hole 1502 described above in relation to Figure 15) that penetrates the magnetic material 232.

[0104] In block 4910, the process example includes plating the walls of the inner through-hole 1502 with a conductive material, leaving the central region open (as illustrated and described in relation to Figure 16). In block 4912, the process example includes filling the central region with a non-magnetic plug (e.g., the non-magnetic plug 228 shown in Figure 16). In block 4914, the process example includes polishing the glass core assembly to produce a flat outer surface. The process example in Figure 49 is then completed, and the process returns to complete the process examples in Figures 47A and 47B.

[0105] The IC package example 100 of Figure 1, having any of the glass core assembly examples 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800 disclosed herein, can be incorporated into any suitable electronic component. Figures 50–53 show various examples of devices that include or may include the IC package 100 disclosed herein.

[0106] Figure 50 is a top view of a wafer 5000 and die 5002 that may be included in the IC package 100 of Figure 1 (for example, as any preferred die among dies 108, 110). The wafer 5000 comprises a semiconductor material and one or more dies 5002 having circuits. Each die 5002 may be a repeating unit of a semiconductor product. After the manufacturing of the semiconductor product is complete, the wafer 5000 may undergo a fragmentation process in which the dies 5002 are separated from each other to provide individual “chips”. The die 5002 includes one or more transistors (for example, some of the transistors 5140 in Figure 51 described below), support circuits for routing electrical signals to the transistors, passive components (for example, traces, resistors, capacitors, inductors, and / or other circuits), and / or any other components. In some examples, die 5002 may include and / or implement memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridging RAM (CBRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuits or electronics. Multiple of these devices may be combined on a single die 5002. For example, a memory array of multiple memory circuits may be formed on the same die 5002 as a programmable circuit (e.g., the processor circuit 5302 in Figure 53) and / or other logic circuits. Such memory may store information for use by the programmable circuit. The IC package example 100 disclosed herein may be manufactured using die-to-wafer assembly technology, in which some dies are mounted on a wafer 5000 containing other dies, and the wafer 5000 is then sectionalized.

[0107] Figure 51 is a side cross-sectional view of an IC device 5100 that may be included in one of the IC package examples 100 disclosed herein (e.g., any of dies 108 or 110). One or more of the IC devices 5100 may be included in one or more dies 5002 (Figure 50). The IC device 5100 may be formed on a die substrate 5102 (e.g., wafer 5000 in Figure 50) and may be included in a die (e.g., die 5002 in Figure 50). The die substrate 5102 may be a semiconductor substrate containing a semiconductor material including, for example, an n-type or p-type material system (or a combination of both). The die substrate 5102 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 5102 may be formed using alternative materials that may or may not be combined with silicon, and such alternative materials may include, but are not limited to, germanium, indium antimony, lead telluride, indium arsenide, indium phosphorus, gallium arsenide, or gallium antimony. Further materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 5102. A few examples of materials on which the die substrate 5102 may be formed are described here, but any material that can function as the basis for the IC device 5100 may be used. The die substrate 5102 may be part of a detached die (e.g., die 5002 in Figure 50) or a wafer (e.g., wafer 5000 in Figure 50).

[0108] The IC device 5100 may include one or more device layers 5104 disposed on and / or on the die substrate 5102. The device layer 5104 may include features of one or more transistors 5140 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 5102. The device layer 5104 may include, for example, one or more source and / or drain (S / D) regions 5120, a gate 5122 for controlling the current between the S / D regions 5120, and one or more S / D contacts 5124 for routing electrical signals to and from the S / D regions 5120. The transistor 5140 may include further features not shown for clarity, such as element isolation regions and gate contacts. The transistor 5140 is not limited to the type and configuration shown in Figure 51 and may include a wide variety of other types and / or configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include, for example, FinFET transistors such as double-gate transistors or tri-gate transistors, as well as wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0109] Each transistor 5140 may include a gate 5122 comprising a gate dielectric and a gate electrode. The gate dielectric may include one or more layers in a stack. These one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric material. High-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. In some cases, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0110] The gate electrode can be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 5140 is a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one which is a filler metal layer. Further metal layers, such as a barrier layer, may also be included. In PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or any of the metals described below with reference to NMOS transistors (e.g., with regard to work function tuning). In NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and / or aluminum carbide), and / or any of the metals mentioned above with reference to PMOS transistors (e.g., with respect to work function tuning).

[0111] In some examples, when viewed as a cross-section of transistor 5140 along the source-channel-drain direction, the gate electrode may include a U-shaped structure comprising a bottom substantially parallel to the surface of the die substrate 5102 and two sidewalls substantially perpendicular to the top surface of the die substrate 5102. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer substantially parallel to the top surface of the die substrate 5102 and not comprising sidewalls substantially perpendicular to the top surface of the die substrate 5102. In other examples, the gate electrode may include a combination of a U-shaped structure and / or a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0112] In some examples, a pair of sidewall spacers may be formed on the sides of the gate stack, flanking the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. The process for forming the sidewall spacers is well known in the art and generally involves deposition and etching processes. In some examples, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on both sides of the gate stack.

[0113] The S / D region 5120 may be formed in the die substrate 5102 adjacent to the gate 5122 of the corresponding (one or more) transistors 5140. The S / D region 5120 may be formed, for example, using an ion implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 5102 to form the S / D region 5120. An annealing process may follow the ion implantation process to activate the dopants and further diffuse them into the die substrate 5102. In the latter process, the die substrate 5102 may first be etched to form a recess at the location of the S / D region 5120. Then, an epitaxial deposition process may be performed to fill the recess with the material used to manufacture the S / D region 5120. In some implementations, the S / D region 5120 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some examples, the S / D region 5120 may be formed using one or more alternative semiconductor materials such as germanium or III-V material or alloy. In further examples, one or more layers of metal and / or metallic alloy may be used to form the S / D region 5120.

[0114] For example, electrical signals such as power and / or input / output (I / O) signals can be routed to and from devices in device layer 5104 (e.g., transistor 5140) through one or more interconnect layers (shown in Figure 51 as interconnect layers 5106-5110) located on device layer 5104. For example, conductive features of device layer 5104 (e.g., gate 5122 and S / D contact 5124) can be electrically coupled to interconnect structures 5128 of interconnect layers 5106-5110. One or more interconnect layers 5106-5110 can form a metallization stack (also referred to as an "ILD stack") 5119 of the IC device 5100.

[0115] The interconnect structure 5128 can be configured within the interconnect layers 5106-5110 to route electrical signals according to a wide variety of designs (in particular, its configuration is not limited to the interconnect structure 5128 in the specific configuration depicted in Figure 51). Although Figure 51 depicts a specific number of interconnect layers 5106-5110, examples of the present disclosure include IC devices with more or fewer interconnect layers than those depicted.

[0116] In some examples, the interconnect structure 5128 may include lines 5128a and / or vias 5128b filled with a conductive material, such as metal. Lines 5128a may be configured to route electrical signals in a plane substantially parallel to the surface of the die substrate 5102 on which the device layer 5104 is formed. For example, lines 5128a may route electrical signals in and / or out of the plane of the paper from the viewpoint of Figure 51. Vias 5128b may be configured to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 5102 on which the device layer 5104 is formed. In some examples, vias 5128b may electrically couple lines 5128a of different interconnect layers 5106-5110 together.

[0117] The interconnect layers 5106-5110 may include dielectric material 5126 disposed between interconnect structures 5128, as shown in Figure 51. In some examples, the dielectric material 5126 disposed between interconnect structures 5128 in different layers of the interconnect layers 5106-5110 may have different compositions, while in other examples, the composition of the dielectric material 5126 between different interconnect layers 5106-5110 may be the same.

[0118] The first interconnect layer 5106 (referred to as metal 1 or “M1”) may be formed directly on the device layer 5104. In some examples, the first interconnect layer 5106 may include lines 5128a and / or vias 5128b, as shown in the figure. Lines 5128a of the first interconnect layer 5106 may be coupled to contacts of the device layer 5104 (e.g., S / D contacts 5124).

[0119] The second interconnect layer 5108 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 5106. In some examples, the second interconnect layer 5108 may include vias 5128b for connecting lines 5128a of the second interconnect layer 5108 to lines 5128a of the first interconnect layer 5106. For clarity, lines 5128a and vias 5128b are structurally contoured by lines within each interconnect layer (e.g., within the second interconnect layer 5108), although lines 5128a and vias 5128b may, in some examples, be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0120] A third interconnect layer 5110 (referred to as metal 3 or “M3”) (and, if applicable, additional interconnect layers) may be formed successively on the second interconnect layer 5108, in accordance with the same techniques and / or configurations described in relation to the second interconnect layer 5108 or the first interconnect layer 5106. In some examples, “higher” interconnect layers (i.e., further away from the device layer 5104) in the metallization stack 5119 within the IC device 5100 can be thicker.

[0121] The IC device 5100 may include a solder resist material 5134 (e.g., polyimide or similar material) formed on interconnect layers 5106-5110 and one or more conductive contacts 5136. In Figure 51, the conductive contacts 5136 are shown as bond pads. The conductive contacts 5136 may be electrically coupled to an interconnect structure 5128 and configured to route electrical signals from (one or more) transistors 5140 to other external devices. For example, solder bonds may be formed on one or more conductive contacts 5136 to mechanically and / or electrically couple a chip containing the IC device 5100 to another component (e.g., a circuit board). The IC device 5100 may include additional or alternative structures for routing electrical signals from interconnect layers 5106-5110; for example, the conductive contacts 5136 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0122] Figure 52 is a side cross-sectional view of an IC device assembly 5200 which may include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 5200 includes several components arranged on a circuit board 5202 (which may be, for example, a motherboard). The IC device assembly 5200 includes components arranged on a first surface 5240 of the circuit board 5202 and a second opposite surface 5242 of the circuit board 5202, and generally, components may be arranged on one or both of surfaces 5240 and 5242. Any of the IC packages described later with reference to the IC device assembly 5200 may take the form of the IC package example 100 shown in Figure 1.

[0123] In some examples, the circuit board 5202 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. One or more of the metal layers may be formed with a desired circuit pattern for routing electrical signals (optionally together with other metal layers) between components coupled to the circuit board 5202. In other examples, the circuit board 5202 may be a non-PCB package substrate.

[0124] The IC device assembly 5200 shown in Figure 52 may include a package-on-interposer structure 5236 coupled to a first surface 5240 of a circuit board 5202 by a coupling component 5216. The coupling component 5216 can electrically and mechanically couple the package-on-interposer structure 5236 to the circuit board 5202 and may also include solder balls (as shown in Figure 52), male and female parts of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0125] The package-on-interposer structure 5236 may include an IC package 5220 coupled to an interposer 5204 by a coupling component 5218. The coupling component 5218 can take any form suitable for the application, such as the form described above with reference to coupling component 5216. Although one IC package 5220 is shown in Figure 52, multiple IC packages may be coupled to the interposer 5204, and in fact, additional interposers may be coupled to the interposer 5204. The interposer 5204 can provide an intervening substrate used to bridge the circuit board 5202 and the IC package 5220. The IC package 5220 may be, for example, a die (die 5002 in Figure 50), an IC device (e.g., IC device 5100 in Figure 51), or any other suitable component, or may include such a component. Generally, the interposer 5204 can spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 5204 may couple an IC package 5220 (e.g., a die) to a set of BGA conductive contacts of a coupling component 5216 for coupling to a circuit board 5202. In the example shown in Figure 52, the IC package 5220 and the circuit board 5202 are mounted on opposite sides of the interposer 5204, while in other examples, the IC package 5220 and the circuit board 5202 may be mounted on the same side of the interposer 5204. In some examples, three or more components may be interconnected by the interposer 5204.

[0126] In some examples, the interposer 5204 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 5204 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polymer material such as polyimide. In some examples, the interposer 5204 may be formed of another rigid or flexible material, which may include the same materials used for semiconductor substrates as described above, such as silicon, germanium, other Group IV materials, and Group III-V materials. The interposer 5204 may include, but is not limited to, through-silicon vias (TSVs) 5206, metal interconnects 5208, and vias 5210. The interposer 5204 may further include embedded devices 5214, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 5204. The package-on-interposer structure 5236 may take any form of package-on-interposer structure known in the art.

[0127] The IC device assembly 5200 may include an IC package 5224 coupled to the first surface 5240 of the circuit board 5202 by a coupling component 5222. The coupling component 5222 can take any form of the examples described above with reference to coupling component 5216, and the IC package 5224 can take any form of the examples described above with reference to IC package 5220.

[0128] The IC device assembly 5200 shown in Figure 52 includes a package-on-package structure 5234 coupled to a second surface 5242 of a circuit board 5202 by a coupling component 5228. The package-on-package structure 5234 may include a first IC package 5226 and a second IC package 5232 coupled together by a coupling component 5230 such that the first IC package 5226 is positioned between the circuit board 5202 and the second IC package 5232. The coupling components 5228 and 5230 can take any form of one of the examples of coupling components 5216 described above, and the IC packages 5226 and 5232 can take any form of one of the examples of IC packages 5220 described above. The package-on-package structure 5234 may be configured according to any package-on-package structure known in the art.

[0129] Figure 53 is a block diagram of an electrical device example 5300 which may include one or more of the IC package examples 100. For example, any preferred components of the electrical device 5300 may include one or more of the device assemblies 5200, IC devices 5100, or dies 5002 disclosed herein, which may be placed within the IC package example 100. Although several components are shown in Figure 53 to be included in the electrical device 5300, one or more of these components may be omitted or repeated as appropriate for the application. In some examples, some or all of the components included in the electrical device 5300 may be mounted on one or more motherboards. In some examples, some or all of these components are manufactured on a single system-on-a-chip (SOC) die.

[0130] Furthermore, in various embodiments, the electrical device 5300 may not include one or more of the components shown in Figure 53, but may include interface circuits for coupling to such one or more components. For example, the electrical device 5300 may not include the display 5306, but may include a display interface circuit (e.g., a connector and a drive circuit) to which the display 5306 can be coupled. In another set of examples, the electrical device 5300 may not include the audio input device 5318 (e.g., a microphone) or the audio output device 5308 (e.g., a speaker, headset, earphone, etc.), but may include an audio input or output device interface circuit (e.g., a connector and a support circuit) to which the audio input device 5318 or the audio output device 5308 can be coupled.

[0131] The electrical device 5300 may include a programmable circuit 5302 (e.g., one or more processing devices). The programmable circuit 5302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or other suitable processing devices. The electrical device 5300 may include a memory 5304 which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some examples, the memory 5304 may include memory that shares a die with the programmable circuit 5302. This memory can be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0132] In some examples, the electrical device 5300 may include a communication chip 5312 (e.g., one or more communication chips). For example, the communication chip 5312 may be configured to manage wireless communication for the transmission of data to and from the electrical device 5300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid medium using modulated electromagnetic radiation. This term does not mean that the devices in question do not include any wires, although in some examples they may not include any wires.

[0133] The communication chip 5312 may implement any of the many wireless standards or protocols. These wireless standards or protocols include, but are not limited to, WiFi (IEEE 802.11 family), IEEE standards including the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), the Long-Term Evolution (LTE) project and its amendments, updates and / or revisions (e.g., the Advanced LTE project), the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc. Broadband wireless access (BWA) networks compliant with IEEE 802.16 are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformity and interoperability testing of the IEEE 802.16 standard. The communication chip 5312 may operate in accordance with Global System for Mobile Communications (GSM; registered trademark), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 5312 may also operate in accordance with Enhanced Data Rate for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Telescopic Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 5312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as other radio protocols designated as 3G, 4G, 5G, and later. In other examples, the communication chip 5312 may operate in accordance with other radio protocols.The electrical device 5300 may include an antenna 5322 for assisting and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0134] In some examples, the communication chip 5312 may manage wired communication, such as electrical, optical, or other suitable communication protocols (e.g., Ethernet®). As described above, the communication chip 5312 may include multiple communication chips. For example, a first communication chip 5312 may be used for shorter-range wireless communication, such as Wi-Fi® and / or Bluetooth®, and a second communication chip 5312 may be used for longer-range wireless communication, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, or others. In some examples, the first communication chip 5312 may be used for wireless communication and the second communication chip 5312 for wired communication.

[0135] The electrical equipment 5300 may include a battery / power circuit 5314. The battery / power circuit 5314 may include a circuit for connecting components of the electrical equipment 5300 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the electrical equipment 5300 (e.g., AC line power).

[0136] The electrical device 5300 may include a display 5306 (or, as described above, a corresponding interface circuit). The display 5306 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0137] The electrical device 5300 may include an audio output device 5308 (or, as described above, a corresponding interface circuit). The audio output device 5308 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0138] The electrical device 5300 may include an audio input device 5318 (or, as described above, a corresponding interface circuit). The audio input device 5318 may include any device that generates a sound signal representation, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a MIDI (musical instrument digital interface; MIDI) output).

[0139] The electrical device 5300 may include a GPS circuit 5316. The GPS circuit 5316 is capable of communicating with a satellite-based system and can receive the position of the electrical device 5300 as is technically known.

[0140] The electrical device 5300 may include any other output device 5310 (or, as described above, a corresponding interface circuit). Examples of other output devices 5310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or further storage devices.

[0141] The electrical device 5300 may include any other input device 5320 (or, as described above, a corresponding interface circuit). Examples of other input devices 5320 may include an accelerometer, gyroscope, compass, image capture device, keyboard, cursor control device such as a mouse, stylus, touchpad, barcode reader, quick response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0142] The electrical device 5300 may have any desired form factor, such as handheld or mobile electrical devices (e.g., mobile phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, netbooks, ultrabooks, personal digital assistants (PDAs), ultramobile personal computers, etc.), desktop electrical devices, servers or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, vehicle control units, digital cameras, digital video recorders, or wearable electrical devices. In some examples, the electrical device 5300 may also be any other computing device that processes data.

[0143] The terms “contain” and “have” (and all their forms and tenses) are used here as open-ended terms. Therefore, whenever a claim uses any form of “contain” or “have” (e.g., have, contain, possess, contained, had, etc.) as a preamble to or within any kind of claim statement, it should be understood that additional elements, clauses, etc., may exist without deviating from the scope of the corresponding claim or statement. When used here, the phrase “at least” is open-ended, for example, when used as a transitional clause in the claim preamble, just as the terms “have” and “contain” are open-ended. For example, the term “and / or” when used in the form A, B, and / or C refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C. When used herein in a context describing a structure, component, item, object, and / or thing, the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in a context describing a structure, component, item, object, and / or thing, the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. When used herein in a context describing a process, instruction, action, activity, etc., or the execution thereof, the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, when used herein in a context describing the performance or execution of a process, command, action, activity, etc., the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0144] Where used herein, singular references (e.g., “a,” “an,” “first,” “second,” etc.) do not exclude plurals. Where used herein, the term “a” or “an” object refers to one or more of those objects. The terms “a” (or “an”), “one or more,” and “at least one” are used interchangeably here. Furthermore, even if listed individually, multiple means, elements, or actions may be implemented, for example, by the same entity or object. In addition, individual features may be included in different examples or claims, but these may be combined in some cases, and inclusion in different examples or claims does not mean that the combination of features is not feasible and / or advantageous.

[0145] As used herein, unless otherwise specified, the term “above” describes the relationship between the two parts to the Earth. The first part is above the second part if the second part has at least one part between the Earth and the first part. Similarly, as used herein, the first part is “below” the second part if the first part is closer to the Earth than the second part. As described above, the first part can be above or below the second part in one or more of the following conditions: there is another part between them, there is no other part between them, the first and second parts are in contact, or the first and second parts are not in direct contact with each other.

[0146] Notwithstanding the foregoing, when referring to semiconductor devices under construction or production (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies, “on” is not relative to the earth, but rather to the substrate on which the components in question are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, unless otherwise noted or indicated by the context, a first component in a semiconductor die (e.g., a transistor or other semiconductor device) is “on” a second component in a semiconductor die when, during manufacturing / production, the first component is further from the substrate (e.g., a semiconductor wafer) on which the two components are fabricated or otherwise provided than the second component. Similarly, unless otherwise noted or indicated by the context, a first component in an IC package (e.g., a semiconductor die) is “on” a second component in an IC package when, during manufacturing / production, the first component is further from the printed circuit board (PCB) on which the IC package is mounted or attached. It should be understood that semiconductor devices are often used in a orientation different from the orientation in which they were manufactured. Therefore, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies in use, the definition of “above” in the previous paragraph (i.e., that the term “above” describes the relationship between two parts relative to the earth) may be governed by the context of use.

[0147] When used in this patent, any statement that any part (e.g., a layer, film, area, region, or plate) is in any way on another part (e.g., positioned on, located on, placed on, or formed on) indicates either that the part in question is in contact with the other part, or that the part in question is above the other part and one or more intermediate parts are located between them.

[0148] When used herein, references to connections (e.g., attached, joined, connected, and joined) may include intermediate members between the elements referred to by the reference to connections and / or relative movement between those elements, unless otherwise specified. Thus, a reference to a connection does not necessarily mean that two elements are directly connected and / or are in a fixed relationship with one another. When used herein, the statement that any part is "in contact" with another part is defined to mean that there is no intermediate part between those two parts.

[0149] Unless otherwise specified, descriptors such as “first,” “second,” and “third” are used here without any implication or indication of any meaning of priority, physical order, placement in a list, and / or ordering, but merely as labels and / or arbitrary names to distinguish elements for the sake of clarity in the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, but the same element may be referred to in the claims using different descriptors such as “second” or “third.”

[0150] When used herein, “approximately” and “about” modify the subject / value to acknowledge the potential existence of variations that may occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may not be precise due to manufacturing tolerances and / or other real-world imperfections, as understood by those skilled in the art. For example, “approximately” and “about” may indicate that such dimensions may be within a tolerance of + / - 10%, unless otherwise specified herein.

[0151] When used here, "virtually real-time" refers to an event occurring in a nearly instantaneous manner, acknowledging that real-world delays such as computation time and transmission may exist. Therefore, unless otherwise specified, "virtually real-time" means real-time plus 1 second.

[0152] As used herein, the phrase “communicate,” including its variations, encompasses direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but rather further includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-off events.

[0153] As used herein, “programmable circuit” is defined to include (i) one or more dedicated electrical circuits (e.g., application-specific circuits (ASICs)) configured to perform a specific (one or more) operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmable with instructions to perform a specific (one or more) function and / or (one or more) operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include, for example, a programmable microprocessor such as a central processor unit (CPU) capable of executing a first instruction to perform one or more operations and / or functions; a field-programmable gate array (FPGA) that can be programmed with a second instruction to produce an FPGA configuration and / or structuring to instantiate one or more operations and / or functions corresponding to a first instruction; a graphics processor unit (GPU) capable of executing a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), XPU, network processing unit (NPU) capable of executing a first instruction to perform one or more operations and / or functions; one or more microcontrollers capable of executing a first instruction to perform one or more operations and / or functions; and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, and / or any combination thereof) and orchestration techniques (e.g., one or more application programming interfaces (APIs)) that allow one or more computing tasks to be assigned to one or more of the multiple types of programmable circuits that are suitable and available for performing said computing tasks.

[0154] As used herein, an integrated circuit (circuit / circuitry) is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, and diodes. For example, an integrated circuit can be implemented as one or more of the following: an ASIC, FPGA, chip, microchip, programmable circuit, semiconductor substrate combining multiple circuit elements, or a system-on-a-chip (SoC).

[0155] From the above, it can be understood that the examples of systems, apparatus, and manufactured articles include glass cores having multiple different types of cavities, holes, and / or openings, which may vary considerably in size. Furthermore, examples of methods are disclosed that enable the manufacture of such glass cores having multiple different types and / or sizes of cavities, holes, and / or openings during a single LIDE process, thereby avoiding the problems that arise from performing the LIDE process multiple times at different times to manufacture different types of cavities, holes, and / or openings. More specifically, in some examples, different types of openings include through-holes for TGV and larger cavities containing embedded electronic components (e.g., CMIL, capacitors, semiconductor devices, etc.). The examples disclosed herein also ensure that mechanisms and / or structures provided within different types of openings can be manufactured without interfering with each other for improved reliability and better yield loss.

[0156] Further examples and combinations thereof include the following:

[0157] Example 1 includes a glass core having a first opening and a second opening spaced apart from the first opening, wherein the second opening has a wider width than the first opening; a conductive material adjacent to the first wall of the first opening; and a dielectric material adjacent to the second wall of the second opening.

[0158] Example 2 includes the apparatus of Example 1, wherein an electronic component is included in the second opening, and the dielectric material is located between the electronic component and the second wall of the second opening.

[0159] Example 3 includes the apparatus of Example 2, wherein the electronic component includes a magnetic material along the inner surface of a circular hole in the dielectric material.

[0160] Example 4 includes the apparatus of Example 3, wherein the conductive material is a first conductive material, the electronic component includes a second conductive material in the circular hole, and the magnetic material separates the second conductive material from the dielectric material.

[0161] Example 5 includes the apparatus of Example 4, wherein the electronic component includes a non-magnetic plug, and the second conductive material separates the non-magnetic plug from the magnetic material.

[0162] Example 6 includes any one of the devices in Examples 3 to 5, wherein the dielectric material is a first dielectric material, the device includes a layer of a second dielectric material extending over at least one of the first and second opposite outer surfaces of the glass core, and the magnetic material extends through the layer of the second dielectric material.

[0163] Example 7 includes an apparatus according to any one of Examples 1 to 6, wherein the open space separates at least a portion of the first wall from at least a portion of the conductive material.

[0164] Example 8 includes the apparatus of Example 7, wherein the open space extends circumferentially around at least half of the conductive material.

[0165] Example 9 includes the apparatus of either Example 7 or 8, wherein the open space has a width and a length, the width is in a first direction radial with respect to the axis of the first opening, and the length is in a second direction parallel to the axis of the first opening, and the length of the open space is greater than the width of the open space.

[0166] Example 10 includes an apparatus from any one of Examples 1 to 9, wherein the dielectric material corresponds to a liquid dispensable material.

[0167] Example 11 includes any one of Examples 1 to 10, wherein the dielectric material is a first dielectric material, and the apparatus includes a second dielectric material different from the first dielectric material, the second dielectric material extending across the outer surface of the glass core and across the outer surface of the first dielectric material.

[0168] Example 12 includes the apparatus of Example 11, wherein the second dielectric material includes an organic laminate dielectric.

[0169] Example 13 includes an apparatus of either Example 11 or 12, comprising a third dielectric material lining the first wall of the first opening and the second wall of the second opening, wherein the third dielectric material is different from the first dielectric material and different from the second dielectric material.

[0170] Example 14 includes the apparatus of Example 13, wherein the third dielectric material separates the second dielectric material from the glass core.

[0171] Example 15 includes a glass core assembly comprising a first build-up region, a second build-up region, a glass core assembly between the first and second build-up regions, the glass core having a cavity having a first width, and a glass through-via extending through the glass core, the glass through-via having a second width, the first width being different from the second width, and the glass through-via being spaced apart from the cavity, and an electronic component in a dielectric material within the cavity.

[0172] Example 16 includes the apparatus of Example 15, wherein the glass through vias do not contain a metal seed layer.

[0173] Example 17 includes an apparatus, either one of Example 15 or 16, wherein the side wall opposite the cavity is non-parallel.

[0174] Example 18 includes any one of Examples 15 to 17, wherein the electronic component includes a coaxial magnetic inductor loop having a conductive material inside a magnetic housing, and the device includes a first contact pad electrically coupled to the glass through via, and a second contact pad electrically coupled to the conductive material of the coaxial magnetic inductor loop and in contact with the magnetic housing.

[0175] Example 19 includes a semiconductor chip, a package substrate having a glass layer having a first surface and a second surface opposite to the first surface, a first opening in the glass layer and a second opening in the glass layer, wherein the first surface has a first aspect ratio and the second surface has a second aspect ratio, the second aspect ratio being greater than the first aspect ratio, a metal substantially filling the first opening, and a coaxial magnetic inductor loop extending through a dielectric material inside the second opening.

[0176] Example 20 includes the apparatus of Example 19, wherein the dielectric material is at least one of (i) in contact with the side wall of the second opening, or (ii) in contact with a dielectric liner that is in contact with the side wall of the second opening.

[0177] Example 21 includes a method comprising etching a first opening and a second opening within a glass layer, wherein the first opening is larger than the second opening, filling the first opening with a dielectric material, filling the second opening with a conductive material, creating a hole through the dielectric material, and arranging an electronic component in the hole in the dielectric material.

[0178] Example 22 includes the method of Example 21, wherein filling the second opening is performed after filling the first opening.

[0179] Example 23 includes the method of Example 22, wherein the drilling of the hole is performed after filling the second opening.

[0180] Example 24 includes a method from any one of Examples 21 to 23, wherein filling the first opening involves dispensing the dielectric material in liquid form into the first opening and curing the dielectric material.

[0181] Example 25 includes any one of the methods in Examples 21 to 24, wherein the filling of the second opening is performed by a bottom-up plating process.

[0182] Example 26 includes any one of the methods in Examples 21 to 25, wherein etching the first aperture and the second aperture is performed in a single laser-induced etching process.

[0183] Example 27 involves arranging the electronic component by depositing a magnetic material in the hole, the hole being a first hole, creating a second hole in the magnetic material, and plating a metal in the second hole. This includes any one of the methods in Examples 21 to 26, including the following:

[0184] Example 28 includes a glass core having a first through-hole and a second through-hole, wherein the first through-hole is spaced apart from and smaller than the second through-hole; a conductive material within the first through-hole; and a dielectric material within the second through-hole, wherein the dielectric material is located between an electronic component in the second through-hole and the side wall of the second through-hole.

[0185] Example 29 includes the apparatus of Example 28, wherein the electronic component includes a coaxial magnetic inductor loop.

[0186] Example 30 includes the apparatus of Example 29, wherein the coaxial magnetic inductor loop comprises a first portion and a second portion, with the dielectric material located between the first portion and the second portion.

[0187] Example 31 includes the apparatus of either Example 29 or 30, wherein the conductive material is a first conductive material, and the coaxial magnetic inductor loop includes a magnetic material and a second conductive material inside the magnetic material.

[0188] Example 32 includes the apparatus of Example 31, wherein the second conductive material extends across the space inside the magnetic material.

[0189] Example 33 includes an apparatus of either Example 31 or 32, wherein the edge of the magnetic material is substantially coplanar with the outer surface of the glass core.

[0190] Example 34 includes any one of Examples 28 to 33, wherein the gap between the inner surface of the first through-hole and the conductive material is said not to contain a solid material.

[0191] Example 35 includes the apparatus of Example 34, wherein the gap extends for most of the length of the first through-hole.

[0192] Example 36 includes any one of Examples 28 to 35, wherein the dielectric material is a first dielectric material, and the apparatus includes a second dielectric material extending over the outer surface of the glass core and over the outer surface of the first dielectric material.

[0193] Example 37 includes the apparatus of Example 36, wherein the second dielectric material is the same material as the first dielectric material in the second through-hole.

[0194] Example 38 includes the apparatus of either Example 36 or 37, wherein the second dielectric material is a different material from the first dielectric material in the second through-hole.

[0195] Example 39 includes the apparatus of Example 38, wherein the first dielectric material in the second through-hole includes a liquid-dispensable material.

[0196] Example 40 includes the apparatus of Example 39, wherein the second dielectric material includes an organic laminate dielectric.

[0197] Example 41 includes any one of Examples 36 to 40, comprising a third dielectric material covering the glass core, wherein the third dielectric material is different from and different from the first dielectric material in the second through-hole.

[0198] Example 42 includes the apparatus of Example 41, wherein the third dielectric material includes silicon.

[0199] Example 43 includes a glass core having a first hole and a second hole, wherein the second hole is larger than the first hole; a first build-up region on a first surface of the glass core; a second build-up region on a second surface of the glass core; a conductive material in the first hole that electrically couples the first build-up region and the second build-up region; and a dielectric material adjacent to the inner wall of the second hole, wherein the dielectric material defines a third hole, and an electronic component is contained within the third hole.

[0200] Example 44 includes the apparatus of Example 43, wherein the glass core includes tooling holes, and the tooling holes contain magnetic material.

[0201] Example 45 includes the apparatus of either Example 43 or 44, wherein the width of the second hole is several times greater than the width of the first hole.

[0202] Example 46 includes a device comprising a package substrate including a glass layer, a semiconductor die mounted on the package substrate, conductive vias in the glass layer, an inductor in a cavity of the glass layer, the cavity being separated from the conductive vias, and a dielectric material between the inductor and the side wall of the cavity.

[0203] Example 47 includes the apparatus of Example 46, wherein there is no metal seed layer between the glass layer and the conductive via.

[0204] Example 48 includes a method comprising performing a laser-induced etching process to simultaneously create through-holes and cavities within a glass core, the through-holes being separated from the cavities, depositing a dielectric material within the cavities, plating a metal within the through-holes, and arranging electronic components within the dielectric material.

[0205] Example 49 includes the method of Example 48, wherein the plating of the metal is performed without a pre-deposited seed layer in the through-hole.

[0206] Example 50 includes the method of Example 49, wherein the deposition of the dielectric material is performed before plating the metal, such that the dielectric material prevents the metal from entering the cavity.

[0207] Example 51 includes any one of the methods in Examples 48 to 50, wherein the dielectric material is dispensed into the cavity in liquid form and then cured.

[0208] Example 52 includes any one of Examples 48 to 51, wherein the electronic component is a coaxial magnetic loop inductor.

[0209] Example 53 includes the method of Example 52, wherein arranging the electronic component involves creating an opening in the dielectric material, adding a magnetic material to the opening, removing the center of the magnetic material, and adding a conductive material to the center of the magnetic material.

[0210] Example 54 includes the method of Example 53, wherein the addition of the conductive material is achieved simultaneously with plating the metal into the through-hole.

[0211] Example 55 includes a glass layer having a first hole and a second hole, wherein the second hole is larger than an electronic component disposed therein, and the electronic component is larger than the first hole; a conductive material substantially filling the first hole; and a dielectric material substantially filling the space in the second hole surrounding the electronic component.

[0212] Example 56 includes the apparatus of Example 55, wherein the electronic component includes a magnetic material in contact with the dielectric material.

[0213] Example 57 includes the apparatus of Example 56, wherein the conductive material is a first conductive material, a first portion of the magnetic material surrounds a first portion of the second conductive material, and a second portion of the magnetic material surrounds a second portion of the second conductive material.

[0214] Example 58 includes the apparatus of Example 57, wherein the second portion of the magnetic material is a continuous extension of the first portion of the magnetic material.

[0215] Example 59 includes any one of the devices in Examples 56 to 58, wherein the outer surface of the magnetic material is substantially coplanar with the outer surface of the glass layer.

[0216] Example 60 includes the apparatus of Example 59, which includes a dielectric layer extending over the outer surface of the magnetic material and over the outer surface of the glass layer.

[0217] Example 61 includes the apparatus of Example 60, wherein the dielectric layer comprises a material different from the dielectric material.

[0218] Example 62 includes the apparatus of Example 61, wherein the dielectric material corresponds to a liquid-dispensable material and the dielectric layer corresponds to an organic laminate dielectric.

[0219] Example 63 includes any one of the devices of Examples 55 to 62, wherein the void is located between the first hole and the opposing surfaces of the conductive material within the first hole.

[0220] Example 64 includes the apparatus of Example 63, wherein the conductive material is a first conductive material, the void is a first void, and the electronic component includes a magnetic material surrounding a second conductive material, with the second void located between opposing surfaces of the magnetic material and the second conductive material.

[0221] Example 65 includes an apparatus of either Example 63 or 64, comprising a thin film dielectric on the glass layer in the first pore, wherein the void is between the thin film dielectric and the conductive material.

[0222] Example 66 includes the apparatus of Example 65, wherein the thin film dielectric is located on the glass layer within the second pore, and the thin film dielectric is located between the dielectric material and the sidewall of the second pore within the glass layer.

[0223] Example 67 includes the apparatus of Example 66, wherein the thin film dielectric is in contact with the glass layer and also in contact with the dielectric material.

[0224] Example 68 includes a glass layer having an opening extending from a first surface of the glass layer to a second surface of the glass layer opposite to the first surface; a first redistribution layer adjacent to the first surface of the glass layer; a second redistribution layer adjacent to the second surface of the glass layer; a metal via extending through the glass layer, spaced apart from the opening; and a dielectric material extending through the glass layer along the wall of the opening.

[0225] Example 69 includes the apparatus of Example 68, wherein the dielectric material contains a coaxial magnetic loop inductor.

[0226] Example 70 includes the apparatus of Example 69, wherein the coaxial magnetic loop inductor includes a coupled coaxial magnetic loop inductor.

[0227] Example 71 includes the device of either Example 69 or 70, wherein the coaxial magnetic loop inductor includes a conductive core surrounded by a magnetic material, and the device includes a dielectric layer extending across the first surface of the glass layer and substantially parallel surfaces of the magnetic material, and a contact pad electrically coupled to the conductive core, the dielectric layer being between the magnetic material and the contact pad.

[0228] Example 72 includes a semiconductor chip and a substrate on which the semiconductor chip is mounted, the substrate including a glass core having a cavity and a through-hole adjacent to the cavity, wherein the cavity is larger than the through-hole; a conductive material in the through-hole; a dielectric material in the cavity, the dielectric material including an opening extending through the dielectric material; and a magnetic material in the opening.

[0229] Example 73 includes the apparatus of Example 72, wherein the magnetic material has a cylindrical shape and is filled with metal.

[0230] Example 74 includes the apparatus of either Example 72 or 73, wherein a portion of the outer surface of the conductive material within the through-hole is separated from the side wall of the through-hole by a void.

[0231] Example 75 includes a method comprising: providing a through-hole to a glass core; providing a cavity to the glass core, wherein both the through-hole and the cavity are provided to the glass core in the same process, the cavity being of a different size from the through-hole; depositing a dielectric material in the cavity; depositing a metal in the through-hole; providing an opening in the dielectric material after the metal has been deposited in the through-hole; and adding an electronic component in the opening.

[0232] Example 76 includes the method of Example 75, wherein the deposition of the dielectric material in the cavity is performed before the deposition of the metal in the through-hole.

[0233] Example 77 includes a method of depositing the dielectric material, which includes dispensing the dielectric material in liquid form, as in either Example 75 or 76.

[0234] Example 78 includes any one of Examples 75 to 77, wherein the deposition of the metal is carried out by a bottom-up plating process without a seed layer.

[0235] Example 79 includes any one of the methods in Examples 75 to 78, wherein the electronic component is an inductor.

[0236] Example 80 includes the method of Example 79, wherein adding the electronic component involves depositing a magnetic material in the opening, drilling holes through the magnetic material, and depositing a conductive material in the holes in the magnetic material.

[0237] Example 81 includes a glass layer having an opening between a first and second surface opposite to the glass layer, an electronic component in the opening, a dielectric material between the electronic component and the side wall of the opening, and a glass through-via containing a conductive material extending through the glass layer.

[0238] Example 82 includes the apparatus of Example 81, wherein the dielectric material substantially surrounds the electronic component.

[0239] Example 83 includes a device, either one of Example 81 or 82, wherein the electronic component includes a capacitor.

[0240] Example 84 includes the apparatus of Example 83, wherein the capacitor includes a deep trench capacitor.

[0241] Example 85 includes any one of the devices in Examples 81 to 84, wherein the electronic component includes a contact pad, the contact pad being substantially coplanar with the first surface of the glass layer.

[0242] Example 86 includes any one of Examples 81 to 85, wherein the electronic component has a first thickness and the glass layer has a second thickness, the second thickness being greater than the first thickness.

[0243] Example 87 includes an apparatus from any one of Examples 81 to 86, comprising a first dielectric layer extending across the first surface of the glass layer and across the first end of the opening, and a second dielectric layer extending across the second surface of the glass layer and across the second end of the opening.

[0244] Example 88 includes the apparatus of Example 87, wherein the dielectric material includes a material different from the first dielectric layer and a material different from the second dielectric layer.

[0245] Example 89 includes a thin film covering the first and second surfaces of the glass layer, the thin film being located between the glass layer and the first dielectric layer and between the glass layer and the second dielectric layer, the apparatus of either Example 87 or 88.

[0246] Example 90 includes the apparatus of Example 89, wherein the thin film separates the dielectric material within the aperture from the glass layer.

[0247] Example 91 includes any one of the apparatuses from Examples 81 to 90, wherein the dielectric material includes a cured liquid-dispensable material.

[0248] Example 92 includes any one of the devices in Examples 81 to 91, wherein the glass through via does not include a seed layer along the length of the glass through via.

[0249] Example 93 includes a first build-up region, a second build-up region, and a glass core between the first build-up region and the second build-up region. The glass core has a first opening and a second opening that extend through the glass core. The first opening is smaller than the second opening and is spaced apart from the second opening. The device includes the glass core, a metal material along a first wall of the first opening, and a dielectric material along a second wall of the second opening.

[0250] Example 94 includes the device of Example 93, wherein an outer surface of the metal material is spaced apart from the first wall of the first opening.

[0251] Example 95 includes the device of either Example 93 or 94, wherein at least one-quarter of an open space extends around a cross-sectional outer periphery of the metal material within the first opening.

[0252] Example 96 includes the device of any one of Examples 93 to 95, wherein an open space extends for at least 10% of a length of the first opening.

[0253] Example 97 includes the device of any one of Examples 93 to 96, wherein an electronic component is included in the dielectric material inside the second opening.

[0254] Example 98 includes the device of Example 97, wherein the electronic component includes a deep trench capacitor.

[0255] Example 99 includes a package substrate including a glass core having a first opening and a second opening larger than the first opening, a conductive material within the first opening, a dielectric material within the second opening, a capacitor within the dielectric material inside the second opening, and a semiconductor chip attached to the package substrate.

[0256] Example 100 includes the device of Example 99, wherein the conductive material within the first opening is separated from a side wall of the first opening by a gap having no solid material.

[0257] Example 101 includes a method having: providing a first opening in a glass core, the first opening extending through the glass core, the first opening having a first width; providing a second opening in the glass core, the second opening extending through the glass core, the second opening having a second width, the second width being different from the first width; disposing an electronic component in the first opening; depositing a dielectric material in the first opening around the electronic component; and depositing a metal in the second opening.

[0258] Example 102 includes the method of Example 101, wherein the first opening and the second opening are provided in the glass core during the same process.

[0259] Example 103 includes the method of either Example 101 or 102, wherein depositing the dielectric material is performed by dispensing the dielectric material in liquid form and then curing the dielectric material.

[0260] Example 104 includes the method of any one of Examples 101 to 103, wherein depositing the metal is performed by a bottom-up plating process without using a seed layer.

[0261] Example 105 includes the method of any one of Examples 101 to 104, wherein the electronic component includes a deep trench capacitor.

[0262] The following claims are incorporated by reference into this detailed description. Although specific examples of systems, devices, articles of manufacture, and methods are disclosed herein, the scope of this patent is not limited thereto. Rather, this patent extends to all systems, devices, articles of manufacture, and methods that fairly fall within the scope of the claims of this patent.

Claims

1. A glass core having a first opening and a second opening spaced apart from the first opening, wherein the second opening has a wider width than the first opening, A conductive material adjacent to the first wall of the first opening, A dielectric material adjacent to the second wall of the second opening, A device having.

2. The apparatus according to claim 1, wherein an electronic component is included in the second opening, and the dielectric material is located between the electronic component and the second wall of the second opening.

3. The apparatus according to claim 2, wherein the electronic component includes a magnetic material along the inner surface of a circular hole in the dielectric material.

4. The apparatus according to claim 3, wherein the conductive material is a first conductive material, the electronic component includes a second conductive material in the circular hole, and the magnetic material separates the second conductive material from the dielectric material.

5. The apparatus according to claim 4, wherein the electronic component includes a non-magnetic plug, and the second conductive material separates the non-magnetic plug from the magnetic material.

6. The apparatus according to any one of claims 3 to 5, wherein the dielectric material is a first dielectric material, the apparatus includes a layer of a second dielectric material extending over at least one of the first and second opposite outer surfaces of the glass core, and the magnetic material extends through the layer of the second dielectric material.

7. The apparatus according to any one of claims 1 to 5, wherein the open space separates at least a portion of the first wall from at least a portion of the conductive material.

8. The apparatus according to claim 7, wherein the open space extends circumferentially for at least half of the distance around the conductive material.

9. The apparatus according to claim 7, wherein the open space has a width and a length, the width is in a first direction radial with respect to the axis of the first opening, and the length is in a second direction parallel to the axis of the first opening, and the length of the open space is greater than the width of the open space.

10. The apparatus according to any one of claims 1 to 5, wherein the dielectric material corresponds to a liquid dispensable material.

11. The apparatus according to any one of claims 1 to 5, wherein the dielectric material is a first dielectric material, and the apparatus includes a second dielectric material different from the first dielectric material, the second dielectric material extending over the outer surface of the glass core and over the outer surface of the first dielectric material.

12. The apparatus according to claim 11, wherein the second dielectric material includes an organic laminate dielectric.

13. The apparatus according to claim 11, comprising a third dielectric material for lining the first wall of the first opening and the second wall of the second opening, wherein the third dielectric material is different from the first dielectric material and different from the second dielectric material.

14. The apparatus according to claim 13, wherein the third dielectric material separates the second dielectric material from the glass core.

15. The first build-up area and The second build-up area, This is a glass core assembly between the first build-up region and the second build-up region. A glass core having a cavity having a first width, and A glass through-via extending through the glass core, the glass through-via having a second width, the first width being different from the second width, and the glass through-via being separated from the cavity, A glass core assembly including, The electronic component in the dielectric material within the cavity, A device having.

16. The apparatus according to claim 15, wherein the glass through via does not contain a metal seed layer.

17. The apparatus according to claim 15, wherein the side wall opposite to the cavity is non-parallel.

18. The aforementioned electronic component includes a coaxial magnetic inductor loop having a conductive material inside a magnetic casing, and the device is A first contact pad electrically coupled to the glass through via, A second contact pad electrically coupled to the conductive material of the coaxial magnetic inductor loop, the second contact pad in contact with the magnetic housing, The apparatus according to any one of claims 15 to 17, including the apparatus described in any one of claims 15 to 17.

19. Semiconductor chips and A package substrate comprising a glass layer having a first surface and a second surface opposite to the first surface, a first opening within the glass layer, and a second opening within the glass layer, wherein the first surface has a first aspect ratio, the second surface has a second aspect ratio, and the second aspect ratio is greater than the first aspect ratio, The metal that substantially fills the first opening, A coaxial magnetic inductor loop extending through the dielectric material inside the second opening, A device having.

20. The apparatus according to claim 19, wherein the dielectric material is at least one of the following: (i) in contact with the side wall of the second opening, or (ii) in contact with a dielectric liner in contact with the side wall of the second opening.

21. A first opening and a second opening are etched into the glass layer, with the first opening being larger than the second opening. The first opening is filled with a dielectric material, The second opening is filled with a conductive material, A hole is made through the dielectric material, An electronic component is placed in the hole of the dielectric material. A method having the following characteristics.

22. The method according to claim 21, wherein filling the second opening is performed after filling the first opening.

23. The method according to claim 22, wherein the drilling of the hole is performed after filling the second opening.

24. Filling the first opening is The dielectric material is dispensed in liquid form into the first opening. The dielectric material is cured. The method according to any one of claims 21 to 23, including the act of

25. The method according to any one of claims 21 to 23, wherein the filling of the second opening is performed by a bottom-up plating process.

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