Wiring board

Abstract

Providing high-quality wiring boards. [Solution] The wiring board of the embodiment consists of a multilayer core substrate and a build-up layer. The multilayer core substrate is formed of a central insulating layer, a first-side insulating layer and a second-side insulating layer, and has through holes, an inner conductor layer and a surface conductor layer. The first surface insulating layer is formed by at least two insulating layers on the first surface side of the central insulating layer, the second surface insulating layer is formed by at least two insulating layers on the second surface side of the central insulating layer, the inner conductor layer consists of first and second inner conductor layers, with the first inner conductor layer formed on the first surface of the central insulating layer and the second inner conductor layer formed on the second surface, the surface conductor layer consists of first and second surface conductor layers, with the first surface conductor layer formed as the outermost layer of the first surface insulating layer and the second surface conductor layer formed as the outermost layer of the second surface insulating layer, through holes are formed between the first surface conductor layer and the second surface conductor layer and are also connected to the first and second inner conductor layers, and components are arranged within the first surface insulating layer.

Description

Technical Field

[0001] The technology disclosed by this specification relates to a wiring board.

Background Art

[0002] Patent Document 1 discloses a wiring board in which through holes are formed, and build-up wiring layers are formed on both sides of a multilayer core substrate. The multilayer core substrate consists of a resin substrate and an adhesive resin layer, and has a multilayer insulation layer structure (a total of 7 layers) composed of a first resin substrate, a second resin substrate laminated on the first resin substrate via an adhesive resin layer, and a third resin substrate laminated on the second resin substrate via an adhesive resin layer. Conductor circuits composed of conductor layers are formed on both sides of each resin substrate. The through holes are connected to the conductor circuits formed on both sides of each resin substrate and are composed of a total of 6 layers of conductor layers.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] [Problems of Patent Document 1] With the requirements of higher signal speed and larger capacity, the problem of transmission delay of signal lines in through holes has occurred. In the wiring board of Patent Document 1, it is considered that signal delay is caused by the number of layers of conductor circuits connected to the through holes in the multilayer core substrate. Therefore, due to the signal delay, it is considered that the parasitic capacitance of the through holes increases.

Means for Solving the Problems

[0005] The wiring board of the present invention comprises a multilayer core substrate and a build-up layer. The multilayer core substrate is formed of a central insulating layer, a first-side insulating layer, and a second-side insulating layer, and has through holes, an inner conductor layer, and a surface conductor layer. The first-side insulating layer is formed on the first-side of the central insulating layer by at least two insulating layers. The second-side insulating layer is formed on the second-side of the central insulating layer by at least two insulating layers. The inner conductor layer consists of a first inner conductor layer and a second inner conductor layer, the first inner conductor layer is formed on the first surface of the central insulating layer, and the second inner conductor layer is formed on the second surface of the central insulating layer. The surface conductor layer consists of a first surface conductor layer and a second surface conductor layer, the first surface conductor layer is formed on the outermost layer of the first-side insulating layer, and the second surface conductor layer is formed on the outermost layer of the second-side insulating layer. The through-hole is formed between the first surface conductor layer and the second surface conductor layer, and is also connected to the first inner conductor layer and the second inner conductor layer. Components are arranged within the first surface-side insulating layer. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view showing the wiring board of the embodiment. [Figure 2] Enlarged view of part II in Figure 1. [Figure 3A] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3B] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3C] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3D] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3E] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3F] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3G] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3H] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Modes for carrying out the invention]

[0007] [Embodiment] Figure 1 is a cross-sectional view showing a wiring board 1 of an embodiment. As shown in Figure 1, the wiring board 1 has a multilayer core substrate 100, a first build-up layer 110, and a second build-up layer 120. The first build-up layer 110 is formed on the first surface 100F of the multilayer core substrate 100. The second build-up layer 120 is formed on the second surface 100S of the multilayer core substrate 100.

[0008] The multilayer core substrate 100 is formed of a central insulating layer 10, a first-side insulating layer 20, and a second-side insulating layer 30, and has through-holes 80, an inner conductor layer, a surface conductor layer, and a connecting conductor 46. Components 60 are arranged inside the multilayer core substrate 100. The first-side insulating layer 20 is formed on the first surface 10F of the central insulating layer 10. The second-side insulating layer 30 is formed on the second surface 10S of the central insulating layer 10. The central insulating layer 10 is sandwiched between the first-side insulating layer 20 and the second-side insulating layer 30. The inner conductor layers are a first inner conductor layer 12 and a second inner conductor layer 14, and the surface conductor layers are a first surface conductor layer 42 and a second surface conductor layer 52.

[0009] The first surface-side insulating layer 20 is formed by the first resin substrate 40, the first insulating layer 22, and the third insulating layer 24. The first insulating layer 22 is formed on the first surface 10F of the central insulating layer 10. The first resin substrate 40 is formed on the surface of the first insulating layer 22 opposite to the central insulating layer 10. The third insulating layer 24 is formed on the surface of the first resin substrate 40 opposite to the first insulating layer 22. The second surface-side insulating layer 30 is formed by the second resin substrate 50, the second insulating layer 32, and the fourth insulating layer 34. The second insulating layer 32 is formed on the second surface 10S of the central insulating layer 10. The second resin substrate 50 is formed on the surface of the second insulating layer 32 opposite to the central insulating layer 10. The fourth insulating layer 34 is formed on the surface of the second resin substrate 50 opposite to the second insulating layer 32. Note that the first surface-side insulating layer 20 and the second surface-side insulating layer 30 are formed by at least two insulating layers. The first-side insulating layer 20 and the second-side insulating layer 30 may be formed of three or four insulating layers.

[0010] In the description of the wiring board 1 of this embodiment, the side of the wiring board 1 furthest from the central insulating layer 10 in the thickness direction is referred to as the "upper side," "upper," or simply "up," while the side closer to the central insulating layer 10 is referred to as the "lower side," "downward," or simply "down." Furthermore, in each conductor layer and each insulating layer, the surface facing away from the central insulating layer 10 is also referred to as the "upper surface," and the surface facing the central insulating layer 10 is also referred to as the "lower surface." Therefore, for example, in the description of the first build-up layer 110 and the second build-up layer 120, the side furthest from the multilayer core substrate 100 is referred to as the "upper side," "upper," or simply "up," while the side closer to the multilayer core substrate 100 is referred to as the "lower side," "downward," or simply "down." Also, in the description of the wiring board 1 of this embodiment, each conductor layer and each insulating layer may be referred to as the "first surface" and the "second surface." In this case, the first surface is referred to as the top surface for convenience, but it could be either the top or bottom surface.

[0011] The first inner conductor layer 12 is formed on the first surface 10F of the central insulating layer 10. The first inner conductor layer 12 is covered by the first insulating layer 22. The first inner conductor layer 12 may be a single-layer conductor layer or a multilayer conductor layer of two or more layers. The first inner conductor layer 12 has a portion connected to the through-hole 80 and a portion that is not directly connected to the through-hole 80. The portion of the first inner conductor layer 12 connected to the through-hole 80 is called the first inner through-hole connection portion 13a. The portion of the first inner conductor layer 12 that is not directly connected to the through-hole 80 is called the first inner through-hole non-connection portion 13b.

[0012] The second inner conductor layer 14 is formed on the second surface 10S of the central insulating layer 10. The second inner conductor layer 14 is covered by the second insulating layer 32. The second inner conductor layer 14 may be a single-layer conductor layer or a multilayer conductor layer of two or more layers. The second inner conductor layer 14 has a portion connected to the through-hole 80 and a portion that is not directly connected to the through-hole 80. The portion of the second inner conductor layer 14 connected to the through-hole 80 is called the second inner through-hole connection portion 15a. The portion of the second inner conductor layer 14 that is not directly connected to the through-hole 80 is called the second inner through-hole non-connection portion 15b.

[0013] The first surface conductor layer 42 is formed on the outermost layer of the first surface insulating layer 20. Specifically, the first surface conductor layer 42 is formed on the third insulating layer 24, which is the outermost layer of the first surface insulating layer 20. The first surface conductor layer 42 is made up of at least two or more conductor layers. The first surface conductor layer 42 may be made up of three or four conductor layers. The first surface conductor layer 42 has a portion that is connected to the through-hole 80 and a portion that is not directly connected to the through-hole 80. The portion of the first surface conductor layer 42 that is connected to the through-hole 80 is called the first surface through-hole connection portion, and the first cover conductor 43 is formed in the first surface through-hole connection portion. The portion of the first surface conductor layer 42 that is not directly connected to the through-hole 80 is called the first surface through-hole non-connection portion 44.

[0014] The second surface conductor layer 52 is formed on the outermost layer of the second surface side insulating layer 30. Specifically, the second surface conductor layer 52 is formed on the fourth insulating layer 34 which is the outermost layer of the second surface side insulating layer 30. The second surface conductor layer 52 is formed of at least two or more conductor layers. The first surface conductor layer 42 may be formed of three or four conductor layers. There are a portion of the second surface conductor layer 52 that is connected to the through hole 80 and a portion that is not directly connected to the through hole 80. Here, the portion of the second surface conductor layer 52 that is connected to the through hole 80 is defined as the second surface through hole connection portion, and the second lid conductor 53 is formed on the second surface through hole connection portion. The portion of the second surface conductor layer 52 that is not directly connected to the through hole 80 is defined as the second surface through hole non-connection portion 54.

[0015] The through hole 80 is formed between the first surface conductor layer 42 and the second surface conductor layer 52. The through hole 80 is connected to the first surface conductor layer 42 and the second surface conductor layer 52, and is also connected to the first inner layer conductor layer 12 and the second inner layer conductor layer 14. That is, the through hole 80 is connected to four conductor layers.

[0016] The through hole 80 is composed of an inner wall conductor layer 81 and a filler 82. The inner wall conductor layer 81 is a conductor layer formed on the inner wall of the through hole 80a. The inner wall conductor layer 81 may be a single-layer conductor layer or a conductor layer of two or more layers. Surface treatment such as roughening treatment may be performed on the surface layer of the inner wall conductor layer 81. The filler 82 is formed in the through hole 80a. The through hole 80a of the through hole 80 penetrates the central insulating layer 10, the first surface side insulating layer 20, and the second surface side insulating layer 30.

[0017] On the outermost layer on the side of the first surface side insulating layer 20 of the through hole 80, an inner wall conductor layer 81 and a first lid conductor 43 which is a first surface layer through hole connection portion of the first surface layer conductor layer 43 are formed. The first lid conductor 43 covers the end face of the filler 82. The first lid conductor 43 is a part of the first surface layer conductor layer 43. Note that the first surface layer through hole connection portion may be in an exposed form without covering the end face of the filler 82. On the outermost layer on the side of the second surface side insulating layer 30 of the through hole 80, an inner wall conductor layer 81 and a second lid conductor 53 which is a second surface layer through hole connection portion of the second surface layer conductor layer 53 are formed. The second lid conductor 53 covers the end face of the filler 82. Note that the second lid conductor 53 is a part of the second surface layer conductor layer 53. Note that the second surface layer through hole connection portion may be in an exposed form without covering the end face of the filler 82.

[0018] The through hole 80 is connected to the first inner layer conductor layer 12 and the second inner layer conductor layer 14. In a first inner layer through hole connection portion 13a where the through hole 80 is connected to the first inner layer conductor layer 12, an opening for forming the through hole 80 is provided. In a second inner layer through hole connection portion 15a where the through hole 80 is connected to the second inner layer conductor layer 14, an opening for forming the through hole 80 is provided.

[0019] The thickness T1 of the inner layer conductor layer and the thickness T2 of the surface layer conductor layer are not particularly limited, but it is desirable that the thickness T1 of the inner layer conductor layer and the thickness T2 of the surface layer conductor layer satisfy the relationship of Equation 1. T1 < T2 ···· Equation 1 When the thickness T1 of the inner layer conductor layer and the thickness T2 of the surface layer conductor layer are in the relationship of Equation 1, the formation of the through hole 80 is stabilized. When the multilayer core substrate 100 is formed, the warpage of the substrate is reduced, and the formation of the build-up layers 110 and 120 is also stabilized. Therefore, it is considered that the warpage is suppressed and the connection of the conductor layers is also stabilized when the wiring substrate is formed. ​​​​S1 < S2 ··· Formula 2 When the number of layers S1 of the inner conductor layer and the number of layers S2 of the surface conductor layer are in the relationship of Formula 2, the formation of the through hole 80 becomes stable. When the multilayer core substrate 100 is formed, the warp of the substrate is reduced, and the formation of the build-up layers 110 and 120 also becomes stable. Therefore, it is considered that the warp is suppressed and the connection of the conductor layers is also stable when it is made into a wiring substrate.

[0021] Also, it is more desirable that the thickness T1 of the inner conductor layer and the thickness T2 of the surface conductor layer satisfy the relationship of Formula 1, and the number of layers S1 of the inner conductor layer and the number of layers S2 of the surface conductor layer satisfy the relationship of Formula 2. By satisfying the two relational expressions, the formation of the through hole 80 becomes stable. When the multilayer core substrate 100 is formed, the warp of the substrate is reduced, and the formation of the build-up layers 110 and 120 also becomes stable. Therefore, it is considered that the warp is suppressed and the connection of the conductor layers is also stable when it is made into a wiring substrate. It is considered that defects such as insulation are less likely to occur early even when a reliability test is performed.

[0022] Component 60 is located within the first surface-side insulating layer 20. The first resin substrate 40 has an opening 45 that penetrates through it. Component 60 is housed within the opening 45. Component 60 is an electronic component. Specifically, electronic components include capacitors, inductors, IVRs, semiconductors, etc. Component 60 has an electrode surface 61 and a non-electrode surface 62 opposite to the electrode surface 61. The non-electrode surface 62 of component 60 faces the first insulating layer 22. The electrode surface 61 of component 60 faces the third insulating layer 24. The third insulating layer 24 has a connecting conductor 46 that penetrates the insulating layer, and the connecting conductor 46 is connected to the first surface through-hole non-connected portion 44, which is a portion of the first surface conductor layer 42 that is not directly connected. The electrode surface 61 is connected to the connecting conductor 46. As a result, the electrode surface 61 of component 60 is connected to the first surface layer through-hole non-connected portion 44 via the connecting conductor 46. Thus, component 60 and the first surface layer conductor layer 42 are connected. The gap between the inner surface of the opening 45 and component 60 is filled with embedding resin 63. The embedding resin 63 is, for example, a thermosetting resin. The embedding resin 63 may also be a photocurable resin. The embedding resin 63 is provided separately from the first insulating layer 22, the first resin substrate 40, and the third insulating layer 24. Multiple components 60 may be housed in the opening 45, and identical components may be placed there, or different components may be placed there.

[0023] A first build-up layer 110 and a second build-up layer 120 are formed on the multilayer core substrate 100. The first build-up layer 110 is formed on the first surface 100F of the multilayer core substrate 100 and consists of at least one build-up layer comprising an insulating layer 111, a conductive layer 112, and a via conductor 113. The second build-up layer 120 is formed on the second surface 100S of the multilayer core substrate 100 and consists of at least one build-up layer comprising an insulating layer 121, a conductive layer 122, and a via conductor 123.

[0024] In the example shown in Figure 1, the first build-up layer 110 is composed of two insulating layers 111 and two conductive layers 112, and the second build-up layer 120 is composed of two insulating layers 121 and two conductive layers 122. Each insulating layer 111 contains via conductors 113 that connect the conductive layer on the insulating layer 111 to the conductive layer below it. Each insulating layer 121 contains via conductors 123 that connect the conductive layer on the insulating layer 121 to the conductive layer below it. It is also possible to form a configuration in which the build-up layer is formed on only one side of the multilayer core substrate. In that case, only the first build-up layer 110 or the second build-up layer 120 is formed on the multilayer core substrate.

[0025] In the illustrated example, both the first build-up layer 110 and the second build-up layer 120 include two conductive layers and two insulating layers, but they may also include three or more conductive layers and three or more insulating layers, or each of the conductive layers and insulating layers may consist of only one layer.

[0026] A connection pad 112a is formed on the surface-side conductor layer 112 of the first build-up layer 110 located in the outermost layer of the wiring board 1, and a connection pad 122a is formed on the surface-side conductor layer 122 of the second build-up layer 120 located in the outermost layer of the wiring board 1. External electronic components, such as a motherboard (not shown), are mounted on the connection pad 112a. When electronic components are mounted, bumps (not shown) made of solder, copper, tin, or any other metal are formed on the connection pad 112a and the connection pad 122a.

[0027] In the wiring board 1, the first inner conductor layer 12, the second inner conductor layer 14, the first surface conductor layer 42, the second surface conductor layer 52, the conductor layer 112 within the first build-up layer 110, and the conductor layer 122 within the second build-up layer 120 are formed with arbitrary conductor patterns. Although each of these conductor layers is shown as having a simple single-layer structure for ease of viewing, they may have a multilayer structure of two or more layers, as will be described later with reference to Figure 2.

[0028] The insulating layer and resin substrate constituting the multilayer core substrate 100 of the present invention are not particularly limited, but it is desirable to use a core material that is impregnated with an insulating resin and cured. As the insulating resin, epoxy resin, bismaleimidotriazine resin (BT resin), or phenolic resin can be used. As the reinforcing material, glass fiber, aramid fiber, glass nonwoven fabric, aramid nonwoven fabric, etc. By including a core material in the insulating layer and resin substrate, a wiring board 1 is provided that has high rigidity and suppresses the occurrence of warping. On the other hand, it is preferable that the insulating layer 111 and insulating layer 121 used as build-up layers be formed from an insulating resin that does not contain a core material. This is because an insulating resin that does not contain a core material is suitable for via formation. Each insulating layer may also contain an inorganic filler such as silica.

[0029] The structure of the conductors included in the wiring board 1 will be explained in detail with reference to Figure 2. Figure 2 shows an enlarged view of part II of Figure 1.

[0030] As shown in Figure 2, the first inner conductor layer 12 is formed by a metal foil layer 12a formed on the first surface 10F of the central insulating layer 10. The second inner conductor layer 14 is formed by a metal foil layer 14a formed on the second surface 10S of the central insulating layer 10. The metal foil layer 12a of the first inner conductor layer 12 and the metal foil layer 14a of the second inner conductor layer 14 have a single-layer structure, but they may also have a multilayer structure of two or more layers. The type of metal foil used for the metal foil layers 12a and 14a is not particularly limited, but considering conductivity, it is preferable to use one whose main component is copper.

[0031] The conductive layer of the present invention is composed of a combination of a metal foil layer, a seed layer, and an electroplated layer. The metal foil layer is a conductive layer patterned starting from a metal foil formed on an insulating layer. The type of metal in the metal foil is not particularly limited, but considering conductivity, it is preferable to use one mainly composed of copper. The seed layer is a conductive layer patterned by forming a seed film such as an electroless plating film or a sputtered film on the entire surface of the substrate. The type of metal in the seed film is not particularly limited, but it is preferable to use one mainly composed of copper, nickel, or titanium. The electroplated layer is a conductive layer patterned by forming a pattern with a resist based on the seed film formed on the substrate, and depositing an electroplated film in the non-formed areas of the resist. The type of metal in the electroplated film is not particularly limited, but considering conductivity, it is preferable to use one mainly composed of copper.

[0032] The first surface conductor layer 42 is composed of a metal foil layer, a seed layer, and an electroplating layer. Specifically, the first surface conductor layer 42 is formed by a metal foil layer 42a formed on the upper surface of the third insulating layer 24, a seed layer 42b on the metal foil layer 42a, an electroplating layer 42c on the seed layer 42b, a seed layer 42d on the electroplating layer 42c, and an electroplating layer 42e on the seed layer 42d. The first surface conductor layer 42 has a five-layer structure consisting of metal foil 42a, seed layer 42b, electroplating layer 42c, seed layer 42d, and electroplating layer 42e. The first cover conductor 43 is formed by the seed layer 42d and the electroplating layer 42e. In other words, the first surface conductor layer 42 has a five-layer structure.

[0033] The connection conductor 46 penetrates the third insulating layer 24 and is formed in a hole 24a that exposes the electrode surface 61 of the component 60. The connection conductor 46 is formed by a seed layer 42b formed on the inner wall surface of the hole 24a and the electrode surface 61, and an electrolytic plating layer 42c formed on the seed layer 42b and filling the hole 24a. The seed layer 42b and the electrolytic plating layer 42c forming the connection conductor 46 are common to the seed layer 42b and the electrolytic plating layer 42c forming the first surface conductor layer 42. The first surface conductor layer 42 and the connection conductor 46 are formed simultaneously. The connection conductor 46 connects the electrode surface 61 of the component 60 and the first surface layer through-hole non-connection portion 44.

[0034] The second surface conductor layer 52 is composed of a metal foil layer, a seed layer, and an electrolytic plating layer. Specifically, the second surface conductor layer 52 includes a metal foil layer 52a formed on the upper surface of the fourth insulating layer 34, a seed layer 52b on the metal foil layer 52a, an electrolytic plating layer 52c on the seed layer 52b, a seed layer 52d on the electrolytic plating layer 52c, and an electrolytic plating layer 52e on the seed layer 52d. The second surface conductor layer 52 has a five-layer structure including the metal foil layer 52a, the seed layer 52b, the electrolytic plating layer 52c, the seed layer 52d, and the electrolytic plating layer 52e. Also, the second cover conductor 53 is formed by the seed layer 52d and the electrolytic plating layer 52e. That is, the second surface conductor layer 52 has a five-layer structure.

[0035] In the wiring board 1 of the embodiment, it is desirable that the thickness T1 of the inner layer conductor layer (the first inner layer conductor layer 12 and the second inner layer conductor layer 14) and the thickness T2 of the surface conductor layer (the first surface conductor layer 42 and the second surface conductor layer 52) satisfy the relationship of the following formula 1. T1 < T2 ··· Formula 1 When the thickness T1 of the inner conductor layer and the thickness T2 of the surface conductor layer satisfy the relationship of Equation 1, the formation of through-holes 80 becomes stable. When forming the multilayer core substrate 100, the warp of the substrate is reduced, and the formation of build-up layers 110 and 120 also becomes stable. Therefore, it is considered that the warp is suppressed and the connection of the conductor layers is stable even when made into a wiring substrate. Specifically, the thickness T1 of the inner conductor layer refers to the thicknesses of the first inner through-hole connection portion 13a and the second inner through-hole connection portion 15a, and the thickness T2 of the surface conductor layer refers to the thicknesses of the first surface through-hole connection portion and the second surface through-hole connection portion.

[0036] Also, it is desirable that the number of layers S1 of the inner conductor layer (the first inner conductor layer 12 and the second inner conductor layer 14) and the number of layers S2 of the surface conductor layer (the first surface conductor layer 42 and the second surface conductor layer 52) satisfy the following relationship of Equation 2. S1 < S2 ··· Equation 2 When the number of layers S1 of the inner conductor layer and the number of layers S2 of the surface conductor layer satisfy the relationship of Equation 2, the formation of through-holes 80 becomes stable. When forming the multilayer core substrate 100, the warp of the substrate is reduced, and the formation of build-up layers 110 and 120 also becomes stable. Therefore, it is considered that the warp is suppressed and the connection of the conductor layers is stable even when made into a wiring substrate. Specifically, the number of layers S1 of the inner conductor layer refers to the number of layers of the first inner through-hole connection portion 13a and the number of layers of the second inner through-hole connection portion 15a, and the number of layers S2 of the surface conductor layer refers to the number of layers of the first surface through-hole connection portion and the number of layers of the second surface through-hole connection portion.

[0037] Furthermore, it is more desirable that the thickness T1 of the inner conductor layer and the thickness T2 of the surface conductor layer satisfy the relationship of Equation 1, and the number of layers S1 of the inner conductor layer and the number of layers S2 of the surface conductor layer satisfy the relationship of Equation 2. By satisfying the two relational expressions, the formation of through-holes 80 becomes stable. When forming the multilayer core substrate 100, the warp of the substrate is reduced, and the formation of build-up layers 110 and 120 also becomes stable. Therefore, it is considered that the warp is suppressed and the connection of the conductor layers is stable even when made into a wiring substrate. It is considered that it is difficult to generate defects such as insulation problems even when a reliability test is performed.

[0038] The through-hole 80 is composed of an inner wall conductor layer 81 and a filler material 82. The inner wall conductor layer 81 of the through-hole 80 is formed of a seed layer 81b formed on the inner wall surface of the through-hole 80a and an electroplating layer 81c on the seed layer 81b. The seed layer 81b is common to the seed layers 42b and 52b and is formed simultaneously with the seed layers 42b and 52b. The electroplating layer 81c is common to the electroplating layers 42c and 52c and is formed simultaneously with the electroplating layers 42c and 52c. The inside of the through-hole 80 is filled with a filler material 82. The filler material 82 is formed using an insulating material containing resin such as epoxy, acrylic, or phenol. Alternatively, the filler material 82 may be a conductive paste or a solidified conductive ink containing metal particles such as silver or copper. By forming the inside of the through-hole 80 with a filler material 82, it becomes possible to form a via conductor directly above the through-hole 80. The first lid conductor 43 and the second lid conductor 53 are formed on the end face of the filler material 82 so as to cover the end face of the filler material 82. Note that the filler material 82 may be made of a conductive material.

[0039] The conductor layer 112 of the first build-up layer 110 is formed of a seed layer 112b and an electroplating layer 112c, and consists of two conductor layers. The conductor layer 122 of the second build-up layer 120 is formed of a seed layer 122b and an electroplating layer 122c, and consists of two conductor layers.

[0040] The via conductor 113 in the first build-up layer 110 is formed from a seed layer 112b and an electroplating layer 112c, and consists of two conductor layers. The seed layer 112b and electroplating layer 112c of the via conductor 113 are the same as the seed layer 112b and electroplating layer 112c of the conductor layer 112. The via conductor 123 in the second build-up layer 120 is formed from a seed layer 122b and an electroplating layer 122c, and consists of two conductor layers. The seed layer 122b and electroplating layer 122c of the via conductor 123 are the same as the seed layer 122b and electroplating layer 122c of the conductor layer 122.

[0041] [Manufacturing method of the wiring board 1 of the embodiment] Figures 3A to 3H show the manufacturing method of the wiring board 1 according to the embodiment. Figures 3A to 3H are cross-sectional views. As shown in Figure 3A, a central insulating layer 10 is prepared in which a first inner layer conductor layer 12 is formed on the first surface 10F and a second inner layer conductor layer 14 is formed on the second surface 10S. The central insulating layer 10 is made from a double-sided copper-clad laminate in which metal foil is formed on both sides of a resin substrate containing a core material. The first inner layer conductor layer 12 and the second inner layer conductor layer 14 having a desired conductor pattern are formed by a subtractive method, such as etching using a mask on which wiring is drawn on the metal foil. This results in a central insulating layer 10 with conductor layers formed on both sides. Alternatively, the central insulating layer 10 may be made by forming a desired conductor pattern on metal formed on both sides of an insulating material by sputtering or plating.

[0042] As shown in Figure 3B, a first resin substrate 40 without metal foil formed on both sides is prepared. The first resin substrate 40 is prepared using a double-sided copper-clad laminate, in which metal foil is formed on both sides of a resin substrate containing a core material, as the starting material. As an example, the first resin substrate 40 is formed by removing the metal foil on both sides of a double-sided copper-clad laminate by etching the entire surface. Similarly, a second resin substrate 50 without metal foil formed on both sides is also prepared. Note that a resin substrate without metal foil may be used from the start.

[0043] As shown in Figure 3C(a), an opening 45 is formed in the first resin substrate 40. The opening 45 penetrates between the upper and lower surfaces of the first resin substrate 40. The opening 45 is formed using a laser, router, or the like.

[0044] As shown in Figure 3C(b), the first resin substrate 40, which has an opening 45 formed therein, is placed on the support plate 66. The lower surface of the first resin substrate 40 faces the support plate 66. The lower side of the opening 45 of the first resin substrate 40 is closed by the support plate 66. The lower surface of the first resin substrate 40 and the support plate 66 may be bonded together via a release agent.

[0045] As shown in Figure 3C(c), the component 60 is placed inside the opening 45. The non-electrode surface 62 of the component 60 is placed on the support plate 66 exposed from the opening 45. At this time, the component 60 is fixed on the support plate 66 by providing an adhesive layer between the non-electrode surface 62 of the component 60 and the support plate 66. The electrode surface 61 of the component 60 is on the same plane as the upper surface of the first resin substrate 40. Note that the electrode surface 61 of the component 60 may be below the upper surface of the first resin substrate 40. The gap between the opening 45 of the first resin substrate 40 and the component 60 is filled with embedding resin 63. The embedding resin 63 is filled by, for example, potting. The embedding resin 63 is preferably a thermosetting resin or a photocurable resin. The embedding resin 63 is cured. The component 60 is fixed inside the opening 45.

[0046] As shown in Figure 3C(d), the support plate 66 is removed after the embedding resin 63 has hardened. The first resin substrate 40 in which the component 60 is housed is formed.

[0047] As shown in Figure 3D, a metal foil 42a, a prepreg 24p that hardens to become the third insulating layer 24, a first resin substrate 40 containing the component 60, a prepreg 22p that hardens to become the first insulating layer 22, a central insulating layer 10, a prepreg 32p that hardens to become the second insulating layer 32, a second resin substrate 50, a prepreg 34p that hardens to become the fourth insulating layer 34, and a metal foil 52a are prepared. The prepreg 22p is placed on the first surface 10F side of the central insulating layer 10, the first resin substrate 40 is placed on the prepreg 22p, the prepreg 24p is placed on the first resin substrate 40, and the metal foil 42a is placed on the prepreg 24p. A prepreg 32p is placed on the second surface 10S side of the central insulating layer 10, a second resin substrate 50 is placed on the prepreg 32p, a prepreg 34p is placed on the second resin substrate 50, and a metal foil 52a is placed on the prepreg 34p.

[0048] As shown in Figure 3E, the metal foil 42a, prepreg 24p, first resin substrate 40, prepreg 22p, central insulating layer 10, prepreg 32p, second resin substrate 50, prepreg 34p, and metal foil 52a are stacked in the arrangement shown in Figure 3D, and then pressed together. Heat curing may be performed simultaneously with the press, or after the press. After the press, the prepregs 22p, 32p, 24p, and 34p are cured to become the first insulating layer 22, second insulating layer 32, third insulating layer 24, and fourth insulating layer 34. A first-side insulating layer 20 consisting of the first insulating layer 22, first resin substrate 40, and third insulating layer 24 is formed on the first surface 10F of the central insulating layer 10. A second-side insulating layer 30 consisting of the second insulating layer 32, second resin substrate 50, and fourth insulating layer 34 is formed on the second surface 10S of the central insulating layer 10. A metal foil 42a is formed on the third insulating layer 24, and a metal foil 52a is formed on the fourth insulating layer 34. After pressing, the first inner conductor layer 12 is embedded in the first insulating layer 22. After pressing, the second inner conductor layer 14 is embedded in the second insulating layer 32. An intermediate substrate 2 is formed, consisting of a first surface insulating layer 20, a central insulating layer 10, and a second surface insulating layer 30.

[0049] In this example, for the sake of explanation, the thickness of the first-side insulating layer 20 and the second-side insulating layer 30 are given as being the same, but the thickness of the first-side insulating layer 20 and the second-side insulating layer 30 may be different. Specifically, the thickness of the first-side insulating layer 20 can be made smaller than the thickness of the second-side insulating layer 30. This allows for adjustment of the overall thickness of the multilayer core substrate. Furthermore, when components are placed inside the resin substrate, the thickness can also be adjusted to match the thickness of the components.

[0050] As shown in Figure 3F, through holes are formed in the intermediate substrate 2. Through holes 80a are formed that penetrate the metal foil 42a, third insulating layer 24, first resin substrate 40, first insulating layer 22, first inner conductor layer 12, central insulating layer 10, second inner conductor layer 14, second insulating layer 32, second resin substrate 50, fourth insulating layer 34, and metal foil 52a of the intermediate substrate 2. The through holes 80a are formed, for example, by drilling with a cutting device such as a drill. The through holes 80a may also be formed by irradiation with laser light. Furthermore, holes 24a are formed that penetrate the metal foil 42a and the third insulating layer 24, exposing the electrode surface 61 of the component 60. The holes 24a are formed, for example, by irradiation with laser light.

[0051] As shown in Figure 3G, a conductor is formed in the through-hole 80a of the intermediate substrate 2. Seed films are formed on the metal foil of the intermediate substrate 2 and on the inner wall of the through-hole. Specifically, a seed film 42b is formed on the metal foil 42a of the intermediate substrate 2, and a seed film 81b is formed on the inner wall of the through-hole 80a. A seed film 52b is formed on the metal foil 52a. Seed films 42b, 81b, and 52b are formed simultaneously, and the metal films are formed, for example, by electroless plating or sputtering. An electroplated film is formed using the metal layer, which is the seed film, as a power supply layer. Electroplated films 42c, 81c, and 52c are formed on the seed films. An inner wall conductor 81 consisting of the seed film 81b and the electroplated film 81c is formed on the inner wall of the through-hole. The electroplated film 42c fills the hole 24a. A connecting conductor 46 is formed by the seed layer 42b formed on the inner wall of the hole 24a and the electroplated layer 42c filling the hole 24a.

[0052] A filler 82 is filled into the cavity of the through hole 80a. For example, a resin such as epoxy, acrylic, or phenol is injected from one or both ends of the through hole 80a. Instead of an insulating resin such as epoxy resin, the through hole 80a may be filled with a conductive paste containing conductive particles such as silver particles. The insulating resin such as epoxy resin or the conductive paste used for the filler 82 is solidified by heating or other means as needed to form the filler 82. The through hole 80 is formed within the through hole 80a by the inner wall conductive layer 81 and the filler 82. The end faces of the solidified filler 82 may be polished by any method such as chemical polishing or mechanical polishing as needed. This polishing preferably makes the end faces of the filler 82 and the surfaces of the electroplating films 42c and 52c substantially flush.

[0053] Furthermore, a seed film 42d and an electroplated film 42e are formed in that order on the electroplated film 42c and filler material 82 on the first surface side of the intermediate substrate 2. Simultaneously, a seed film 52d and an electroplated film 52e are formed in that order on the electroplated film 52c and filler material 82 on the second surface side of the intermediate substrate 2. The seed films 42d, 52d and the electroplated films 42e, 52e are formed, for example, in the same manner as the seed layers 42b, 52b and the electroplated layers 42c, 52c. A five-layer structure consisting of a metal foil film 42a, a seed film 42b, an electroplated film 42c, a seed film 42d, and an electroplated film 42e is formed on the third insulating layer 24. A five-layer structure consisting of a metal foil film 52a, a seed film 52b, an electroplated film 52c, a seed film 52d, and an electroplated film 52e is formed on the fourth insulating layer 34. Subsequently, as shown in Figure 3H, a first surface conductor layer 42 and a second surface conductor layer 52 having the desired conductor pattern are formed by a subtractive method, such as etching using a mask on which the wiring is drawn. At the same time, a first cover conductor 43 consisting of a seed layer 42d and an electroplating layer 42e is formed on the end of the filler material 82 on the first surface insulating layer 20 side (third insulating layer 24 side). The first cover conductor 43 has a five-layer structure consisting of a metal foil layer 42a, a seed layer 42b, an electroplating layer 42c, a seed layer 42d, and an electroplating layer 42e. A second cover conductor 53 consisting of a seed layer 52d and an electroplating layer 52e is formed on the end of the filler material 82 on the second surface insulating layer 30 side (fourth insulating layer 34 side). The second cover conductor 53 has a five-layer structure consisting of a metal foil layer 52a, a seed layer 52b, an electroplating layer 52c, a seed layer 52d, and an electroplating layer 52e. A multilayer core substrate 100 is formed having a central insulating layer 10, a first surface insulating layer 20, a second surface insulating layer 30, through holes 80, a first inner layer conductor layer 12, a second inner layer conductor layer 14, a first surface layer conductor layer 42, and a second surface layer conductor layer 52. As an example of the multilayer core substrate 100, the thickness T1 of the first inner layer conductor layer 12 and the second inner layer conductor layer 14 is 10 μm, and the total number S1 of the first inner layer conductor layer 12 and the second inner layer conductor layer 14 is 1 layer. The thickness T2 of the first surface layer conductor layer 42 and the second surface layer conductor layer 54 is 25 μm, and the total number S2 of the first surface layer conductor layer 42 and the second surface layer conductor layer 54 is 5 layers.

[0054] Build-up layers are formed on both sides of the multilayer core substrate 100. A first build-up layer 110 is formed on the first surface 100F of the multilayer core substrate 100. A second build-up layer 120 is formed on the second surface 100S of the multilayer core substrate 100. For example, a film-like insulating resin (e.g., epoxy resin) without reinforcing material is thermocompressed onto the first surface 100F and the second surface 100S to form the insulating layer 111 on the first surface 100F side of the two insulating layers 111 and the insulating layer 121 on the second surface 100S side of the two insulating layers 121. Through holes are formed in the via conductors 113 or via conductors 123 in each of these insulating layers 111 and 121, for example, by a carbon dioxide laser. A seed film made of a conductor such as copper is formed on the inner wall of the through holes and on the surfaces of the insulating layers 111 and 121 by electroless plating or sputtering. A seed film is used as a power supply layer, and a plating resist having openings for forming a conductor layer is formed. An electroplated film is then formed in the openings by electroplating. Through resist stripping and etching, conductor layers 112 and 122, consisting of the seed layer and the electroplated layer, as well as via conductors 113 and 123, are formed. Specifically, by a semi-additive method (SAP) without using metal foil, the conductor layer 112 on the first surface 100F side of the two conductor layers 112, and the conductor layer 122 on the second surface 100S side of the two conductor layers 122 are formed. Along with these conductor layers 112 and 122, a via conductor 113 penetrating the insulating layer 111 on the first surface 100F side, and a via conductor 123 penetrating the insulating layer 121 on the second surface 100S side are formed.

[0055] Furthermore, the insulating layer 111 and insulating layer 121 on the surface side are formed in the same manner as the insulating layer 111 on the first surface 100F side and the insulating layer 121 on the second surface 100S side. Also, the conductor layers 112 and 122 on the surface side are formed in the same manner as the conductor layer 112 on the first surface 100F side and the conductor layer 122 on the second surface 100S side. In addition, the via conductors 113 and 123 that penetrate the insulating layers 111 and 121 on the surface side are formed in the same manner as the via conductor 113 that penetrates the insulating layer 111 on the first surface 100F side and the via conductor 123 that penetrates the insulating layer 121 on the second surface 100S side. In this way, the first build-up layer 110 and the second build-up layer 120 are formed. As a result, the wiring board 1 of the embodiment (Figure 1) is obtained.

[0056] In the wiring board 1 of this embodiment, the through-hole 80 is connected to the first surface conductor layer 42, the second surface conductor layer 52, the first inner conductor layer 12, and the second inner conductor layer 14. The through-hole 80 is connected to four conductor layers. As a result, the number of conductor layers connected to the through-hole is reduced, which suppresses delay in signal line transmission within the through-hole 80. Furthermore, because signal delay is suppressed, the parasitic capacitance of the through-hole 80 is reduced. Specifically, compared to the number of conductor layers in the through-hole of the multilayer core substrate in Patent Document 1, the wiring board 1 of this embodiment has a reduced number of conductor layers connected to the through-hole.

[0057] In the wiring board according to the embodiment of the present invention, the through-holes are connected to a first surface conductor layer, a second surface conductor layer, a first inner conductor layer, and a second inner conductor layer. The through-holes are connected to four conductor layers. Therefore, since the number of conductor layers connected to the through-holes is reduced, delays in signal line transmission within the through-holes are suppressed. Furthermore, because signal delays are suppressed, the parasitic capacitance of the through-holes is reduced. [Explanation of Symbols]

[0058] 1: Wiring board 10: Central insulating layer 10F: 1st page 10S: 2nd side 12: First inner conductor layer 14: Second inner conductor layer 20: First side insulating layer 30: Second side insulating layer 42: First surface conductor layer 46: Connecting conductor 52: Second surface conductor layer 60: Parts 80: Through Hole 100: Multilayer core substrate 110: First build-up layer 120: Second build-up layer

Claims

1. A wiring substrate consisting of a multilayer core substrate and a build-up layer, The multilayer core substrate is formed of a central insulating layer, a first-side insulating layer, and a second-side insulating layer, and has through holes, an inner conductor layer, and a surface conductor layer. The first surface insulating layer is formed on the first surface side of the central insulating layer by at least two insulating layers. The second surface insulating layer is formed on the second surface side of the central insulating layer by at least two insulating layers. The aforementioned inner conductor layer consists of a first inner conductor layer and a second inner conductor layer. The first inner conductor layer is formed on the first surface of the central insulating layer, and the second inner conductor layer is formed on the second surface of the central insulating layer. The aforementioned surface conductor layer consists of a first surface conductor layer and a second surface conductor layer. The first surface conductor layer is formed as the outermost layer of the first surface insulating layer, The second surface conductor layer is formed as the outermost layer of the second surface insulating layer, The through-hole is formed between the first surface conductor layer and the second surface conductor layer, and is also connected to the first inner conductor layer and the second inner conductor layer. The components are placed within the first surface insulating layer.

2. A wiring board according to claim 1, wherein the thickness T1 of the inner layer conductor and the thickness T2 of the surface layer conductor satisfy the relationship in formula 1. T1<T2...Formula 1

3. The wiring board according to claim 1, wherein the number of layers S1 of the inner conductor layer and the number of layers S2 of the surface conductor layer satisfy the relationship in equation 2. S1<S2...Formula 2

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