Wiring board
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- IBIDEN CO LTD
- Filing Date
- 2024-12-05
- Publication Date
- 2026-06-17
Smart Images

Figure 2026098237000001_ABST
Abstract
Claims
1. A wiring substrate consisting of a multilayer core substrate and a build-up layer, The multilayer core substrate is formed of a central insulating layer, a first-side insulating layer, and a second-side insulating layer, and has through holes, an inner conductor layer, and a surface conductor layer. The first surface insulating layer is formed on the first surface side of the central insulating layer by at least two insulating layers. The second surface insulating layer is formed on the second surface side of the central insulating layer by at least two insulating layers. The aforementioned inner conductor layer consists of a first inner conductor layer and a second inner conductor layer. The first inner conductor layer is formed on the first surface of the central insulating layer, and the second inner conductor layer is formed on the second surface of the central insulating layer. The aforementioned surface conductor layer consists of a first surface conductor layer and a second surface conductor layer. The first surface conductor layer is formed as the outermost layer of the first surface insulating layer, The second surface conductor layer is formed as the outermost layer of the second surface insulating layer, The through-hole is formed between the first surface conductor layer and the second surface conductor layer, and is also connected to the first inner conductor layer and the second inner conductor layer. The components are arranged within the first-side insulating layer and the second-side insulating layer.
2. A wiring board according to claim 1, wherein the thickness T1 of the inner layer conductor and the thickness T2 of the surface layer conductor satisfy the relationship in formula 1. T1<T2...Formula 1
3. The wiring board according to claim 1, wherein the number of layers S1 of the inner conductor layer and the number of layers S2 of the surface conductor layer satisfy the relationship in equation 2. S1<S2...Formula 2