Manufacturing method of wiring boards

Abstract

To provide a wiring board in which the peripheral region is effectively utilized. [Solution] The method for manufacturing a wiring board according to the embodiment includes laminating a semi-cured resin insulating layer 11 onto a substrate, pressing the resin insulating layer 11 toward the substrate 100, removing the peripheral portion of the resin insulating layer 11, and forming a wiring layer on the resin insulating layer 11. Laminating the resin insulating layer 11 onto the substrate 100 includes arranging the resin insulating layer 11 on the substrate 100 such that it has dimensions greater than or equal to the dimensions of the substrate 100 in at least one direction in a plan view, and removing the peripheral portion includes removing the portion of the resin insulating layer 11 that is outside the peripheral edge of the substrate 100 in a plan view.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a printed wiring board. On an inner layer substrate, a first resin sheet provided with a first support on a first resin composition layer is joined, and an insulating layer is formed by thermally curing the first resin composition layer. At the end (peripheral portion) of the first resin sheet, the first support has a blank portion that does not contact the first resin composition layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method disclosed in Patent Document 1, the end (peripheral portion) of the inner layer substrate is not joined to the first resin composition layer, and therefore, it is considered that an insulating layer is not formed at the peripheral portion of the inner layer substrate. It is considered that the peripheral portion of the inner layer substrate cannot be used as a printed wiring board.

Means for Solving the Problems

[0005] The present invention provides a method for manufacturing a wiring board, comprising: laminating a semi-cured resin insulating layer onto a substrate; applying pressure to the resin insulating layer toward the substrate; removing the peripheral edge of the resin insulating layer; and forming a wiring layer on the resin insulating layer. Laminating the semi-cured resin insulating layer onto the substrate includes arranging the resin insulating layer on the substrate having dimensions greater than or equal to the dimensions of the substrate in at least one direction in a plan view, and removing the peripheral edge includes removing the portion of the resin insulating layer outside the peripheral edge of the substrate in a plan view.

[0006] According to embodiments of the present invention, it is considered that the peripheral region of the wiring board in a plan view can be effectively utilized. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example of a wiring board manufactured by the wiring board manufacturing method of the embodiment. [Figure 2] A plan view of the wiring board shown in Figure 1. [Figure 3A] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3B] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3C] Figure 3B is a plan view of a wiring board under manufacturing. [Figure 3D] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3E] Figure 3D shows a plan view of a wiring board under manufacturing. [Figure 3F] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3G] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3H] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3I] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3J]A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3K] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Modes for carrying out the invention]

[0008] A method for manufacturing a wiring board according to one embodiment of the present invention will be described with reference to the drawings. Figure 1 shows a cross-sectional view of a wiring board 1, which is an example of a wiring board manufactured using the wiring board manufacturing method of this embodiment. Figure 2 shows a plan view of the wiring board 1. The illustrated example wiring board 1 has a substrate 100 having one surface 100A and the other surface 100B which is the opposite surface of the first surface 100A.

[0009] On one surface 100A of the laminate 100, a first build-up section 10 is formed, in which resin insulating layers 11 and wiring layers 12 are alternately laminated. On the other surface 100B, a second build-up section 20 is formed, in which resin insulating layers 21 and wiring layers 22 are alternately laminated. In the following description, the substrate 100 is also referred to as the core substrate 100. The core substrate 100 has an insulating layer (core insulating layer) 101 and a conductive layer (core conductive layer) 102. The resin insulating layers 11 and 21 are also referred to simply as insulating layers 11 and 21 below.

[0010] The wiring board 1 shown in Figure 1 is merely one example of a wiring board manufactured by the wiring board manufacturing method of the embodiment. That is, the wiring board manufacturing method of the embodiment can be used to manufacture a wiring board having a different structure from the laminated structure of wiring board 1, and / or containing a different number of wiring layers and resin insulating layers than the wiring layers and resin insulating layers of wiring board 1. Note that in the drawings referenced in the following description, certain parts may be enlarged to facilitate understanding of the disclosed embodiment, and the size and length of each component may not be depicted in the exact proportions relative to each other.

[0011] In the description of the wiring board, the side of the wiring board 1 furthest from the core insulating layer 101 in the thickness direction is referred to as "upper" or "upper side," and the side closer to the core insulating layer 101 is referred to as "lower" or "lower side." Furthermore, in each resin insulating layer, conductor layer, and wiring layer, the surface facing away from the core insulating layer 101 is also referred to as the "upper surface," and the surface facing the core insulating layer 101 is also referred to as the "lower surface." Therefore, for example, in the description of each element constituting the core substrate 100, the first build-up section 10, and the second build-up section 20, the side furthest from the core insulating layer 101 is referred to as "upper side," "upper," "upper layer side," or simply "up," and the side closer to the core insulating layer 101 is referred to as "lower side," "downward," "lower layer side," or simply "down." Furthermore, when viewing the wiring board 1 from a plan view along the thickness direction of the wiring board 1, the direction closer to the center of the wiring board 1 is referred to as the "inside" or "inner side," and the direction further from the center is referred to as the "outside" or "outer side."

[0012] The core conductor layer 102 constituting one side 100A of the core substrate 100 and the core conductor layer 102 constituting the other side 100B are connected by a through-conductor 103 that penetrates the core insulating layer 101 in the thickness direction. The hollow portion inside the through-conductor 103 is filled with a filler material 103f.

[0013] The first build-up section 10 is composed of resin insulating layers 11 and wiring layers 12 that are alternately laminated on one surface 100A of the core substrate 100. The second build-up section 20 is composed of resin insulating layers 21 and wiring layers 22 that are alternately laminated on the other surface 100B of the core substrate 100. The resin insulating layer 11 that constitutes the first build-up section 10 includes a wiring layer 12 formed in contact with two opposite surfaces in the thickness direction, and via conductors 13 that connect the conductor layer 102. The resin insulating layer 21 that constitutes the second build-up section 20 includes a wiring layer 22 formed in contact with two opposite surfaces in the thickness direction, and via conductors 23 that connect the conductor layer 102.

[0014] On the first build-up portion 10, a solder resist layer SR1 is formed. On the second build-up portion 20, a solder resist layer SR2 is formed. An opening SR1o is formed in the solder resist layer SR1, and the conductor pad 12p of the outermost wiring layer 12 in the first build-up portion 10 is exposed from the opening SR1o. An opening SR2o is formed in the solder resist layer SR2, and the conductor pad 22p of the outermost wiring layer 22 in the second build-up portion 20 is exposed from the opening SR2o.

[0015] The core insulating layer 101, the resin insulating layer 11 constituting the first build-up portion 10, and the resin insulating layer 21 constituting the second build-up portion 20 are each formed using an insulating resin such as, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenolic resin, or a fluororesin. Each insulating layer 101, 11, 21 may contain a reinforcing material (core material) such as glass fiber and / or an inorganic filler such as silica or alumina. In the illustrated example, the core insulating layer 101 contains a core material, and the other resin insulating layers 11, 21 do not contain a core material.

[0016] The core conductor layer 102, the wiring layers 12, 22, the through conductor 103, and the via conductors 13, 23 can be formed using any metal such as copper or nickel. For example, the core conductor layer 102, the wiring layers 12, 22 can be formed by a metal foil such as a copper foil and / or a metal film formed by plating or sputtering. The core conductor layer 102, the wiring layers 12, 22, the through conductor 103, and the via conductors 13, 23 are shown in a simplified single-layer structure in FIG. 1 for ease of viewing, but may have a multilayer structure of two or more layers. The core conductor layer 102 can have a five-layer structure including a metal foil, a metal film layer (e.g., electroless copper plating film), and a plating film layer (e.g., electrolytic copper plating film). The wiring layers 12, 22, the through conductor 103, and the via conductors 13, 23 can have a two-layer structure including, for example, a metal film layer (e.g., electroless copper plating film) and a plating film layer (e.g., electrolytic copper plating film).

[0017] The core conductor layer 102 included in the wiring substrate 1 and each of the wiring layers 12 and 22 are patterned to have a predetermined conductor pattern. As will be described in detail later, in the manufacturing method of the wiring substrate of the embodiment, a relatively wide area of the manufactured wiring substrate can be used as an area where the wiring layer can be formed. FIG. 2 is a top view when the wiring substrate 1 shown in FIG. 1 is viewed in plan from above the first build-up portion 10. The wiring substrate 1 has a rectangular planar shape. FIG. 1 shows a cross section taken along line I-I in FIG. 2. As shown in FIG. 2, the wiring substrate 1 has a region FA along its periphery. The region FA is an area where the wiring layers 12 and 22 cannot be formed. The region FA is provided over the entire periphery of the wiring substrate 1.

[0018] According to the manufacturing method of the wiring substrate of the embodiment, it is possible to manufacture a wiring substrate in which the region FA where the wiring layer is not formed is relatively small. As shown in FIG. 1, in the region FA occupying a predetermined range from the periphery of the wiring substrate 1 inward, the wiring layers 12 and 22 are not formed. The shortest distance between the outer edge OP (that is, the periphery of the wiring substrate 1) and the inner edge IP of the region FA can be, for example, 15 mm. That is, the wiring layers 12 and 22 can be formed in the region 15 mm or more inward from the periphery of the wiring substrate 1. In the illustrated example, on the four rectangular sides in the plan view of the wiring substrate 1, the shortest distances between the outer edge OP and the inner edge IP of the region FA are substantially equal.

[0019] Next, taking the case where the wiring substrate 1 in FIG. 1 is manufactured as an example, an example of the manufacturing method of the wiring substrate of an embodiment will be described with reference to FIGS. 3A to 3K. Among FIGS. 3A to 3K, in FIGS. 3A to 3B, FIG. 3D, and FIGS. 3F to 3K, cross sections corresponding to FIG. 1 are shown, and each conductor layer and each wiring layer are shown as single layers.

[0020] First, a substrate is prepared. As shown in Figure 3A, a core substrate 100 is prepared having one surface 100A and the other surface 100B which is the opposite surface of the first surface 100A. For the preparation of the core substrate 100, for example, a double-sided copper-clad laminate is prepared in which a metal foil (copper foil) is provided on the surface of the core insulating layer 101. Through holes 103o are formed in the double-sided copper-clad laminate, for example by drilling, and a metal film layer, for example, an electroless copper plating film, is formed on the inner wall of the through holes 103o and the upper surface of the metal foil. On the metal film layer, a plating film layer, for example, an electrolytic copper plating film, is formed by electrolytic plating using this metal film layer as a power supply layer. A through conductor 103 is formed.

[0021] The inside of the through-conductor 103 formed on the inner wall of the through-hole 103o is filled with filler 103f, for example by injecting epoxy resin. After the filler 103f has solidified, a metal film layer and a plating film layer are further formed on the upper surface of the filler 103f and the plating film layer. As a result, although shown as a single layer in the figure, a core wiring layer 102 having a five-layer structure of metal foil, metal film layer, plating film, metal film layer, and plating film layer is formed on both sides of the core insulating layer 101. Then, by patterning the core wiring layer 102 using the subtractive method, a core substrate 100 having a predetermined conductor pattern is obtained.

[0022] Next, a resin insulating layer is laminated onto the substrate. Semi-cured resin insulating layers 11 and 21 are laminated onto the core substrate 100. Specifically, as shown in Figures 3B to 3F, a semi-cured resin insulating layer 11 is laminated onto one side 100A of the core substrate 100, and a resin insulating layer 21 is laminated onto the other side 100B. Hereinafter, the resin insulating layer 11 laminated on one side 100A will also be referred to as the first resin insulating layer 11, and the resin insulating layer 21 laminated on the other side 100B will also be referred to as the second resin insulating layer 21.

[0023] The first resin insulating layer 11 and the second resin insulating layer 21 are formed from a material containing either a thermosetting resin such as epoxy resin or a thermoplastic resin such as fluororesin. As shown in Figure 3B, the first resin insulating layer 11 and the second resin insulating layer 21 are placed on the core substrate 100 in a semi-cured state, a so-called B-stage state. The first resin insulating layer 11 and the second resin insulating layer 21 are provided with a protective film PF on their upper surfaces. Examples of protective films PF include polyethylene terephthalate (PET) and polyethylene naphthalate (PEN) films. The protective film PF is applied over the entire upper surface of the first resin insulating layer 11 and the second resin insulating layer 21.

[0024] In the manufacturing method of the embodiment, the semi-cured resin insulating layer placed on the substrate has dimensions greater than or equal to the dimensions of the substrate in at least one direction (in a plan view) in its extending direction. In the example of manufacturing the wiring board 1 described, the first resin insulating layer 11 and the second resin insulating layer 21 placed on the core substrate 100 have dimensions greater than the dimensions of the core substrate 100 in all directions in which they extend. The first resin insulating layer 11 and the second resin insulating layer 21 may have dimensions equivalent to the dimensions of the core substrate 100 in their extending direction.

[0025] Figure 3C shows a plan view of the state shown in Figure 3B, viewed from above on one side 100A of the core substrate 100. As shown in Figure 3C, the first resin insulating layer 11 has dimensions larger than the dimensions of the core substrate 100 in all directions in the plan view. The first resin insulating layer 11 covers the entire area of ​​one side 100A of the core substrate 100 and is positioned to protrude outward from the periphery of the core substrate 100 around its entire circumference (i.e., at all peripheries).

[0026] In the plan view shown in Figure 3C, the periphery of the second resin insulating layer 21, located towards the back of the paper, overlaps with the periphery of the first resin insulating layer 11. That is, like the first resin insulating layer 11, the second resin insulating layer 21 has dimensions larger than the dimensions of the core substrate 100 in all directions in a plan view. The second resin insulating layer 21 covers the entire other surface 100B (see Figure 3B) of the core substrate 100 and is positioned to protrude outward from the periphery of the core substrate 100 around its entire circumference. Therefore, the periphery of the first resin insulating layer 11, the periphery of the second resin insulating layer 21, and the periphery of the protective layer PF provided on the upper surfaces of the first resin insulating layer 11 and the second resin insulating layer 21 are located outside the core substrate 100.

[0027] In the process of thermocompressing the first resin insulating layer 11, described later, to the core substrate 100, it is preferable that the thickness of the first resin insulating layer 11 on the core substrate 100 be formed more uniformly. From this viewpoint, it is preferable that the extent to which the first resin insulating layer 11 protrudes outward from the periphery of the core substrate 100 (the shortest distance from the periphery of the core substrate 100 to the periphery of the first resin insulating layer 11 in a plan view) is substantially uniform over the entire circumference of the first resin insulating layer 11 (on all four sides). Similarly, from the same viewpoint, it is preferable that the extent to which the second resin insulating layer 21 protrudes outward from the periphery of the core substrate 100 is substantially uniform over the entire circumference of the second resin insulating layer 21.

[0028] In the manufacturing method of the wiring board of the embodiment, the substrate that serves as the base for the resin insulating layer is not limited to having the form of a so-called core substrate such as the core substrate 100 described above, but may be, for example, a laminate in which insulating layers and wiring layers formed using a build-up method are alternately stacked, or it may be a substrate having only an insulating layer. The substrate that serves as the base for the resin insulating layer may be a silicon substrate, a ceramic substrate, or a glass substrate.

[0029] Next, the first resin insulating layer 11 and the second resin insulating layer 21 are heated and pressed against the core substrate 100 together with the protective film PF. The resins constituting the first resin insulating layer 11 and the second resin insulating layer 21 are softened by heating, and pressure is applied from above the protective film PF toward one side 100A or the other side 100B by a pressure plate (not shown). As a result, the first resin insulating layer 11 is heat-pressed onto the entire surface 100A of the core substrate 100, and the second resin insulating layer 21 is heat-pressed onto the entire surface 100B of the other side 100B.

[0030] As a result of the first resin insulating layer 11 and the second resin insulating layer 21 being heat-pressed onto the core substrate 100, the state shown in Figures 3D and 3E is achieved. Figure 3E is a plan view of the state shown in Figure 3D, viewed from above one side 100A. When the first resin insulating layer 11 and the second resin insulating layer 21 are pressed against the core substrate 100 while softened by heating, the softened resin of the first resin insulating layer 11 and the second resin insulating layer 21 is pushed outwards. As a result, the softened resin of the first resin insulating layer 11 and the second resin insulating layer 21 wraps around the periphery of the core substrate 100, covering the side surfaces that make up the periphery of the core substrate 100.

[0031] When the first resin insulating layer 11 and the second resin insulating layer 21 are softened by heating and pressed against the core substrate 100, the first resin insulating layer 11 and the second resin insulating layer 21 come into contact. Specifically, as shown in Figure 3D, the portion of the first resin insulating layer 11 that extends outward from the periphery of the core substrate 100 and the portion of the second resin insulating layer 21 that extends outward from the periphery of the core substrate 100 come into contact. When the softened resin of the first resin insulating layer 11 and the softened resin of the second resin insulating layer 21 come into contact, the softened resin is further pushed outward, and as shown, a localized deformation (expansion) EP is formed that protrudes outward from the periphery of the protective film PF. As shown in Figure 3E, the expansion EP can be formed to protrude outward from the protective film PF around the entire circumference of the first resin insulating layer 11 and the second resin insulating layer 21 (all four sides of the protective film PF).

[0032] In the manufacturing method of the wiring board of this embodiment, during the thermocompression bonding of the resin insulating layer to the substrate, local deformation of the resin insulating layer due to the flow of softened resin occurs on the outside of the substrate. Local deformation of the resin insulating layer does not occur in the portion that overlaps with the substrate in the thickness direction. A wider area of ​​the substrate becomes available for use as a wiring board.

[0033] After the first resin insulating layer 11 and the second resin insulating layer 21 are thermocompressed onto the surface of the core substrate 100, the semi-cured first resin insulating layer 11 and the second resin insulating layer 21 are fully cured. Through this full curing, the resins constituting the first resin insulating layer 11 and the second resin insulating layer 21 are cured to the final stage of curing, the so-called C stage. The first resin insulating layer 11 and the second resin insulating layer 21 are fully cured, for example, by heating them at a temperature suitable for the full curing of the resins constituting the first resin insulating layer 11 and the second resin insulating layer 21 for an appropriate time. The first resin insulating layer 11 and the second resin insulating layer 21 may be fully cured by any other method, such as ultraviolet irradiation, rather than just by thermocuring.

[0034] Next, the peripheral portion of the resin insulating layer is removed. As shown in Figure 3F, the portions of the first resin insulating layer 11 and the second resin insulating layer 21 that extend beyond the periphery of the core substrate 100 are removed by cutting along with the protective film PF. The portions of the first resin insulating layer 11 and the second resin insulating layer 21 that extend beyond the periphery of the core substrate 100 in a plan view are removed, and as shown in the figure, the entire periphery (side surface) of the core substrate 100 is exposed. Any method can be used to remove the portions of the first resin insulating layer 11 and the second resin insulating layer 21 that extend beyond the periphery of the core substrate 100 by cutting, such as router processing or processing using a roller blade such as a dicing saw.

[0035] Next, as shown in Figure 3G, via holes 13a are formed in the first resin insulating layer 11 on one side 100A of the core substrate 100, and via holes 23a are formed in the second resin insulating layer 21 on the other side 100B. The via holes 13a and 23a are formed by irradiation with laser light, for example, a carbon dioxide laser or a UV laser. The via holes 13a and 23a are formed in the first resin insulating layer 11 and the second resin insulating layer 21, respectively, while the protective film PF (see Figure 3F) is still in place. By forming the via holes 13a and 23a while the protective film PF is in place, the adhesion of resin debris generated from the first resin insulating layer 11 and the second resin insulating layer 21 to the surfaces of the first resin insulating layer 11 and the second resin insulating layer 21 can be prevented. Furthermore, the laser beam is irradiated onto the surface of the protective film PF, but the laser beam is not directly irradiated onto the surfaces of the first resin insulating layer 11 and the second resin insulating layer 21. Therefore, the formation of excessive via through-holes 13a and 23a in the first resin insulating layer 11 and the second resin insulating layer 21 due to the impact during laser beam irradiation can be prevented.

[0036] The via through-holes 13a and 23a formed may be subjected to a desmearing treatment (so-called desmearing treatment) to remove resin residue generated during the formation of the via through-holes 13a and 23a. The resin residue removal treatment may be performed while the first resin insulating layer 11 and the second resin insulating layer 21 are still equipped with the protective film PF. The resin residue removal treatment may be a wet process, for example, including immersion in a dissolving solution such as a permanganate solution. Alternatively, the resin residue removal treatment may be performed as a dry process without using a dissolving solution. A dry process for removing resin residue may be a plasma treatment using a plasma gas such as argon, methane tetrafluoride, a mixture of methane tetrafluoride and oxygen, or sulfur hexafluoride.

[0037] Subsequently, the protective film PF is removed by any method, forming the state shown in Figure 3G. The protective film PF can be removed, for example, by simply pulling it in the opposite direction to the resin insulating layers 11 and 21. Alternatively, the protective film PF may be removed by dissolution using a suitable solvent.

[0038] In the state shown in Figure 3G, the first resin insulating layer 11 completely covers one surface 100A of the core substrate 100, and the second resin insulating layer 21 completely covers the other surface 100B. In a plan view, the first resin insulating layer 11 and the second resin insulating layer 21 extend to the periphery of the core substrate 100. In the manufacturing method disclosed in Patent Document 1, which is shown as prior art, the resin composition layer is not formed up to the periphery of the inner layer substrate, and the portion of the inner layer substrate near the periphery that is not covered by the resin composition layer cannot be used as a printed circuit board. In contrast, according to the manufacturing method of the wiring board of this embodiment, the entire surface perpendicular to the thickness direction of the substrate (core substrate) is covered by the resin insulating layer. Therefore, it is considered that the region up to the periphery of the substrate can be effectively used as a wiring board.

[0039] In the state shown in Figure 3G, the upper surfaces of the resin insulating layers 11 and 21 have relatively good flatness in a relatively wide area including the vicinity of the periphery in a plan view. This makes it possible to form the wiring layers 12 and 22, which will be described later with reference to Figure 3H, over a relatively wide area of ​​the upper surfaces of the resin insulating layers 11 and 21. Specifically, the wiring layers 12 and 22 can be formed in an area that is more than a predetermined distance, for example, 15 mm or more, from the periphery of the resin insulating layers 11 and 12 (i.e., from the periphery of the core substrate 100).

[0040] Next, as shown in Figure 3H, via through-holes 13a and 23a penetrating the resin insulating layers 11 and 21 are filled with conductors to form via conductors 13 and 23, and at the same time, wiring layers 12 and 22 are formed integrally with the via conductors 13 and 23. The wiring layer 12 is formed on the resin insulating layer 11 covering one side 100A of the core substrate 100. The wiring layer 22 is formed on the resin insulating layer 21 covering the other side 100B of the core substrate 100. The wiring layers 12 and 22 are formed in the region where the wiring layers 12 and 22 can be formed, which is located at a predetermined distance or more inward from the periphery of the resin insulating layers 11 and 12 as described above.

[0041] The wiring layers 12, 22 and via conductors 13, 23 can be formed, for example, by a general semi-additive method. That is, a seed layer (not shown) made of a metal film such as copper is formed on the surface of each resin insulating layer 11, 21 and on the inner surface of the via through holes 13a, 23a by electroless plating or sputtering. The wiring layers 12, 22 and via conductors 13, 23 can then be formed by forming a plating resist (not shown) with appropriate openings on the formed seed layer and forming an electroplated film (not shown) using the seed layer as a power supply layer within the openings of the plating resist. The wiring layers 12, 22 and via conductors 13, 23 can then be formed by peeling off the plating resist and removing the exposed portion of the seed layer by quick etching or the like.

[0042] Next, the same process as described with reference to Figures 3B to 3H, which involves placing the resin insulating layers 11 and 21 onto the core substrate 100, thermocompressing them onto the core substrate 100, removing the outer portion from the periphery of the core substrate 100, and forming the via conductors 13 and 23 and wiring layers 12 and 22, is repeated any number of times on top of the resin insulating layers 11 and 21. That is, in the manufacturing method of a wiring board, multiple resin insulating layers may be laminated on the substrate, in which case the outer portion from the periphery of each resin insulating layer on the substrate may be removed by cutting before forming the wiring layer on each resin insulating layer. The first build-up section 10 and the second build-up section 20 are formed, creating the state shown in Figure 3I.

[0043] Next, as shown in Figure 3J, a solder resist layer SR1 is formed on the first build-up section 10, and a solder resist layer SR2 is formed on the second build-up section 20. The solder resist layers SR1 and SR2 are composed of, for example, a photosensitive epoxy resin or polyimide resin, and can be formed by spray coating, curtain coating, or lamination.

[0044] Next, as shown in Figure 3K, an opening SR1o is formed in the solder resist layer SR1 to expose the conductor pad 12p, and an opening SR2o is formed in the solder resist layer SR2 to expose the conductor pad 22p. The openings SR1o and SR2o are formed by exposure and development using a mask having an appropriate opening pattern. A surface protective film (not shown) made of Au, Ni / Au, Ni / Pd / Au, solder, or heat-resistant preflux may be formed on the exposed surfaces of the conductor pads 12p and 22p by electroless plating, solder leveling, or spray coating. The wiring board 1 is completed by going through the above steps.

[0045] The method for manufacturing the wiring board of the embodiment is not limited to the method described with reference to Figures 3A to 3K. For example, in the example shown in Figures 3D and 3E, the deformed portion (expanded portion) EP may not protrude outward from the protective film PF, and the outer edges of the first resin insulating layer 11 and the second resin insulating layer 21 may coincide with the periphery of the protective film PF located outside the core substrate 100. Furthermore, the method for manufacturing the wiring board of the embodiment may produce a wiring board having a different structure from the laminated structure shown in each drawing, or a wiring board containing a different number of resin insulating layers than the number of resin insulating layers shown in each drawing. The method for manufacturing the wiring board of the embodiment includes, at least, placing a resin insulating layer having dimensions greater than or equal to the dimensions of the substrate in at least one direction in a plan view on the substrate, applying pressure, and removing the peripheral portion of the resin insulating layer that is outside the periphery of the substrate in a plan view. For example, when multiple resin insulating layers are laminated on a substrate, the peripheral portions of the resin insulating layers may be removed by cutting the peripheral portions of multiple layers together. Any additional steps may be added to the processes described above, and any part of the processes described above may be omitted. In the description of the manufacturing method using the manufacturing of the wiring board 1 as an example, an example was shown in which resin insulating layers are laminated on both sides of the board, but the resin insulating layer laminated on the board only needs to be laminated on at least one side of the board. [Explanation of Symbols]

[0046] 1 Wiring board 101 Insulating layer (core insulating layer) 102 Conductor layer (core conductor layer) 10. First Build-up Department 20. Second Build-up Department 13, 23 via conductors 100 substrates (core substrates) 103 Through conductor 11. Insulating layer (first resin insulating layer) 21. Insulating layer (second resin insulating layer) 12, 22 wiring layer PF protective film SR1, SR2 Solder Resist Layer

Claims

1. Laminating a semi-cured resin insulating layer onto a substrate, Pressurizing the resin insulating layer toward the substrate, Removing the peripheral edge of the aforementioned resin insulating layer, Forming a wiring layer on the aforementioned resin insulating layer, A method for manufacturing a wiring board, including, Laminating the semi-cured resin insulating layer onto the substrate includes arranging the resin insulating layer on the substrate such that the dimensions of the resin insulating layer are greater than or equal to the dimensions of the substrate in at least one direction in a plan view. Removing the peripheral portion includes removing the portion of the resin insulating layer that is outside the peripheral edge of the substrate in a plan view.

2. A method for manufacturing a wiring board according to claim 1, wherein the board has a first surface and a second surface which is the opposite surface of the first surface, and the lamination of the resin insulating layer on the board includes laminating the first resin insulating layer on the first surface and laminating the second resin insulating layer on the second surface.

3. A method for manufacturing a wiring board according to claim 2, wherein pressurizing the resin insulating layer includes bringing the portion of the first resin insulating layer outside the periphery of the substrate into contact with the portion of the second resin insulating layer outside the periphery of the substrate.

4. A method for manufacturing a wiring board according to claim 1, wherein a protective film is provided on the side of the resin insulating layer laminated on the substrate that is opposite to the substrate, and the pressurization is performed with the protective film provided on the resin insulating layer.

5. A method for manufacturing a wiring board according to claim 4, further comprising removing the protective film from the resin insulating layer after removing the peripheral portion.

6. A method for manufacturing a wiring board according to claim 1, wherein a protective film having dimensions greater than or equal to the dimensions of the substrate is provided on the side of the resin insulating layer opposite to the substrate, and the periphery of the protective film is located outside the periphery of the substrate.

7. A method for manufacturing a wiring board according to claim 1, wherein the resin insulating layer has dimensions greater than or equal to the dimensions of the board in all directions in a plan view.

8. A method for manufacturing a wiring board according to claim 1, wherein removing the portion of the resin insulating layer that is outside the periphery of the board includes exposing the periphery of the board.

9. A method for manufacturing a wiring board according to claim 1, wherein the wiring layer is formed in a region at least 15 mm inward from the periphery of the board.

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