Apparatus and method for filling gaps in a substrate, and related semiconductor devices

Abstract

The present invention provides apparatus and methods for partially manufacturing semiconductor devices using semiconductor processing, particularly periodic deposition etching processes. [Solution] The apparatus includes at least one reactor having a reaction chamber, a metal precursor source for delivering metal precursor vapor, and an etchant source for delivering etchant vapor. A vapor distribution and removal system supplies these vapors to the reaction chamber and then removes them. A sequence controller connected to the distribution and removal system includes a memory having a program for controlling the vapor flow from the metal precursor source during one or more deposition cycles.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor processing, and more specifically, to apparatuses and methods for partially manufacturing semiconductor devices by a periodic deposition etching process. The present disclosure further relates to the provision of related semiconductor devices such as memory devices and sub-structures thereof.

Background Art

[0002] Semiconductor manufacturing processes for fabricating devices such as memory elements, transistors, integrated circuits, and sub-structures thereof typically involve multi-step procedures that precisely manipulate the material atomic scale and nanometer scale. These processes often include deposition, etching, thermal annealing, lithography, and doping, each of which requires dedicated tools and precise control to achieve the desired device characteristics.

[0003] However, the increasing complexity of modern semiconductor devices combined with shrinking feature sizes and the introduction of advanced materials has made it difficult to efficiently use a wide range of disparate tools. The need for tight integration between these processes, as well as the requirements for improving uniformity, scalability, and yield, further amplifies these challenges.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In view of the above, there remains a need to rationalize the workflow, enhance compatibility between different manufacturing processes, and improve the overall efficiency of semiconductor manufacturing. Accordingly, an object of the present disclosure is to provide a simple and reliable apparatus and method for controlled semiconductor processing.

Means for Solving the Problems

[0005] In the present day, the devices and methods described herein have been found to address some or all of the above-mentioned problems individually or in any combination, and to achieve the objectives described herein.

[0006] This summary is provided to introduce a selection of concepts in a simplified form. These concepts will be described in more detail below in the detailed description of exemplary embodiments of the present disclosure. This summary is not intended to identify any major or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] In general, the technologies disclosed herein relate to the field of semiconductor processing, and more specifically to apparatus and methods for streamlining deposition and etching processes for precisely shaping and / or defining one or more features of semiconductor devices, such as trenches, vias, or isolated components.

[0008] In particular, the apparatus described herein enables the integration of deposition and etching processes within a single reactor (i.e., the same tool). This configuration offers several significant advantages over reactors of the art, reducing and advantageously eliminating the need for substrate transfer between separate tools required by conventional apparatuses and methods.

[0009] Another advantage of combining metal-containing film deposition and subsequent etching within a single reactor is improved semiconductor processing speed and reduced reliance on multiple tools. This integration leads to increased throughput, lower labor costs per substrate, and improved overall operational efficiency.

[0010] Furthermore, the described apparatus and methods can optimize existing workflows and provide cost-effective and easily implementable solutions.

[0011] According to the manner of this disclosure, - At least one reactor comprising at least one reaction chamber configured to process at least one semiconductor substrate, wherein the semiconductor substrate comprises one or more gap portions, - A metal precursor source configured to provide a vapor of at least one metal precursor containing at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, cobalt, nickel, and mixtures thereof, - An etchant source configured to provide steam for at least one etchant, - A vapor distribution and removal system configured to supply vapors from a metal precursor source and an etchant source to at least one reaction chamber in the reactor, and to remove the vapors from the reaction chamber, - A sequence controller operably connected to a distribution and removal system, comprising a memory containing a program configured to control the flow from a metal precursor source to a reaction chamber by activating the vapor distribution and removal system during one or more deposition cycles, thereby, as a result of the deposition cycles, a metal-containing film is deposited to at least partially fill one or more gaps in a semiconductor substrate, The program is further configured to control the flow from the etchant source to the reaction chamber by activating a vapor distribution and removal system during one or more etching cycles, thereby providing an apparatus in which a metal-containing film undergoes subtractive etching as a result of the etching cycle.

[0012] In certain embodiments, the apparatus further comprises a reactant source configured to supply vapors of reactants, a vapor distribution and removal system further configured to supply vapors from the reactant source to the reactor, and a program provided in memory configured to control the flow of reactants from the reactant source to at least one reaction chamber during one or more deposition cycles.

[0013] In certain embodiments, the reactants are selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reducing reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

[0014] In certain embodiments, the program provided in memory is further configured to control the flow from a metal precursor source to at least one reaction chamber by activating a vapor distribution and removal system during one or more deposition cycles that are part of a periodic deposition process as part of an atomic layer deposition (ALD) process.

[0015] In certain embodiments, at least one semiconductor substrate further includes a material selected from the group consisting of silicon, silicon oxide, silicon germanium, carbon-doped silicon oxide, silicon nitride, silicon carbide, germanium, gallium arsenide, gallium nitride, glass, sapphire, and combinations thereof.

[0016] In certain embodiments, the metal precursor is a metal halide, a metal chalcogenized halide, or a metal-organic precursor.

[0017] In certain embodiments, the etchant comprises one or more halogen-containing etching compounds.

[0018] In certain embodiments, the etchant comprises one or more halogen-containing etching compounds selected from the group consisting of F2, Cl2, Br2, quaternary ammonium fluoride, quaternary ammonium chloride, quaternary ammonium bromide, HF, HCl, HBr, tetrafluoroboric acid, tetrachloroboric acid, tetrabromoboric acid, hexafluorosilicic acid, hexachlorosilicic acid, hexabromosilicic acid, tetrabutylammonium tetrafluoroborate, H2ZrF6, H2TiF6, HPF6, MoCl5, WCl5, ammonium hexafluorosilicate, ammonium hexachlorosilicate, ammonium hexabromosilicate, ammonium hexafluorotianoate, ammonium hexachlorotianoate, ammonium hexabromotianoate, thionyl chloride, and mixtures thereof.

[0019] In certain embodiments, at least one reactor further comprises heating means configured to supply a temperature of 200°C to 800°C into the reaction chamber.

[0020] In certain embodiments, at least one reactor further comprises a pressure regulating mechanism configured to supply a pressure of 0.2 Torr to 200 Torr into the reaction chamber.

[0021] In certain embodiments, the apparatus is designed to be a vertical furnace comprising at least one reaction chamber, one or more of the reactors, configured to simultaneously receive and process multiple semiconductor substrates.

[0022] In certain embodiments, the reactor comprises a reactor housing that encloses at least one reaction chamber.

[0023] In certain embodiments, the reactor comprises a reactor housing enclosing at least a first reaction chamber and a second reaction chamber, and a handling chamber configured for transporting a semiconductor substrate between the first reaction chamber and the second reaction chamber, wherein a deposition cycle is carried out in the first reaction chamber, an etching cycle is carried out in the second reaction chamber, and a vapor distribution and removal system is further configured to selectively direct a flow of metal precursor vapor to the first reaction chamber and a flow of etchant vapor to the second reaction chamber.

[0024] In certain embodiments, the reactor comprises a reactor housing enclosing a single reaction chamber, wherein the deposition cycle and the etching cycle are carried out in the (single) reaction chamber, and a vapor distribution and removal system is further configured to selectively direct and remove a flow of metal precursor vapor and a flow of etchant vapor to the (single) reaction chamber.

[0025] Another aspect of the present disclosure provides a method for at least partially manufacturing a semiconductor substrate, the method comprising: a) supplying at least one semiconductor substrate comprising one or more gap portions into a reactor comprising at least one reaction chamber; b) performing one or more deposition cycles in the reaction chamber, each cycle including a metal precursor pulse, wherein at least a portion of the semiconductor substrate is contacted by at least one metal precursor by introducing at least one metal precursor into the reactor, the at least one metal precursor comprising at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, and mixtures thereof, and as a result of the cycle, a metal-containing film is deposited to at least partially fill one or more gap portions of the semiconductor substrate; performing one or more deposition cycles. c) Performing one or more etching cycles in a reaction chamber, each cycle comprising an etchant pulse, wherein at least a portion of the metal-containing film is contacted by at least one etchant by introducing at least one etchant into the reactor, thereby, as a result of the cycle, the metal-containing film undergoes subtractive etching.

[0026] In certain embodiments, at least one deposition cycle further comprises a reactant pulse, wherein at least a portion of a semiconductor substrate is contacted by at least one reactant by introducing at least one reactant into a reactor, and the at least one reactant is selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reducing reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

[0027] Another aspect of the present disclosure provides a semiconductor device comprising one or more gaps filled with a metal-containing film prepared in an apparatus, by an aspect of the present disclosure or a (preferred) embodiment thereof, or by a method according to an aspect of the present disclosure or a (preferred) embodiment thereof.

[0028] In certain embodiments, the reactor comprises a reactor housing enclosing at least one reaction chamber, and the deposition cycle and etching cycle are carried out without removing the semiconductor substrate from the reactor, particularly the reactor housing.

[0029] In certain embodiments, the reactor comprises a reactor housing enclosing at least a first reaction chamber and a second reaction chamber, and a handling chamber configured for transporting a semiconductor substrate between the first and second reaction chambers, wherein the deposition cycle is carried out in the first reaction chamber and the etching cycle is carried out in the second reaction chamber without removing the semiconductor substrate from the reactor.

[0030] In certain embodiments, the reactor comprises a reactor housing enclosing a single reaction chamber, and the deposition cycle and etching cycle are carried out within the (single) reaction chamber without removing the semiconductor substrate from the reactor, preferably without removing the semiconductor substrate from the (single) reaction chamber.

[0031] In certain embodiments, the semiconductor device is a memory device comprising at least one of a 3D-NAND device, a DRAM device, a 3D integrated device, or an integrated logic device, or a partially fabricated memory device structure comprising at least one of a 3D-NAND device structure, a DRAM device structure, a 3D integrated device structure, or a partially fabricated integrated logic device structure.

[0032] It should be understood that the elements in the figures are illustrated for simplification and clarity and are not necessarily drawn to actual size. For example, the dimensions of some elements in the figures may be exaggerated relative to others in order to help improve understanding of the illustrated embodiments of this disclosure. [Brief explanation of the drawing]

[0033] [Figure 1] A schematic diagram of an apparatus 100 according to an embodiment of the present disclosure, comprising a first reaction chamber 112 and a second reaction chamber 113 as described herein, is shown. [Figure 2] A schematic example of an apparatus 200 according to another embodiment of the present disclosure is provided, comprising a reactor 201 having a single reaction chamber 212 as described herein. [Figure 3] A method 300 according to an embodiment of the present disclosure for at least partially fabricating a semiconductor device or a substructure of a semiconductor device is described, wherein the reactor comprises a single reaction chamber. [Figure 4] A method 400 according to another embodiment of the present disclosure for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device, wherein the reactor comprises a single reaction chamber as described herein. [Figure 5] A method 500 according to yet another embodiment of the present disclosure for fabricating a semiconductor device or a substructure of a semiconductor device, wherein the reactor comprises a single reaction chamber, and the reactor comprises a first reaction chamber and a second reaction chamber as described herein. [Figure 6] A method 600 according to yet another embodiment of the present disclosure for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device is described, wherein the reactor comprises a single reaction chamber, and the reactor comprises a first reaction chamber and a second reaction chamber as described herein. [Figure 7] A method 700 according to yet another embodiment of the present disclosure for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device is described, wherein the reactor comprises a single reaction chamber, and the reactor comprises a first reaction chamber, a second reaction chamber, and a third reaction chamber as described herein. [Figure 8] A schematic diagram of a vertical furnace system 900 according to one embodiment of the present disclosure, comprising at least one reaction chamber as described herein, is shown. [Figure 9] A schematic cross-sectional view of a semiconductor memory device 800 according to one embodiment of the present disclosure, which is at least partially manufactured using the apparatus and / or methods described herein, is shown. [Modes for carrying out the invention]

[0034] While certain embodiments and examples are disclosed below, it will be understood by those skilled in the art that the disclosure extends beyond the specifically disclosed embodiments and / or uses thereof, as well as their obvious modifications and equivalents. Therefore, the scope of the disclosure is not limited by the specific disclosed embodiments described below.

[0035] In the detailed description below, the underlying technology of this disclosure will be described in different embodiments. The embodiments of this disclosure may be arranged, substituted, combined, and designed in a wide variety of different configurations, as generally described herein and as shown in the figures, all of which are clearly intended and readily apparent to form part of this disclosure. This description is intended to assist the reader in more easily understanding the technical concepts, but is not intended to limit the scope of this disclosure, which is limited solely by the claims. Therefore, the following description should be considered essentially illustrative and not restrictive.

[0036] As used herein, singular nouns include both singular and plural nouns unless otherwise explicitly indicated by the context. For example, “process” can mean one process or two or more processes.

[0037] As used herein, the terms “equipped with” and “consisted of” are synonymous with “included” and “having,” and are comprehensive or open-ended, not excluding additional, undescribed components, elements, or process steps. These terms also include “consisted of” and “essentially made from,” which enjoy established meanings in patent terminology.

[0038] The terms “one or more,” “one or more,” and “at least one,” for example, at least one of one or more members or groups of members, are self-evident, but by further examples, these terms include, among other things, any one of those members, or any two or more of those members, such as three or more, four or more, five or more, six or more, or seven or more, and references to all of those members. In another example, “one or more” or “at least one” could refer to 1, 2, 3, 4, 5, 6, 7 or more.

[0039] In this description and claims, the terms 1, 2, 3, and similar are used to distinguish between similar elements, unless otherwise specified, and are not necessarily used to indicate order or chronology. It is understood that such terms are interchangeable under appropriate circumstances, and that embodiments of the disclosure described herein may be capable of operating in any order other than those described or illustrated herein.

[0040] As used herein, the term "and / or" when used in a list of two or more items means that any one of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a list is described as containing group A, B, and / or C, the list may contain A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C.

[0041] Throughout this specification, any reference to “one embodiment” or “one embodiment” means that a particular feature, structure, or characteristic described in relation to the embodiment is included in at least one embodiment of this disclosure. Thus, the occurrence of the phrases “in one embodiment)” or “in one embodiment” or “in a particular embodiment” in various parts of this specification does not necessarily all refer to the same embodiment, although they may. Furthermore, a particular configuration, structure, or characteristic may be combined in any preferred manner in one or more embodiments, as will be apparent to those skilled in the art from this disclosure. Moreover, a particular embodiment described herein includes some features included in other embodiments but does not include other configurations, while combinations of configurations from different embodiments mean that, as will be understood to those skilled in the art, they are within the scope of the invention and form different embodiments.

[0042] Enumerations of numerical ranges by endpoint include all integers and, where appropriate, fractions within that range (for example, 1–5 may include 1, 2, 3, 4 if referring to the number of elements, and 1.5, 2, 2.75, 3.80 if referring to measured values). Enumerations of endpoints also include the endpoint values ​​themselves (for example, 1.0–5.0 includes both 1.0 and 5.0). Any numerical range enumerated herein is intended to include all subranges contained within it. This applies to numerical ranges whether they begin with expressions such as "from... to...", "between... and...", or other expressions.

[0043] As used herein, the terms “about” or “approximately” are used to provide flexibility to numerical or range endpoints by specifying that, depending on the particular context, a given value may be “slightly above” or “slightly below” the value or endpoint. Thus, as used herein, when referring to measurable values ​​such as parameters, quantities, durations, and the like, the terms “about” or “approximately” mean to include variations from a specified value or endpoint, such as variations of ±10%, preferably ±5%, more preferably ±1%, and even more preferably ±0.1%, to the extent that it is appropriate to perform such variations in the disclosed disclosure.

[0044] Unless otherwise stated, the use of the terms “approximately” or “about” in reference to a particular number or range of numbers is also understood to support such numerical terms or ranges without the term “approximately.” For example, the statement “approximately 30” is interpreted to support not only values ​​slightly above and slightly below 30, but also the actual number 30.

[0045] As used herein, the term “substantially” refers to the complete or near-complete range or extent of a function, feature, characteristic, state, structure, item, or result. For example, an object “substantially” enclosed means that the object is completely enclosed or nearly completely enclosed. The exact acceptable degree of deviation from absolute completeness may, in some cases, depend on the specific context. However, generally speaking, near-complete means having the same overall result as if absolute and complete completeness had been achieved. The use of “substantially” is equally applicable when used in a negative sense to refer to the complete or near-complete absence of a function, structure, characteristic, state, structure, item, or result.

[0046] The terms "wt.%", "vol%", and "mol%" refer to the weight percentage, volume percentage, or mole percentage of an ingredient, respectively, based on the total weight, volume, or total number of moles of the material containing the ingredient.

[0047] References herein may be made to devices, apparatus, structures, systems, or methods that “improve” performance (e.g., increase or decrease results, depending on the context). Unless otherwise stated, such “improvement” is understood to be a measure of benefit obtained based on comparison with devices, apparatus, structures, systems, or methods in the prior art. Furthermore, it should be understood that the degree of performance improvement may vary between the disclosed embodiments, and that the quantity, degree, or uniformity or consistency in the realization of performance improvement is not assumed to be universally applicable.

[0048] The relative terms used herein, such as “left,” “right,” “front,” “back,” “top,” “bottom,” “up,” and “down,” are for illustrative purposes only and are not necessarily intended to describe permanent relative positions. It is understood that such terms are interchangeable under appropriate circumstances, and that embodiments as described herein can operate in orientations other than those illustrated or described herein unless the context clearly indicates otherwise.

[0049] In this specification, objects described as “adjacent” to each other reflect a functional relationship between the objects described. That is, the term indicates that the objects described must be adjacent to each other to perform a specified function, where appropriate to the context in which the phrase is used, and this may be direct (i.e., physical) or indirect (i.e., very close or nearby) contact.

[0050] In this specification, objects described as “connected” or “joined” reflect a functional relationship between the objects described. That is, the term indicates that the objects described must be connected to perform a specified function, where appropriate to the context in which the term is used, and this may be a direct or indirect connection in an electrical or non-electrical (i.e., physical) manner.

[0051] Furthermore, embodiments of the present disclosure may include hardware, software, and electronic components or modules, which may be illustrated and described for the purposes of discussion as if the majority of the components were implemented solely in hardware. However, those skilled in the art will recognize, by reading this detailed description, that in at least one embodiment, the electronic-based aspects of the present disclosure may be implemented in software (e.g., instructions stored on a non-temporary computer-readable medium) executable by one or more processing units, such as microprocessors and / or application-specific integrated circuits. Therefore, it should be noted that multiple hardware and software-based devices, as well as multiple different structural components, may be used to implement the technology of the present disclosure. For example, the “server” and “computing device” described herein may include one or more processing units, one or more computer-readable medium modules, one or more input / output interfaces, and various connections for connecting the components.

[0052] As used herein, the term “semiconductor substrate” may refer to any underlying material or material that can be used to form devices, circuits, or films, or on which devices, circuits, or films can be formed. A “semiconductor substrate” can be continuous or discontinuous, rigid or flexible, solid or porous, or a combination thereof. A semiconductor substrate may include a bulk material such as silicon (e.g., single-crystal silicon), another Group IV material such as germanium, or other semiconductor materials such as Group II-VI or Group III-V semiconductor materials, and may include one or more layers on or beneath the bulk material. Furthermore, the substrate may have various features, such as depressions, protrusions, and the like, formed in or on at least a portion of the layers of the substrate. As an example, a substrate may include a bulk semiconductor material and an insulating or (high-K) dielectric material layer on at least a portion of the bulk semiconductor material.

[0053] The semiconductor substrate may include materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, sapphire, doped or undoped polysilicon, doped or undoped silicon, patterned or unpatterned silicon on an insulator (SOI), carbon-doped silicon oxide, silicon nitride, germanium, gallium arsenide, gallium nitride, glass, or combinations thereof.

[0054] As used in this disclosure, the term “semiconductor device structure” may refer to any part of a processed or partially processed semiconductor structure that is at least a portion of, or includes or defines, active or passive components of a semiconductor device formed on or within a semiconductor substrate. For example, semiconductor device structures may include active and passive components of integrated circuits, such as transistors, memory elements, transducers, capacitors, resistors, conductive wires, conductive vias, and conductive contact pads.

[0055] In this disclosure, “gas” may include materials that are gases at room temperature and pressure (NTP), vaporized solids, and / or vaporized liquids, and may, depending on the context, consist of a single gas or a mixture of gases. Gases other than process gases or purge gases, i.e., gases introduced without passing through (gas) distribution and removal systems, other gas distribution devices, etc., can be used, for example, to seal reaction spaces, and include sealing gases, such as noble gases.

[0056] Where used in this disclosure, “film” and / or “layer” can encompass any continuous or discontinuous structure and material, such as any material deposited by the apparatus and methods disclosed herein. For example, films and / or layers may be two-dimensional materials, three-dimensional materials, nanoparticles, or partial or complete molecular layers, or partial or complete atomic layers, or clusters of atoms and / or molecules, or layers consisting of solitary atoms and / or solitary molecules. Films or layers may include materials or layers having pinholes, which may be continuous or discontinuous.

[0057] The implementations described herein are further described below with reference to apparatus for manufacturing semiconductor devices or substructures thereof. However, it is clear that other systems that benefit from the apparatus configured to perform the periodic deposition etching process described herein may also be adapted to benefit from the implementations described herein. The devices described herein are illustrative and are not intended or construed as limiting the scope of the embodiments described herein.

[0058] One aspect of this disclosure is, - At least one reactor comprising at least one reaction chamber configured to process at least one semiconductor substrate, wherein the semiconductor substrate comprises one or more gap portions, - A metal precursor source configured to provide a vapor of at least one metal precursor containing at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, cobalt, nickel, and mixtures thereof, - An etchant source configured to provide steam for at least one etchant, - A vapor distribution and removal system configured to supply vapors from a metal precursor source and an etchant source to at least one reaction chamber in the reactor, and to remove the vapors from the reaction chamber, - A sequence controller operably connected to a distribution and removal system, comprising a memory containing a program configured to control the flow from a metal precursor source to a reaction chamber by activating the vapor distribution and removal system during one or more deposition cycles, thereby, as a result of the deposition cycles, a metal-containing film is deposited to at least partially fill one or more gaps in a semiconductor substrate, The program is further configured to control the flow from the etchant source to the reaction chamber by activating a vapor distribution and removal system during one or more etching cycles, thereby providing an apparatus in which a metal-containing film undergoes subtractive etching as a result of the etching cycle.

[0059] In other words, the present disclosure generally relates to processing apparatus configured to process semiconductor substrates and, more specifically, to process processes including deposition and etching steps. For example, the apparatus may be particularly suitable for constructing or partially constructing memory devices.

[0060] Advantageously, the sequence controller may be configured to precisely control the introduction and removal of reactive gases during the deposition etching process, which has been found to result in a well-controlled chemical reaction that provides a uniform and reproducible film and other configurations. Furthermore, the sequence controller may adjust the flow rate and introduction timing to further optimize the reaction dynamics.

[0061] Another advantage of the present invention is that the vapor distribution removal system is configured to supply vapors from both the metal precursor source and the etchant source to one or more reaction chambers of the same reactor.

[0062] In certain embodiments, the apparatus may be configured such that the reactor comprises a reactor housing enclosing at least a first reaction chamber, at least a second reaction chamber, and at least a handling chamber configured to transport a semiconductor substrate between the first and second reaction chambers without removing the reactor housing from the reactor, wherein a deposition cycle is carried out in the first reaction chamber, an etching cycle is carried out in the second reaction chamber, and a vapor distribution and removal system is further configured to selectively direct a flow of metal precursor vapor to at least the first reaction chamber and a flow of etchant vapor to at least the second reaction chamber.

[0063] Figure 1 schematically illustrates apparatus 100 according to one embodiment of the present disclosure. Apparatus 100 comprises a reactor 101 including a first reaction chamber 112 and a second reaction chamber 113. Furthermore, apparatus 100 includes a metal precursor source 102, an etchant source 103, optionally one or more reactant sources 104, a purge gas source 105, an exhaust system 106, and a sequence controller 107. The apparatus is configured to carry out the method disclosed herein and / or to manufacture semiconductor devices such as memory devices or substructures thereof.

[0064] The apparatus 100 may further include a storage device for holding semiconductor substrates. For example, the storage device may be a cassette storage carousel designed to store wafer cassettes, each containing multiple semiconductor substrates. The storage device can be operably connected to a substrate handler, such as a robotic arm, configured to transport individual semiconductor substrates or cassettes between the storage device and the reactor 101.

[0065] The reactor 101 may be enclosed within a suitable (reactor) housing that physically houses and separates the first reaction chamber 112 and the second reaction chamber 113. To avoid doubt, the reactor housing specifically refers to a structural enclosure that forms part of the apparatus 100 described herein and is not construed to include a cleanroom or other external environmental enclosure in which the apparatus may be located. This housing configuration forms a closed system or toolset, which is advantageous as it allows both the deposition and etching processes to be carried out within the same apparatus.

[0066] In certain embodiments, the reactor housing is a sealed enclosure specifically designed to house and isolate the first and second reaction chambers from the external environment. The reactor housing may be provided with dedicated access ports or windows for maintenance and material handling, which are designed to prevent contamination and leakage during operation. The reactor housing may also be provided with ports for the controlled delivery and removal of gases, such as those supplied by a metal precursor source, an etchant source, and any reactant source, as well as ports for an exhaust system. The housing may further include integrated seals and barriers to prevent contamination from the external environment, ensuring that internal process conditions remain unaffected by ambient conditions outside the apparatus.

[0067] Unlike a cleanroom, which serves as a general environmental enclosure for housing equipment, the reactor housing is structurally and functionally integrated with the equipment 100. It does not rely on external environmental controls, such as those provided by a cleanroom air filtration system, to maintain the purity of the reaction environment. Instead, the reactor housing incorporates its own environmental control features, such as temperature control, pressure containment, and gas flow management, tailored to the specific requirements of the deposition and etching processes.

[0068] Therefore, the reactor 101 comprises a first reaction chamber 112 and a second reaction chamber 113 for processing the semiconductor substrate without removing it from the reactor, particularly from the (reactor) housing. By utilizing a single reactor, the processing time of the deposition etching deposition process is significantly reduced by eliminating the need to transport the substrate between different reactors or tools, which would otherwise result in significant delays and reduced operational efficiency.

[0069] For example, the reactor 101 may further include components such as insulating material, heating element, temperature sensor, tube, injector, flange, rack, and / or pedestal.

[0070] Apparatus 100 may comprise any number of suitable gas sources 102-105 connected via lines 108-111 to the first reaction chamber 112 and / or the second reaction chamber 113 in reactor 101, which may include flow controllers, valves, heaters, etc. Exhaust 106 may include one or more vacuum pumps. Lines 108-111 and exhaust pipe 106 may be used as a distribution and removal system configured to supply vapors of one or more metal precursors, one or more etchants, and optionally one or more reactants to the first reaction chamber 108 and / or the second reaction chamber 109 in reactor 101, and to remove vapors from the first reaction chamber 112 and / or the second reaction chamber 113 in reactor 101.

[0071] In a non-limiting exemplary setup, a metal precursor source 102, optionally one or more reactant sources 104, and a purge gas source 105 may be connected to a first reaction chamber 112 configured to carry out a deposition cycle. Furthermore, an etchant source 103 and a purge gas source 105 may be connected to a second reaction chamber 113 configured to carry out an etching cycle.

[0072] The metal precursor source 102 may include a container and one or more metal precursors described herein, either alone or in combination with one or more carrier gases (e.g., inert gases).

[0073] The etchant source 103 may include a container and one or more etchants described herein, either alone or in combination with one or more carrier gases (e.g., inert gases).

[0074] An optional reactant gas source 104 may contain a container and one or more reactants described herein, either alone or in combination with one or more carrier gases (e.g., inert gases). For example, the apparatus 100 may comprise a first reactant source containing a container and an oxide reactant, and a second reactant source containing a container and a nitrogen reactant.

[0075] The purge gas source 105 may include one or more inert gases, such as N2 or a noble gas (e.g., argon), as described herein.

[0076] The sequence controller 107 may include electronic circuits and software for selectively operating valves, manifolds, heaters, pumps, and other components included in the apparatus 100. Such circuits and components operate to introduce precursors, reactants, and purge gases from their respective sources 102-105.

[0077] The sequence controller 107 may include memory containing an executable program that can automate specific tasks such as the flow and timing of gas pulse sequences, the temperature of the semiconductor substrate and / or reactor 101, the pressure inside the reactor 101, and various other operations to provide proper operation of the apparatus 100. The sequence controller 107 may further include control software that electrically or pneumatically controls valves to control the flow of precursors, etchants, reactants (e.g., oxide reactants, nitrogen reactants, boron reactants, reducing reactants, phosphorus reactants, carbon reactants, or sulfur reactants), and purge gases into and out of the first reaction chamber 112 and / or second reaction chamber 113 within the reactor 101. The sequence controller 107 may include one or more software and / or hardware components, such as modules, including FPGAs or ASICs, that perform certain tasks. The modules may be advantageously configured to reside on an addressable storage medium of the control system and may be configured to perform one or more processes and to activate distribution and removal systems between deposition and etching processes.

[0078] It will be understood that other configurations of apparatus 100 are possible, including different numbers and types of metal precursors, etchants, reactants, and purge gas sources. It will also be understood that there are various configurations of valves, conduits, metal precursor sources, etchant sources, reactant sources, and purge gas sources that can be used to achieve the goal of selectively supplying vapor into at least one reaction chamber within reactor 101. Furthermore, many components have been omitted from the schematic diagram of the apparatus for the sake of simplicity. Such components may include, for example, various valves, manifolds, purifiers, heaters, vessels, vents, and / or bypasses.

[0079] During the operation of apparatus 100, semiconductor substrates such as wafers (not shown) can be transported by a handler from the storage device to the first reaction chamber 112 and / or the second reaction chamber 113 in reactor 101. Once one or more semiconductor substrates have been transported to at least one reaction chamber, one or more vapors from their respective sources 102-105, such as metal precursors, etchants, reactants, and / or purge gases, can be introduced into the first reaction chamber 112 and / or the second reaction chamber 113 in reactor 101 by distribution and removal systems (106, and 108-111) operably connected to the sequence controller 107.

[0080] Advantageously, it has been found herein that the apparatus configured schematically shown in Figure 1 can carry out the deposition of a metal-containing film and subsequent etching of this film within the same reactor without requiring additional specialized equipment. This thus results in a cost-effective technique that can reduce overall processing time.

[0081] In an alternative configuration, and in other embodiments, the apparatus may be configured to include a reactor housing that encloses a single reaction chamber, the deposition cycle and etching cycle being carried out within the reaction chamber, and a vapor distribution and removal system further configured to selectively direct and remove flows of metal precursor vapor and etching vapor into the reaction chamber.

[0082] Furthermore, those skilled in the art will recognize that the configuration of the apparatus schematically shown in Figure 1 can be readily adapted to include a reactor housing having three or more reaction chambers as described herein, such as three, four, five, or more chambers. This expansion remains within the scope of the disclosure, provided that the reactor incorporates a transport system, such as a handling chamber, configured to transport the semiconductor substrate between two or more reaction chambers without removing the semiconductor substrate from the reactor, particularly the reactor housing.

[0083] Figure 2 schematically shows an apparatus 200 according to another embodiment of the present disclosure. The apparatus comprises a reactor 201 including a first reactor 201, a metal precursor source 202, an etchant source 203, optionally one or more reactant sources 204, a purge gas source 205, an exhaust pipe 206, and a sequence controller 207. The apparatus 200 may be used to carry out the methods disclosed herein and / or to form semiconductor devices such as memory devices or substructures thereof.

[0084] The reactor 201 may be provided with a suitable (reactor) housing for enclosing a single reaction chamber. This configuration forms a closed system or toolset.

[0085] Therefore, the reactor 201 is provided with a single reaction chamber 212 for processing the semiconductor substrate without removing it from the reactor, particularly from a single reaction chamber. By utilizing a single reaction chamber, the need to transport the substrate between different reaction chambers is eliminated, significantly reducing the processing time of the deposition etching process, which would otherwise result in significant delays and decreased operational efficiency.

[0086] The apparatus 200 may further include storage equipment for storing semiconductor substrates, such as a cassette storage carousel configured for storing wafer cassettes, each containing multiple semiconductor substrates. The storage equipment may be connected to a handler, such as a substrate handling robot, configured to transport individual semiconductor substrates or cassettes between the storage equipment and the reactor 201.

[0087] The reactor 201 may further comprise components such as insulating material, heating element, temperature sensor, tube, injector, flange, rack, and / or pedestal.

[0088] The apparatus 200 may comprise any number of preferred gas sources 202-205, each connected to a reaction chamber 212 in reactor 201 via lines 208-211, each of which may include flow controllers, valves, heaters, and the like. The exhaust pipe 206 may comprise one or more vacuum pumps. Lines 208-211 and the exhaust pipe 206 may be used as a distribution and removal system configured to supply vapors of one or more metal precursors, one or more etchants, and optionally one or more reactants to at least one reaction chamber in reactor 201 and to remove vapors from at least one reaction chamber in reactor 201.

[0089] In a non-limiting exemplary setup, a metal precursor source 202, one or more optional reactant sources 204, and a purge gas source 205 may be connected to a reaction chamber 212 configured to carry out a deposition cycle. Furthermore, an etchant source 203 and a purge gas source 205 may be connected to a reaction chamber 212 configured to carry out an etching cycle. Advantageously, this configuration offers that both the deposition and etching processes can be carried out within the same single reaction chamber without the need to transport the semiconductor substrate to other reaction chambers or specialized equipment.

[0090] The metal precursor source 202 may include a container and one or more metal precursors described herein, either alone or in combination with one or more carrier gases (e.g., inert gases).

[0091] The etchant source 203 may include a container and one or more etchants described herein, either alone or in combination with one or more carrier gases (e.g., inert gases).

[0092] An optional reactant source 204 may include one or more containers and one or more reactants described herein, either alone or in combination with one or more carrier (e.g., inert) gases. For example, the apparatus 200 may comprise a first reactant source containing a container and an oxide reactant, and a second reactant source containing a container and a nitrogen reactant.

[0093] The purge gas source 205 may include one or more inert gases, such as N2 or a noble gas (e.g., argon), as described herein.

[0094] The sequence controller 207 may include electronic circuits and software that selectively operate valves, manifolds, heaters, pumps, and other components included in the apparatus 200. Such circuits and components operate to introduce precursors, reactants, and purge gases from their respective sources 202-205.

[0095] The sequence controller 207 may include memory containing executable programs that can automate specific tasks such as the flow and timing of gas pulse sequences, the temperature of the semiconductor substrate and / or reactor 201, the pressure within the reactor 201, and various other operations to provide proper operation of the apparatus 200. The sequence controller 207 may further include control software that electrically or pneumatically controls valves to control the flow of precursors, etchants, reactants (e.g., oxide reactants, nitrogen reactants, boron reactants, reducing reactants, phosphorus reactants, carbon reactants, or sulfur reactants), and purge gases into and out of the reaction chamber 212 within the reactor 201. The sequence controller 207 may include one or more software and / or hardware components, such as modules, including FPGAs or ASICs, that perform certain tasks. The modules may be advantageously configured to reside on an addressable storage medium of the control system and may be configured to perform one or more processes and to initiate distribution and removal systems between deposition and etching processes.

[0096] Furthermore, other configurations of the apparatus 200 are possible, comprising different numbers and types of metal precursors, etchants, reactants, and purge gas sources. It will also be understood that the configurations of valves, conduits, metal precursor sources, etchant sources, reactant sources, and purge gas sources can vary to achieve the goal of selectively feeding vapor into at least one reaction chamber within the reaction chamber 201. Moreover, many components have been omitted from the schematic diagram of the apparatus for the sake of simplicity. Such components may include, for example, various valves, manifolds, purifiers, heaters, vessels, vents, and / or bypasses.

[0097] During the operation of apparatus 200, semiconductor substrates such as wafers (not shown) can be transported by a handler from the storage device to the reaction chamber 212 in reactor 201. Once one or more semiconductor substrates have been transported to the reaction chamber 212, one or more vapors from their respective sources 202-205, such as metal precursors, etchants, reactants, and / or purge gases, can be introduced into the reaction chamber 212 by distribution and removal systems 206 and 208-211, which are operably connected to the sequence controller 207.

[0098] Advantageously, it has been found herein that the apparatus configured schematically shown in Figure 2 can perform the deposition of a metal-containing film and subsequent etching of this film within the same reaction chamber without requiring additional specialized equipment. Specifically, the apparatus can perform both (1) periodic deposition-etching deposition (etching decomposition) in which each deposition cycle forms a portion of the intended film thickness, and (2) deposition of the entire intended film thickness followed by etching. The periodic deposition-etching deposition process can be carried out entirely within a single reaction chamber, improving throughput by eliminating the need for substrate transport during processing. Thus, it results in a cost-effective and versatile technology that can reduce overall processing time while accommodating different manufacturing workflows.

[0099] Furthermore, those skilled in the art will recognize that the configuration of the apparatus schematically illustrated in Figure 2 can be readily adapted to include a reactor housing having two, three, four, or more reaction chambers. This expansion is within the scope of the disclosure, provided that at least one reaction chamber maintains a single reaction chamber configuration according to the embodiment shown in Figure 2. For example, the reactor may comprise two or more reaction chambers as described herein, such as three reaction chambers, four reaction chambers, etc., each reaction chamber enabling the processing of semiconductor substrates in the aforementioned single reaction chamber.

[0100] At least one reactor in this apparatus may be a CVD reactor equipped with suitable apparatus and means for supplying precursors, reactants, and etchants, as well as any suitable system for processing semiconductor substrates, such as an ALD reactor. According to some embodiments, a showerhead reactor may be used. According to some embodiments, a cross-flow, batch, mini-batch, or space ALD reactor may be used.

[0101] In some embodiments, the apparatus may include a vertical furnace as a single reactor. In other embodiments, the apparatus may include a vertical furnace as a first reactor and further include a second reactor. In other embodiments, the apparatus may include a vertical furnace as a first reactor and further include a vertical furnace as a second reactor.

[0102] A vertical furnace operates in a vertical configuration to optimize space utilization, enhance heat treatment uniformity, and enable precise control of environmental conditions. At least one reaction chamber of the vertical furnace (e.g., a vertically oriented cylindrical or tubular structure) may, advantageously, be configured to simultaneously accept and process multiple semiconductor substrates. The reaction chamber may be fabricated from a heat-resistant material such as silicon carbide, silicon, or quartz, and is typically enclosed to create a controlled, inert environment for processing the reaction. Process gases, such as precursor gases, reactant gases, etching gases, cleaning gases, and purging gases, may be supplied to the reaction chamber via one or more injectors.

[0103] In some embodiments, the apparatus may comprise a vertical furnace having a first reaction chamber and a second reaction chamber, which may have a vertically oriented cylindrical or tubular structure. In other embodiments, the apparatus may comprise a vertical furnace having a single reaction chamber which may have a vertically oriented cylindrical or tubular structure.

[0104] The vertical furnace may further comprise carriers constructed and arranged to hold semiconductor substrates, preferably in a vertically stacked configuration. Suitable carriers include boats designed to vertically hold multiple semiconductor substrates in a stacked configuration. The vertical furnace may further comprise a boat elevator designed to raise and lower the boats in and out of at least one reaction chamber within the vertical furnace. A loading station or substrate handler may be connected to the vertical furnace to load the substrates into the boats before insertion into the furnace.

[0105] A vertical furnace may further include a heating element typically arranged around the outer periphery of at least one reaction chamber to provide uniform heat.

[0106] In a preferred embodiment, the apparatus of the present disclosure may be designed such that one or more of the at least one reactor is a vertical furnace comprising at least one reaction chamber configured to simultaneously receive and process a plurality of semiconductor substrates.

[0107] In certain embodiments, the apparatus of the present disclosure may be designed to further include a heating means configured to supply a temperature of 200°C to 800°C into at least one reaction chamber, and / or a pressure regulating mechanism configured to supply a pressure of 0.2 Torr to 200 Torr into the reaction chamber.

[0108] Figure 8 shows a schematic diagram of an exemplary vertical furnace system 900 according to one embodiment of the present disclosure. The system is designed for processing semiconductor substrates, such as semiconductor wafers, in a high-temperature reaction chamber through automated substrate processing.

[0109] The vertical furnace system 900 includes a cassette transfer port 910 that serves as an entry point for introducing cassettes 950 containing semiconductor substrates into the system 900. Adjacent to the cassette transfer port 910 is a cassette handling chamber 920 in which cassettes containing semiconductor substrates are temporarily stored and prepared for further handling within the system.

[0110] The cassette 950 can be included as a FOUP (Front Opening Unified Pod) configured to dock at the substrate transport port 930, enabling safe and controlled access to the substrate for subsequent processing. The substrate handling chamber 940 is located adjacent to the substrate transport port 930 and provides a clean and isolated environment for substrate transport.

[0111] The cassette 950 is moved within the cassette handling chamber 920 by a cassette handling robot 960. This robot 960 may include a robotic arm configured to transport the cassette between the cassette handling chamber 920 and the substrate handling chamber 940.

[0112] Within the substrate handling chamber 940, the substrate handling robot 970 facilitates the transfer of individual substrates from the cassette 950 to the boat 980, which is designed to firmly hold the substrates vertically for processing.

[0113] Vertically above the boat 980 is a reaction chamber 990 in which high-temperature processes such as chemical vapor deposition (CVD) or thermal oxidation are carried out. The reaction chamber 990 is insulated and configured to maintain the precise environmental conditions necessary for processing semiconductor substrates. The reaction chamber 990 may be configured according to any of the embodiments described herein and may incorporate features detailed with reference to those embodiments.

[0114] In the context of this disclosure, a semiconductor substrate is provided that includes one or more gap features. As used in this disclosure, the term “gap feature” may mean an opening or recess located between two surfaces of a non-planar surface. The term “gap feature” may mean an opening or recess located between the inclined sidewalls of two projections extending perpendicularly from the surface of the semiconductor substrate, or between the opposing inclined sidewalls of a notch extending perpendicularly into the surface of the substrate, and such a gap feature may be referred to as a “vertical gap feature.” The term “gap feature” may also mean an opening or recess located between two opposing substantially horizontal surfaces, where the horizontal surfaces connect the horizontal opening or recess, and such a gap feature may be referred to as a “horizontal gap feature.”

[0115] In certain embodiments, one or more gaps are predetermined trenches or slots in a memory cell. For example, in the context of a memory device, one or more gaps may include or form part of individual word lines or word line separators.

[0116] In some embodiments, the semiconductor substrate may further include metallic materials and metallic surfaces, such as, but not limited to, pure metals, metal nitrides, metal carbides, metal borides, and combinations or mixtures thereof.

[0117] The apparatus described herein is configured such that the deposition cycle allows for the partial filling of one or more gaps with a metal-containing film comprising at least one metal selected from the group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), and mixtures thereof.

[0118] In certain embodiments, the metal precursor is a metal halide, metal chalcogenized halide, or metal-organic precursor as further defined herein.

[0119] The apparatus described herein is further configured so that a deposited metal-containing film can undergo subtractive etching as a result of an etching cycle. As used herein, the term “subtractive etching” generally refers to a material removal process used in semiconductor manufacturing to (further) precisely define or shape feature areas of a semiconductor substrate or deposited material layer by selectively removing undesirable material. Subtractive etching may be used to form feature areas such as trenches, vias, or isolated components in a semiconductor device or a partially fabricated semiconductor device. For example, in the context of a memory device, subtractive etching may include cutting a portion of a word line metal embedding, thereby separating each word line from its adjacent word lines.

[0120] In certain embodiments, the etchant comprises one or more halogen-containing etching compounds.

[0121] In certain embodiments, the etchant may be fluorine gas (F2), chlorine gas (Cl2), bromine gas (Br2), quaternary ammonium fluoride, quaternary ammonium chloride, quaternary ammonium bromide, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), tetrafluoroboric acid (HBF4), tetrachloroboric acid (HBCl4), tetrabromoboric acid (HBBr4), hexafluorosilicic acid (H2SiF6), hexachlorosilicic acid (H2SiCl6), hexabromosilicic acid (H2SiBr6), tetrabutylammonium tetrafluoroborate, hexafluorozirconate (H2ZrF6), or hexafluorotitanic acid (H2TiF6). The etching compound comprises one or more halogen-containing etchants selected from the group consisting of hexafluorophosphate (HPF6), molybdenum pentachloride (MoCl5), tungsten pentachloride (WCl5), ammonium hexafluorosilicate [(NH4)2SiF6], ammonium hexachlorosilicate [(NH4)2SiCl6], ammonium hexabromosilicate [(NH4)2SiBr6], ammonium hexafluorotiatate [(NH4)2TiF6], ammonium hexachlorotiatate [(NH4)2TiCl6], ammonium hexabromotiatate [(NH4)2TiBr6], thionyl chloride (SOCl2), and mixtures thereof.

[0122] Another aspect of this disclosure provides a method for at least partially fabricating a semiconductor device or a substructure of a semiconductor device, the method is a) To provide at least one semiconductor substrate having one or more gap portions in a reactor having at least one reaction chamber, b) Performing one or more deposition cycles in a reaction chamber, each cycle comprising a metal precursor pulse, wherein at least a portion of a semiconductor substrate is contacted by at least one metal precursor by introducing at least one metal precursor into the reactor, the at least one metal precursor comprising at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, and mixtures thereof, and as a result of the cycle, a metal-containing film is deposited such that it at least partially fills one or more gaps in the semiconductor substrate. c) Performing one or more etching cycles in a reaction chamber, each cycle comprising an etchant pulse, wherein at least a portion of the metal-containing film is contacted by at least one etchant by introducing at least one etchant into the reactor, thereby, as a result of the cycle, the metal-containing film undergoes subtractive etching.

[0123] It will be apparent that a preferred embodiment of a device according to one aspect of the present disclosure and related advantages also constitute a preferred embodiment of a method for manufacturing a partially semiconductor device according to one aspect of the present disclosure, and vice versa.

[0124] One or more methods disclosed herein generally relate to the formation of configurations for semiconductor devices having specific electronic properties. In particular, the method provides for the deposition of a metal-containing film onto a semiconductor substrate including one or more gaps (e.g., a predetermined trench), also known as wordline metal filling in the context of memory devices, followed by subtractive etching to remove excess metal-containing film and shape the structure into a desired pattern.

[0125] In some embodiments, the formed configuration may function as individual phrases or electrical connections for dealing with and programming memory cells.

[0126] In this disclosure, the terms “deposition” or “periodic deposition process” refer to the process of depositing layers onto a substrate by continuously introducing precursors (and / or reactants) into a reaction chamber, and include processing techniques such as atomic layer deposition (ALD), periodic chemical vapor deposition (periodic CVD), and hybrid periodic deposition processes such as ALD components and periodic CVD components. Typically, one deposition cycle may form a metal-containing film or layer of about 0.10 nm. However, experimental thicknesses may vary depending on the quantity and type of cycles, as well as the available reaction sites on the semiconductor substrate.

[0127] In some embodiments, the metal-containing film may have a growth rate of about 0.01 nm or less per cycle of one or more precursors, optionally one or more reactive gases, and one or more purge (e.g., inert carrier) gases.

[0128] The term "atomic layer deposition" (ALD) may refer to a vapor deposition process in which a deposition cycle, typically multiple consecutive deposition cycles, are carried out within a reactor. As used herein, the term atomic layer deposition also means to include processes designated by related terms such as chemical vapor deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy, when carried out using alternating pulses of one or more precursor / periodic reactive gases and periodic purge (e.g., inert carrier) gases.

[0129] In a preferred embodiment, the method includes a periodic deposition process as part of an atomic layer deposition (ALD) process.

[0130] In the ALD process, during each cycle, a precursor (e.g., a metal precursor) is generally introduced into the reactor and chemisorbed onto the deposition surface (e.g., a semiconductor substrate surface, which may contain deposited material from a previous ALD cycle or other materials) to form a material that does not readily react with other precursors (i.e., exhibits self-controlled reactions), such as a monolayer or partial monolayer of a material, several monolayers of a material, or multiple monolayers of a material. Subsequently, in some cases, a reactant (e.g., another precursor or reactant gas) may be introduced into the reactor to be used to convert the chemisorbed precursor into a desired material on the deposition surface. The reactant can further react with the precursor. Note that, as used in this disclosure, the ALD process does not necessarily consist of a sequence of self-controlled surface reactions.

[0131] Optionally, a purging step can be utilized during one or more iterations, for example, between each deposition cycle and / or etching cycle, to remove any excess metal precursor from the reactor and / or any excess reactants and / or reaction byproducts from the reactor. As used herein, the term “purging” may refer to a procedure in which an inert gas or substantially inert gas is supplied to the reactor between two pulses of gases reacting with each other. For example, a purge using an inert gas, such as a noble gas, may be provided between the metal precursor pulse and the reactant pulse, thus avoiding, or at least minimizing, gas-phase interactions between the metal precursor and the reactants.

[0132] Optionally, prior to deposition, the method may provide a pre-cleaning step to remove any impurities from at least one reaction chamber and / or the semiconductor substrate being processed.

[0133] Advantageously, the periodic deposition processes disclosed herein may be thermal deposition processes. In other words, in some embodiments, neither pulsed nor purged plasma is employed in the periodic deposition process.

[0134] A periodic deposition process comprising one or more deposition cycles described herein may include heating a semiconductor substrate to a desired deposition temperature. In some embodiments of this disclosure, the semiconductor substrate may be heated to a temperature below about 800°C. For example, and in some embodiments, the semiconductor substrate may be heated to a temperature between approximately 20°C and approximately 800°C, or below approximately 650°C, or below approximately 600°C, or between approximately 200°C and approximately 600°C, or between approximately 200°C and approximately 550°C, or between approximately 200°C and approximately 500°C, or between approximately 200°C and approximately 450°C. In some cases, the temperature of the semiconductor substrate may remain substantially constant during a periodic etching process comprising one or more etching cycles. In other configurations, and in some cases, the temperature of the semiconductor substrate may be lower during a periodic etching process comprising one or more etching cycles.

[0135] In addition to controlling the temperature of the semiconductor substrate, the pressure inside the reactor may also be adjusted. For example, in some embodiments, the pressure inside the reactor in one or more of the above steps may be less than 760 Torr, or about 0.2 to about 200 Torr, about 0.5 to about 50 Torr, or about 0.5 to about 20 Torr.

[0136] In some embodiments, the periodic deposition process employs plasma-enhanced deposition techniques. For example, the periodic deposition process may include plasma-enhanced atomic layer deposition and / or plasma-enhanced chemical deposition. In such cases, one of the pulses in the periodic deposition process may include generating plasma in a reactor.

[0137] In some embodiments, the methods disclosed herein may be a continuous vacuum deposition process or a continuous vacuum deposition etching process.

[0138] A continuous vacuum deposition process may involve depositing a material (e.g., a metal-containing film) onto a semiconductor substrate in a reactor without introducing atmospheric pressure or interruptions that could disrupt a controlled vacuum environment. This process involves maintaining a consistent vacuum pressure within the reactor. In certain embodiments, the methods disclosed herein provide that the metal-containing film is formed without any intervening vacuum disruption. The advantage of avoiding intervening vacuum disruption is that it prevents the need for repeated discharge and purging, which is common in conventional batch deposition methods.

[0139] A continuous vacuum deposition etching process may include depositing a material (e.g., a metal-containing film) onto a semiconductor substrate in a reactor, and then etching portions of the deposited material without introducing air or interrupting the controlled vacuum environment. This process involves maintaining a consistent vacuum pressure within at least one reaction chamber. The advantage of avoiding vacuum breakage during metal-containing film deposition and etching is that it prevents the need for repeated discharge, purging, and / or removal of the semiconductor substrate from the apparatus, which is common in conventional batch approaches.

[0140] In certain embodiments, the methods disclosed herein provide that the formation of a metal-containing film may be configured to include at least one deposition cycle, at least two deposition cycles, at least five deposition cycles, at least ten deposition cycles, at least twenty deposition cycles, at least forty deposition cycles, at least one hundred deposition cycles, at least two hundred deposition cycles, at least four hundred deposition cycles, at least six hundred deposition cycles, or at least one thousand deposition cycles. In some embodiments, the process may be repeated for at least one deposition cycle to a maximum of one thousand deposition cycles, or at least two deposition cycles to a maximum of one hundred deposition cycles, or at least five deposition cycles to a maximum of five hundred deposition cycles.

[0141] The deposition cycle may include one or more pulses. In some embodiments, at least one pulse is accompanied by a self-controlled surface reaction. In some embodiments, all pulses are accompanied by a self-controlled surface reaction. In the context of ALD, a self-controlled surface reaction refers to a chemical reaction that automatically stops or slows down when a certain threshold or coverage is reached on the surface, for example, when a complete monolayer or sub-monolayer is formed, by preventing further reaction with additional metal precursors.

[0142] In some embodiments, the deposition cycle may include one or more metal precursor pulses and / or optionally one or more reactant pulses.

[0143] In some embodiments, an etching cycle may follow a deposition cycle, followed by another deposition cycle. Preferably, these deposition-etching deposition processes are carried out within the same reaction chamber without any transfer to another reaction chamber. This is advantageous because time-consuming transfers between reaction chambers can be avoided, thus reducing processing time.

[0144] In alternative embodiments, the deposition cycle may be carried out in a first reaction chamber, while the etching cycle may be carried out in a second reaction chamber. The semiconductor substrate is then transported from the first reaction chamber to the second reaction chamber by a suitable handler (robot). Preferably, the first and second reaction chambers are enclosed within a single reactor, particularly within the same reactor housing that encloses the first and second reaction chambers.

[0145] In some embodiments, one or more metal precursor pulses are sustained for at least 0.01 seconds to a maximum of 120 seconds, or at least 0.01 seconds to a maximum of 0.1 seconds, or at least 0.01 seconds to a maximum of 0.02 seconds, or at least 0.02 seconds to a maximum of 0.05 seconds, or at least 0.05 seconds to a maximum of 0.1 seconds, or at least 0.1 seconds to a maximum of 20 seconds, or at least 0.1 seconds to a maximum of 0.2 seconds, or at least 0.2 seconds to a maximum of 0.5 seconds, or at least 0.5 seconds to a maximum of 1.0 seconds, or at least 1.0 seconds to a maximum of 2.0 seconds, or at least 2.0 seconds to a maximum of 5.0 seconds, or at least 5.0 seconds to a maximum of 10.0 seconds, or at least 10.0 seconds to a maximum of 20.0 seconds.

[0146] In some embodiments, one or more optional reactant pulses are sustained for at least 0.1 seconds to a maximum of 20 seconds, or at least 0.1 seconds to a maximum of 0.2 seconds, or at least 0.2 seconds to a maximum of 0.5 seconds, or at least 0.5 seconds to a maximum of 1.0 seconds, or at least 1.0 seconds to a maximum of 2.0 seconds, or at least 2.0 seconds to a maximum of 5.0 seconds, or at least 5.0 seconds to a maximum of 10.0 seconds, or at least 10.0 seconds to a maximum of 20.0 seconds, or at least 20.0 seconds to a maximum of 120.0 seconds, or at least 20.0 seconds to a maximum of 50.0 seconds, or at least 50.0 seconds to a maximum of 80.0 seconds, or at least 80.0 seconds to a maximum of 120.0 seconds.

[0147] In some embodiments, one or more etchant pulses last for at least 0.1 seconds to a maximum of 20 seconds, or at least 0.1 seconds to a maximum of 0.2 seconds, or at least 0.2 seconds to a maximum of 0.5 seconds, or at least 0.5 seconds to a maximum of 1.0 seconds, or at least 1.0 seconds to a maximum of 2.0 seconds, or at least 2.0 seconds to a maximum of 5.0 seconds, or at least 5.0 seconds to a maximum of 10.0 seconds, or at least 10.0 seconds to a maximum of 20.0 seconds, or at least 20.0 seconds to a maximum of 120.0 seconds, or at least 20.0 seconds to a maximum of 50.0 seconds, or at least 50.0 seconds to a maximum of 80.0 seconds, or at least 80.0 seconds to a maximum of 120.0 seconds.

[0148] In some cases, the term “precursor” in this disclosure may refer to a compound involved in a chemical reaction that produces another compound, particularly a compound that constitutes a membrane matrix or the main backbone of a membrane. The “metal precursor” as described in this disclosure may generally refer to a compound involved in a chemical reaction that produces a metal-containing film as disclosed herein.

[0149] In the context of this disclosure, at least one metal precursor comprises at least one metal (element) selected from the group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), and mixtures thereof. The metal precursor may include, for example, a molybdenum precursor, a tungsten precursor, a ruthenium precursor, a cobalt precursor, a nickel precursor, or a mixture thereof. Preferably, at least one metal precursor comprises one or more molybdenum (Mo) precursors for generating a molybdenum-containing film.

[0150] Naturally, this deposition etching method is not limited to the production of a single film or layer of one type of material, but may include several combinations, such as two, three, four, five, six, seven, eight, nine, ten, or more metal-containing films.

[0151] In non-limiting exemplary embodiments, molybdenum-containing films and tungsten-containing films may be manufactured. Alternatively, the first molybdenum-containing film and the second molybdenum-containing film may be manufactured having different shapes and / or thicknesses.

[0152] In another non-limiting exemplary embodiment, a first metal-containing film (e.g., a first molybdenum-containing film) may be deposited, followed by subtractive etching, and then a second metal-containing film (e.g., a second molybdenum-containing film) may be deposited, followed optionally by subtractive etching.

[0153] In preferred embodiments, the metal precursor is a metal halide, a metal chalcogenized halide, or a metal-organic precursor. Suitable metal-organic precursors may include cyclopentadienyl, amide, amine, imide, amidinate, alkyl, alkoxide, diketonate, and / or diazabutadiene ligands.

[0154] Examples of molybdenum precursors include halide molybdenum precursors. As used herein, the term “halide molybdenum precursor” generally refers to a compound containing at least a molybdenum component and a halide component, the halide component may contain one or more of the following: a chlorine component, a bromine component, or an iodine component. As a non-limiting example, the halide molybdenum precursor may include at least one of the following: molybdenum pentachloride (MoCl5), molybdenum tetrachloride (MoCl4), molybdenum hexachloride (MoCl6), molybdenum trichloride (MoCl3), molybdenum dichloride (MoCl2), molybdenum pentabromide (MoBr5), molybdenum tetrabromide (MoBr4), molybdenum hexabromide (MoBr6), molybdenum tribromide (MoBr3), molybdenum dibromide (MoBr2), molybdenum pentaiodide (MoI5), molybdenum tetraiodide (MoI4), molybdenum hexiodide (MoI6), molybdenum triiodide (MoI3), or molybdenum diiodide (MoI2). In some embodiments, the halide molybdenum precursor may include chalcogenized molybdenum, and in certain embodiments, the halide molybdenum precursor may include molybdenum chalcogenide halide. For example, the molybdenum chalcogenide halide precursor may include oxyhalogenated molybdenum, selected from the group including molybdenum oxychloride, molybdenum oxyiodide, or molybdenum oxybromide. In certain embodiments of the present disclosure, the halide molybdenum precursor may include, but is not limited to, molybdenum oxychloride, including molybdenum(V) trichloride oxide (MoOCl3), molybdenum(VI) tetrachloride oxide (MoOCl4), or molybdenum(VI) dichloride dioxide (MoO2Cl2). As an additional or alternative configuration, the molybdenum precursor may include organometallic molybdenum precursors, such as Mo(CO)6, Mo(tBuN)2(NMe2)2, Mo(NBu)2(StBu)2, (Me2N)4Mo, or (iPrCp)2MoH2.

[0155] Examples of tungsten precursors include tungsten halogen precursors. As used in this disclosure, the term “tungsten halogen precursor” refers to a precursor comprising at least a tungsten component and a halide component, the halide component may comprise one or more of a chlorine component, a bromine component, or an iodine component. In non-limiting examples, tungsten halogen precursors may comprise at least one of tungsten pentachloride (WCl5), tungsten tetrachloride (WCl4), tungsten trichloride (WCl3), tungsten dichloride (WCl2), tungsten pentabromide (WBr5), tungsten tetrabromide (WBr4), tungsten tribromide (WBr3), tungsten dibromide (WBr2), tungsten pentaiodide (WI5), tungsten tetraiodide (WI4), tungsten triiodide (WI3), or tungsten diiodide (WI2). In some embodiments, the tungsten halogen precursor may include chalcogenized tungsten, and in certain embodiments, the tungsten halogen precursor may include chalcogenized tungsten. For example, the chalcogenized tungsten halogen precursor may include oxyhalogenated tungsten, selected from the group including tungsten oxychloride, tungsten oxyiodide, or tungsten oxybromide. As an additional or alternative configuration, the tungsten precursor may include cyclopentadienyl compounds of tungsten, tungsten β-diketonate compounds, tungsten alkylamine compounds, tungsten amidine compounds, or other metal organotungsten compounds. In some embodiments, the organometallic tungsten precursor may include bis(tert-butylimino)bis(tert-butylamino)tungsten(VI), bis(isopropylcyclopentadienyl)tungsten(IV) dihydrogenate, or tetracarbonyl(1,5-cyclooctadiene)tungsten(0).

[0156] Exemplary ruthenium precursors include at least one of ruthenium tetroxide (RuO4), bis(cyclopentadienyl)ruthenium(II), bis(ethylcyclopentadienyl)ruthenium(II), and tolruthenium.

[0157] Examples of cobalt precursors include metal-organocobalt precursors such as cyclopentadienyl cobalt compounds, β-diketonate cobalt compounds, or amidate cobalt compounds or other metal-organocobalt compounds. In some embodiments, the organometallic cobalt precursor may be selected from the group consisting of bis(acetylacetonate)cobalt(II), bis(ethylcyclopentadienyl)cobalt(II), bis(2,2,6,6-tetramethyl-3,5-heptanedionato)cobalt(II), bis(1,4-di-tert-butyl-1,3-diazabutadiene)cobalt(II), or bis(N-tert-butyl-N'-ethylpropanimidoamidato)cobalt(II). Alternatively, cobalt halides such as cobalt chloride, cobalt bromide, or cobalt iodide may be used.

[0158] Exemplary nickel precursors include nickel β-diketonate compounds, nickel β-dikethyminate compounds, nickel amidate compounds, nickel cyclopentadienyl compounds, nickel carbonyl compounds, and combinations thereof. Nickel precursors may also contain one or more halide ligands. In preferred embodiments, the precursor is a nickel β-diketonate compound, such as bis(4-N-ethylamino-3-penten-2-N-ethyliminato)nickel(II)[Ni(EtN-EtN-pento)2], nickel ketoimate, bis(3Z)-4-n-butylamino-penta-3-en-2-one-nickel(II), nickel amidate compounds, such as methylcyclopentadienyl-isopropylacetamidinate-nickel(II), nickel β-diketonate compounds, such as Ni(acac)2, Ni(thd)2, or nickelcyclopentadienyl compounds, such as Ni(cp)2, Ni(Mecp)2, Ni(Etcp)2 or derivatives thereof, such as methylcyclopentadienyl-isopropylacetamidinate-nickel(II). In a more preferred embodiment, the precursor is bis(4-N-ethylamino-3-pentene-2-N-ethyliminato)nickel(II).

[0159] At least one of the deposition cycles may further include a reactant pulse, in which at least a portion of the semiconductor substrate is contacted by at least one reactant by introducing at least one reactant into the reactor. Preferably, the at least one reactant is selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reducing reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

[0160] Examples of oxide reactants include H2O, O2, O3, H2O2, N2O, NO2, and N2O. 4、 Examples include pyridine N-oxide and O2 plasma, or mixtures thereof.

[0161] Examples of nitrogen reactants include NH3, N2H4, tert-butylhydrazine, 1,1-dimethylhydrazine, methylhydrazine, phenylhydrazine, tert-butylamine, isobutylamine, tert-pentylamine, N2 plasma, NH3 plasma, and N2 / H2 plasma, or mixtures thereof.

[0162] Examples of boron reactants include BH3, B2H6, and B 10 H 14 Examples include BF3, BCl3, BBr3, BI3, B(CH3)3, B(CH2CH3)3, B(OCH3)3, B[N(CH3)2]3, BH3[S(CH3)2], borazine, trichloroborazine, ammonia borane, trimethylamine-borane, triethylamine-borane, pyridine-borane, dimethylamine-borane, 2-picoline-borane, tert-butylamine-borane, tetrahydrofuran-borane, and pinacolborane, or mixtures thereof.

[0163] Examples of reducing reaction substances include H2, H2 plasma, N2 / H2 plasma, N2H4, tert-butylhydrazine, 1,1-dimethylhydrazine, formic acid, formalin, pincolborane, B2H6, B 10 H 14 Examples include BH3[S(CH3)2], ammonia-borane, trimethylamine-borane, triethylamine-borane, pyridine-borane, dimethylamine-borane, 2-picoline-borane, tert-butylamine-borane, tetrahydrofuran-borane, pinacol-borane, silane, disilane, trisilane, bis(diethylamino)silane, diisopropylaminosilane, and cyclohexadiene, or mixtures thereof.

[0164] Examples of phosphorus reactants include phosphine (PH3), phosphorus halides, phosphorus oxyhalides, organophosphates, organophosphates, aminophosphines, alkylphosphines, and silylphosphines, or mixtures thereof.

[0165] Examples of carbon reactants include H2, H2 plasma, N2 / H2 plasma, iodomethane, diiodomethane, iodoethane, 1,2-diiodoethane, bromoethane, 1,2-dibromoethane, bromobenzene, iodobenzene, 1-bromobutane, 1-iodobutane, dicyclopentadiene, acetylene, propargyl chloride, propargyl bromide, propargyl iodide, allyl chloride, allyl bromide, allyl iodide, and cyclohexadiene, or mixtures thereof.

[0166] Examples of sulfur reactants include H2S, S8, S2Cl2, tert-butylthiol, bis(trimethylsilyl) sulfide, 1,2-ethanedithiol, dimethyl disulfide, diethyl disulfide, di-tert-butyl disulfide, and carbon disulfide, or mixtures thereof.

[0167] As used herein, the terms etching, periodic etching, or periodic etching process refer to the sequential introduction of an etchant into a reactor to define or form feature areas of a semiconductor substrate or deposited material layer by selectively removing undesirable material.

[0168] In certain embodiments, the methods disclosed herein provide that etching of a deposited metal-containing film may be configured to include at least one etching cycle, at least two etching cycles, at least five etching cycles, at least ten etching cycles, at least 20 etching cycles, at least 40 etching cycles, at least 100 etching cycles, at least 200 etching cycles, at least 400 etching cycles, at least 600 etching cycles, or at least 1000 etching cycles. In some embodiments, these steps may be repeated in increments of at least one etching cycle to a maximum of 1000 etching cycles, or at least two etching cycles to a maximum of 100 etching cycles, or at least five etching cycles to a maximum of 50 etching cycles. Each etching cycle may include one or more etchant pulses.

[0169] In some embodiments, one or more etchant pulses last for at least 0.1 seconds to a maximum of 20 seconds, or at least 0.1 seconds to a maximum of 0.2 seconds, or at least 0.2 seconds to a maximum of 0.5 seconds, or at least 0.5 seconds to a maximum of 1.0 seconds, or at least 1.0 seconds to a maximum of 2.0 seconds, or at least 2.0 seconds to a maximum of 5.0 seconds, or at least 5.0 seconds to a maximum of 10.0 seconds, or at least 10.0 seconds to a maximum of 20.0 seconds, or at least 20.0 seconds to a maximum of 120.0 seconds, or at least 20.0 seconds to a maximum of 50.0 seconds, or at least 50.0 seconds to a maximum of 80.0 seconds, or at least 80.0 seconds to a maximum of 120.0 seconds.

[0170] The etching step of this method may use the same process temperature as the deposition step, or a different temperature may be used as an alternative configuration. In some embodiments, the process temperature, i.e., the substrate temperature, may be less than about 800°C, or less than about 700°C, or less than about 600°C, or less than about 500°C, or less than about 400°C, or less than about 300°C, or less than about 200°C during the etching step. In some embodiments of this disclosure, the substrate temperature during the etching step may be between 200°C and 800°C, or between 300°C and 700°C, or between 400°C and 600°C, or between 525°C and 575°C.

[0171] More specifically, in addition to achieving a desired process temperature, i.e., a desired substrate temperature, the pressure in the reaction chamber during the (partial) etching of the metal-containing film may be adjusted to the same pressure used in the deposition process, or, as an alternative configuration, during the (partial) etching of the molybdenum metal film, the pressure in the reaction chamber may be different from that used in the deposition process. In some embodiments, the reaction chamber pressure may be adjusted to less than 760 Torr, or about 0.2 Torr to about 200 Torr, or about 0.5 Torr to about 50 Torr, or about 0.5 to about 20 Torr.

[0172] In some embodiments, the etching rate of the metal-containing film may be less than 10 Å / s, or less than 8 Å / s, or less than 6 Å / s, or less than 4 Å / s, or even less than 2 Å / s. For example, (partial) etching of the metal-containing film may include etching a thickness of less than 20 Å, or less than 10 Å, or even less than 5 Å. In some embodiments, the etchant may preferentially etch the metal-containing film near the entrance of one or more gap portions, thereby maintaining openings to one or more gap portions for a subsequent metal gap-filling process.

[0173] Following the etchant pulse, each cycle may further include purging the reaction chamber. For example, etchant gas and reaction byproducts (if any) can be removed from the surface of the semiconductor substrate by exhausting with an inert gas, for example. In some embodiments of the present disclosure, the purging process may include a purging cycle in which the surface of the semiconductor substrate is purged for a time of less than about 10.0 seconds, or less than about 5.0 seconds, or even less than 2.0 seconds. Excess etchant gas and any reaction byproducts that may be generated can be removed using the vacuum generated by an exhaust system that is in fluid communication with the reaction chamber.

[0174] As used in this disclosure, the term etching may refer to a chemical or reactive medium used in semiconductor manufacturing to selectively remove material from a substrate or thin film layer during an etching process. Suitable etchants in this context include halogen-containing compounds.

[0175] In certain embodiments, the etchant may be fluorine gas (F2), chlorine gas (Cl2), bromine gas (Br2), quaternary ammonium fluoride, quaternary ammonium chloride, quaternary ammonium bromide, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), tetrafluoroboric acid (HBF4), tetrachloroboric acid (HBCl4), tetrabromoboric acid (HBBr4), hexafluorosilicic acid (H2SiF6), hexachlorosilicic acid (H2SiCl6), hexabromosilicic acid (H2SiBr6), tetrabutylammonium tetrafluoroborate, hexafluorozirconate (H2ZrF6), or hexafluorotitanic acid (H2TiF6). The etching compound comprises one or more halogen-containing etchants selected from the group consisting of hexafluorophosphate (HPF6), molybdenum pentachloride (MoCl5), tungsten pentachloride (WCl5), ammonium hexafluorosilicate [(NH4)2SiF6], ammonium hexachlorosilicate [(NH4)2SiCl6], ammonium hexabromosilicate [(NH4)2SiBr6], ammonium hexafluorotiatate [(NH4)2TiF6], ammonium hexachlorotiatate [(NH4)2TiCl6], ammonium hexabromotiatate [(NH4)2TiBr6], thionyl chloride (SOCl2), and mixtures thereof.

[0176] Figure 3 illustrates a method 300 according to an embodiment of the present disclosure for partially fabricating a semiconductor device or a substructure of a semiconductor device.

[0177] The method begins when a semiconductor substrate containing one or more gaps is provided to a reaction chamber configured within a reactor. The semiconductor substrate may be any substrate as defined herein. The reactor may be a standalone reactor or part of a cluster tool.

[0178] Periodic deposition involves contacting one or more metal precursors with at least a portion of the semiconductor substrate in a metal precursor pulse 302. Optionally, the reaction chamber may be purged 303 after the metal precursor pulse 302. The metal precursor pulse 302 and the optional purge 303 may be repeated any number of times 304 to obtain a metal-containing film of a desired thickness.

[0179] Next, method 300 is continued by bringing one or more etchants into contact with at least a portion of the formed metal-containing film in an etchant pulse 305. Optionally, the reaction chamber may be purged 306 after the etchant pulse 305. The etchant pulse 305 and the optional purge 306 may be repeated any number of times 307.

[0180] Method 300 is completed when a semiconductor device configuration of a desired shape and thickness is formed based on any combination of the steps described above. Once the method is completed, the semiconductor substrate may be subjected to additional processes known in the art for forming semiconductor devices such as memory device structures and / or memory devices.

[0181] Figure 4 illustrates a method 400 according to another embodiment of the present disclosure for partially fabricating a semiconductor device or a substructure of a semiconductor device.

[0182] The method is initiated after a semiconductor substrate containing one or more gaps is provided to a reaction chamber configured to be placed in a reactor. The semiconductor substrate may be any substrate as defined herein. The reactor may be a standalone reactor or part of a cluster tool.

[0183] Periodic deposition involves contacting one or more metal precursors with at least a portion of the semiconductor substrate in a metal precursor pulse 402. Optionally, the reaction chamber is purged 403 after the metal precursor pulse 402. The metal precursor pulse 402 and the optional purge 403 can be repeated any number of times 404 to obtain a metal-containing film of a desired thickness.

[0184] Next, the periodic deposition process is continued by bringing one or more reactants into contact with at least a portion of the semiconductor substrate and / or the deposited metal-containing film in a reactant pulse 405. Optionally, the reaction chamber may be purged 406 after the reactant pulse 405. The reactant pulse 405 and the optional purge 406 may be repeated any number of times 407.

[0185] Next, method 400 is continued by bringing one or more etchants into contact with at least a portion of the formed metal-containing film in an etchant pulse 408. Optionally, the reaction chamber may be purged 409 after the etchant pulse 408. The etchant pulse 408 and the optional purge 409 may be repeated any number of times 410.

[0186] Method 400 is completed when the features of a semiconductor device of a desired shape and thickness are formed based on any combination of the steps described above. Once the Method is completed, the semiconductor substrate may be subjected to additional processes known in the Art for forming semiconductor devices such as memory device structures and / or memory devices.

[0187] Figure 5 illustrates a method 500 according to yet another embodiment of the present disclosure for partially fabricating a semiconductor device or a substructure of a semiconductor device.

[0188] The method is initiated after a semiconductor substrate containing one or more gaps is provided to a first reaction chamber configured within a reactor. The semiconductor substrate may be any substrate as defined herein. The reactor may be a standalone reactor or part of a cluster tool.

[0189] Periodic deposition involves contacting one or more metal precursors with at least a portion of the semiconductor substrate in a metal precursor pulse 502. Optionally, the first reaction chamber is purged 503 after the metal precursor pulse 502. The metal precursor pulse 502 and the optional purge 503 can be repeated any number of times 504 to obtain a metal-containing film of a desired thickness.

[0190] After the deposition of the metal-containing film, the semiconductor substrate is transported from the first reaction chamber to a second reaction chamber configured within the reactor 505. The process is then continued by bringing one or more etchants into contact with at least a portion of the formed metal-containing film in an etchant pulse 506. Optionally, the second reaction chamber may be purged 507 after the etchant pulse 506. The etchant pulse 506 and the optional purge 507 may be repeated any number of times 508.

[0191] Method 500 is completed when the features of a semiconductor device of a desired shape and thickness are formed based on any combination of the steps described above. Once the Method is completed, the semiconductor substrate may undergo additional processes known in the Art for forming a semiconductor device such as a memory device structure and / or a memory device.

[0192] Figure 6 illustrates a method 600 according to yet another embodiment of the present disclosure for partially fabricating a semiconductor device or a substructure of a semiconductor device.

[0193] Method 600 begins after a semiconductor substrate including one or more gaps is provided to a first reaction chamber configured within a reactor. The semiconductor substrate may be any substrate as defined herein. The reactor may be a standalone reactor or part of a cluster tool.

[0194] Periodic deposition involves contacting one or more metal precursors with at least a portion of the semiconductor substrate in a metal precursor pulse 602. Optionally, the first reaction chamber is purged 603 after the metal precursor pulse 602. The metal precursor pulse 602 and the optional purge 603 can be repeated any number of times 604 to obtain a metal-containing film of a desired thickness.

[0195] Next, the periodic deposition process is continued by bringing one or more reactants into contact with at least a portion of the semiconductor substrate and / or the deposited metal-containing film during a reactant pulse 605. Optionally, the first reaction chamber may be purged 606 after the reactant pulse 605. The reactant pulse 605 and the optional purge 606 may be repeated any number of times 607.

[0196] After the metal-containing film is brought into contact with one or more reactants, the semiconductor substrate is transferred from the first reaction chamber to a second reaction chamber configured within the reactor 608. The process is then continued by bringing one or more etchants into contact with at least a portion of the formed metal-containing film in an etchant pulse 609. Optionally, the second reaction chamber may be purged 610 after the etchant pulse. The etchant pulse 609 and the optional purge 610 may be repeated any number of times 611.

[0197] Method 600 is completed when individual phrases of the desired shape and thickness are formed based on any combination of the steps described above. Once the Method is completed, the semiconductor substrate may undergo additional processes known in the Art for forming semiconductor devices such as memory device structures and / or memory devices.

[0198] Figure 7 illustrates a method 700 according to yet another embodiment of the present disclosure for partially fabricating a semiconductor device or a substructure of a semiconductor device.

[0199] Method 700 begins 701 after a semiconductor substrate including one or more gaps is provided to a first reaction chamber configured to be placed in a reactor. The semiconductor substrate may be any substrate as defined herein. The reactor may be a standalone reactor or part of a cluster tool.

[0200] Periodic deposition involves contacting one or more metal precursors with at least a portion of the semiconductor substrate in a metal precursor pulse 702. Optionally, the first reaction chamber is purged 703 after the metal precursor pulse 702. The metal precursor pulse 702 and the optional purge 703 can be repeated any number of times 704 to obtain a metal-containing film of a desired thickness.

[0201] After the deposition of the metal-containing film, the semiconductor substrate is transported from the first reaction chamber to a second reaction chamber configured within the reactor 705. The periodic deposition process is then continued by bringing one or more reactants into contact with at least a portion of the semiconductor substrate and / or the deposited metal-containing film in a reactant pulse 706. Optionally, the first reaction chamber may be purged 707 after the reactant pulse 706. The reactant pulse 706 and the optional purge 707 may be repeated any number of times 708.

[0202] After the metal-containing film is brought into contact with one or more reactants, the semiconductor substrate is transferred from the second reaction chamber to a third reaction chamber configured within the reactor 709. The process is then continued by bringing one or more etchants into contact with at least a portion of the formed metal-containing film in an etchant pulse 710. Optionally, the second reaction chamber may be purged 711 after the etchant pulse. The etchant pulse 710 and the optional purge 711 can be repeated any number of times 712.

[0203] Method 700 is completed when individual phrases of a desired shape and thickness are formed based on any combination of the steps described above. Once the Method is completed, the semiconductor substrate may undergo additional processes known in the Art for forming semiconductor devices such as memory device structures and / or memory devices.

[0204] Another aspect of the present disclosure provides a semiconductor device comprising one or more gaps filled with a metal-containing film prepared in an apparatus, by an aspect of the present disclosure or a (preferred) embodiment thereof, or by a method according to an aspect of the present disclosure or a (preferred) embodiment thereof.

[0205] It is clear that the (preferred) embodiments and related advantages of the apparatus and method according to one aspect of the present disclosure are also the (preferred) embodiments of the semiconductor device according to one aspect of the present disclosure, and vice versa.

[0206] In certain embodiments, the semiconductor device is a memory device. As used herein, the term “memory device” refers to an electronic component designed to store, retain, and retrieve digital information. It may employ a variety of physical mechanisms known in the art to represent and store data in a manner that allows for subsequent access and manipulation. Memory devices are essential components of computing systems and electronic devices, facilitating tasks such as data storage, retrieval, processing, and transfer. In the context of memory devices, MIM capacitors are important components for data storage and retrieval. The methods disclosed herein are particularly suitable for manufacturing MIM capacitors having high charge retention and rapid charge release, and thus result in memory devices with more reliable data storage and retrieval. Non-limiting exemplary memory devices include at least one of a 3D-NAND device, a DRAM device, a 3D integrated device, or an integrated logic device, or a partially fabricated memory device structure including at least one of a 3D-NAND device structure, a DRAM device structure, a 3D integrated device structure, or a partially fabricated integrated logic device structure.

[0207] In embodiments comprising a DRAM device structure in which a semiconductor device is (partially) fabricated, the semiconductor substrate may have multiple features comprising multiple DRAM word lines.

[0208] Figure 9 illustrates a schematic cross-sectional view of an exemplary semiconductor memory device 800 according to one embodiment of the present disclosure. Specifically, this figure shows a channel cross-section of the 3D NAND device 800. The device 800 comprises bit lines 810, which may be used to read and write data to the memory device by connecting to the drains or sources of a plurality of transistors in a memory array (not shown).

[0209] Bit line 810 is located at the top of the memory string, opposite the bottom selection gate 820, which is located at the base of the vertical memory string. The bottom selection gate 820 controls the connection between the memory string and the source line, enabling or disabling the flow of current during memory operations such as reading, writing, or erasing. The bottom selection gate 820 is located adjacent to a conductive channel 860, which serves as a carrier conduction path between the source terminal and the drain terminal.

[0210] Distributed between the bit line 810 and the bottom selection gate 820 are a plurality of floating-gate transistors 840 configured to store charges representing the binary data of the memory device. Each floating-gate transistor 840 is provided for a specific word line 850 as described herein. The floating-gate transistors 840 are vertically supported by spacers 870 that define the dimensions of the word line and the channel opening. The spacers 870 may include a dielectric material.

[0211] Word line 850 acts as the control gate for the floating-gate transistor and can be used to address and operate transistor 840 during memory operation. Each layer of the vertical stack contains word lines that control the floating-gate transistors at that level. For example, a memory string with 64 layers has 64 word lines that control the 64 floating-gate transistors in that string. A shared channel in the vertical stack is connected to drain 830, allowing the flow of current necessary for memory operation.

Claims

1. A reactor comprising at least one reaction chamber configured to process at least one semiconductor substrate having one or more gap portions, A metal precursor source configured to provide a vapor of at least one metal precursor containing at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, cobalt, nickel, and mixtures thereof, An etchant source configured to provide steam for at least one etchant, A vapor distribution and removal system configured to supply the vapor of the metal precursor and the vapor of the etchant to at least one reaction chamber of the reactor and to remove the vapor from the reaction chamber, A sequence controller operably connected to the vapor distribution and removal system, the sequence controller having a memory comprising a program configured to control the flow of the metal precursor from the metal precursor source to the reaction chamber by activating the vapor distribution and removal system during one or more deposition cycles, As a result of the deposition cycle, a metal-containing film is deposited to at least partially fill one or more gaps in the semiconductor substrate. The apparatus wherein the program is further configured to control the flow of the etchant from the etchant source to the reaction chamber by activating the vapor distribution and removal system during one or more etching cycles, and as a result of the etching cycles, the metal-containing film undergoes subtractive etching.

2. Further comprising a reactant source configured to supply vapors of reactants, The apparatus according to claim 1, wherein the vapor distribution and removal system is further configured to supply vapor of the reactants to the reactor, and the program stored in the memory is configured to control the flow of the reactants from the reactant source to the at least one reaction chamber during the one or more deposition cycles.

3. The apparatus according to claim 2, wherein the reactant is selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reducing reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

4. The apparatus according to claim 1 or 2, wherein the program stored in the memory is further configured to control the flow of the metal precursor from the metal precursor source to the at least one reaction chamber by activating the vapor distribution and removal system during one or more deposition cycles included in a periodic deposition process as part of an atomic layer deposition process.

5. The apparatus according to claim 1 or 2, wherein the at least one semiconductor substrate comprises a material selected from the group consisting of silicon, silicon oxide, silicon germanium, carbon-doped silicon oxide, silicon nitride, silicon carbide, germanium, gallium arsenide, gallium nitride, glass, sapphire, and combinations thereof.

6. The apparatus according to claim 1 or 2, wherein the metal precursor is a metal halide, a metal chalcogenized halide, or a metal-organic precursor.

7. The apparatus according to claim 1 or 2, wherein the etchant comprises one or more halogen-containing etching compounds.

8. The etchant is F ２ , Cl ２ , Br ２ , quaternary ammonium fluoride, quaternary ammonium chloride, quaternary ammonium bromide, HF, HCl, HBr, tetrafluoroboric acid, tetrachloroboric acid, tetra-bromoboric acid, hexafluorosilicic acid, hexachlorosilicic acid, hexabromosilicic acid, tetrabutylammonium tetrafluoroborate, H ２ ZrF ６ , H ２ TiF ６ , HPF ６ , MoCl ５ , WCl ５ , ammonium hexafluorosilicate, ammonium hexachlorosilicate, ammonium hexabromosilicate, ammonium hexafluorotitanate, ammonium hexachlorotitanate, ammonium hexabromotitanate, thionyl chloride, and one or more halogen-containing etching compounds selected from the group consisting of mixtures thereof, the apparatus according to claim 1 or 2.

9. The apparatus according to claim 1 or 2, wherein the at least one reactor further comprises a heating means configured to raise the temperature in the reaction chamber to 200°C to 800°C.

10. The apparatus according to claim 1 or 2, wherein the at least one reactor further comprises a pressure regulating mechanism configured to set the pressure in the reaction chamber to 0.2 Torr to 200 Torr.

11. The apparatus according to claim 1 or 2, wherein one or more of the at least one reactor is a vertical furnace comprising at least one reaction chamber configured to simultaneously receive and process a plurality of semiconductor substrates.

12. The apparatus according to claim 1 or 2, wherein the reactor comprises a reactor housing enclosing at least a first reaction chamber and a second reaction chamber, and a handling chamber configured for transporting the semiconductor substrate between the first reaction chamber and the second reaction chamber, wherein one or more deposition cycles are carried out in the first reaction chamber, one or more etching cycles are carried out in the second reaction chamber, and the vapor distribution and removal system is further configured to selectively direct the vapor flow of the metal precursor to at least the first reaction chamber and the vapor flow of the etchant to at least the second reaction chamber.

13. The apparatus according to claim 1 or 2, wherein the reactor comprises a reactor housing enclosing a single reaction chamber, the one or more deposition cycles and the one or more etching cycles are carried out within the reaction chamber, and the vapor distribution and removal system is further configured to selectively direct and remove flows of vapor of the metal precursor and vapor of the etchant into the reaction chamber.

14. A method for manufacturing a semiconductor device, at least partially, a) The step of providing at least one semiconductor substrate having one or more gap portions into a reactor comprising at least one reaction chamber, b) A step of performing one or more deposition cycles in the reaction chamber, each deposition cycle comprising a metal precursor pulse, wherein at least a portion of the semiconductor substrate comes into contact with the at least one metal precursor by introducing at least one metal precursor into the reactor in the metal precursor pulse, the at least one metal precursor comprising at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, and mixtures thereof, and as a result of the deposition cycle, a metal-containing film is deposited to at least partially fill one or more gaps in the semiconductor substrate; c) A method comprising the step of performing one or more etching cycles in the reaction chamber, each etching cycle comprising an etchant pulse, wherein at least a portion of the metal-containing film comes into contact with the at least one etchant by introducing at least one etchant into the reactor in the etchant pulse, and as a result of the etching cycle, at least a portion of the metal-containing film undergoes subtractive etching.

15. The method according to claim 14, wherein the one or more deposition cycles further include a reactant pulse, and in the reactant pulse, at least a portion of the semiconductor substrate comes into contact with the at least one reactant by introducing at least one reactant into the reactor.

16. The method according to claim 15, wherein the at least one reactant is selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reducing reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

17. The method according to claim 14 or 15, wherein the reactor comprises a reactor housing enclosing at least a first reaction chamber and a second reaction chamber, and a handling chamber configured for transporting the semiconductor substrate between the first reaction chamber and the second reaction chamber, and the one or more deposition cycles are carried out in the first reaction chamber, and the etching cycles are carried out in the second reaction chamber without removing the semiconductor substrate from the reactor.

18. The method according to claim 14 or 15, wherein the reactor comprises a reactor housing enclosing a single reaction chamber, and the one or more deposition cycles and the one or more etching cycles are carried out within the reaction chamber without removing the semiconductor substrate from the reactor.

19. A semiconductor device comprising one or more gap portions filled with a metal-containing film manufactured using the apparatus described in claim 1 and / or by the method described in claim 14.

20. The semiconductor device is a memory device that includes at least one of a 3D-NAND device, a DRAM device, a 3D integrated device, or an integrated logic device, or The semiconductor device according to claim 19, wherein the semiconductor device is a partially fabricated memory device structure that includes at least one of a 3D-NAND device structure, a DRAM device structure, a 3D integrated device structure, or a partially fabricated integrated logic device structure.

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