Wiring board

Abstract

Providing high-quality wiring boards. [Solution] The wiring board comprises a core substrate having a glass substrate, through holes penetrating the substrate, and through-hole conductors formed within the through holes; a resin insulating layer formed on the core substrate, having a first surface, a second surface opposite to the first surface, and openings for via conductors extending from the first surface to the second surface; a first conductor layer formed on the first surface of the resin insulating layer; and via conductors formed within the openings and electrically connected to the through-hole conductors. The end faces of the through-hole conductors are located below the surface of the substrate.

Description

Technical Field

[0001] The technology disclosed by this specification relates to a wiring board.

Background Art

[0002] Patent Document 1 discloses a wiring board having a core substrate and build-up layers formed on both the front and back surfaces of the core substrate. The core substrate is formed of a glass substrate and through-hole conductors penetrating the substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] [Problems of Patent Document 1] In Patent Document 1, the surface of the substrate and the upper end of the through-hole conductor form the same plane. The CTE (Coefficient of Thermal Expansion) of the copper forming the through-hole conductor is larger than that of the glass forming the substrate. Therefore, when a resin insulation layer forming a build-up layer is laminated on the surface of the core substrate, it is considered that the upper end of the through-hole conductor protrudes above the surface of the substrate due to thermal expansion. Or, it is considered that the protrusion is suppressed by the pressure during lamination. Therefore, it is considered that the through-hole conductor bulges in a direction parallel to the surface of the substrate. It is considered that cracks occur in at least one of the resin insulation layer and the substrate.

Means for Solving the Problems

[0005] The wiring board of the present invention comprises a core substrate having a glass substrate, through holes penetrating the substrate, and through-hole conductors formed within the through holes; a resin insulating layer formed on the core substrate, having a first surface, a second surface opposite to the first surface, and openings for via conductors extending from the first surface to the second surface; a first conductor layer formed on the first surface of the resin insulating layer; and via conductors formed within the openings and electrically connected to the through-hole conductors. The end faces of the through-hole conductors are located below the surface of the substrate. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view showing the wiring board of the embodiment. [Figure 2] A partially enlarged view of the wiring board of the embodiment. [Figure 3A] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3B] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3C] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3D] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3E] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3F] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3G] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3H] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3I] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Modes for carrying out the invention]

[0007] [Embodiment] Figure 1 is a cross-sectional view showing a wiring board 2 of an embodiment. As shown in Figure 1, the wiring board 2 has a core substrate 3, a front-side build-up layer 300F, and a back-side build-up layer 300B. The core substrate 3 has a substrate 4, through holes 6, and through-hole conductors 8. The substrate 4 has a front surface 5F and a back surface 5B opposite to the front surface 5F. The front surface 5F of the core substrate 3 and the front surface 5F of the substrate 4 are the same surface. The back surface 5B of the core substrate 3 and the back surface 5B of the substrate 4 are the same surface. The front surface 5F is closer to the mounting surface than the back surface 5B. Electronic components are mounted on the front-side build-up layer 300F.

[0008] The front-side build-up layer 300F is formed on the surface 5F of the substrate 4. The front-side build-up layer 300F has a front-side resin insulating layer, a front-side conductor layer, and a front-side via conductor that penetrates the front-side resin insulating layer. The front-side conductor layer and the front-side via conductor are electrically connected to the through-hole conductor 8. The front-side resin insulating layer and the front-side conductor layer are stacked alternately. In Figure 1, the front-side resin insulating layer consists of a first resin insulating layer (front-side first resin insulating layer) 20F and a second resin insulating layer (front-side second resin insulating layer) 120F. The front-side conductor layer consists of a first conductor layer (front-side first conductor layer) 30F and a second conductor layer (front-side second conductor layer) 130F. The front-side via conductor consists of a first via conductor (front-side first via conductor) 40F and a second via conductor (front-side second via conductor) 140F. The number of resin insulating layers and conductor layers forming the front-side build-up layer 300F may be three or more.

[0009] The back-side build-up layer 300B is formed on the back surface 5B of the substrate 4. The back-side build-up layer 300B has a back-side resin insulating layer, a back-side conductor layer, and a back-side via conductor that penetrates the back-side resin insulating layer. The back-side resin insulating layer and the back-side conductor layer are stacked alternately. The back-side conductor layer and the back-side via conductor are electrically connected to the through-hole conductor 8. In Figure 1, the back-side resin insulating layer is the first resin insulating layer (back-side first resin insulating layer) 20B and the second resin insulating layer (back-side second resin insulating layer) 120B. The back-side conductor layer is the first conductor layer (back-side first conductor layer) 30B and the second conductor layer (back-side second conductor layer) 130B. The back-side via conductor is the first via conductor (back-side first via conductor) 40B and the second via conductor (back-side second via conductor) 140B. The number of resin insulating layers and conductor layers forming the back-side build-up layer 300B may be three or more.

[0010] The substrate 4 is made of glass. The through-hole 6 penetrates the substrate 4. The shape of the through-hole 6 is approximately cylindrical. The diameter of the through-hole 6 is approximately constant. The shape of the through-hole 6 may also be approximately frustoconical. The shape of the through-hole 6 may also be a shape obtained by connecting two approximately cones. The two cones are a cone on the front side and a cone on the back side. The base of the cone on the front side is located on the front surface 5F, and the base of the cone on the back side is located on the back surface 5B. In this case, the side surface of the through-hole 6 is formed by a tapered surface from the front surface 5F toward the back surface 5B and a tapered surface from the back surface 5B toward the front surface 5F.

[0011] The through-hole conductor 8 is formed within the through-hole 6. The through-hole conductor 8 is mainly made of copper. The through-hole conductor 8 includes a seed layer 10a formed on the inner wall surface of the through-hole 6 and an electroplating layer 10b formed on the seed layer 10a. The electroplating layer 10b fills the through-hole 6. The seed layer 10a is formed by electroless plating. The through-hole conductor 8 has an end face 8F on the front surface 5F side and an end face 8B on the back surface 5B side.

[0012] Figure 2 is an enlarged view of parts A1 and A2 of Figure 1. As shown in Figure 2(a), the end face 8F is located below the surface 5F. The end face 8B is located below the back surface 5B. The end faces 8F and 8B are located within the substrate 4. The embodiment has a recess (front side recess) 7F on the end face 8F, surrounded by the end face 8F and the inner wall surface of the through hole 6. The first resin insulating layer 20F is formed within the recess 7F. The embodiment also has a recess (back side recess) 7B on the end face 8B, surrounded by the end face 8B and the inner wall surface of the through hole 6. The first resin insulating layer 20B is formed within the recess 7B.

[0013] The distance L1 between surface 5F and end face 8F is less than 10 μm. The distance L2 between back surface 5B and end face 8B is less than 10 μm. Distance L2 may be greater than distance L1.

[0014] The end face 8F may be formed by an adhesive surface (front adhesive surface) 50F in contact with the first resin insulating layer 20F and a connection surface (front connection surface) 52F connected to the first via conductor 40F. The adhesive surface 50F may have a first uneven surface 60F. The end face 8F and the first resin insulating layer 20F may be bonded via the first uneven surface 60F of the adhesive surface 50F. The connection surface 52F may have a second uneven surface 62F. The connection surface 52F may be a substantially smooth surface. The size of the first uneven surface 60F may be larger than the size of the second uneven surface 62F. The end face 8B may be formed by an adhesive surface (back adhesive surface) 50B in contact with the first resin insulating layer 20B and a connection surface (back connection surface) 52B connected to the first via conductor 40B. The adhesive surface 50B may have a first uneven surface 60B. The end face 8B and the first resin insulating layer 20B may be bonded via the first irregularities 60B of the adhesive surface 50B. The connecting surface 52B may have second irregularities 62B. The connecting surface 52B may be a substantially smooth surface. The size of the first irregularities 60B may be larger than the size of the second irregularities 62B.

[0015] As shown in Figure 2(b), end faces 8F and 8B may be curved surfaces. For example, a curved surface can be formed by spraying an etching solution onto the end of the through-hole conductor 8. For example, the etching solution can be sprayed onto the end such that the spray intensity decreases from the center of the end towards the periphery. End face 8F may be formed as a curved surface such that the distance L1 between surface 5F and end face 8F increases substantially from the periphery towards the center. The distance L1 may be the shortest distance between surface 5F and end face 8F. The bonding surface 50F may be formed as a first curved surface (first curved surface on the front side) 70F, and the connecting surface 52F may be formed as a second curved surface (second curved surface on the front side) 72F. The first curved surface 70F and the second curved surface 72F may be formed as different curved surfaces. Preferably, the curvature of the first curved surface 70F is smaller than the curvature of the second curved surface 72F. The first curved surface 70F does not have to be formed by extending the second curved surface 72F. The end face 8B may be formed as a curved surface such that the distance L2 between the back surface 5B and the end face 8B increases substantially from the periphery towards the center. The distance L2 may be the shortest distance between the back surface 5B and the end face 8B. The bonding surface 50B may be formed as a first curved surface (first curved surface on the back side) 70B, and the connecting surface 52B may be formed as a second curved surface (second curved surface on the back side) 72B. The first curved surface 70B and the second curved surface 72B may be formed as different curved surfaces. The first curved surface 70B does not have to be formed by extending the second curved surface 72B. It is preferable that the curvature of the first curved surface 70B is smaller than the curvature of the second curved surface 72B.

[0016] As shown in FIG. 2(c), the embodiment may have gaps 11F and 11B having predetermined depths D1 and D2 between the through-hole conductor 8 and the inner wall surface of the through-hole 6. Gap 11F is the gap on the surface 5F side, and gap 11B is the gap on the back surface 5B side. For example, the central portion of the end of the through-hole conductor 8 is covered with a mask. Thereafter, the gaps 11F and 11B are formed by removing the end of the through-hole conductor 8 exposed from the mask. Alternatively, the gaps 11F and 11B may be formed by removing a part of the seed layer 10a. The gap 11F may be filled with the first resin insulating layer 20F, and the gap 11B may be filled with the first resin insulating layer 20B. By filling the gaps 11F and 11B with the first resin insulating layers 20F and 20B, the first resin insulating layers 20F and 20B are less likely to be peeled off from the substrate 4.

[0017] The depth D1 of the gap 11F and the depth D2 of the gap 11B may be 10 μm or less. The depths D1 and D2 may be 5 μm or less. The depth D2 may be greater than the depth D1. The ratio of depth D2 / depth D1 may be 1.2 or more and 1.5 or less. In a wiring board, the back surface side is farther from the mounting surface than the front surface side. Therefore, it is considered that the back surface side is more likely to warp than the front surface side. Accordingly, it is considered that the resin insulating layer on the back surface side is likely to be peeled off from the substrate 4. In the embodiment, since the depth D2 is greater than the depth D1, the first resin insulating layer 20B is less likely to be peeled off from the substrate 4.

[0018] As shown in FIG. 1, the first resin insulating layer 20F has a first surface 22F and a second surface 24F opposite to the first surface 22F. The first resin insulating layer 20F is formed on the surface 5F of the substrate 4 such that the second surface 24F faces the surface 5F. In the example of FIG. 1, the second surface 24F is in contact with the surface 5F. The second surface 24F is in contact with the adhesion surface 50F of the end face 8F. There is no conductor circuit between the surface 5F and the second surface 24F. No conductor circuit is formed on the surface 5F. The first resin insulating layer 20F has a first opening 26F reaching the end face 8F of the through-hole conductor 8. The first resin insulating layer 20F is formed of a resin and a large number of inorganic particles dispersed in the resin. The resin is an epoxy resin. Examples of the resin are thermosetting resins and photocurable resins. The inorganic particles are glass particles. The inorganic particles may be alumina. The content of the inorganic particles in the first resin insulating layer 20F is 75 wt% or more.

[0019] The first conductor layer 30F is formed on the first surface 22F of the first resin insulating layer 20F. The first conductor layer 30F includes a first signal wiring 32F, a second signal wiring 34F, and a land 36F. Although not shown in the figure, the first conductor layer 30F also includes conductor circuits other than the first signal wiring 32F, the second signal wiring 34F, and the land 36F. The first signal wiring 32F and the second signal wiring 34F form a pair wiring. The first conductor layer 30F is mainly formed of copper. The first conductor layer 30F is formed of a seed layer 30Fa and an electrolytic plating layer 30Fb on the seed layer 30Fa. The seed layer 30Fa is formed by sputtering. The seed layer 30Fa is formed of a first layer 31Fa on the first surface 22F and a second layer 31Fb on the first layer 31Fa. The first layer 31Fa is in contact with the first surface 22F. The second layer 31Fb is not essential. The first layer 31Fa is formed of a copper alloy. The content of copper in the copper alloy is 90 wt% or more. The second layer 31Fb is formed of copper. The electrolytic plating layer 30Fb is formed of copper.

[0020] The first resin insulating layer 20F is formed on a glass substrate 4. Since glass has excellent flatness, the first surface 22F of the first resin insulating layer 20F also has excellent flatness. If no conductive circuit is formed between the surface 5F and the first resin insulating layer 20F, the first surface 22F can follow the surface 5F. The first surface 22F can have the same flatness as the surface 5F. In this embodiment, fine wiring can be formed on the first surface 22F. For example, the first conductor layer 30F can have wiring with a width of 1.5 μm or more and 3.5 μm or less. The width of the space between adjacent wirings is 1.5 μm or more and 3.5 μm or less.

[0021] The first via conductor 40F is formed within the first opening 26F. The first via conductor 40F electrically connects the through-hole conductor 8 and the first conductor layer 30F. The first via conductor 40F electrically connects the through-hole conductor 8 and the land 36F of the first via conductor 40F. The first via conductor 40F is formed of a seed layer 30Fa and an electroplating layer 30Fb on the seed layer 30Fa. The seed layer 30Fa forming the first via conductor 40F and the seed layer 30Fa forming the first conductor layer 30F are common. The electroplating layer 30Fb forming the first via conductor 40F and the electroplating layer 30Fb forming the first conductor layer 30F are common. The seed layer 30Fa forming the first via conductor 40F is formed of a first layer 31Fa formed on the inner wall surface 27F of the first opening 26F and on the end face 8F of the through-hole conductor 8 exposed from the first opening 26F, and a second layer 31Fb on the first layer 31Fa. In Figure 1, the first via conductor 40F is connected to the end face 8F. The first via conductor 40F is connected to the end face 8F via the connection surface 52F. The first layer 31Fa is in contact with the end face 8F (connection surface 52F) and the inner wall surface 27F of the through-hole conductor 8. The first via conductor 40F is formed directly above the end face 8F. The first via conductor 40F is directly connected to the end face 8F.

[0022] The second resin insulating layer 120F is formed on the first surface 22F of the first resin insulating layer 20F and on the first conductor layer 30F. The first conductor layer 30F is formed between the second resin insulating layer 120F and the first resin insulating layer 20F. The second resin insulating layer 120F has a first surface 122F and a second surface 124F opposite to the first surface 122F. The second surface 124F of the second resin insulating layer 120F faces the first conductor layer 30F. The second resin insulating layer 120F is formed of resin and inorganic particles, similar to the first resin insulating layer 20F. Therefore, the material of the second resin insulating layer 120F and the material of the first resin insulating layer 20F are the same. The first surface 122F of the second resin insulating layer 120F and the first surface 22F of the first resin insulating layer 20F are the same.

[0023] The second resin insulating layer 120F has a second opening 126F that exposes the first conductor layer 30F. The second opening 126F exposes the land 36F.

[0024] The second conductor layer 130F is formed on the first surface 122F of the second resin insulating layer 120F. The second conductor layer 130F and the first conductor layer 30F are similar. Therefore, the second conductor layer 130F has the same wiring as the first conductor layer 30F. Furthermore, the second conductor layer 130F is formed of a seed layer 130Fa and an electroplating layer 130Fb on the seed layer 130Fa. The seed layer 130Fa is formed of a first layer 131Fa and a second layer 131Fb on the first layer 131Fa.

[0025] The second via conductor 140F is formed within the second opening 126F. The second via conductor 140F electrically connects the first conductor layer 30F and the second conductor layer 130F. In Figure 1, the second via conductor 140F electrically connects land 36F and land 136F. The second via conductor 140F and the first via conductor 40F are similar. Therefore, the second via conductor 140F is formed from the seed layer 130Fa and the electroplated layer 130Fb on the seed layer 130Fa. The seed layer 130Fa is formed from the first layer 131Fa and the second layer 131Fb on the first layer 131Fa.

[0026] The front-side build-up layer 300F and the back-side build-up layer 300B are identical. The first resin insulating layer 20B has a first surface 22B and a second surface 24B. The second resin insulating layer 120B has a first surface 122B and a second surface 124B. A detailed description of the other components of the back-side build-up layer 300B is omitted.

[0027] Although not shown in the figure, the length of each side of the wiring board 2 is 50 mm or more. Preferably, the length of each side is 100 mm or more. The length of each side is 250 mm or less. The length of the signal wiring formed by the embodiment is 5 mm or more. The length of the signal wiring may be 10 mm or more and 20 mm or less.

[0028] [Manufacturing method for the wiring board 2 of the embodiment] Figures 3A to 3I show a manufacturing method for the wiring board 2 of an embodiment. Figures 3A to 3I are cross-sectional views. Figure 3A shows a glass substrate 4. The substrate 4 has a front surface 5F and a back surface 5B. As shown in Figure 3B, a through hole 6 is formed from the front surface 5F to the back surface 5B. The through hole 6 penetrates the substrate 4. Laser light is irradiated from the front surface 5F side of the substrate 4. After that, the substrate 4 is immersed in hydrofluoric acid. The through hole 6 is formed.

[0029] As shown in Figure 3C, a seed layer 10a is formed. The seed layer 10a is formed by electroless plating. The seed layer 10a is formed of an electroless copper plating film. The seed layer 10a is formed on the inner wall surface of the through hole 6, on the surface 5F, and on the back surface 5B.

[0030] As shown in Figure 3D, an electroplating layer 10b is formed. The electroplating layer 10b is formed on the seed layer 10a. The electroplating layer 10b fills the through-hole 6. The electroplating layer 10b is formed of an electrolytic copper plating film.

[0031] As shown in Figure 3E, the electroplating layer 10b and seed layer 10a on the surface 5F are removed by polishing. The electroplating layer 10b and seed layer 10a on the back surface 5B are removed by polishing. The surface 5F and back surface 5B of the substrate 4 are exposed. The through-hole conductor 8 is formed by the seed layer 10a on the inner wall surface of the through-hole 6 and the electroplating layer 10b on the seed layer 10a. The end 9F of the through-hole conductor 8 on the surface 5F side is exposed from the surface 5F. The end 9B of the through-hole conductor 8 on the back surface 5B side is exposed from the back surface 5B. The surface forming end 9F and the surface 5F form the same plane. The surface forming end 9B and the back surface 5B form the same plane.

[0032] The ends 9F and 9B of the through-hole conductor 8 are dissolved with an etching solution. A portion of the through-hole conductor 8 near end 9F is removed. A portion of the through-hole conductor 8 near end 9B is removed. For example, the removal of both is performed separately. In this embodiment, the distance L1 can be made smaller than the distance L2. For example, the removal of both is performed simultaneously. In this embodiment, the distances L1 and L2 can be made approximately the same. As shown in Figure 3F, the end face 8F on the surface 5F side and the end face 8B on the back surface 5B side of the through-hole conductor 8 are formed. The core substrate 3 is formed. End face 8F is located below the surface 5F. End face 8B is located below the back surface 5B. A recess 7F is formed, surrounded by the end face 8F and the inner wall surface of the through-hole 6. A recess 7B is formed, surrounded by the end face 8B and the inner wall surface of the through-hole 6. It is preferable that the distance L1 is smaller than 3 μm. It is preferable that the distance L2 is smaller than 3 μm.

[0033] Since the front-side build-up layer 300F and the back-side build-up layer 300B are manufactured using similar methods, the explanation of the manufacturing method for the back-side build-up layer 300B is omitted.

[0034] As shown in Figure 3G, a first resin insulating layer 20F is formed on the surface 5F and edge 8F of the substrate 4. The second surface 24F of the first resin insulating layer 20F faces the surface 5F of the substrate 4. The first resin insulating layer 20F is formed within a recess 7F. The first resin insulating layer 20F fills the recess 7F. The first surface 22F is formed as a substantially flat surface. Surface 5F and the first surface 22F are approximately parallel.

[0035] A laser beam is shone from above the first surface 22F of the first resin insulating layer 20F. The laser beam penetrates the first resin insulating layer 20F. The laser beam is, for example, a UV laser beam or a CO2 laser beam. As shown in Figure 3H, a first opening 26F for a via conductor is formed, leading to the end face 8F of the through-hole conductor 8. The first opening 26F exposes the end face 8F of the through-hole conductor 8.

[0036] A seed layer 30Fa is formed on the first surface 22F of the first resin insulating layer 20F. The seed layer 30Fa is formed by sputtering. The formation of the seed layer 30Fa is carried out by a dry process. The seed layer 30Fa is also formed on the end face 8F of the through-hole conductor 8 exposed from the first opening 26F and on the inner wall surface 27F of the first opening 26F. The seed layer 30Fa is mainly made of copper. The first layer 31Fa is formed on the first surface 22F by sputtering. The first layer 31Fa is formed by sputtering on the inner wall surface 27F exposed from the first opening 26F and on the end face 8F of the through-hole conductor 8. The second layer 31Fb is formed on the first layer 31Fa by sputtering.

[0037] A plating resist is formed on the seed layer 30Fa. An electroplating layer 30Fb is formed on the seed layer 30Fa that is exposed from the plating resist. The electroplating layer 30Fb fills the first opening 26F.

[0038] The plating resist is removed. The seed layer 30Fa exposed from the electroplating layer 30Fb is removed. As shown in Figure 3I, the first conductor layer 30F and the first via conductor 40F are formed simultaneously.

[0039] A second resin insulating layer 120F is formed on the first surface 22F of the first resin insulating layer 20F and on the first conductor layer 30F. A second conductor layer 130F is formed on the first surface 122F of the second resin insulating layer 120F. A second via conductor 140F is formed in the second opening 126F of the second resin insulating layer 120F. The second resin insulating layer 120F is formed in the same manner as the first resin insulating layer 20F. The second conductor layer 130F is formed in the same manner as the first conductor layer 30F. The second via conductor 140F is formed in the same manner as the first via conductor 40F. A wiring board 2 of the embodiment is obtained. A front-side build-up layer 300F is formed on the front surface 5F and the end surface 8F. A back-side build-up layer 300B is formed on the back surface 5B and the end surface 8B.

[0040] In the wiring board 2 of the embodiment, the end face 8F of the through-hole conductor 8 is located below the surface 5F of the substrate 4. The end face 8B of the through-hole conductor 8 is located below the back surface 5B of the substrate 4. When the first resin insulating layers 20F and 20B are laminated on the core substrate 3, even if the through-hole conductor 8 expands due to heat, the through-hole conductor 8 does not press against the first resin insulating layers 20F and 20B. Or, even if the through-hole conductor 8 presses against the first resin insulating layers 20F and 20B, the pressing force is weak. Therefore, the embodiment can suppress the occurrence of cracks within the first resin insulating layers 20F and 20B. When the first resin insulating layers 20F and 20B are laminated on the core substrate 3, even if the through-hole conductor 8 expands due to heat, the through-hole conductor 8 does not press against the substrate 4. Or, even if the through-hole conductor 8 presses against the substrate 4, the pressing force is weak. Therefore, the embodiment can suppress the occurrence of cracks within the substrate 4. The embodiment has a recess 7F on the end face 8F of the through-hole conductor 8, surrounded by the end face 8F and the wall surface of the through-hole 6. A first resin insulating layer 20F is formed within the recess 7F. Because the contact area between the first resin insulating layer 20F and the substrate 4 is large, the first resin insulating layer 20F is less likely to peel off from the substrate 4. [Explanation of symbols]

[0041] 2: Wiring board 3: Core board 4: Circuit board 6: Through hole 5F: Surface 5B: Reverse side 8: Through-hole conductor 8F: End face 8B: End face 20F, 20B: First resin insulating layer 30F, 30B: First conductor layer 40F, 40B: First via conductor

Claims

1. A core substrate having a glass substrate, through holes penetrating the substrate, and through-hole conductors formed within the through holes, A resin insulating layer formed on the core substrate, having a first surface, a second surface opposite to the first surface, and openings for via conductors extending from the first surface to the second surface, A first conductor layer formed on the first surface of the resin insulating layer, A wiring board having via conductors formed within the opening and electrically connected to the through-hole conductor, The end face of the through-hole conductor is located below the surface of the substrate.

2. A wiring board according to claim 1, wherein the distance between the surface and the end face is less than 10 μm.

3. A wiring board according to claim 1, wherein the end face is formed of a connection surface connected to the via conductor and an adhesive surface in contact with the resin insulating layer, the adhesive surface has a first uneven surface, and the end face and the resin insulating layer are bonded together via the first uneven surface.

4. The wiring board according to claim 3, wherein the connection surface has a second uneven surface, and the size of the first uneven surface is larger than the size of the second uneven surface.

5. A wiring board according to claim 1, wherein the end face is curved.

6. A wiring board according to claim 5, wherein the end face is formed of a connection surface connected to the via conductor and an adhesive surface in contact with the resin insulating layer, the adhesive surface is formed of a first curved surface, the connection surface is formed of a second curved surface, and the first curved surface and the second curved surface are formed of different curved surfaces.

7. The wiring board according to claim 6, wherein the first curved surface is not formed by extending the second curved surface.

8. A wiring board according to claim 1, wherein a gap having a predetermined depth is formed between the through-hole conductor and the inner wall surface of the through-hole, and the gap is filled with the resin insulating layer.

9. The wiring board according to claim 8, wherein the depth is 10 μm or less.

10. The wiring board according to claim 8, wherein the depth is 5 μm or less.

11. A wiring board according to claim 8, wherein the core board has a surface and a back surface opposite to the surface, the surface is closer to the mounting surface than the back surface, the gap includes a gap on the surface side and a gap on the back side, and the depth of the gap on the back side is greater than the depth of the gap on the surface side.

12. The wiring board according to claim 11, wherein the ratio of the depth of the gap on the back side to the depth of the gap on the front side is 1.2 or more and 1.5 or less.

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