Circuit board and its manufacturing method

Abstract

This invention provides a circuit board and a method for manufacturing the same that can improve the adhesion of conductive wires, facilitate the miniaturization of conductive wires into circuits, and improve manufacturing yield. [Solution] The circuit board according to the present invention comprises an insulating layer, a primer layer disposed on the insulating layer and having a first uneven portion, and a conductive wire disposed on the first uneven portion of the primer layer, wherein the conductive wire includes a first conductive wire having a second uneven portion corresponding to the first uneven portion, and a second conductive wire disposed on the first conductive wire.

Description

Technical Field

[0001] The present invention relates to a circuit board and a method for manufacturing the same, and more particularly, to a circuit board and a method for manufacturing the same that can easily achieve miniaturization of conductive lines and improve manufacturing yield.

Background Art

[0002] A circuit board is formed by forming a circuit pattern with a conductive material on an insulating layer. In recent years, due to the trend of miniaturization and weight reduction of electronic components, a higher-density fine circuit pattern has been demanded. To form such a fine circuit pattern, various processing methods such as the Tenting method, the MSAP (Modified Semi-Additive Process) method, and the SAP (Semi-Additive Process) method are used.

[0003] The Tenting method is a method of removing an unnecessary part by etching. Although the processing of the circuit pattern is simple, it is difficult to perform fine processing. The MSAP method is a method of forming a circuit pattern on a thin seed layer remaining after etching a copper foil. It is advantageous for forming a circuit pattern with a certain pitch or more, but it is difficult to form a finer circuit pattern below that pitch. Since the SAP method forms a circuit pattern only by plating, there is almost no difference in line width between the upper and lower parts of the circuit pattern, so a fine circuit pattern can be easily realized, but the process is complicated and special materials are required. In particular, the Prepreg that constitutes the CCL (copper clad laminate), which is the material of the core layer used in the SAP method, has low plating adhesion and is not suitable for forming a circuit pattern by the SAP method. Therefore, the development of forming a higher-density fine circuit pattern has become an everyday issue.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems of the above-mentioned conventional circuit boards, and the object of the present invention is to provide a circuit board and a method for manufacturing the same that can improve the adhesion force of conductive wires, facilitate the miniaturization of conductive wires, and improve the manufacturing yield. [Means for solving the problem]

[0005] To achieve the above objective, the circuit board according to the present invention comprises an insulating layer, a primer layer disposed on the insulating layer and having a first uneven portion, and a conductive wire disposed on the first uneven portion of the primer layer, wherein the conductive wire includes a first conductive wire having a second uneven portion corresponding to the first uneven portion, and a second conductive wire disposed on the first conductive wire.

[0006] Preferably, the first conductive wire is a copper foil layer, and the second conductive wire includes a seed wire and a plated wire which is plated with the seed wire as a seed layer. Preferably, the surface roughness of the first uneven portion is greater than the surface roughness of the portion of the primer layer that does not overlap with the first conductive wire. The second thickness, which is the thickness of the plated wire, is preferably greater than the first thickness, which is the thickness of the seed wire. The second uneven portion is preferably located at the interface between the primer layer and the first conductive wire. Preferably, the first uneven portion is recessed from the surface of the primer layer, and the second uneven portion is protruding from the surface of the first conductive wire. It is preferable that a portion of the first uneven portion and the second uneven portion interlock with each other. Preferably, the insulating layer contains a composite material of resin and fibers, and the primer layer contains a high-molecular polymer.

[0007] A method for manufacturing a circuit board according to the present invention, made to achieve the above objective, is characterized by comprising the steps of: preparing an insulating layer; sequentially laminating a primer layer having a first uneven portion and a first conductive layer having a second uneven portion corresponding to the first uneven portion on the insulating layer; forming a seed layer on the first conductive layer; exposing a first portion of the seed layer on the seed layer and forming a pattern mask covering a second portion of the seed layer; forming a plated wire on the first portion of the seed layer; removing the pattern mask; and removing the second portion of the seed layer and the first conductive layer below it to form a conductive wire.

[0008] The step of removing the second portion of the seed layer and the first conductive layer below it preferably includes a step of making the surface roughness of the primer layer below the second portion of the seed layer smaller than the surface roughness of the first uneven portion of the primer layer. Preferably, the seed layer is formed by an electroless plating process, and the plated wire is formed by an electrolytic plating process. The step of forming the pattern mask preferably includes the steps of forming a dry film resist on the seed layer and exposing and developing the dry film resist. The step of forming the conductive wire preferably includes the steps of: using the plated wire as an etching mask to etch the second portion of the seed layer to form a seed wire and complete the second conductive wire; and using the plated wire as an etching mask to etch a part of the exposed first conductive layer to form the first conductive wire. [Effects of the Invention]

[0009] According to the circuit board and its manufacturing method according to the present invention, the first uneven portion of the primer layer and the second uneven portion of the first conductive wire, which is a seed layer for forming conductive wires, interlock with each other, thereby improving the adhesion force of conductive wires, including the first conductive wire. Therefore, it is possible to easily realize miniaturization of conductive wires and improve the manufacturing yield of circuit boards. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing a schematic configuration of a circuit board according to an embodiment of the present invention. [Figure 2] This is a flowchart illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 3] This is a series of cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 4] This is a series of cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 5] This is a series of cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 6] This is a series of cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 7] This figure illustrates a method for measuring the adhesion force of conductive wires on a circuit board according to an embodiment of the present invention. [Modes for carrying out the invention]

[0011] Next, specific examples of embodiments for carrying out the circuit board and manufacturing method thereof according to the present invention will be described with reference to the drawings.

[0012] The present invention can be realized in various different forms and is not limited to the embodiments described herein. To clearly explain the present invention, unnecessary explanatory parts have been omitted, and the same or similar reference numerals are used throughout the specification for identical or similar components. Furthermore, the accompanying drawings are merely intended to facilitate a brief understanding of the embodiments disclosed herein, and it should be understood that the accompanying drawings do not limit the technical ideas disclosed herein and include any modifications, equivalents, or substitutions that fall within the concept and technical scope of the present invention.

[0013] In addition, the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for the convenience of explanation, and thus the present invention is not necessarily limited to those shown. The thicknesses are shown enlarged in the drawings in order to clearly represent the various layers and regions. In the drawings, for the convenience of explanation, the thicknesses of some of the layers and regions are shown exaggerated. Also, when a part such as a layer, film, region, or plate is "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there are other parts in between. Conversely, when a part is "directly above" another part, it means that there are no other parts in between. Also, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the direction opposite to gravity.

[0014] Throughout the specification, when a part "includes" a certain component, this means that other components can be further included, rather than excluding other components, unless otherwise stated to the contrary. Throughout the specification, when referring to "on a plane", this means when the target part is viewed from above, and when referring to "in a cross-section", this means when the cross-section obtained by vertically cutting the target part is viewed from the side. Throughout the specification, when referring to "being connected", this does not only mean that two or more components are directly connected, but also means that two or more components are indirectly connected through other components, not only physically connected but also electrically connected, or can mean being integrated although referred to by different names depending on their positions and functions.

[0015] Hereinafter, embodiments of the present invention and modifications thereof will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a schematic configuration of a circuit board according to an embodiment of the present invention. As shown in FIG. 1, the circuit board according to the embodiment of the present invention includes an insulating layer 100, a primer layer 200, and a conductive line 300.

[0016] The insulating layer 100 includes a composite material of resin and fibers. For example, the insulating layer 100 may include prepreg, ABF (Ajinomoto Buildup Film), PID (Photo Image-able Dielectric), etc. The primer layer 200 is placed on the insulating layer 100 to improve the adhesion between the insulating layer 100 and the conductive wire 300. The primer layer 200 has a first uneven portion 200a on the surface facing the first conductive wire 310. The first uneven portion 200a is recessed from the surface of the primer layer 200. The surface roughness (Ra) of such first uneven portion 200a may be 0.05 to 0.4 μm. At this time, the surface roughness of the first uneven portion 200a is greater (rougher) than the surface roughness of the portion of the primer layer 200 that does not overlap with the first conductive wire 310. In other words, although this embodiment shows the first uneven portion 200a being formed only beneath the first conductive wire 310, finer roughness (smaller surface roughness) is also formed in the portion that does not overlap with the first conductive wire 310, with a roughness smaller than that of the first uneven portion 200a.

[0017] The primer layer 200 contains a high-molecular polymer. For example, the primer layer 200 may contain at least one of the following: epoxy resin, polyimide (PI) resin, polyamideimide (PAI) resin, polyamide (PA) resin, liquid crystal polymer (LCP) resin, or cycloolefin (COP) resin. The conductive wire 300 is placed on the first uneven portion 200a of the primer layer 200. Such conductive wires 300 can be applied to peripheral bumps and signal lines on circuit boards where a high level of adhesion is required. The conductive wire 300 includes a laminated first conductive wire 310 and a second conductive wire 320.

[0018] The first conductive wire 310 may contain conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first conductive wire 310 may be copper foil (Cu foil). The first conductive wire 310 has a second uneven portion 310a on its surface that corresponds to the first uneven portion 200a. The second uneven portion 310a is positioned at the interface between the primer layer 200 and the first conductive wire 310. The second uneven portion 310a protrudes from the surface of the first conductive wire 310 and is inserted into the first uneven portion 200a of the primer layer 200. In other words, the first protrusion 200a and the second protrusion 310a interlock with each other. Here, the first uneven portion 200a and the second uneven portion 310a both become uneven portions (indicated by the symbol UE in Figure 3).

[0019] In this way, the first uneven portion 200a of the primer layer 200 and the second uneven portion 310a of the first conductive wire 310 interlock and make contact with each other, thereby improving the adhesion force of the conductive wires 300, including the first conductive wire 310. Therefore, it is easier to miniaturize the conductive wire 300 and improve the manufacturing yield of circuit boards.

[0020] The second conductive wire 320 has the same pattern as the first conductive wire 310 and is arranged on the first conductive wire 310. In other words, on a plane, the second conductive wire 320 and the first conductive wire 310 overlap each other, and the boundary lines at both ends of the second conductive wire 320 and the boundary lines at both ends of the first conductive wire 310 can coincide with each other. The second conductive wire 320 includes a seed wire 321 and a plated wire 322. The seed wire 321 acts as a seed layer for forming the plated wire in the plating process. The seed wire 321 may contain conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0021] The plated wire 322 is a plated layer that is plated using the seed wire 321 as the seed layer. In this case, the plated wire 322 is the plated layer and the seed wire 321 is the seed layer, so the second thickness t2, which is the thickness of the plated wire 322, is greater than the first thickness t1, which is the thickness of the seed wire 321. The plated wire 322 may contain conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0022] The following will describe in detail the method for manufacturing a circuit board according to an embodiment of the present invention, with reference to Figures 1 and 2 to 6. Figure 2 is a flowchart illustrating the method for manufacturing a circuit board according to an embodiment of the present invention, and Figures 3 to 6 are cross-sectional views showing the method for manufacturing a circuit board according to an embodiment of the present invention in order. As shown in Figures 2 and 3, an insulating layer 100 is prepared by sequentially laminating a primer layer 200 and a first conductive layer 30 on an insulating layer 100 (step S100).

[0023] At this time, a primer layer 200 is formed on the insulating layer 100, and the first conductive layer 30 is formed on the primer layer 200 under pressure, or the first conductive layer 30 is formed by attaching the pressurized primer layer 200 to the insulating layer 100. Here, since the first conductive layer 30 has a second uneven portion 310a, the first conductive layer 30 is pressed to transfer the shape of the second uneven portion 310a to the surface of the primer layer 200 that is in contact with the second uneven portion 310a, thereby forming a first uneven portion 200a on the surface of the primer layer 200. The first conductive layer 30 may contain conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first conductive layer 300 may be copper foil (Cu foil). Here, both the first uneven portion 200a and the second uneven portion 310a form an uneven portion (indicated by the symbol UE in Figure 3).

[0024] Next, as shown in Figures 2 and 4, a seed layer 40 is formed on the first conductive layer 30 by an electroless plating process (step S200). The seed layer 40 may contain conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Next, a pattern mask (PM) is formed that exposes the first portion 41 of the seed layer 40 (step S300). At this point, the pattern mask (PM) covers the second portion 42, which is the remaining portion of the first portion 41 of the seed layer 40. The pattern mask (PM) is formed by forming a dry film resist (DFR) on the first conductive layer 30, and then exposing and developing the dry film resist.

[0025] Next, as shown in Figures 2 and 5, a plated wire 322 is formed on the first portion 41 of the exposed seed layer 40 by an electroplating process (step S400). Next, the pattern mask (PM) is removed (step S500), as shown in Figures 2 and 6. Therefore, the second portion 42 of the seed layer 40 located below the pattern mask (PM) is exposed to the outside. Next, as shown in Figures 1 and 2, the plated wire 322 is used as an etching mask to simultaneously etch the second portion 42 of the seed layer 40 and the second portion 32 (see Figure 6) of the first conductive layer 30 below it, thereby forming the conductive wire 300 (step S600).

[0026] Specifically, by etching the second portion 42 of the seed layer 40 using the plated wire 322 as an etching mask, the first portion 41 of the seed layer 40 remains in the same pattern as the plated wire 322, forming the seed wire 321, and thus forming the second conductive wire 320 consisting of the seed wire 321 and the plated wire 322. Subsequently, by etching the second portion 32, which is a part of the exposed first conductive layer 30, using the plated wire 322 as an etching mask, the first portion 31 (see Figure 6), which is a part of the first conductive layer 30 other than the second conductive wire 320, remains, forming the first conductive wire 310. Therefore, a conductive wire 300 is formed, consisting of the second conductive wire 320 and the first conductive wire 310. At this time, while etching the second portion 32 of the first conductive layer 30, the surface of the primer layer 200 located beneath the second portion 32 of the first conductive layer 30 is also etched to reduce (fine) the surface roughness. Therefore, the surface roughness of the first uneven portion 200a is greater than the surface roughness of the portion of the primer layer 200 that does not overlap with the first conductive wire 310.

[0027] In this way, by forming the conductive wire 300 using the MSAP method, the wire width of the conductive wire 300 can be minimized, and the first uneven portion 200a of the primer layer 200 and the second uneven portion 310a of the first conductive wire 310 interlock with each other, increasing the contact area between the primer layer 200 and the first conductive wire 310, thereby improving the adhesion force of the conductive wire 300 including the first conductive wire 310. Therefore, miniaturization of the conductive wire 300 can be easily achieved, and the manufacturing yield of the circuit board can also be improved. In this case, the conductive wire 300 is formed using the MSAP method with the primer layer 200 applied, which improves the adhesion of the conductive wire 300 compared to the conventional SAP method or the conventional MSAP method.

[0028] Figure 7 is a diagram illustrating a method for measuring the adhesion force of conductive wires on a circuit board according to an embodiment of the present invention. As shown in Figure 7, a first sample S1 is produced by the conventional SAP method, a second sample S2 is produced by the conventional MSAP method, and a third sample S3 is produced by the MSAP method with the primer layer 200 according to the embodiment of the present invention applied. Specifically, the conventional SAP method forms a first sample S1 having conductive wires in the following manner. In other words, a primer layer is formed on the sample insulating layer, and a seed layer is formed on the primer layer by electroless plating. Then, a pattern mask is formed on the seed layer, and a plating layer is formed on the seed layer exposed by the pattern mask using electroplating. Then, the pattern mask is removed, and the seed layer exposed by the removed pattern mask is removed to form the conductive wire.

[0029] Furthermore, the conventional MSAP method forms a second sample S2 having conductive wires in the following manner. In other words, a copper foil layer is formed on the sample insulating layer, and a seed layer is formed on the copper foil layer by electroless plating. Then, a pattern mask is formed on the seed layer, and a plating layer is formed on the seed layer exposed by the pattern mask using electroplating. Then, the pattern mask is removed, and the seed layer and copper foil layer exposed by the removed pattern mask are both removed in an etching process to form a conductive wire.

[0030] Then, the adhesion force of the conductive wire 300 is measured at multiple positions in each of the first sample S1, second sample S2, and third sample S3, for example, the first position P1, the second position P2, the third position P3, the fourth position P4, and the fifth position P5. At this time, the adhesion force is measured for the first sample S1, the second sample S2, and the third sample S3 by peeling the conductive wire 300 from the insulating layer 100. Table 1 below shows the adhesion force of the conductive wire 300 measured at the first position P1, second position P2, third position P3, fourth position P4, and fifth position P5 for the first sample S1, second sample S2, and third sample S3. [Table 1]

[0031] As can be seen from Table 1, the average adhesion strength of sample 1 (S1) produced by the conventional SAP method is 0.63 kgf / cm². 2 Therefore, the average adhesion strength of sample 2(S2) produced by the conventional MSAP method was 0.72 kgf / cm². 2 However, the average adhesion force of sample 3(S3) produced according to the embodiment of the present invention is 1.2 kgf / cm². 2 In this respect, it can be seen that the adhesion strength of the embodiment of the present invention has improved by more than 60% compared to the conventional MSAP method.

[0032] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0033] 30 First conductive layer 31 First portion of the first conductive layer 32 Second portion of the first conductive layer 40 Seed Layer 41. Part 1 of the seed layer 42. Second part of the seed layer 100 Insulating layer 200 Primer layer 200a 1st uneven part 300 conductive wires 310 First conductive wire 310a 2nd uneven part 320 Second conductive wire 321 Seed line 322 Plated wire PM Pattern Mask

Claims

1. Insulating layer and, A primer layer having a first uneven portion is disposed on the insulating layer, The primer layer comprises a conductive wire disposed on the first uneven portion, The conductive wire is, A first conductive wire having a second uneven portion corresponding to the first uneven portion, A circuit board characterized by including a second conductive wire arranged on the first conductive wire.

2. The first conductive wire is a copper foil layer, The second conductive wire is, Seed line and, The circuit board according to claim 1, further comprising a plated wire plated with the aforementioned seed wire as a seed layer.

3. The circuit board according to claim 2, characterized in that the surface roughness of the first uneven portion is greater than the surface roughness of the portion of the primer layer that does not overlap with the first conductive wire.

4. The circuit board according to claim 2, characterized in that the second thickness, which is the thickness of the plated wire, is greater than the first thickness, which is the thickness of the seed wire.

5. The circuit board according to claim 2, characterized in that the second uneven portion is arranged at the interface between the primer layer and the first conductive wire.

6. The first uneven portion recesses from the surface of the primer layer, The circuit board according to claim 5, characterized in that the second uneven portion protrudes from the surface of the first conductive wire.

7. The circuit board according to claim 6, characterized in that a part of the first uneven portion and the second uneven portion interlock with each other.

8. The insulating layer includes a composite material of resin and fiber, The circuit board according to claim 1, characterized in that the primer layer contains a polymer.

9. The process involves preparing an insulating layer, and sequentially laminating a primer layer having a first uneven portion and a first conductive layer having a second uneven portion corresponding to the first uneven portion onto the insulating layer. The steps include forming a seed layer on the first conductive layer, A step of exposing a first portion of the seed layer on the seed layer and forming a pattern mask that covers a second portion of the seed layer, The steps include forming a plated wire on the first portion of the seed layer, The step of removing the aforementioned pattern mask, A method for manufacturing a circuit board, comprising the step of removing the second portion of the seed layer and the first conductive layer below it to form a conductive wire.

10. The method for manufacturing a circuit board according to claim 9, characterized in that the step of removing the second portion of the seed layer and the first conductive layer below it includes the step of making the surface roughness of the primer layer below the second portion of the seed layer smaller than the surface roughness of the first uneven portion of the primer layer.

11. The seed layer is formed by an electroless plating process. The method for manufacturing a circuit board according to claim 9, characterized in that the plated wire is formed by an electrolytic plating process.

12. The step of forming the aforementioned pattern mask is: The steps include forming a dry film resist on the seed layer, The method for manufacturing a circuit board according to claim 9, characterized by comprising the step of exposing and developing the dry film resist.

13. The step of forming the conductive wire is, The steps include: using the plated wire as an etching mask, etching the second portion of the seed layer to form a seed wire and complete the second conductive wire; The method for manufacturing a circuit board according to claim 9, comprising the step of using the plated wire as an etching mask to etch a part of the exposed first conductive layer to form a first conductive wire.

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