Semiconductor memory devices and memory systems

Abstract

To provide a semiconductor memory device and memory system that can realize high read endurance memory cells. [Solution] A semiconductor memory device of one embodiment comprises a plurality of memory strings, each spaced apart from one another in a first direction. Each of the plurality of memory strings includes a semiconductor layer extending in a second direction intersecting the first direction, a first string disposed on the first side of the semiconductor layer in a third direction intersecting the first and second directions, and a second string disposed on the second side of the semiconductor layer in the third direction. Each of the first strings includes a first selection transistor and a plurality of first memory cell transistors, each with a semiconductor layer as a channel and spaced apart from one another in a second direction. Each of the second strings includes a plurality of first transistors and second selection transistors, each with a semiconductor layer as a channel and spaced apart from one another in a second direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a memory system.

Background Art

[0002] A memory system including a semiconductor memory device and a memory controller that controls the semiconductor memory device is known. As the semiconductor memory device, a NAND type flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device and a memory system capable of realizing a memory cell with high read tolerance.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment comprises a plurality of memory strings, each spaced apart from one another in a first direction. Each of the plurality of memory strings includes a semiconductor layer extending in a second direction intersecting the first direction, a first string disposed on the first side of the semiconductor layer in a third direction intersecting the first and second directions, and a second string disposed on the second side of the semiconductor layer in the third direction. Each of the first strings includes a first selection transistor and a plurality of first memory cell transistors, each with a semiconductor layer as a channel and spaced apart from one another in a second direction. Each of the second strings includes a plurality of first transistors and second selection transistors, each with a semiconductor layer as a channel and spaced apart from one another in a second direction. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a memory system including a semiconductor storage device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 3] A plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 4] A cross-sectional view along line IV-IV in Figure 3, showing an example of the cross-sectional structure of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 5] A cross-sectional view along the VV line in Figure 3, showing an example of the cross-sectional structure of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 3 shows an example of the cross-sectional structure of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 7] A cross-sectional view along line VII-VII in Figure 3, showing an example of the cross-sectional structure of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 8] A diagram showing the voltage of each wiring during the first read operation of the semiconductor memory device according to the first embodiment. [Figure 9] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor memory device according to a modified example of the first embodiment. [Figure 10] A plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to a modified example of the first embodiment. [Figure 11] A diagram showing the voltage of each wiring during the first read operation of a semiconductor memory device according to a modified example of the first embodiment. [Figure 12] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor memory device according to the second embodiment. [Figure 13] A plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to the second embodiment. [Figure 14] A flowchart showing an example of the writing operation of a semiconductor memory device according to the second embodiment. [Figure 15] A diagram showing the voltage across each wiring during the first read operation of the semiconductor memory device according to the second embodiment. [Figure 16] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor memory device according to a modified example of the second embodiment. [Figure 17] A plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to a modified example of the second embodiment. [Figure 18] A diagram showing the voltage of each wiring during the first read operation of a semiconductor memory device according to a modified example of the second embodiment. [Figure 19] A diagram illustrating the string flag used in the semiconductor memory device according to the third embodiment. [Figure 20] A flowchart showing an example of the writing operation of a semiconductor memory device according to the third embodiment. [Figure 21] A flowchart showing an example of the read operation of a semiconductor memory device according to the third embodiment. [Figure 22] A diagram showing the voltage across each wire during the first read operation of the semiconductor memory device according to the third embodiment. [Figure 23]Conceptual diagram of a string table used in a semiconductor memory device according to the first modification of the third embodiment. [Figure 24] Flowchart showing an example of the write operation of a semiconductor memory device according to the first modification of the third embodiment. [Figure 25] Flowchart showing an example of the read operation of a semiconductor memory device according to the first modification of the third embodiment. [Figure 26] Diagram showing the voltages of each wiring during the first read operation of a semiconductor memory device according to the second modification of the third embodiment. [Figure 27] Diagram for explaining a method of designating the storage mode of a block in a semiconductor memory device according to the fourth embodiment. [Figure 28] Flowchart showing an example of the write operation of a semiconductor memory device according to the fourth embodiment. [Figure 29] Flowchart showing an example of the read operation of a semiconductor memory device according to the fourth embodiment. [Figure 30] Diagram showing the voltages of each wiring during the second read operation of a semiconductor memory device according to the fourth embodiment. [Figure 31] Diagram showing the voltages of each wiring during the second read operation of a semiconductor memory device according to the first modification of the fourth embodiment. [Figure 32] Diagram for explaining a method of designating the storage mode of a block in a semiconductor memory device according to the second modification of the fourth embodiment. [Figure 33] Diagram for explaining a mode flag used in a semiconductor memory device according to the second modification of the fourth embodiment. [Figure 34] Flowchart showing an example of the block area variable operation of a semiconductor memory device according to the second modification of the fourth embodiment. [Figure 35] Flowchart showing an example of the first variable operation of a semiconductor memory device according to the second modification of the fourth embodiment. [Figure 36] Flowchart showing an example of the second variable operation of a semiconductor memory device according to the second modification of the fourth embodiment. [Figure 37] Flowchart showing an example of the read operation of a semiconductor memory device according to the second modification of the fourth embodiment. [Figure 38] A conceptual diagram of a mode table used in a semiconductor memory device according to a third modified example of the fourth embodiment. [Figure 39] A flowchart showing an example of a writing operation of a semiconductor memory device according to a third modified example of the fourth embodiment. [Figure 40] A flowchart showing an example of variable block area operation of a semiconductor memory device according to a third modification of the fourth embodiment. [Figure 41] A flowchart showing an example of the first variable operation of a semiconductor memory device according to a third modified example of the fourth embodiment. [Figure 42] A flowchart showing an example of the second variable operation of a semiconductor memory device according to a third modified example of the fourth embodiment. [Figure 43] A flowchart showing an example of a read operation of a semiconductor memory device according to a third modified example of the fourth embodiment. [Figure 44] A diagram illustrating a method for specifying the storage mode of a block in a semiconductor memory device according to a fourth modified example of the fourth embodiment. [Figure 45] A flowchart showing an example of a writing operation of a semiconductor memory device according to a fourth modification of the fourth embodiment. [Figure 46] A flowchart showing an example of a writing operation of a semiconductor memory device according to a fifth modification of the fourth embodiment. [Figure 47] A block diagram showing an example of the configuration of a memory system including a semiconductor storage device according to the fifth embodiment. [Figure 48] A block diagram showing an example of the configuration of an arithmetic module included in a semiconductor memory device according to the fifth embodiment. [Figure 49] A flowchart showing an example of arithmetic processing by the arithmetic module of the semiconductor memory device according to the fifth embodiment. [Figure 50] A block diagram showing an example of the configuration of an AI module incorporating a memory system including a semiconductor storage device according to the fifth embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. The drawings are schematic, and the dimensions and proportions shown in the drawings are not necessarily the same as those of actual objects. In the following description, components having substantially the same function and configuration will be denoted by the same reference numeral. When elements with similar configurations need to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] In the following description, "connected" to another second element means that the first element is connected to the second element indirectly, either through an intermediate element that is always or selectively conductive, or directly without an intermediate element.

[0009] 1. First Embodiment A semiconductor memory device according to the first embodiment will be described.

[0010] 1.1 Configuration 1.1.1 Memory System Configuration The configuration of a memory system including a semiconductor storage device according to the first embodiment will be described with reference to Figure 1. Figure 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor storage device according to the first embodiment.

[0011] Memory system 1 is a storage device configured to be connected to an external host (not shown). Memory system 1 is, for example, an SD TM These include memory cards, UFS (universal flash storage), and SSDs (solid state drives). Memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0012] The memory controller 2 is composed of an integrated circuit, such as a system-on-a-chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from the host. Specifically, for example, the memory controller 2 writes data requested by the host to the semiconductor memory device 3. The memory controller 2 also reads data requested by the host from the semiconductor memory device 3 and sends it to the host.

[0013] The semiconductor memory device 3 is a non-volatile memory. The semiconductor memory device 3 is, for example, a NAND flash memory. The semiconductor memory device 3 stores data in a non-volatile manner.

[0014] Communication between the memory controller 2 and the semiconductor memory device 3 conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0015] 1.1.2 Configuration of Semiconductor Memory Devices Next, the internal configuration of the semiconductor memory device 3 will be described with reference to the block diagram shown in Figure 1. The semiconductor memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0016] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). The number of blocks BLK included in the memory cell array 10 may be one or less. A block BLK is a collection of multiple memory cells. A block BLK is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0017] The command register 11 stores the command CMD received by the semiconductor memory device 3 from the memory controller 2. The command CMD includes, for example, instructions that cause the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0018] The address register 12 stores the address information ADD received by the semiconductor memory device 3 from the memory controller 2. The address information ADD includes, for example, the block address BAd, the page address PAAd, and the column address CAD. For example, the block address BAd, the page address PAAd, and the column address CAD are used for selecting the block BLK, word lines, and bit lines, respectively.

[0019] The sequencer 13 controls the operation of the entire semiconductor memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD stored in the command register 11, to perform read operations, write operations, erase operations, etc.

[0020] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PAd stored in the address register 12.

[0021] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0022] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller 2 as read data DAT.

[0023] 1.1.3 Circuit configuration of memory cell array The circuit configuration of the memory cell array 10 will be explained using Figure 2. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10. Figure 2 shows the circuit configuration of a block BLK included in the memory cell array 10 as an example of the circuit configuration of the memory cell array 10. Other block BLKs have a similar configuration to that shown in Figure 2.

[0024] Block BLK includes, for example, four string units SU0 to SU3. A string unit SU is a set of multiple NAND strings NS that are selected collectively in, for example, a write or read operation. A string unit SU includes multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). A NAND string NS is a set of multiple memory cell transistors MT connected in series.

[0025] The NAND string NS includes a first string NSa and a second string NSb. The first string NSa is a string that stores data (hereinafter also referred to as the "memory string"). The second string NSb is a string that carries read current (hereinafter also referred to as the "read string"). The first string NSa includes, for example, memory cell transistors MT0e to MT7e, and selection transistors ST1a and ST1b. The second string NSb includes, for example, transistors TR0 to TR7, and selection transistors ST2a and ST2b. The memory cell transistor MTe stores data non-volatilely. The memory cell transistor MTe includes a control gate and a charge storage layer. Transistors TR0 to TR7, and selection transistors ST1a, ST1b, ST2a, and ST2b are switching elements. Each of the selection transistors ST1a and ST2a is used to select the string unit SU during various operations.

[0026] In the NAND string NS, memory cell transistors MT0e to MT7e are connected in series. One end of the series-connected memory cell transistors MT0e to MT7e (one end of memory cell transistor MT7e) is connected to the source of selection transistor ST1b. The drain of selection transistor ST1b is connected to the source of selection transistor ST1a. The drain of selection transistor ST1a is connected to the associated bit line BL. The other end of the series-connected memory cell transistors MT0e to MT7e (the other end of memory cell transistor MT0e) is connected to the drain of selection transistor ST2b. Transistors TR0 to TR7 are connected in series. One end of the series-connected transistors TR0 to TR7 (one end of transistor TR7) is connected to the source of selection transistor ST1b. The other end of the series-connected transistors TR0 to TR7 (the other end of transistor TR0) is connected to the drain of selection transistor ST2b. The source of selection transistor ST2b is connected to the drain of selection transistor ST2a. The source of selection transistor STab is connected to the source line SL.

[0027] Furthermore, in the NAND string NS, one end of memory cell transistor MT7e is connected to one end and the other end of transistor TR7, respectively. One end of transistor TR6 is connected to the other end of memory cell transistor MT7e. One end of memory cell transistor MT6e is connected to the other end of transistor TR6. One end of transistor TR5 is connected to the other end of memory cell transistor MT6e. One end of memory cell transistor MT5e is connected to the other end of transistor TR5. One end of transistor TR4 is connected to the other end of memory cell transistor MT5e. One end of memory cell transistor MT4e is connected to the other end of transistor TR4. One end of transistor TR3 is connected to the other end of memory cell transistor MT4e. One end of memory cell transistor MT3e is connected to the other end of transistor TR3. One end of transistor TR2 is connected to the other end of memory cell transistor MT3e. One end of memory cell transistor MT2e is connected to the other end of transistor TR2. One end of transistor TR1 is connected to the other end of memory cell transistor MT2e. One end of memory cell transistor MT1e is connected to the other end of transistor TR1. One end of transistor TR0 is connected to the other end of memory cell transistor MT1e. One end of memory cell transistor MT0e is connected to the other end of transistor TR0. The drain of selection transistor ST2b is connected to the other end of memory cell transistor MT0e.

[0028] In the same block BLK, the control gates of memory cell transistors MT0e to MT7e are commonly connected to word lines WL0e to WL7e. The gates of transistors TR0 to TR7 are commonly connected to word lines WL0o to WL7o. The gates of each selection transistor ST1a in string units SU0 to SU3 are connected to selection gate decode lines SGD0a to SGD3a. Hereafter, when selection gate decode lines SGD0a to SGD3a are not distinguished, they will simply be referred to as selection gate decode line SGDa. The gates of each selection transistor ST1b in string units SU0 to SU3 are connected to selection gate decode lines SGD0b to SGD3b. Also, selection gate decode line SGD0b is connected to selection gate decode line SGD0a. Selection gate decode line SGD1b is connected to selection gate decode line SGD1a. Selection gate decode line SGD2b is connected to selection gate decode line SGD2a. The selection gate decode line SGD3b is connected to the selection gate decode line SGD3a. Hereafter, when the selection gate decode lines SGD0b to SGD3b are not distinguished, they will simply be referred to as selection gate decode line SGDb. The gate of the selection transistor ST2a, which is included in the same block BLK, is connected to the selection gate decode line SGSa. The gate of the selection transistor ST2b, which is included in the same block BLK, is connected to the selection gate decode line SGSb. Furthermore, the selection gate decode line SGSb is connected to the selection gate decode line SGSa.

[0029] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared, for example, by multiple NAND strings NS to which the same column address CA is assigned in multiple string units SU. The source line SL is shared, for example, between multiple blocks BLK.

[0030] A collection of multiple memory cell transistors MT connected to a common word line WL within a string unit SU is referred to, for example, as a cell unit CU. Block BLK contains multiple cell unit CUs. The data stored in a cell unit CU, each containing multiple memory cell transistors MT that store 1 bit of data according to a threshold voltage, corresponds to one page of data. A cell unit CU can store two or more pages of data, based on the number of bits of data stored by the memory cell transistors MT. In this embodiment, the memory cell transistors MT are shown as SLC (Single Level Cell) storing 1 bit of data, MLC (Multi Level Cell) storing 2 bits of data, TLC (Triple Level Cell) storing 3 bits of data, or QLC (Quad Level Cell) storing 4 bits of data, but it is also possible to store other numbers of bits.

[0031] Furthermore, the circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, the number of string units SU included in block BLK, and the number of memory cell transistors MT, TR, and selection transistors ST1 and ST2 included in NAND string NS can each be any number.

[0032] 1.1.4 Structure of a memory cell array The structure of the memory cell array 10 will now be described. The memory cell array 10 is provided above the substrate. In the following, the plane parallel to the surface of the substrate will be referred to as the XY plane. The directions that intersect each other within the XY plane will be referred to as the X direction and the Y direction. The direction from the substrate toward the memory cell array 10 will be referred to as the Z direction. That is, the Z direction is the Y direction and the direction that intersects the Y direction. The Z direction may also be interpreted as the upward direction.

[0033] 1.1.4.1 Planar layout of memory cell array The planar layout of the memory cell array will be described. Figure 3 is a plan view showing an example of the planar layout of the memory cell array 10. In Figure 3, the plan view of the layers of block BLK that have approximately equal height from the substrate (i.e., position in the Z direction) is shown. The portion shown in Figure 3 corresponds to one NAND string NS in the circuit diagram shown in Figure 2.

[0034] As shown in Figure 3, within the same layer, the memory cell array 10 includes a semiconductor CPS, wiring LBI, source line SL, multiple insulators INS, multiple conductive pillars CGP, SGP, and TRP, multiple memory structures MS, and multiple contact plugs BC.

[0035] A semiconductor CPS is a semiconductor that extends in the XY plane. A semiconductor CPS includes, for example, polysilicon. The semiconductor CPS has a line shape extending in the Y direction. One end of the semiconductor CPS in the Y direction is connected to wiring LBI. The other end of the semiconductor CPS in the Y direction is connected to source line SL. The semiconductor CPS functions as a channel in the NAND string NS.

[0036] Wiring LBI is a conductor extending in the X direction. Wiring LBI is connected to bit line BL (not shown).

[0037] The source wire SL is a conductor extending in the X direction.

[0038] The insulator INS is an insulator that extends in the Y direction. The insulator INS includes, for example, silicon oxide. The insulator INS is provided in the region between the wiring LBI and the source wire SL. The example in Figure 3 shows a case where two insulators INS are spaced apart from each other in the X direction. The semiconductor CPS is located between the two insulators INS.

[0039] Each of the multiple conductive pillars CGP, SGP, and TRP, and each of the multiple contact plugs BC, extends in the Z direction so as to intersect with the insulator INS and the semiconductor CPS. Each of the multiple conductive pillars CGP, SGP, and TRP, and each of the multiple contact plugs BC, is provided on the left and right sides of the semiconductor CPS in the region between the wiring LBI and the source wire SL. Hereinafter, the left side of the semiconductor CPS will also be referred to as the "front side of the semiconductor CPS" or the "first side of the semiconductor CPS in the X direction." The right side of the semiconductor CPS will also be referred to as the "back side of the semiconductor CPS" or the "second side of the semiconductor CPS in the X direction."

[0040] A first string NSa is arranged on the front side of the semiconductor CPS. Within the first string NSa, for example, two conductive pillars SGP, eight conductive pillars CGP, and one contact plug BC are arranged in the Y direction, starting from the top of the paper. Each of the two conductive pillars SGP, eight conductive pillars CGP, and one contact plug BC is spaced apart from each other in the Y direction. Hereafter, the two conductive pillars SGP will also be referred to as conductive pillars SGP0e and SGP1e, starting from the top of the paper. The eight conductive pillars CGP will also be referred to as conductive pillars CGP0e to CGP7e, starting from the bottom of the paper.

[0041] A second string NSb is located on the back side of the semiconductor CPS. Within the second string NSb, for example, along the Y direction, from the top of the paper, one contact plug BC, eight conductive pillars TRP, and two conductive pillars SGP are arranged. Each of the one contact plug BC, eight conductive pillars TRP, and two conductive pillars SGP is spaced apart from each other in the Y direction. Hereafter, the eight conductive pillars TRP will also be referred to as conductive pillars TRP0 to TRP7, from the bottom of the paper in order. The two conductive pillars SGP will also be referred to as conductive pillars SGP0o and SGP1o, from the bottom of the paper in order.

[0042] In a top view (viewed from the Z direction), the centers of the multiple conductive pillars CGP, SGP, and TRP, and the multiple contact plugs BC, are offset from each other in the Y direction. In other words, each of the multiple conductive pillars CGP, SGP, and TRP, and the multiple contact plugs BC, are arranged in a staggered pattern, for example, in 22 rows, in the region between the wiring LBI and the source wire SL.

[0043] This document describes multiple conductive pillars CGP and SGP on the front side of a semiconductor CPS, as well as the contact plug BC.

[0044] A portion of the side surface of the conductive pillar CGP (a portion of the side surface facing the semiconductor CPS) is in contact with one of the two sides of the memory structure MS that face the semiconductor CPS. The other of the two sides of the memory structure MS that face the semiconductor CPS is in contact with the semiconductor CPS. In other words, a portion of the side surface of the conductive pillar CGP is in contact with the semiconductor CPS via the memory structure MS. The portion of the side surface of the conductive pillar CGP that is not in contact with the memory structure MS is in contact with the insulator INS.

[0045] The conductive pillar CGP includes a conductive film 30 and an insulating film 31. The conductive film 30 includes, for example, tungsten, titanium nitride, or tungsten and titanium nitride. The conductive film 30 functions as a word line WL. The insulating film 31 surrounds the sides of the conductive film 30. The insulating film 31 includes, for example, silicon oxide. The insulating film 31 functions as a block insulating film. The insulating film 31 may be formed by laminating multiple layers.

[0046] The memory structure MS includes a charge storage film 32 and an insulating film 33. The charge storage film 32 covers a portion of the side surface of the insulating film 31. The charge storage film 32 contains a material that has the function of storing charge. Specifically, the charge storage film 32 may contain a conductor such as silicon or a metal. Alternatively, the charge storage film 32 may contain an insulator such as silicon nitride. The insulating film 33 covers a portion of the side surface of the charge storage film 32. The insulating film 33 is, for example, silicon oxide. The insulating film 33 functions as a tunnel insulating film. The semiconductor CPS covers a portion of the side surface of the insulating film 33.

[0047] The above structure, which includes one conductive pillar CGP, one memory structure MS, and a semiconductor CPS, functions as a memory cell transistor MT. The eight above structures shown in Figure 3 function as memory cell transistors MT7e, MT6e, MT5e, MT4e, MT3e, MT2e, MT1e, and MT0e, respectively, from top to bottom of the paper. When the charge storage film 32 contains a conductor such as silicon or metal, the memory cell transistor MT functions as a floating gate type memory cell transistor MT. When the charge storage film 32 contains an insulator such as silicon nitride, the memory cell transistor MT functions as a MONOS (metal-oxide-nitride-oxide-silicon) type memory cell transistor MT.

[0048] A portion of the side surface of the conductive pillar SGP (a portion of the side surface facing the semiconductor CPS) is in contact with the semiconductor CPS. The portion of the side surface of the conductive pillar SGP that is not in contact with the semiconductor CPS is in contact with the insulator INS.

[0049] The conductive pillar SGP includes a conductive film 40 and an insulating film 41. The conductive film 40 includes, for example, tungsten, titanium nitride, or tungsten and titanium nitride. The conductive film 40 functions as a selective gate decode line SGD. The insulating film 41 surrounds the sides of the conductive film 40. The insulating film 41 includes, for example, silicon oxide. The insulating film 41 may be formed by laminating multiple layers.

[0050] The above structure, which includes one conductive pillar SGP and a semiconductor CPS, functions as a selection transistor ST. The two above structures shown in Figure 3 function as selection transistors ST1a and ST1b, respectively, from top to bottom of the page.

[0051] Thus, the first string NSa includes selection transistors ST1a and ST1b, and memory cell transistors MT0e to MT7e, each having a semiconductor CPS as its channel and being spaced apart from each other in the Y direction.

[0052] A portion of the side surface of the contact plug BC (the portion of the side surface facing the semiconductor CPS) is in contact with the semiconductor CPS. The portion of the side surface of the contact plug BC that is not in contact with the semiconductor CPS is in contact with the insulator INS.

[0053] The contact plug BC includes a conductive film 60 and a semiconductor film 61. The conductive film 60 includes, for example, tungsten, titanium nitride, or tungsten and titanium nitride. The semiconductor film 61 surrounds the sides of the conductive film 60. The semiconductor film 61 includes, for example, polysilicon containing P-type impurities. The contact plug BC functions, for example, as a hole source for injecting holes into the charge storage film 32 of the memory cell transistor MT during an erase operation.

[0054] The above structure, which includes a semiconductor CPS, two conductive pillars SGP on the front side of the semiconductor CPS, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC, corresponds to the first string NSa.

[0055] This document describes the conductive pillars TRP and SGP on the back side of the semiconductor CPS, as well as the contact plug BC.

[0056] A portion of the side surface of the conductive pillar TRP (a portion of the side surface facing the semiconductor CPS) is in contact with the semiconductor CPS. The portion of the side surface of the conductive pillar TRP that is not in contact with the semiconductor CPS is in contact with the insulator INS.

[0057] The conductive pillar TRP includes a conductive film 50 and an insulating film 51. The conductive film 50 includes, for example, tungsten, titanium nitride, or tungsten and titanium nitride. The conductive film 50 functions as a word line WL. The insulating film 51 surrounds the sides of the conductive film 50. The insulating film 51 includes, for example, silicon oxide. The insulating film 51 may be formed by laminating multiple layers. Furthermore, the conductive pillar TRP may have a structure similar to that of the conductive pillar SGP, or it may have a structure different from that of the conductive pillar SGP.

[0058] The above structure, which includes one conductive pillar TRP and a semiconductor CPS, functions as a transistor TR. The eight above structures shown in Figure 3 function as transistors TR7, TR6, TR5, TR4, TR3, TR2, TR1, and TR0, respectively, from top to bottom of the paper.

[0059] A portion of the side surface of the conductive pillar SGP (a portion of the side surface facing the semiconductor CPS) is in contact with the semiconductor CPS. The portion of the side surface of the conductive pillar SGP that is not in contact with the semiconductor CPS is in contact with the insulator INS. The conductive pillar SGP has the same structure as the conductive pillar SGP on the front side of the semiconductor CPS. The conductive film 30 functions as a selective gate decode line SGS.

[0060] The above structure, which includes one conductive pillar SGP and a semiconductor CPS, functions as a selection transistor ST. The two above structures shown in Figure 3 function as selection transistors ST2b and ST2a, respectively, from top to bottom of the page.

[0061] Thus, the second string NSb includes transistors TR0 to TR7, and selection transistors ST2a and ST2b, each having a semiconductor CPS as its channel and being spaced apart from each other in the Y direction. Furthermore, transistors TR0 to TR7 may have the same structure as selection transistors ST1a, ST1b, ST2a, and ST2b.

[0062] A portion of the side surface of the contact plug BC (the portion of the side surface facing the semiconductor CPS) is in contact with the semiconductor CPS. The portion of the side surface of the contact plug BC that is not in contact with the semiconductor CPS is in contact with the insulator INS. The contact plug BC has the same structure as the contact plug BC on the front side of the semiconductor CPS.

[0063] The above structure, which includes a semiconductor CPS, two conductive pillars SGP on the back of the semiconductor CPS, eight conductive pillars TRP, and one contact plug BC, corresponds to the second string NSb.

[0064] Multiple NAND strings NS connected to the same bit line BL are arranged, for example, in the region between the wiring LBI and the source line SL, with the structure shown in Figure 3 spaced apart from each other in the X direction. More specifically, a structure (hereinafter also referred to as "first structure") including a semiconductor CPS, a front-side structure of the semiconductor CPS (two conductive pillars SGP, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC), and a back-side structure of the semiconductor CPS (one contact plug BC, eight conductive pillars TRP, and two conductive pillars SGP) are arranged spaced apart from each other in the X direction.

[0065] Furthermore, multiple NAND strings NS connected to the same bit line BL may be arranged alternately in the X direction and spaced apart from each other in the region between the wiring LBI and the source line SL, for example, with a first structure and a structure in which the front and back sides of the semiconductor CPS are reversed in the first structure (hereinafter also referred to as the "second structure"). In this case, a conductive pillar CGP may be shared between the first and second structures adjacent to each other in the X direction. The shared conductive pillar CGP can drive two memory cell transistors MT on the first structure side and the second structure side.

[0066] 1.1.4.2 Three-dimensional structure of memory cell array The three-dimensional structure of the memory cell array 10 will now be described. The three-dimensional structure of the memory cell array 10 has a planar layout as shown in Figure 3, in which the elements are spaced apart from each other in the Z direction. That is, the multiple NAND strings NS are spaced apart from each other in the Z direction.

[0067] 1.1.4.3 Cross-sectional structure of conductive pillar CGP Figure 4 is a cross-sectional view along line IV-IV in Figure 3, showing an example of the cross-sectional structure of the memory cell array 10.

[0068] As shown in Figure 4, the memory cell array 10 includes a substrate 20, insulating layers 21 and 23, a semiconductor layer 22, an insulator 34, a conductive pillar CGP, and a memory structure MS.

[0069] The substrate 20 is, for example, a P-type semiconductor. An insulating layer 21 is provided on the upper surface of the substrate 20. The substrate 20 and the insulating layer 21 may include circuits not shown. The circuits included in the substrate 20 and the insulating layer 21 correspond to, for example, a low decoder module 15 and a sense amplifier module 16.

[0070] On the upper surface of the insulating layer 21, multiple semiconductor layers 22 and multiple insulating layers 23 are stacked alternately, one layer at a time. In the example shown in Figure 4, five semiconductor layers 22 and five insulating layers 23 are stacked alternately, one layer at a time. In other words, multiple semiconductor layers 22 are provided on the substrate 20, stacked at intervals in the Z direction. The number of stacked semiconductor layers 22 corresponds, for example, to the number of bit lines BL connected to one wiring LBI.

[0071] The semiconductor layer 22 corresponds to the semiconductor CPS and has a portion extending in the Y direction. The portion of the semiconductor layer 22 extending in the Y direction (i.e., the portion shown in Figure 4) functions as a channel in the NAND string NS. The insulating layers 21 and 23 include, for example, silicon oxide. The semiconductor layer 22 includes, for example, polysilicon.

[0072] The insulator 34 corresponds to the insulator INS and has a portion that extends in the XY plane within the same layer as the semiconductor layer 22.

[0073] The conductive pillar CGP extends in the Z direction so as to intersect with multiple semiconductor layers 22 and insulating layers 23. For example, the lower end of the conductive pillar CGP reaches the insulating layer 21. The upper end of the conductive pillar CGP aligns with the upper end of the uppermost insulating layer 23. The conductive pillar CGP functions as a word line WL by being electrically connected to the row decoder module 15 via a conductor (not shown) provided above it.

[0074] The memory structure MS is provided on the same layer as the semiconductor layer 22.

[0075] Within the same layer as the semiconductor layer 22, a portion of the side surface of the conductive pillar CGP is in contact with the insulator 34. The portion of the side surface of the conductive pillar CGP in the same layer as the semiconductor layer 22 that is not in contact with the insulator 34 is in contact with the memory structure MS.

[0076] The conductive film 30 of the conductive pillar CGP extends in the Z direction. For example, the lower end of the conductive film 30 is located below the lowest semiconductor layer 22. The upper end of the conductive film 30 aligns with the upper end of the uppermost insulating layer 23. The insulating film 31 of the conductive pillar CGP covers the periphery of the conductive film 30, excluding the upper surface.

[0077] The charge storage film 32 of the memory structure MS covers a portion of the side surface of the insulating film 31 in the same layer as the semiconductor layer 22. The insulating film 33 of the memory structure MS covers a portion of the side surface of the charge storage film 32 in the same layer as the semiconductor layer 22. The insulating film 33 is in contact with the semiconductor layer 22.

[0078] 1.1.4.4 Cross-sectional structure of conductive pillar SGP Figure 5 is a cross-sectional view along the VV line in Figure 3, showing an example of the cross-sectional structure of the memory cell array 10.

[0079] As shown in Figure 5, the memory cell array 10 further includes conductive pillar SGPs. The structure other than the conductive pillar SGPs is equivalent to the structure shown in Figure 4, and therefore its explanation is omitted.

[0080] The conductive pillar SGP extends in the Z direction so as to intersect with multiple semiconductor layers 22 and insulating layers 23. For example, the lower end of the conductive pillar SGP reaches the insulating layer 21. The upper end of the conductive pillar SGP aligns with the upper end of the uppermost insulating layer 23. The conductive pillar SGP functions as a selected gate decode line SGD by being electrically connected to the low decoder module 15 via a conductor (not shown) provided above it.

[0081] Within the same layer as the semiconductor layer 22, a portion of the side surface of the conductive pillar SGP is in contact with the insulator 34. The portion of the side surface of the conductive pillar SGP within the same layer as the semiconductor layer 22 that is not in contact with the insulator 34 is in contact with the semiconductor layer 22.

[0082] The conductive film 40 of the conductive pillar SGP extends in the Z direction. For example, the lower end of the conductive film 40 is located below the lowest semiconductor layer 22. The upper end of the conductive film 40 aligns with the upper end of the uppermost insulating layer 23. The insulating film 41 of the conductive pillar SGP covers the periphery of the conductive film 40, excluding the upper surface.

[0083] 1.1.4.5 Cross-sectional structure of conductive pillar TRP Figure 6 is a cross-sectional view along the line VI-VI in Figure 3, showing an example of the cross-sectional structure of the memory cell array 10.

[0084] As shown in Figure 6, the memory cell array 10 further includes conductive pillar TRPs. The structure other than the conductive pillar TRPs is equivalent to the structure shown in Figure 4, and therefore its explanation is omitted.

[0085] The conductive pillar TRP extends in the Z direction so as to intersect with multiple semiconductor layers 22 and insulating layers 23. For example, the lower end of the conductive pillar TRP reaches the insulating layer 21. The upper end of the conductive pillar TRP aligns with the upper end of the uppermost insulating layer 23. The conductive pillar TRP functions as a word line WL by being electrically connected to the row decoder module 15 via a conductor (not shown) provided above it.

[0086] Within the same layer as the semiconductor layer 22, a portion of the side surface of the conductive pillar TRP is in contact with the insulator 34. The portion of the side surface of the conductive pillar TRP in the same layer as the semiconductor layer 22 that is not in contact with the insulator 34 is in contact with the semiconductor layer 22.

[0087] The conductive film 50 of the conductive pillar TRP extends in the Z direction. For example, the lower end of the conductive film 50 is located below the lowest semiconductor layer 22. The upper end of the conductive film 50 aligns with the upper end of the uppermost insulating layer 23. The insulating film 51 of the conductive pillar TRP covers the periphery of the conductive film 50, excluding the upper surface.

[0088] 1.1.4.6 Cross-sectional structure of contact plug BC Figure 7 is a cross-sectional view along line VII-VII in Figure 3, showing an example of the cross-sectional structure of the memory cell array 10.

[0089] As shown in Figure 7, the memory cell array 10 further includes a contact plug BC. The structure other than the contact plug BC is equivalent to the structure shown in Figure 4, and therefore its explanation is omitted.

[0090] The contact plug BC extends in the Z direction so as to intersect with multiple semiconductor layers 22 and insulating layers 23. For example, the lower end of the contact plug BC reaches the insulating layer 21. The upper end of the contact plug BC aligns with the upper end of the uppermost insulating layer 23. The contact plug BC functions as a contact plug for supplying voltage to the conductive film 60 via a conductor (not shown) provided above it.

[0091] Within the same layer as the semiconductor layer 22, a portion of the side surface of the contact plug BC is in contact with the insulator 34. The portion of the side surface of the contact plug BC within the same layer as the semiconductor layer 22 that is not in contact with the insulator 34 is in contact with the semiconductor layer 22.

[0092] The conductive film 60 of the contact plug BC extends in the Z direction. For example, the lower end of the conductive film 60 is located below the lowest semiconductor layer 22. The upper end of the conductive film 60 aligns with the upper end of the uppermost insulating layer 23. The semiconductor film 61 of the contact plug BC covers the periphery of the conductive film 60, excluding its upper surface.

[0093] 1.2 Writing Operation First, let's explain the overview of the writing operation.

[0094] The write operation includes a program operation and a verify operation. By repeating the program loop, which includes the program operation and the verify operation, the threshold voltage of the memory cell transistor MT is raised to the target level.

[0095] Program operation is an operation that increases the threshold voltage by injecting electrons into the charge storage film (or maintains the threshold voltage by prohibiting injection). Hereinafter, the operation that increases the threshold voltage will be referred to as the "0 program". The bit line BL targeted for the "0 program" is supplied with a voltage for the "0 program" (e.g., voltage VSS) from the sense amplifier module 16. On the other hand, the operation that maintains the threshold voltage will be referred to as the "1 program" or "write disable". The bit line BL targeted for the "1 program" is supplied with a voltage for the "1 program" from the sense amplifier module 16.

[0096] The verification operation is performed after the program operation to read the data and determine whether the threshold voltage of the memory cell transistor MT has reached the target level. If the threshold voltage of the memory cell transistor MT has reached the target level, it is then disabled for writing.

[0097] Next, the write operation of the semiconductor memory device 3 according to the first embodiment will be described. The write operation of the semiconductor memory device 3 according to this embodiment includes a write operation to the memory string (hereinafter referred to as the "first write operation").

[0098] For example, when the memory controller 2 receives a write request from the host, the write operation is initiated, and the memory controller 2 instructs the semiconductor memory device 3 to perform the first write operation.

[0099] Next, the sequencer 13 executes a first write operation based on instructions received from the memory controller 2. More specifically, in the selection block BLK, a program loop is repeated for memory cell transistors MT corresponding to conductive pillars CGP that function as selected word lines WL in all first strings NSa within the string unit SU corresponding to the selected selection gate decode line SGDa. Hereinafter, conductive pillars CGP that function as selected word lines WL will also be referred to as "selected CG pillars CGPsel". Conductive pillars CGP that function as unselected word lines WL will also be referred to as "unselected CG pillars CGPusel".

[0100] In the first write operation, during program operation, a voltage VPGMe is applied to the conductive film 30 of the selected CG pillar CGPsel in all first strings NSa in the selected string unit SU. The voltage VPGMe is a high voltage capable of raising the threshold voltage of the memory cell transistor MT. The voltage VPGMe is stepped up, for example, in accordance with the iteration of the program loop.

[0101] In this state, the sense amplifier module 16 applies, for example, a voltage VSS to the bit line BL designated as "0" and, for example, a power supply voltage VCC to the bit line BL designated as "1". That is, voltage VSS or voltage VCC is applied to the wiring BLI via the bit line BL.

[0102] Then, in the selection string unit SU, data is written to the memory cell transistor MT corresponding to the selected CG pillar CGPsel in all first strings NSa connected to the bit line BL that was programmed as "0". On the other hand, the data in the memory cell transistor MT corresponding to the selected CG pillar CGPsel in all first strings NSa connected to the bit line BL that was programmed as "1" is maintained.

[0103] After the program operation is executed, the verification operation is performed. Thereafter, the program loop is repeated in the same manner. In the selection string unit SU, when all memory cell transistors MT corresponding to the selected CG pillar CGPsel in the first string NSa are set to write-protected, the program loop for the memory cell transistors MT corresponding to the selected CG pillar CGPsel terminates.

[0104] For example, in the first string NSa, conductive pillars CGP0e to CGP7e are selected in the order of CGP7e, CGP6e, ..., CGP1e, CGP0e. When the program loop for each conductive pillar CGP finishes, the first write operation ends. In this way, the data is written to the first string NSa. When the first write operation ends, the write operation ends.

[0105] 1.3 Read Operation The read operation of the semiconductor memory device 3 according to the first embodiment will now be described. The read operation of the semiconductor memory device 3 according to this embodiment includes a first read operation. In the first read operation, no cell current is supplied to the memory cell transistor MT corresponding to the non-selected CG pillar CGPusel and the transistor TR corresponding to the conductive pillar TRP located near the selected CG pillar CGPsel, while cell current is supplied to the transistor TR corresponding to the conductive pillar TRP not located near the selected CG pillar CGPsel.

[0106] For example, when the memory controller 2 receives a read request from the host, the read operation is initiated, and the memory controller 2 instructs the semiconductor storage device 3 to perform a first read operation.

[0107] Next, the sequencer 13 performs a first read operation based on instructions received from the memory controller 2. Figure 8 shows the voltages of each wire during the first read operation. In the example in Figure 8, multiple memory cell transistors MT4e in the selection string unit SU are selected as read targets in the selection block BLK, and a memory cell transistor MT4e in one NAND string NS is turned ON.

[0108] As shown in Figure 8, during the first read operation, the following voltages are applied to each conductive pillar SGP and CGP in the first string NSa by the row decoder module 15.

[0109] A voltage VSG is applied to the conductive film 40 of each conductive pillar SGP0e, which functions as a select gate decode line SGDa, and conductive pillar SGP1e, which functions as a select gate decode line SGDb. The voltage VSG is a voltage that turns on the select transistor ST1 regardless of the voltage of the corresponding bit line BL. Hereinafter, the conductive pillar SGP that functions as the selected select gate decode line SGDa will also be referred to as the "select SG pillar SGPsel". A voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP4e (select CG pillar CGPsel), which functions as a word line WL4e (select word line WL). The voltage VCGRV is a read voltage corresponding to the threshold voltage level of the read data. A voltage Vcut is applied to each conductive film 30 of the conductive pillars CGP0e to CGP3e and CGP5e to CGP7e, which function as word lines WL0e to WL3e and WL5e to WL7e (non-selected word lines WL), respectively. The voltage Vcut is a voltage that puts the memory cell transistors MT and TR into a cutoff state, regardless of the threshold voltage. For example, the voltage Vcut may be a negative voltage.

[0110] Furthermore, during the first read operation, the following voltages are applied to each conductive pillar SGP and TRP within the NAND string NSb by the raw decoder module 15.

[0111] A voltage VSG is applied to the conductive film 40 of conductive pillars SGP0o and SGP1o, which function as select gate decode lines SGSa and SGSb, respectively. A voltage Vcut is applied to the conductive film 50 of conductive pillars TRP3 and TRP4, which function as word lines WL3o and WL4o, respectively. Conductive pillars TRP3 and TRP4 are conductive pillar TRPs located on the back side of the semiconductor CPS and in the vicinity of the select CG pillar CGPsel. More specifically, conductive pillars TRP3 and TRP4 are two conductive pillar TRPs on the back side of the semiconductor CPS, located in the +Y and -Y directions, respectively, from the position opposite the select CG pillar CGPsel on the front side of the semiconductor CPS in the X direction. Hereinafter, a conductive pillar located on the opposite side of the semiconductor CPS from the select CG pillar CGPsel in the X direction and in the vicinity of the select CG pillar CGPsel will also be referred to as the "cutoff pillar Pcut". A voltage, for example, Vread, is applied to the conductive film 50 of each of the conductive pillars TRP0 to TRP2 and TRP5 to TRP7, which function as word lines WL0o to WL2o and WL5o to WL7o, respectively. Voltage Vread is the voltage that turns on the transistor TR, regardless of the threshold voltage. Voltage Vread is a higher voltage than voltage VCGRV. Hereinafter, conductive pillars located on the opposite side of the semiconductor CPS's selectable CG pillar CGPsel in the X direction and not in the vicinity of the selectable CG pillar CGPsel will also be referred to as "non-cutoff pillars Pucut".

[0112] In this state, the sense amplifier module 16 applies a voltage Vbl to the bit line BL to be read. That is, the voltage Vbl is applied to the wiring BLI via the bit line BL. Also, the voltage VSS is applied to the source line SL. The voltage Vbl is a higher voltage than the voltage VSS.

[0113] In a semiconductor CPS, a conduction region, i.e., a channel region, is formed near the portion in contact with each conductive pillar SGP (conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o) to which the voltage VSG is applied. No conduction region is formed near the portions in contact with each conductive pillar CGP and TRP (conductive pillars CGP0e~CGP3e, CGP5e~CGP7e, TRP3, and TRP4) to which the voltage Vcut is applied. A conduction region is formed near the portions in contact with each conductive pillar TRP (conductive pillars TRP0~TRP2, and TRP5~TRP7) to which the voltage Vread is applied. When the selective memory cell transistor MT4e is ON, a conduction region is formed near the portion in contact with the conductive pillar CGP (conductive pillar CGP4e) to which the voltage VCGRV is applied. On the other hand, when the selective memory cell transistor MT4e is OFF, no conduction region is formed.

[0114] Furthermore, because the width (distance in the X direction) of the semiconductor CPS is relatively small, a conductive region is also formed in the semiconductor CPS between the conductive region formed near the conductive pillar SGP1e and the conductive region formed near the conductive pillar TRP7. When the selective memory cell transistor MT4e is ON, a conductive region is also formed between the conductive region formed near the conductive pillar TRP5 and the conductive region formed near the selective CG pillar CGPsel, and between the conductive region formed near the selective CG pillar CGPsel and the conductive region formed near the conductive pillar TRP2.

[0115] Because the semiconductor film 61 of the contact plug BC (for example, polysilicon containing P-type impurities) is in contact with the semiconductor CPS, a conductive region is not formed in the vicinity of the part of the semiconductor CPS that is in contact with the contact plug BC.

[0116] Therefore, when the selective memory cell transistor MT4e is ON, as shown in Figure 8, the wiring LBI and the source line SL are electrically connected by the conductive region of the semiconductor CPS. As a result, electron current flows from the wiring LBI to the source line SL. On the other hand, when the selective memory cell transistor MT4e is OFF, the wiring LBI and the source line SL are not electrically connected. As a result, in the selective string unit SU, the data of the memory cell transistor MT corresponding to the selected CG pillar CGPsel in all first strings NSa is read out all at once.

[0117] For example, in the first string NSa, conductive pillars CGP0e to CGP7e are selected in the order of CGP7e, CGP6e, ..., CGP1e, CGP0e. Once reading for each conductive pillar CGP is complete, the first read operation ends. This completes the read operation.

[0118] When the memory cell transistor MT7e is the target of readout, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. A voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP7e (selected CG pillar CGPsel). A voltage Vcut is applied to the conductive film 30 of each of the conductive pillars CGP0e to CGP6e, and to the conductive film 50 of each of the conductive pillars TRP6 and TRP7. A voltage Vread is applied to the conductive film 50 of each of the conductive pillars TRP0 to TRP5.

[0119] Furthermore, when the memory cell transistor MT0e is the target of readout, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. A voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP0e (selected CG pillar CGPsel). A voltage Vcut is applied to the conductive film 30 of each of the conductive pillars CGP1e to CGP7e, and the conductive film 50 of the conductive pillar TRP0. A voltage Vread is applied to the conductive film 50 of each of the conductive pillars TRP1 to TRP7.

[0120] 1.4 Effects of this embodiment During a read operation, if a voltage Vread is applied to a non-selected word line WL connected in series with a selected word line WL, read disturbance may occur. In this case, the cell tolerance of the memory cell transistor MT corresponding to the non-selected word line WL may be reduced.

[0121] In contrast, the semiconductor memory device 3 according to this embodiment includes a plurality of NAND strings, each spaced apart from each other in the Z direction. Each of the plurality of NAND strings NS includes a semiconductor CPS extending in the Y direction, a first string NSa located on the front side of the semiconductor CPS, and a second string NSb located on the back side of the semiconductor CPS. Each of the first strings NSa includes selection transistors ST1a and ST1b, and memory cell transistors MT0e to MT7e, each with the semiconductor CPS as a channel and spaced apart from each other in the Y direction. Each of the second strings NSb includes transistors TR0 to TR7, and selection transistors ST2a and ST2b, each with the semiconductor CPS as a channel and spaced apart from each other in the Y direction.

[0122] As described above, in the semiconductor memory device 3 according to this embodiment, in the NAND string NS, the first string NSa and the second string NSb are arranged with the semiconductor CPS in between, the first string NSa is used as the memory string and the second string NSb is used as the read string.

[0123] Because of the above configuration, as described with reference to Figure 8, during a read operation, in the first string NSa, cell current can be supplied to the memory cell transistor MT corresponding to the selected CG pillar CGPsel, while cell current can not be supplied to the memory cell transistor MT corresponding to the unselected CG pillar CGPusel. Furthermore, in the second string NSb, cell current can not be supplied to the memory cell transistor MT corresponding to the cutoff pillar Pcut, while cell current can be supplied to the memory cell transistor MT corresponding to the non-cutoff pillar Pucut. As a result, no cell current flows to the memory cell transistor MT corresponding to the unselected CGPusel. Therefore, according to the semiconductor memory device 3 of this embodiment, a memory cell with high read endurance can be realized.

[0124] Furthermore, because no cell current flows through the memory cell transistors MT corresponding to the two cutoff pillars Pcut located on the back side of the semiconductor CPS and near the selected CG pillar CGPsel, the data from the memory cell transistors MT corresponding to the selected CG pillar CGPsel can be read out appropriately.

[0125] Furthermore, since the second string NSb is equipped with a transistor TR that is more efficient than the memory cell transistor MT, it is easier to obtain cell current.

[0126] Furthermore, if the conductive pillar TRP within the second string NSb has the same structure as the conductive pillar SGP, the conductive pillar TRP and SGP can be formed simultaneously during the manufacturing process.

[0127] 1.5 Variations A modified semiconductor memory device 3A of the first embodiment will now be described. In this modified semiconductor memory device 3A, the circuit configuration of the memory cell array 10A, the planar layout of the memory cell array 10A, and the read operation differ from those of the first embodiment. The following will focus on the differences from the first embodiment.

[0128] 1.5.1 Circuit configuration of memory cell array The circuit configuration of the memory cell array 10A will be explained using Figure 9. Figure 9 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10A. Figure 9 shows the circuit configuration of a block BLK included in the memory cell array 10A as an example of the circuit configuration of the memory cell array 10A. Other block BLKs have a similar configuration to that shown in Figure 9.

[0129] The first string NSa includes, for example, memory cell transistors MT0e to MT7e, and selection transistors ST1a, ST1b, and ST2c. The second string NSb includes, for example, transistors TR0 to TR7, and selection transistors ST2a, ST2b, and ST1c. Selection transistors ST1c and ST2c are switching elements.

[0130] In the NAND string NS, memory cell transistors MT0e to MT7e are connected in series. One end of the series-connected memory cell transistors MT0e to MT7e (one end of memory cell transistor MT7e) is connected to the source of selection transistor ST1b. The drain of selection transistor ST1b is connected to the source of selection transistor ST1a. The drain of selection transistor ST1a is connected to the associated bit line BL. The source of selection transistor ST1c is connected to the drain of selection transistor ST1b. The drain of selection transistor ST1c is connected to the associated bit line BL. The other end of the series-connected memory cell transistors MT0e to MT7e (the other end of memory cell transistor MT0e) is connected to the drain of selection transistor ST2b. Transistors TR0 to TR7 are connected in series. One end of the series-connected transistors TR0 to TR7 (one end of transistor TR7) is connected to the source of selection transistor ST1b. The other end of the series-connected transistors TR0 to TR7 (the other end of transistor TR0) is connected to the drain of selection transistor ST2b. The source of selection transistor ST2b is connected to the drain of selection transistor ST2a. The source of selection transistor ST2a is connected to source wire SL. The drain of selection transistor ST2c is connected to the drain of selection transistor ST2a. The source of selection transistor ST2c is connected to source wire SL.

[0131] Furthermore, in the NAND string NS, one end of memory cell transistor MT6e is connected to one end of transistor TR6. One end of memory cell transistor MT5e is connected to one end of transistor TR5. One end of memory cell transistor MT4e is connected to one end of transistor TR4. One end of memory cell transistor MT3e is connected to one end of transistor TR3. One end of memory cell transistor MT2e is connected to one end of transistor TR2. One end of memory cell transistor MT1e is connected to one end of transistor TR1. One end of memory cell transistor MT0e is connected to one end of transistor TR0.

[0132] Within the same block BLK, the gates of each selection transistor ST1c in string units SU0 to SU3 are connected to selection gate decode lines SGD0c to SGD3c, respectively. Furthermore, selection gate decode line SGD0c is connected to selection gate decode line SGD0a. Selection gate decode line SGD1c is connected to selection gate decode line SGD1a. Selection gate decode line SGD2c is connected to selection gate decode line SGD2a. Selection gate decode line SGD3c is connected to selection gate decode line SGD3a. Hereafter, when selection gate decode lines SGD0c to SGD3c are not distinguished, they will simply be referred to as selection gate decode line SGDc. The gate of selection transistor ST2c included in the same block BLK is connected to selection gate decode line SGSc. Furthermore, selection gate decode line SGSc is connected to selection gate decode line SGSa.

[0133] Furthermore, the circuit configuration of the memory cell array 10A is not limited to the configuration described above. For example, the number of string units SU included in block BLK, and the number of memory cell transistors MT, TR, and selection transistors ST1 and ST2 included in NAND string NS can each be any number.

[0134] 1.5.2 Planar layout of memory cell array Figure 10 is a plan view showing an example of the planar layout of the memory cell array 10A. In Figure 10, the plan view of the layer of block BLK that is approximately equal in height to the substrate is shown. The portion shown in Figure 10 corresponds to one NAND string NS in the circuit diagram shown in Figure 9.

[0135] As shown in Figure 10, within the same layer, the memory cell array 10A includes a semiconductor CPS, wiring LBI, source line SL, multiple insulators INS, multiple conductive pillars CGP, SGP, and TRP, multiple memory structures MS, and multiple contact plugs BC.

[0136] The planar layout of the semiconductor CPS, wiring LBI, source line SL, and insulator INS is the same as that shown in Figure 3 of the first embodiment.

[0137] A first string NSa is arranged on the front side of the semiconductor CPS. Within the first string NSa, for example, two conductive pillars SGP, eight conductive pillars CGP, one contact plug BC, and one conductive pillar SGP are arranged in the Y direction, starting from the top of the paper. Each of the two conductive pillars SGP, eight conductive pillars CGP, one contact plug BC, and one conductive pillar SGP is spaced apart from each other in the Y direction. Hereafter, the three conductive pillars SGP will also be referred to as conductive pillars SGP0e, SGP1e, and SGP2e, starting from the top of the paper.

[0138] A second string NSb is located on the back side of the semiconductor CPS. Within the second string NSb, for example, along the Y direction, from the top of the paper, one conductive pillar SGP, one contact plug BC, eight conductive pillars TRP, and two conductive pillars SGP are arranged. Each of the one conductive pillar SGP, one contact plug BC, eight conductive pillars TRP, and two conductive pillars SGP are spaced apart from each other in the Y direction. Hereafter, the three conductive pillars SGP will also be referred to as conductive pillars SGP0o, SGP1o, and SGP2o, respectively, from the bottom of the paper.

[0139] In a top view, each of the two conductive pillars SGP, eight conductive pillars CGP, one contact plug BC, and one conductive pillar SCP on the front side of the semiconductor CPS, and each of the one conductive pillar SGP, eight conductive pillars TRP, one contact plug BC, and two conductive pillars SCP on the back side of the semiconductor CPS, are facing each other in the X direction.

[0140] On the front side of the semiconductor CPS, the conductive pillar SGP2e has the same structure as the other conductive pillars SGP. The structures of the two conductive pillars SGP, eight conductive pillars CGP, and one contact plug BC, excluding conductive pillar SGP2e, are the same as those shown in Figure 3 of the first embodiment. The above structure, including the semiconductor CPS and the three conductive pillars SGP, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC on the front side of the semiconductor CPS, corresponds to the first string NSa.

[0141] On the back side of the semiconductor CPS, the conductive pillar SGP2o has the same structure as the other conductive pillars SGP. The structures of the two conductive pillars SGP, eight conductive pillars TRP, and one contact plug BC, excluding conductive pillar SGP2o, are the same as those shown in Figure 3 of the first embodiment. The above structure, including the semiconductor CPS and the three conductive pillars SGP, eight conductive pillars TRP, and one contact plug BC on the back side of the semiconductor CPS, corresponds to the second string NSb.

[0142] Multiple NAND strings NS connected to the same bit line BL are arranged, for example, in the same manner as in the first embodiment.

[0143] 1.5.3 Three-dimensional structure of memory cell array The three-dimensional structure of the memory cell array 10A will now be described. The three-dimensional structure of the memory cell array 10A has a planar layout as shown in Figure 10, in which the elements are spaced apart from each other in the Z direction. That is, the multiple NAND strings NS are spaced apart from each other in the Z direction.

[0144] 1.5.4 Writing Operation The writing operation of the semiconductor memory device 3A according to a modification of the first embodiment is the same as the writing operation described in the first embodiment.

[0145] 1.5.5 Read Operation A read operation of the semiconductor memory device 3A according to a modification of the first embodiment will be described. The read operation of the semiconductor memory device 3A according to the modification of this embodiment includes a first read operation.

[0146] Figure 11 shows the voltage across each wire during the first read operation. In the example in Figure 11, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets in the selection block BLK, and one memory cell transistor MT4e within the NAND string NS is turned ON.

[0147] As shown in Figure 11, during the first read operation, the following voltages are applied to each conductive pillar SGP and CGP in the first string NSa.

[0148] For example, a voltage VSG is applied to the conductive film 40 of each conductive pillar SGP0e, SGP1e, and SGP2e, which function as the selected gate decode lines SGDa, SGDb, and SGSc, respectively. For example, a voltage VCGRV is applied to the conductive film 30 of conductive pillar CGP4e. For example, a voltage Vcut is applied to the conductive film 30 of each conductive pillar CGP0e to CGP3e and CGP5e to CGP7e.

[0149] Furthermore, during the first read operation, the following voltages are applied to each conductive pillar SGP and TRP within the NAND string NSb.

[0150] A voltage, for example, VSG is applied to the conductive film 40 of each conductive pillar SGP0o, SGP1o, and SGP2o, which function as the selected gate decode lines SGSa, SGSb, and SGDc, respectively. A voltage, for example, Vcut is applied to the conductive film 50 of conductive pillar TRP4. Conductive pillar TRP4 is a conductive pillar TRP located on the back side of the semiconductor CPS and in the vicinity of the selected CG pillar CGPsel. More specifically, conductive pillar TRP4 is a conductive pillar TRP on the back side of the semiconductor CPS, located in the X direction opposite the selected CG pillar CGPsel on the front side of the semiconductor CPS. A voltage, for example, Vread is applied to the conductive film 50 of each conductive pillar TRP0 to TRP3 and TRP5 to TRP7.

[0151] In this state, a voltage Vbl is applied to the bit line BL to be read, and a voltage VSS is applied to the source line SL.

[0152] In a semiconductor CPS, conductive regions are formed near the portions in contact with each of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. No conductive regions are formed near the portions in contact with each of the conductive pillars CGP0e~CGP3e, CGP5e~CGP7e, and TRP4. Conductive regions are formed near the portions in contact with each of the conductive pillars TRP0~TRP3 and TRP5~TRP7. When the selective memory cell transistor MT4e is ON, conductive regions are formed near the portions in contact with each of the conductive pillars CGP4e. On the other hand, when the selective memory cell transistor MT4e is OFF, no conductive regions are formed.

[0153] Furthermore, because the width of the semiconductor CPS is relatively small, conductive regions are also formed in the semiconductor CPS between the conductive region formed near conductive pillar SGP2o and the conductive region formed near conductive pillar SGP1e, between the conductive region formed near conductive pillar SGP1e and the conductive region formed near conductive pillar TRP7, and between the conductive region formed near conductive pillar SGP1o and the conductive region formed near conductive pillar SGP2e. When the selective memory cell transistor MT4e is ON, conductive regions are also formed between the conductive region formed near conductive pillar TRP5 and the conductive region formed near selective CG pillar CGPsel, and between the conductive region formed near selective CG pillar CGPsel and the conductive region formed near conductive pillar TRP3.

[0154] In semiconductor CPS, no conductive region is formed near the part in contact with the contact plug BC.

[0155] Therefore, when the selective memory cell transistor MT4e is ON, as shown in Figure 11, the wiring LBI and the source line SL are electrically connected, and an electron current flows from the wiring LBI to the source line SL. On the other hand, when the selective memory cell transistor MT4e is OFF, the wiring LBI and the source line SL are not electrically connected.

[0156] When the memory cell transistor MT7e is the target of readout, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. A voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP7e (selected CG pillar CGPsel). A voltage Vcut is applied to the conductive film 30 of each of the conductive pillars CGP0e to CGP6e, and the conductive film 50 of the conductive pillar TRP7. A voltage Vread is applied to the conductive film 50 of each of the conductive pillars TRP0 to TRP6.

[0157] Furthermore, when the memory cell transistor MT0e is the target of readout, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. A voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP0e (selected CG pillar CGPsel). A voltage Vcut is applied to the conductive film 30 of each of the conductive pillars CGP1e to CGP7e, and the conductive film 50 of the conductive pillar TRP0. A voltage Vread is applied to the conductive film 50 of each of the conductive pillars TRP1 to TRP7.

[0158] 1.5.6 Effects of this modified example This modified version achieves the same effects as the first embodiment.

[0159] Furthermore, as described with reference to Figure 11, during the readout operation, a conductive region is formed in the semiconductor CPS between the conductive region formed near the conductive pillar SGP2o and the conductive region formed near the conductive pillar SGP1e, thereby increasing the cell current.

[0160] 2. Second Embodiment The semiconductor memory device 3B according to the second embodiment will now be described. In the semiconductor memory device 3B according to the second embodiment, the circuit configuration of the second string NSb, the planar layout of the second string NSb, and the writing operation differ from those of the first embodiment. The following description will focus on the differences from the first embodiment.

[0161] 2.1 Circuit configuration of memory cell array The circuit configuration of the memory cell array 10B will be explained using Figure 12. Figure 12 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10B. Figure 12 shows the circuit configuration of a block BLK included in the memory cell array 10B as an example of the circuit configuration of the memory cell array 10B. Other block BLKs have a similar configuration to that shown in Figure 12.

[0162] As shown in Figure 12, the circuit configuration of the memory cell array 10B is the same as the circuit configuration shown in Figure 2 in the first embodiment, except that the transistors TR0 to TR7 in the second string NSb shown in Figure 2 are replaced with memory cell transistors MT0o to MT7o. The configuration of the memory cell transistors MT0o to MT7o is the same as that of the memory cell transistors MT0e to MT7e. The first string NSa is a memory string, and the second string NSb is a read string.

[0163] 2.2 Planar layout of memory cell array Figure 13 is a plan view showing an example of the planar layout of the memory cell array 10B. In Figure 13, the plan view of the layer of block BLK that is approximately equal in height from the substrate is shown. The portion shown in Figure 13 corresponds to one NAND string NS in the circuit diagram shown in Figure 12.

[0164] As shown in Figure 13, the planar layout of the memory cell array 10B is the same as the planar layout of Figure 3 shown in the first embodiment, except that the eight conductive pillars TRP in the second string NSb shown in Figure 3 are replaced with eight conductive pillars CGP and eight memory structures MS.

[0165] A second string NSb is located on the back side of the semiconductor CPS. Within the second string NSb, for example, along the Y direction, from the top of the paper in order, there is one contact plug BC, eight conductive pillars CGP, and two conductive pillars SGP. Each of the one contact plug BC, eight conductive pillars CGP, and two conductive pillars SGP is spaced apart from each other in the Y direction. Hereafter, the eight conductive pillars CGP will also be referred to as conductive pillars CGP0o to CGP7o, from the bottom of the paper in order.

[0166] On the back side of the semiconductor CPS, the conductive pillar CGP and memory structure MS have the same structure as the conductive pillar CGP and memory structure MS on the front side of the semiconductor CPS. The above structure, including one conductive pillar CGP, one memory structure MS, and the semiconductor CPS, functions as a memory cell transistor MT. The eight above structures shown in Figure 13 function as memory cell transistors MT7o, MT6o, MT5o, MT4o, MT3o, MT2o, MT1o, and MT0o, respectively, from the top of the page. The above structure, including the semiconductor CPS and the three conductive pillars SGP, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC on the back side of the semiconductor CPS, corresponds to the second string NSb.

[0167] Thus, the second string NSb includes memory cell transistors MT0o to MT7o, and selection transistors ST2a and ST2b, each having a semiconductor CPS as its channel and being spaced apart from each other in the Y direction.

[0168] Multiple NAND strings NS connected to the same bit line BL are arranged, for example, in the same manner as in the first embodiment.

[0169] 2.3 Three-dimensional structure of memory cell array The three-dimensional structure of the memory cell array 10B will now be described. The three-dimensional structure of the memory cell array 10B has a planar layout as shown in Figure 13, in which the elements are spaced apart from each other in the Z direction. That is, the multiple NAND strings NS are spaced apart from each other in the Z direction.

[0170] 2.4 Writing Operation The write operation of the semiconductor memory device 3B according to the second embodiment will now be described. The write operation of the semiconductor memory device 3B according to this embodiment includes a first write operation and a write operation to the read string (hereinafter referred to as the "second write operation"). Figure 14 is a flowchart showing an example of the write operation of the semiconductor memory device 3B according to this embodiment.

[0171] For example, when a write operation is initiated, the memory controller 2 instructs the semiconductor memory device 3B to perform a first write operation and a second write operation.

[0172] Next, the sequencer 13 performs a first write operation based on the instruction received from the memory controller 2 (S101). That is, the write data is written to the first string NSa.

[0173] Next, the sequencer 13 performs a second write operation based on the instructions received from the memory controller 2 (S102). More specifically, in the selection block BLK, the program loop is repeated for all memory cell transistors MT corresponding to the selected CG pillars CGPsel in the second string NSb within the selection string unit SU.

[0174] In the second write operation, during program operation, a voltage VPGMo is applied to the conductive film 30 of the selected CG pillar CGPsel in all second strings NSb in the selected string unit SU. The voltage VPGMo is a high voltage capable of raising the threshold voltage of the memory cell transistor MT. The voltage VPGMo is stepped up, for example, according to the iteration of the program loop.

[0175] In this state, for example, a voltage VSS is applied to the bit line BL designated as "0" for programming, and for example, a voltage VCC is applied to the bit line BL designated as "1" for programming.

[0176] Then, in the selection string unit SU, data is written to the memory cell transistor MT corresponding to the selected CG pillar CGPsel in all second strings NSb connected to the bit line BL that was programmed as "0". On the other hand, the data in the memory cell transistor MT corresponding to the selected CG pillar CGPsel in all second strings NSb connected to the bit line BL that was programmed as "1" is maintained.

[0177] After the program operation is executed, the verification operation is performed. From there, the program loop is repeated, similar to the first write operation.

[0178] For example, in the second string NSb, conductive pillars CGP0o to CGP7o are selected in the order of CGP7o, CGP6o, ..., CGP1o, CGP0o. When the program loop for each conductive pillar CGP is completed, the second write operation is completed. For example, data that is relatively resistant to read disturb and retention is written to the second string NSb. Such data is, for example, data at the write level in SLC or equivalent. In other words, predetermined data is written to the second string NSb. When the second write operation is completed, the write operation is completed.

[0179] Note that the data written to the read string may or may not be erased during the erase operation. If it is erased, the second write operation can be performed again during the write operation after erasure to write the data as described above, thus restoring the state where the data has been written. On the other hand, if it is not erased, the written data is retained, so the second write operation can be omitted during the write operation after erasure to prevent the data from being written.

[0180] 2.5 Read Operation The read operation of the semiconductor memory device 3B according to the second embodiment will now be described. The read operation of the semiconductor memory device 3B according to this embodiment includes a first read operation. In the first read operation, no cell current is supplied to the memory cell transistor MT corresponding to the non-selected CG pillar CGPusel and the memory cell transistor MT corresponding to the conductive pillar CGPo located near the selected CG pillar CGPsel, while cell current is supplied to the memory cell transistor MT corresponding to the conductive pillar CGPo not located near the selected CG pillar CGPsel.

[0181] Figure 15 shows the voltage across each wiring during the first read operation. In the example in Figure 15, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets in the selection block BLK, and one memory cell transistor MT4e within the NAND string NS is turned ON.

[0182] As shown in Figure 15, the voltage of each wire during the first read operation is the same as the voltage of each wire during the first read operation shown in Figure 8 in the first embodiment, except that the application of voltage to the eight conductive pillars TRP in the second string NSb shown in Figure 8 is replaced by the application of voltage to the eight conductive pillars CGP.

[0183] A voltage Vcut is applied to the conductive film 30 of each conductive pillar CGP3o and CGP4o, which function as word lines WL3o and WL4o, respectively. Conductive pillars CGP3o and CGP4o are conductive pillars CGPo located on the back side of the semiconductor CPS and in the vicinity of the selected CG pillar CGPsel. More specifically, conductive pillars CGP3o and CGP4o are two conductive pillars CGPo on the back side of the semiconductor CPS, located in the +Y and -Y directions, respectively, from the position facing the selected CG pillar CGPsel on the front side of the semiconductor CPS in the X direction. A voltage Vread is applied to the conductive film 30 of each conductive pillar CGP0o to CGP2o and CGP5o to CGP7o, which function as word lines WL0o to WL2o and WL5o to WL7o, respectively. Voltage Vread is a voltage that turns on the memory cell transistor MT, regardless of the threshold voltage. The voltage Vread is a higher voltage than the voltage VCGRV.

[0184] In the semiconductor CPS, a conductive region is formed, similar to the first embodiment. Therefore, when the selective memory cell transistor MT4e is ON, the wiring LBI and the source line SL are electrically connected, as shown in Figure 15, and an electron current flows from the wiring LBI to the source line SL. On the other hand, when the selective memory cell transistor MT4e is OFF, the wiring LBI and the source line SL are not electrically connected.

[0185] 2.6 Effects according to this embodiment According to the second embodiment, the same effects as the first embodiment are achieved.

[0186] Furthermore, since the conductive pillar CGP in the first string NSa has the same structure as the conductive pillar CGP in the second string NSb, these conductive pillar CGPs can be formed simultaneously during the manufacturing process.

[0187] Furthermore, since data that is relatively resistant to read disturbance and retention is written to the second string NSb, a memory cell with high read endurance can be realized.

[0188] 2.7 Variations A modified semiconductor memory device 3C of the second embodiment will now be described. In this modified semiconductor memory device 3C, the circuit configuration of the memory cell array 10C, the planar layout of the memory cell array 10C, and the read operation differ from those of the second embodiment. The following will focus on the differences from the second embodiment.

[0189] 2.7.1 Circuit configuration of memory cell array The circuit configuration of the memory cell array 10C will be explained using Figure 16. Figure 16 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10C. Figure 16 shows the circuit configuration of a block BLK included in the memory cell array 10C as an example of the circuit configuration of the memory cell array 10C. Other block BLKs have a similar configuration to that shown in Figure 16.

[0190] As shown in Figure 16, the circuit configuration of the memory cell array 10C is the same as the circuit configuration in Figure 9 shown in the modified example of the first embodiment, except that the transistors TR0 to TR7 in the second string NSb shown in Figure 9 are replaced with memory cell transistors MT0o to MT7o. The configuration of the memory cell transistors MT0o to MT7o is the same as that of the memory cell transistors MT0e to MT7e. The first string NSa is a memory string, and the second string NSb is a read string.

[0191] 2.7.2 Planar layout of memory cell array Figure 17 is a plan view showing an example of the planar layout of the memory cell array 10C. In Figure 17, the plan view of the layer of block BLK that is approximately equal in height to the substrate is shown. The portion shown in Figure 17 corresponds to one NAND string NS in the circuit diagram shown in Figure 16.

[0192] As shown in Figure 17, the planar layout of the memory cell array 10C is the same as the planar layout of Figure 10 shown in the modification of the first embodiment, except that the eight conductive pillars TRP in the second string NSb shown in Figure 10 are replaced with eight conductive pillars CGP and eight memory structures MS.

[0193] A second string NSb is positioned on the back side of the semiconductor CPS. Within the second string NSb, for example, along the Y direction, from the top of the paper, one conductive pillar SGP, one contact plug BC, eight conductive pillars CGP, and two conductive pillars SGP are arranged in that order. Each of the one conductive pillar SGP, one contact plug BC, eight conductive pillars CGP, and two conductive pillars SGP are spaced apart from each other in the Y direction.

[0194] On the back side of the semiconductor CPS, the conductive pillar CGP and memory structure MS have the same structure as the conductive pillar CGP and memory structure MS on the front side of the semiconductor CPS. The above structure, including one conductive pillar CGP, one memory structure MS, and the semiconductor CPS, functions as a memory cell transistor MT. The eight above structures shown in Figure 17 function as memory cell transistors MT7o, MT6o, MT5o, MT4o, MT3o, MT2o, MT1o, and MT0o, in order from the top of the page. The above structure, including the semiconductor CPS and the three conductive pillars SGP, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC on the back side of the semiconductor CPS, corresponds to the second string NSb.

[0195] Multiple NAND strings NS connected to the same bit line BL are arranged, for example, in the same manner as in the first embodiment.

[0196] 2.7.3 Three-dimensional structure of memory cell array The three-dimensional structure of the memory cell array 10C will now be described. The three-dimensional structure of the memory cell array 10C has a planar layout as shown in Figure 17, in which the elements are spaced apart from each other in the Z direction. That is, the multiple NAND strings NS are spaced apart from each other in the Z direction.

[0197] 2.7.4 Writing Operation The writing operation of the semiconductor memory device 3C according to the modified version of the second embodiment is the same as the writing operation described in the second embodiment.

[0198] 2.7.5 Read Operation The read operation of the semiconductor memory device 3C according to a modified example of the second embodiment will now be described. The read operation of the semiconductor memory device 3C according to the modified example of this embodiment includes a first read operation.

[0199] Figure 18 shows the voltage across each wire during the first read operation. In the example in Figure 18, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets in the selection block BLK, and one memory cell transistor MT4e within the NAND string NS is turned ON.

[0200] As shown in Figure 18, the voltage of each wire during the first read operation is the same as the voltage of each wire during the first read operation shown in Figure 11, which is a modified example of the first embodiment, except that the application of voltage to the eight conductive pillars TRP in the second string NSb shown in Figure 11 is replaced by the application of voltage to the eight conductive pillars CGP.

[0201] A voltage Vcut is applied to the conductive film 30 of conductive pillar CGP4o. Conductive pillar CGP4o is a conductive pillar CGPo located on the back side of the semiconductor CPS and in the vicinity of the selected CG pillar CGPsel. More specifically, conductive pillar CGP4o is a conductive pillar CGPo on the back side of the semiconductor CPS, located in the X direction opposite the selected CG pillar CGPsel on the front side of the semiconductor CPS. A voltage Vread is applied to the conductive film 30 of each of the conductive pillars CGP0o to CGP3o and CGP5o to CGP7o.

[0202] In the semiconductor CPS, a conductive region is formed, similar to the modified example of the first embodiment. Therefore, when the selective memory cell transistor MT4e is ON, the wiring LBI and the source line SL are electrically connected, as shown in Figure 18, and an electron current flows from the wiring LBI to the source line SL. On the other hand, when the selective memory cell transistor MT4e is OFF, the wiring LBI and the source line SL are not electrically connected.

[0203] 2.7.6 Effects of this modified example This modified version achieves the same effects as the second embodiment.

[0204] Furthermore, similar to the modification of the first embodiment, the cell current can be increased.

[0205] 3. Third Embodiment A semiconductor memory device 3D according to the third embodiment will now be described. The semiconductor memory device 3D according to this embodiment differs from the second embodiment in that the memory string and the read string can be switched in block units (BLK). The circuit configuration of the memory cell array 10D is the same as that shown in Figure 12 of the second embodiment. Of the first string NSa and the second string NSb, one is the memory string and the other is the read string. The planar layout of the memory cell array 10D is the same as that shown in Figure 13 of the second embodiment. The following description will focus on the differences from the second embodiment.

[0206] 3.1 String Flags In this embodiment, in the NAND string NS within block BLK, a string flag flgS is used as information indicating which of the first string NSa and the second string NSb is the memory string (hereinafter referred to as "string information"). The string flag flgS will be explained with reference to Figure 19. Figure 19 is a diagram illustrating the string flag flgS used in the semiconductor memory device 3D according to this embodiment.

[0207] As shown in Figure 19, each block BLK stores a string flag flgS in the memory cell transistor MT within the memory area. For example, if the first string NSa is a memory string, "0" is stored as the string flag flgS, and if the second string NSb is a memory string, "1" is stored.

[0208] 3.2 Writing Operation The writing operation of the semiconductor memory device 3D according to the third embodiment will now be described. The writing operation of the semiconductor memory device 3D according to this embodiment includes a first writing operation and a second writing operation. Figure 20 is a flowchart showing an example of the writing operation of the semiconductor memory device 3D according to this embodiment.

[0209] For example, when a write operation is initiated, the memory controller 2 accesses the semiconductor memory device 3D and obtains the string flag flgS from the selected block BLK (S201).

[0210] Next, the memory controller 2 swaps the memory string and the read string based on the string flag flgS (S202). This determines the swapped memory string and read string.

[0211] Next, the memory controller 2 instructs the semiconductor memory device 3D to perform a first write operation on the replaced memory string and a second write operation on the replaced read string.

[0212] Next, the sequencer 13 performs a first write operation based on the instruction received from the memory controller 2 (S203). During the first write operation, the sequencer 13 also writes (updates) the string flag flgS in the selected block BLK.

[0213] Next, the sequencer 13 performs a second write operation based on the instructions received from the memory controller 2 (S204). Once the second write operation is complete, the write operation ends.

[0214] Thus, of the first string NSa and the second string NSb, the string to which the write data is written is periodically switched on a block-by-block basis.

[0215] In the example described above, the string to which the data is written is switched each time a write operation is performed on the block BLK (selected block BLK) specified by block address BAd. However, the write operation of the semiconductor memory device 3D according to this embodiment is not limited to this. For example, the string to which the data is written may be switched each time multiple write operations are performed on the selected block BLK, or each time an erase operation is performed.

[0216] 3.3 Read Operation The read operation of the semiconductor memory device 3D according to the third embodiment will now be described. The read operation of the semiconductor memory device 3D according to this embodiment includes a first read operation. Figure 21 is a flowchart showing an example of the read operation of the semiconductor memory device 3D according to this embodiment.

[0217] For example, when a read operation is initiated, the memory controller 2 accesses the semiconductor memory device 3D and obtains the string flag flgS from the selected block (S211).

[0218] Next, the memory controller 2 instructs the semiconductor memory device 3D to perform a first read operation based on the string flag flgS.

[0219] Next, the sequencer 13 performs a first read operation based on the instruction received from the memory controller 2 (S212). Figure 22 shows the voltage across each wire during the first read operation. In the example in Figure 22, in the selection block BLK, multiple memory cell transistors MT4o in the selection string unit SU are selected as read targets, and one memory cell transistor MT4o in the NAND string NS is turned ON.

[0220] As shown in Figure 22, during the first read operation, the following voltages are applied to each conductive pillar SGP and CGP in the first string NSa.

[0221] A voltage VSG is applied to the conductive film 40 of each conductive pillar SGP0e and SGP1e. A voltage Vcut is applied to the conductive film 30 of each conductive pillar CGP4e and CGP5e. Conductive pillars CGP4e and CGP5e are conductive pillars CGPe located on the front side of the semiconductor CPS and in the vicinity of the selected CG pillar CGPsel. More specifically, conductive pillars CGP4e and CGP5e are two conductive pillars CGPe on the front side of the semiconductor CPS, located in the +Y and -Y directions, respectively, from the position facing the selected CG pillar CGPsel on the back side of the semiconductor CPS in the X direction. A voltage Vread is applied to the conductive film 30 of each conductive pillar CGP0e~CGP3e, CGP6e, and CGP7e.

[0222] Furthermore, during the first read operation, the following voltages are applied to each conductive pillar SGP and CGP within the NAND string NSb.

[0223] For example, a voltage VSG is applied to the conductive film 40 of conductive pillars SGP0o and SGP1o. For example, a voltage VCGRV is applied to the conductive film 30 of conductive pillar CGP4o (selected CG pillar CGPsel). For example, a voltage Vcut is applied to the conductive film 30 of conductive pillars CGP0o to CGP3o and CGP5o to CGP7o.

[0224] In this state, a voltage Vbl is applied to the bit line BL to be read, and a voltage VSS is applied to the source line SL.

[0225] In a semiconductor CPS, conductive regions are formed near the portions in contact with each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. No conductive regions are formed near the portions in contact with the conductive pillars CGP4e, CGP5e, CGP0o to CGP3o, and CGP5o to CGP7o. Conductive regions are formed near the portions in contact with the conductive pillars CGP0e to CGP3e, CGP6e, and CGP7e. When the selective memory cell transistor MT4o is ON, a conductive region is formed near the portion in contact with the conductive pillar CGP4o. On the other hand, when the selective memory cell transistor MT4o is OFF, no conductive region is formed.

[0226] Furthermore, because the width of the semiconductor CPS is relatively small, in the semiconductor CPS, when the selective memory cell transistor MT4o is ON, conductive regions are formed between the conductive region formed near the conductive pillar CGP6e and the conductive region formed near the selective CG pillar CGPsel, and also between the conductive region formed near the selective CG pillar CGPsel and the conductive region formed near the conductive pillar CGP3e. Conductive regions are also formed between the conductive region formed near the conductive pillar CGP0e and the conductive region formed near the conductive pillar SGP1o.

[0227] In semiconductor CPS, no conductive region is formed near the part in contact with the contact plug BC.

[0228] Therefore, when the selective memory cell transistor MT4o is ON, as shown in Figure 22, the wiring LBI and the source line SL are electrically connected, and an electron current flows from the wiring LBI to the source line SL. On the other hand, when the selective memory cell transistor MT4o is OFF, the wiring LBI and the source line SL are not electrically connected.

[0229] When the memory cell transistor MT7o is the target of readout, for example, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. For example, a voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP7o (selected CG pillar CGPsel). For example, a voltage Vcut is applied to the conductive film 30 of each of the conductive pillars CGP7e and CGP0o to CGP6o. For example, a voltage Vread is applied to the conductive film 30 of each of the conductive pillars CGP0e to CGP6e.

[0230] Furthermore, when the memory cell transistor MT0o is the target of readout, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. A voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP0o (selected CG pillar CGPsel). A voltage Vcut is applied to the conductive film 30 of each of the conductive pillars CGP0e, CGP1e, and CGP1o to CGP7o. A voltage Vread is applied to the conductive film 30 of each of the conductive pillars CGP2e to CGP7e.

[0231] 3.4 Effects of this embodiment According to the third embodiment, the same effects as those of the second embodiment are achieved.

[0232] Furthermore, since the memory string and the read string are switched periodically (for example, during write or erase operations), the write or erase stress can be equalized, and the cycle limit of the memory cell can be extended.

[0233] 3.5 First Variation Next, we will describe a semiconductor memory device 3E according to the first modification of the third embodiment. This modified semiconductor memory device 3E differs from the third embodiment in that a string table tblS is used as string information. The circuit configuration and planar layout of the memory cell array 10E are the same as in the third embodiment. The following will focus on the differences from the third embodiment.

[0234] 3.5.1 String Table The string table tblS will be explained using Figure 23. Figure 23 is a conceptual diagram of the string table tblS used in the semiconductor memory device 3E according to this modified example.

[0235] As shown in Figure 23, the string table tblS has multiple entries. Each entry contains a block address BAd and a string flag flgS. In the example in Figure 23, the string flag flgS corresponding to block addresses BAd0 and BAd1 is "0". The string flag flgS corresponding to block address BAd2 is "1". For example, in block BLK corresponding to block addresses BAd0 and BAd1, the first string NSa is a memory string, and in block BLK corresponding to block address BAd2, the second string NSb is a memory string.

[0236] The string table tblS is stored, for example, in one of the block BLKs of the memory cell array 10E. The string table tblS is loaded from the semiconductor memory device 3E into a RAM (Random Access Memory) in the memory controller 2 (not shown), for example, immediately after power-on. The string table tblS in RAM is updated, for example, each time a memory string is switched. The initial value of the string flag flgS is, for example, "1". The string table tblS in the block BLK is also updated at any time.

[0237] 3.5.2 Writing Operation The write operation of the semiconductor memory device 3E according to the first modification of the third embodiment will be described. FIG. 24 is a flowchart showing an example of the write operation of the semiconductor memory device 3E according to this modification.

[0238] For example, when the write operation is started, the memory controller 2 acquires the string flag flgS corresponding to the selected block BLK from the string table tblS (S221).

[0239] Next, the memory controller 2 exchanges the memory string and the read string based on the string flag flgS, and updates the string flag flgS corresponding to the selected block BLK in the string table tblS (S222).

[0240] Next, the memory controller 2 instructs the semiconductor memory device 3E to execute the first write operation on the memory string after the exchange and the second write operation on the read string after the exchange.

[0241] Next, the sequencer 13 executes the first write operation based on the instruction received from the memory controller 2 (S223).

[0242] Next, the sequencer 13 executes the second write operation based on the instruction received from the memory controller 2 (S224). When the second write operation ends, the write operation ends.

[0243] 3.5.3 Read Operation The read operation of the semiconductor memory device 3E according to the first modification of the third embodiment will be described. FIG. 25 is a flowchart showing an example of the read operation of the semiconductor memory device 3E according to this modification.

[0244] For example, when the read operation is started, the memory controller 2 acquires the string flag flgS corresponding to the selected block BLK from the string table tblS (S231).

[0245] Next, based on the string flag flgS, the memory controller 2 instructs the semiconductor memory device 3E to execute the first read operation.

[0246] Next, based on the instruction received from the memory controller 2, the sequencer 13 executes the first read operation (S232).

[0247] 3.5.4 Effects of this modification According to this modification, the same effects as those of the third embodiment are achieved.

[0248] 3.6 Second modification A semiconductor memory device 3F according to the second modification of the third embodiment will be described. In the semiconductor memory device 3F according to this modification, the circuit configuration of the memory cell array 10F, the planar layout of the memory cell array 10F, and the read operation are different from those of the third embodiment. The circuit configuration of the memory cell array 10F is the same as that shown in FIG. 16 in the modification of the second embodiment. Of the first string NSa and the second string NSb, one is a memory string and the other is a read string. The planar layout of the memory cell array 10F is the same as that shown in FIG. 17 in the modification of the second embodiment. Hereinafter, the description will focus on the differences from the third embodiment.

[0249] 3.6.1 Write operation The write operation of the semiconductor memory device 3F according to the second modification of the third embodiment is the same as the write operation described in the third embodiment.

[0250] 3.6.2 Read operation The read operation of the semiconductor memory device 3F according to the second modification of the third embodiment will be described. A flowchart showing an example of the read operation of the semiconductor memory device 3F according to this modification is the same as that shown in FIG. 21 in the third embodiment.

[0251] Figure 26 shows the voltage across each wiring during the first read operation. In the example in Figure 26, multiple memory cell transistors MT4o within the selection string unit SU are selected as read targets in the selection block BLK, and one memory cell transistor MT4o within the NAND string NS is turned ON.

[0252] As shown in Figure 26, during the first read operation, the following voltages are applied to each conductive pillar SGP and CGP in the first string NSa.

[0253] A voltage VSG is applied to the conductive film 40 of each conductive pillar SGP0e to SGP2e. A voltage Vcut is applied to the conductive film 30 of conductive pillar CGP4e. Conductive pillar CGP4e is a conductive pillar CGPe located on the front side of the semiconductor CPS and in the vicinity of the selected CG pillar CGPsel. More specifically, conductive pillar CGP4e is a conductive pillar CGPe on the front side of the semiconductor CPS, located in the X direction opposite the selected CG pillar CGPsel on the back side of the semiconductor CPS. A voltage Vread is applied to the conductive film 30 of each conductive pillar CGP0e to CGP3e and CGP5e to CGP7e.

[0254] Furthermore, during the first read operation, the following voltages are applied to each conductive pillar SGP and CGP within the NAND string NSb.

[0255] A voltage VSG is applied to the conductive film 40 of each conductive pillar SGP0o to SGP2o. A voltage VCGRV is applied to the conductive film 30 of conductive pillar CGP4o. A voltage Vcut is applied to the conductive film 30 of each conductive pillar CGP0o to CGP3o and CGP5o to CGP7o.

[0256] In this state, a voltage Vbl is applied to the bit line BL to be read, and a voltage VSS is applied to the source line SL.

[0257] In a semiconductor CPS, conductive regions are formed near the portions in contact with each of the conductive pillars SGP0e to SGP2e and SGP0o to SGP2o. Conductive regions are not formed near the portions in contact with each of the conductive pillars CGP4e, CGP0o to CGP3o, and CGP5o to CGP7o. Conductive regions are formed near the portions in contact with each of the conductive pillars CGP0e to CGP3e and CGP5e to CGP7e. When the selective memory cell transistor MT4o is ON, a conductive region is formed near the portion in contact with conductive pillar CGP4o. On the other hand, when the selective memory cell transistor MT4o is OFF, no conductive region is formed.

[0258] Furthermore, because the width of the semiconductor CPS is relatively small, conductive regions are also formed in the semiconductor CPS between the conductive region formed near conductive pillar SGP2o and the conductive region formed near conductive pillar SGP1e, between the conductive region formed near conductive pillar CGP0e and the conductive region formed near conductive pillar SGP0o, and between the conductive region formed near conductive pillar SGP0o and the conductive region formed near conductive pillar SGP2e. When the selective memory cell transistor MT4o is ON, conductive regions are also formed between the conductive region formed near conductive pillar CGP5e and the conductive region formed near selective CG pillar CGPsel, and between the conductive region formed near selective CG pillar CGPsel and the conductive region formed near conductive pillar CGP3e.

[0259] In semiconductor CPS, no conductive region is formed near the part in contact with the contact plug BC.

[0260] Therefore, when the selective memory cell transistor MT4o is ON, the wiring LBI and the source line SL are electrically connected, as shown in Figure 26, and an electron current flows from the wiring LBI to the source line SL. On the other hand, when the selective memory cell transistor MT4o is OFF, the wiring LBI and the source line SL are not electrically connected.

[0261] When the memory cell transistor MT7o is the read target, for example, a voltage VSG is applied to each of the conductor films 40 of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. For example, a voltage VCGRV is applied to the conductor film 30 of the conductive pillar CGP7o (selected CG pillar CGPsel). For example, a voltage Vcut is applied to each of the conductor films 30 of the conductive pillars CGP7e and CGP0o - CGP6o. For example, a voltage Vread is applied to each of the conductor films 30 of the conductive pillars CGP0e - CGP6e.

[0262] Also, when the memory cell transistor MT0o is the read target, for example, a voltage VSG is applied to each of the conductor films 40 of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. For example, a voltage VCGRV is applied to the conductor film 30 of the conductive pillar CGP0o (selected CG pillar CGPsel). For example, a voltage Vcut is applied to each of the conductor films 30 of the conductive pillars CGP0e and CGP1o - CGP7o. For example, a voltage Vread is applied to each of the conductor films 30 of the conductive pillars CGP1e - CGP7e.

[0263] 3.6.3 Effects of this modification According to this modification, the same effects as those of the third embodiment are achieved.

[0264] Also, similar to the modification of the first embodiment, the cell current can be increased.

[0265] 4. Fourth Embodiment The semiconductor memory device 3G according to the fourth embodiment will now be described. The semiconductor memory device 3G according to this embodiment differs from the second embodiment in that it is possible to select on a block BLK basis whether to use the first string NSa as a memory string and the second string NSb as a read string, or to use both the first string NSa and the second string NSb as memory strings. Hereinafter, the storage mode of a block BLK in which the first string NSa is a memory string and the second string NSb is a read string will be referred to as the "high read endurance mode". The storage mode of a block BLK in which both the first string NSa and the second string NSb are memory strings will be referred to as the "normal mode". The circuit configuration of the memory cell array 10G is the same as that shown in Figure 12 in the second embodiment. The planar layout of the memory cell array 10G is the same as that shown in Figure 13 in the second embodiment. The differences from the second embodiment will be described below.

[0266] 4.1 How to specify the block storage mode This embodiment describes a case where the storage mode of a fixed block BLK is specified as high read endurance mode. Figure 27 is a diagram illustrating the method for specifying the storage mode of a block BLK in the semiconductor memory device 3G according to this embodiment. As shown in Figure 27, in this embodiment, the storage mode of a fixed block BLK is specified as high read endurance mode. In the example in Figure 27, the storage mode of block BLK0 is specified as high read endurance mode. The storage modes of the other block BLKs are specified as normal mode. Hereinafter, a block BLK specified as high read endurance mode will also be referred to as "high read endurance BLK". A block BLK specified as normal mode will also be referred to as "normal BLK".

[0267] A highly read-tolerant block block (BLK) stores information with a defined purpose, such as a File Allocation Table (FAT). For example, a user can specify a block BLK that stores information with a defined purpose in highly read-tolerant mode via the host.

[0268] 4.2 Writing Operation The writing operation of the semiconductor memory device 3G according to the fourth embodiment will now be described. The writing operation of the semiconductor memory device 3G according to this embodiment includes a first writing operation and a second writing operation. Figure 28 is a flowchart showing an example of the writing operation of the semiconductor memory device 3G according to this embodiment.

[0269] For example, when a write operation is initiated, the memory controller 2 determines whether the selected block BLK is a high read-endurance BLK (S301).

[0270] If the selected block BLK is a high read-endurance BLK (S301_Yes), the memory controller 2 instructs the semiconductor memory device 3G to perform a first write operation on the memory string (first string NSa) and a second write operation on the read string (second string NSb). Next, the sequencer 13 executes the first write operation based on the instruction received from the memory controller 2 (S302). That is, in the block BLK where the storage mode is specified as high read-endurance mode, the write data is written to the first string NSa. Next, the sequencer 13 executes the second write operation based on the instruction received from the memory controller 2 (S303).

[0271] On the other hand, if the selected block BLK is not a high read-endurance BLK (i.e., it is a normal BLK) (S301_No), the memory controller 2 instructs the semiconductor memory device 3G to perform a first write operation on the memory strings (first string NSa and second string NSb). Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S304). That is, in a block BLK where the storage mode is specified as normal mode, write data is written to both the first string NSa and the second string NSb. For example, in the NAND string NS, the conductive pillars CGP0e~CGP7e and CGP0o~CGP7o are selected in the order of conductive pillars CGP7e, CGP6e, ..., CGP1e, CGP0e, CGP7o, CGP6o, ..., CGP1o, CGP0o.

[0272] 4.3 Read Operation The read operation of the semiconductor memory device 3G according to the fourth embodiment will now be described. The read operation of the semiconductor memory device 3G according to this embodiment includes a first read operation and a second read operation. The first read operation is a read operation for a high read-endurance BLK. The second read operation is a read operation for a normal BLK. Figure 29 is a flowchart showing an example of the read operation of the semiconductor memory device 3G according to this embodiment.

[0273] For example, when a read operation is initiated, the memory controller 2 determines whether the selected block BLK is a high read-endurance BLK (S311).

[0274] If the selected block BLK is a high read-endurance BLK (S311_Yes), the memory controller 2 instructs the semiconductor memory device 3G to perform a first read operation. Next, the sequencer 13 performs the first read operation based on the instruction received from the memory controller 2 (S312).

[0275] On the other hand, if the selection block BLK is not a high read-endurance BLK (S311_No), the memory controller 2 instructs the semiconductor memory device 3G to perform a second read operation. Next, the sequencer 13 performs the second read operation based on the instruction received from the memory controller 2 (S313). Figure 30 shows the voltage of each wiring during the second read operation. In the example in Figure 30, it is shown that in the selection block BLK, multiple memory cell transistors MT4e in the selection string unit SU are selected as read targets, and one memory cell transistor MT4e in the NAND string NS is turned ON.

[0276] As shown in Figure 30, during the second read operation, the following voltages are applied to each conductive pillar SGP and CGP in the first string NSa.

[0277] A voltage VSG is applied to the conductive film 40 of each conductive pillar SGP0e and SGP1e. A voltage VCGRV is applied to the conductive film 30 of conductive pillar CGP4e (selected CG pillar CGPsel). A voltage Vread is applied to the conductive film 30 of each conductive pillar CGP0e to CGP3e and CGP5e to CGP7e.

[0278] Furthermore, during the second read operation, the following voltages are applied to each conductive pillar SGP and CGP within the NAND string NSb.

[0279] A voltage VSG is applied to the conductive film 40 of each conductive pillar SGP0o and SGP1o. A voltage Vcut is applied to the conductive film 30 of each conductive pillar CGP3o and CGP4o. A voltage Vread is applied to the conductive film 30 of each conductive pillar CGP0o to CGP2o and CGP5o to CGP7o.

[0280] In this state, a voltage Vbl is applied to the bit line BL to be read, and a voltage VSS is applied to the source line SL.

[0281] In the semiconductor CPS, conductive regions are formed near the portions in contact with each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. Conductive regions are not formed near the portions in contact with each of the conductive pillars CGP3o and CGP4o. Conductive regions are formed near the portions in contact with each of the conductive pillars CGP0e to CGP3e, CGP5e to CGP7e, CGP0o to CGP2o, and CGP5o to CGP7o. When the selective memory cell transistor MT4e is ON, a conductive region is formed near the portion in contact with the conductive pillar CGP4e. On the other hand, when the selective memory cell transistor MT4e is OFF, no conductive region is formed.

[0282] Furthermore, because the width of the semiconductor CPS is relatively small, conductive regions are also formed in the semiconductor CPS between the conductive region formed near conductive pillar SGP1e and the conductive region formed near conductive pillar CGP7o, and between the conductive region formed near conductive pillar CGP0e and the conductive region formed near conductive pillar SGP1o. When the selective memory cell transistor MT4e is ON, conductive regions are also formed between the conductive region formed near conductive pillar CGP5o and the conductive region formed near selective CG pillar CGPsel, and between the conductive region formed near selective CG pillar CGPsel and the conductive region formed near conductive pillar CGP2o.

[0283] In semiconductor CPS, no conductive region is formed near the part in contact with the contact plug BC.

[0284] Therefore, when the selective memory cell transistor MT4e is ON, as shown in Figure 30, the wiring LBI and the source line SL are electrically connected, and an electron current flows from the wiring LBI to the source line SL. On the other hand, when the selective memory cell transistor MT4e is OFF, the wiring LBI and the source line SL are not electrically connected.

[0285] For example, in the NAND string NS, the conductive pillars CGP0e to CGP7e and CGP0o to CGP7o are selected in the order of conductive pillars CGP7e, CGP6e, ..., CGP1e, CGP0e, CGP7o, CGP6o, ..., CGP1o, CGP0o.

[0286] 4.4 Effects of this embodiment According to the fourth embodiment, the same effects as those of the second embodiment are achieved.

[0287] Furthermore, in the semiconductor memory device 3G according to this embodiment, in the high read-endurance BLK, either the first string NSa or the second string NSb is used as a memory string, while in the normal BLK, both the first string NSa and the second string NSb are used as memory strings. Therefore, a highly read-endurance memory cell can be realized in the high read-endurance BLK, and the storage capacity of the memory cell can be increased in the normal BLK.

[0288] Furthermore, as described using Figure 30, during the second read operation, cell current can be increased by supplying cell current to the memory cell transistor MT corresponding to the unselected CGPusel.

[0289] Furthermore, since a fixed block blackout can be specified as a high read blackout, it can be used, for example, when the purpose is predetermined.

[0290] 4.5 First Variation Next, we will describe a semiconductor memory device 3H according to the first modification of the fourth embodiment. In this modification, the circuit configuration of the memory cell array 10H, the planar layout of the memory cell array 10H, and the read operation differ from those of the fourth embodiment. The circuit configuration of the memory cell array 10H is the same as that shown in Figure 16 of the modification of the second embodiment. The planar layout of the memory cell array 10H is the same as that shown in Figure 17 of the modification of the second embodiment. The following will focus on the differences from the fourth embodiment.

[0291] 4.5.1 Writing Operation The writing operation of the semiconductor memory device 3H according to the first modification of the fourth embodiment is the same as the writing operation described in the fourth embodiment.

[0292] 4.5.2 Read Operation The read operation of the semiconductor memory device 3H according to the first modified example of the fourth embodiment will now be described. The flowchart showing an example of the read operation of the semiconductor memory device 3H according to this modified example is the same as that shown in Figure 29 of the fourth embodiment.

[0293] Figure 31 shows the voltage across each wiring during the second read operation. In the example in Figure 31, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets in the selection block BLK, and one memory cell transistor MT4e within the NAND string NS is turned ON.

[0294] As shown in Figure 31, during the second read operation, the following voltages are applied to each conductive pillar SGP and CGP in the first string NSa.

[0295] For example, a voltage VSG is applied to the conductive film 40 of each conductive pillar SGP0e to SGP2e. For example, a voltage VCGRV is applied to the conductive film 30 of conductive pillar CGP4e (selected CG pillar CGPsel). For example, a voltage Vread is applied to the conductive film 30 of each conductive pillar CGP0e to CGP3e and CGP5e to CGP7e.

[0296] Furthermore, during the second read operation, the following voltages are applied to each conductive pillar SGP and CGP within the NAND string NSb.

[0297] A voltage VSG is applied to each conductive film 40 of conductive pillars SGP0o to SGP2o. A voltage Vcut is applied to each conductive film 30 of conductive pillar CGP4o. A voltage Vread is applied to each conductive film 30 of conductive pillars CGP0o to CGP3o and CGP5o to CGP7o.

[0298] In this state, a voltage Vbl is applied to the bit line BL to be read, and a voltage VSS is applied to the source line SL.

[0299] In a semiconductor CPS, conductive regions are formed near the portions in contact with each of the conductive pillars SGP0e to SGP2e and SGP0o to SGP2o. No conductive regions are formed near the portion in contact with conductive pillar CGP4o. Conductive regions are formed near the portions in contact with each of the conductive pillars CGP0e to CGP3e, CGP5e to CGP7e, CGP0o to CGP3o, and CGP5o to CGP7o. When the selective memory cell transistor MT4e is ON, a conductive region is formed near the portion in contact with conductive pillar CGP4e. On the other hand, when the selective memory cell transistor MT4e is OFF, no conductive region is formed.

[0300] Furthermore, because the width of the semiconductor CPS is relatively small, conductive regions are also formed in the semiconductor CPS between the conductive region formed near conductive pillar SGP2o and the conductive region formed near conductive pillar SGP1e, and between the conductive region formed near conductive pillar SGP1e and the conductive region formed near conductive pillar CGP7o. Conductive regions are also formed between the conductive region formed near conductive pillar CGP0e and the conductive region formed near conductive pillar SGP1o, and between the conductive region formed near conductive pillar SGP1o and the conductive region formed near conductive pillar SGP2e. When the selective memory cell transistor MT4e is ON, conductive regions are also formed between the conductive region formed near conductive pillar CGP5o and the conductive region formed near selective CG pillar CGPsel, and between the conductive region formed near selective CG pillar CGPsel and the conductive region formed near conductive pillar CGP3o.

[0301] In semiconductor CPS, no conductive region is formed near the part in contact with the contact plug BC.

[0302] Therefore, when the selective memory cell transistor MT4e is ON, as shown in Figure 31, the wiring LBI and the source line SL are electrically connected, and an electron current flows from the wiring LBI to the source line SL. On the other hand, when the selective memory cell transistor MT4e is OFF, the wiring LBI and the source line SL are not electrically connected.

[0303] 4.5.3 Effects of this modified example This modified version achieves the same effects as the fourth embodiment.

[0304] Furthermore, similar to the modification of the first embodiment, the cell current can be increased.

[0305] 4.6 Second Variation Next, we will describe a semiconductor memory device 3I according to a second modification of the fourth embodiment. In this modified semiconductor memory device 3I, the method for specifying the storage mode of block BLK differs from that of the fourth embodiment. The following will focus on the differences from the fourth embodiment.

[0306] 4.6.1 How to specify the block storage mode This modification describes a case where the region of block BLK designated as high-read-endurance mode is variable. Figure 32 illustrates the method for specifying the storage mode of block BLK in the semiconductor memory device 3I according to this modification. As shown in Figure 32, in this modification, the region of block BLK designated as high-read-endurance mode is variable. That is, the boundary position between high-read-endurance BLK and normal BLK is changed. In the example in Figure 32, the storage mode of blocks BLK0 to BLK2 is designated as high-read-endurance mode. The storage mode of the other block BLKs is designated as normal mode.

[0307] 4.6.2 Mode Flags In this modified example, the mode flag flgM is used as information indicating whether the storage mode of the selected block BLK is set to high read endurance mode or normal mode (hereinafter referred to as "storage mode information"). The mode flag flgM will be explained using Figure 33. Figure 33 is a diagram illustrating the mode flag flgM used in the semiconductor memory device 3I according to this modified example.

[0308] As shown in Figure 33, each block BLK stores a mode flag flgM in the memory cell transistor MT within the memory area. For example, "0" is stored for normal mode, and "1" is stored for high read endurance mode.

[0309] 4.6.3 Writing Operation The writing operation of the semiconductor memory device 3I according to the second modification of the fourth embodiment will now be described. The writing operation of the semiconductor memory device 3I according to this modification includes a first writing operation.

[0310] For example, when a write operation is initiated, the memory controller 2 instructs the semiconductor memory device 3I to perform a first write operation on the memory strings (first string NSa and second string NSb). Next, the sequencer 13 performs the first write operation based on the instructions received from the memory controller 2. During the first write operation, the sequencer 13 also writes (updates) the mode flag flgM (e.g., "0") in the selection block BLK.

[0311] 4.6.4 Variable block area operation The block area variable operation of the semiconductor memory device 3I according to the second modification of the fourth embodiment will be described. The block area variable operation of the semiconductor memory device 3I according to this modification includes a first variable operation and a second variable operation. Figure 34 is a flowchart showing an example of the block area variable operation of the semiconductor memory device 3I according to this modification.

[0312] For example, at regular time intervals, the memory controller 2 accesses the semiconductor memory device 3I and obtains the mode flag flgM from the selected block BLK (S321).

[0313] Next, the memory controller 2 determines whether the mode flag flgM indicates normal mode (S322).

[0314] If the mode flag flgM is in normal mode (S322_Yes), the memory controller 2 performs the first variable operation (S323).

[0315] On the other hand, if the mode flag flgM is in high read endurance mode (S322_No), the memory controller 2 performs a second variable operation (S324).

[0316] (First variable action) The first variable operation will now be described. Figure 35 is a flowchart showing an example of the first variable operation of the semiconductor memory device 3I according to this modified example.

[0317] For example, the memory controller 2 determines whether the number of reads of the data in the selected block BLK within a certain period of time exceeds the threshold TH1 (S331).

[0318] If the number of read operations exceeds the threshold TH1 (S331_Yes), the memory controller 2 switches the storage mode (S332). This switches the storage mode to high read endurance mode. Next, the memory controller 2 instructs the semiconductor memory device 3I to perform a first write operation and a second write operation. Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S333). During the first write operation, the sequencer 13 also writes (updates) the mode flag flgM (e.g., "1") in the selected block BLK. Next, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S334). In this way, if the number of read operations for the data in a normal BLK within a certain period of time exceeds the threshold TH1, the storage mode of the normal BLK is switched to high read endurance mode, and the normal BLK is changed to a high read endurance BLK. This increases the area of ​​the high-read-tolerance block (changing the boundary between the high-read-tolerance block and the normal block), and the first variable operation ends.

[0319] On the other hand, if the number of read operations does not exceed the threshold TH1 (S331_No), the first variable operation ends.

[0320] (Second variable operation) The second variable operation will now be described. Figure 36 is a flowchart showing an example of the second variable operation of the semiconductor memory device 3I according to this modified example.

[0321] For example, the memory controller 2 determines whether or not data in the selected block BLK has been read within a certain time period (S341).

[0322] If a read operation occurs within a certain time (S341_Yes), the second variable operation ends.

[0323] On the other hand, if there is no read operation within a certain period of time (S341_No), the memory controller 2 switches the storage mode (S342). This switches the storage mode to normal mode. Next, the memory controller 2 instructs the semiconductor memory device 3I to perform the first write operation. Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S343). During the first write operation, the sequencer 13 also writes (updates) the mode flag flgM (for example, "0") in the selected block BLK. In this way, if there is no read operation within a certain period of time for the data in the high read-tolerant BLK, the storage mode of the high read-tolerant BLK is switched to normal mode, and the high read-tolerant BLK is changed to a normal BLK. As a result, the area of ​​the high read-tolerant BLK decreases (the boundary position between the high read-tolerant BLK and the normal BLK changes), and the second variable operation ends.

[0324] As described above, in variable block area operation, the boundary position between high-read-tolerance blocks and normal blocks within multiple block blocks is changed based on the number of times the data in the selected block block is accessed.

[0325] 4.6.5 Read Operation The read operation of the semiconductor memory device 3I according to the second modified example of the fourth embodiment will now be described. Figure 37 is a flowchart showing an example of the read operation of the semiconductor memory device 3I according to this modified example.

[0326] For example, when a read operation is initiated, the memory controller 2 accesses the semiconductor memory device 3I and obtains the mode flag flgM from the selected block BLK (S351).

[0327] Next, the memory controller 2 determines whether the mode flag flgM is in normal mode (S352).

[0328] If the mode flag flgM is in normal mode (S352_Yes), the memory controller 2 instructs the semiconductor memory device 3I to perform the second read operation. Next, the sequencer 13 performs the second read operation based on the instruction received from the memory controller 2 (S353).

[0329] On the other hand, if the mode flag flgM is in high read endurance mode (S352_No), the memory controller 2 instructs the semiconductor memory device 3I to perform a first read operation. Next, the sequencer 13 performs the first read operation based on the instruction received from the memory controller 2 (S354).

[0330] 4.6.6 Effects of this modified example This modified version achieves the same effects as the fourth embodiment.

[0331] Furthermore, since the boundary between high-read-tolerance blackouts and normal blackouts can be changed, they can be used, for example, as a cache. For instance, depending on the number of accesses, the data storage location can be shifted from an external DRAM cache (not shown) to a high-read-tolerance blackout, and then from a high-read-tolerance blackout to a normal blackout.

[0332] 4.7 Third Variation Next, we will describe a semiconductor memory device 3J according to a third modification of the fourth embodiment. This semiconductor memory device 3J differs from the second modification of the fourth embodiment in that a mode table tblM is used as the memory mode information. The circuit configuration and planar layout of the memory cell array 10J are the same as those of the second modification of the fourth embodiment. The following will focus on the differences from the second modification of the fourth embodiment.

[0333] 4.7.1 Mode Table The mode table tblM will be explained using Figure 38. Figure 38 is a conceptual diagram of the mode table tblM used in the semiconductor memory device 3J according to this modified example.

[0334] As shown in Figure 38, the mode table tblM has multiple entries. Each entry contains a block address BAd and a mode flag flgM. In the example in Figure 38, the mode flag flgM corresponding to block addresses BAd0 and BAd1 is "1". The mode flag flgM corresponding to block address BAd2 is "0". For example, block BLK corresponding to block addresses BAd0 and BAd1 is in high read-tolerant mode, and block BLK corresponding to block address BAd2 is in normal mode.

[0335] The mode table tblM is stored, for example, in one of the block BLKs of the memory cell array 10J. The mode table tblM is loaded from the semiconductor memory device 3J into the RAM in the memory controller 2, for example, immediately after power-on. The mode table tblM in RAM is updated, for example, each time the memory mode is switched. The initial value of the mode flag flgM is, for example, "0". The mode table tblM in the block BLK is also updated at any time.

[0336] 4.7.2 Writing Operation The writing operation of the semiconductor memory device 3J according to the third modified example of the fourth embodiment will now be described. The writing operation of the semiconductor memory device 3J according to this modified example includes a first writing operation. Figure 39 is a flowchart showing an example of the writing operation of the semiconductor memory device 3J according to this modified example.

[0337] For example, when a write operation is initiated, the memory controller 2 updates the mode flag flgM corresponding to the selected block BLK in the mode table tblM (S361).

[0338] Next, the memory controller 2 instructs the semiconductor memory device 3J to perform a first write operation on the memory strings (first string NSa and second string NSb). Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S362). When the first write operation is completed, the write operation is terminated.

[0339] 4.7.3 Variable block area operation The block area variable operation of the semiconductor memory device 3J according to the third modified example of the fourth embodiment will now be described. The block area variable operation of the semiconductor memory device 3J according to this modified example includes a first variable operation and a second variable operation. Figure 40 is a flowchart showing an example of the block area variable operation of the semiconductor memory device 3J according to this modified example.

[0340] For example, at regular intervals, the memory controller 2 obtains the mode flag flgM corresponding to the selected block BLK from the mode table tblM (S371).

[0341] Next, the memory controller 2 determines whether the mode flag flgM indicates normal mode (S372).

[0342] If the mode flag flgM is in normal mode (S372_Yes), the memory controller 2 performs the first variable operation (S373).

[0343] On the other hand, if the mode flag flgM is in high read endurance mode (S372_No), the memory controller 2 performs a second variable operation (S374).

[0344] (First variable action) The first variable operation will now be described. Figure 41 is a flowchart showing an example of the first variable operation of the semiconductor memory device 3J according to this modified example.

[0345] For example, the memory controller 2 determines whether the number of reads of the data in the selected block BLK within a certain period of time exceeds the threshold TH1 (S381).

[0346] If the number of read operations exceeds the threshold TH1 (S381_Yes), the memory controller 2 switches the storage mode and updates the mode flag flgM corresponding to the selected block BLK in the mode table tblM (S382). This switches the storage mode to high read endurance mode.

[0347] Next, the memory controller 2 instructs the semiconductor memory device 3J to perform a first write operation and a second write operation. Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S383). Next, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S384). As a result, the area of ​​high read-endurance BLK increases, and the first variable operation ends.

[0348] On the other hand, if the number of read operations does not exceed the threshold TH1 (S381_No), the first variable operation ends.

[0349] (Second variable operation) The second variable operation will now be described. Figure 42 is a flowchart showing an example of the second variable operation of the semiconductor memory device 3J according to this modified example.

[0350] For example, the memory controller 2 determines whether or not data in the selected block BLK has been read within a certain period of time (S391).

[0351] If a read operation occurs within a certain time period (S391_Yes), the second variable operation ends.

[0352] On the other hand, if there is no read operation within a certain period of time (S391_No), the memory controller 2 switches the storage mode and updates the mode flag flgM corresponding to the selected block BLK in the mode table tblM (S392). This switches the storage mode to normal mode. Next, the memory controller 2 instructs the semiconductor memory device 3J to perform the first write operation. Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S393). This reduces the area of ​​high read-endurance BLK, and the second variable operation ends.

[0353] 4.7.4 Read operation The read operation of the semiconductor memory device 3J according to the third modified example of the fourth embodiment will now be described. Figure 43 is a flowchart showing an example of the read operation of the semiconductor memory device 3J according to this modified example.

[0354] For example, when a read operation is initiated, the memory controller 2 obtains the mode flag flgM corresponding to the selected block BLK from the mode table tblM (S401).

[0355] Next, the memory controller 2 determines whether the mode flag flgM is in normal mode (S402).

[0356] If the mode flag flgM is in normal mode (S402_Yes), the memory controller 2 instructs the semiconductor memory device 3J to perform the second read operation. Next, the sequencer 13 performs the second read operation based on the instruction received from the memory controller 2 (S403).

[0357] On the other hand, if the mode flag flgM is in high read endurance mode (S402_No), the memory controller 2 instructs the semiconductor memory device 3J to perform the first read operation. Next, the sequencer 13 performs the first read operation based on the instruction received from the memory controller 2 (S404).

[0358] 4.7.5 Effects of this modified example This modified example provides the same effects as the second modified example of the fourth embodiment.

[0359] 4.8 Fourth Variation Next, we will describe a semiconductor memory device 3K according to a fourth modification of the fourth embodiment. In this modified semiconductor memory device 3K, the method for specifying the memory mode of block BLK differs from that of the fourth embodiment. The following will focus on the differences from the fourth embodiment.

[0360] 4.8.1 How to specify the block storage mode This modified example describes a case where the storage mode of a block BLK is specified during a write operation. Figure 44 illustrates the method for specifying the storage mode of a block BLK in the semiconductor memory device 3K according to this modified example. As shown in Figure 44, in this modified example, either high read endurance mode or normal mode can be specified. In the example in Figure 44, the storage modes of blocks BLK0, BLK3, and BLK5 are specified as high read endurance mode. The storage modes of the other block BLKs are specified as normal mode.

[0361] 4.8.2 Mode Flags In this modified example, the mode flag flgM is used as the memory mode information, similar to the second modified example in the fourth embodiment.

[0362] 4.8.3 Writing Operation The writing operation of the semiconductor memory device 3K according to the fourth modification of the fourth embodiment will now be described. The writing operation of the semiconductor memory device 3K according to this modification includes a first writing operation and a second writing operation. Figure 45 is a flowchart showing an example of the writing operation of the semiconductor memory device 3K according to this modification.

[0363] For example, when a write operation is initiated, the memory controller 2 selects a storage mode for the selected block BLK based on the data to be written (S411). The memory controller 2 can select either a high read endurance mode or a normal mode based on, for example, the type of data to be written.

[0364] Next, the memory controller 2 determines whether the selected storage mode is the normal mode (S412).

[0365] If the selected memory mode is normal mode (S412_Yes), the memory controller 2 instructs the semiconductor memory device 3K to perform the first write operation. Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S413). During the first write operation, the sequencer 13 also writes (updates) the mode flag flgM in the selected block BLK. When the first write operation is completed, the write operation ends.

[0366] On the other hand, if the selected memory mode is high read endurance mode (S412_No), the memory controller 2 instructs the semiconductor memory device 3K to perform a first write operation and a second write operation. Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S414). During the first write operation, the sequencer 13 also writes (updates) the mode flag flgM in the selected block BLK. Next, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S415). When the second write operation is completed, the write operation ends.

[0367] 4.8.4 Read Operation The read operation of the semiconductor memory device 3K according to the fourth modification of the fourth embodiment will now be described. The read operation of the semiconductor memory device 3K according to this modification is the same as the read operation described in the second modification of the fourth embodiment.

[0368] 4.8.5 Effects of this modified example This modified version achieves the same effects as the fourth embodiment.

[0369] Furthermore, since the storage mode can be specified based on the type of data being written during the write operation, the flexibility of data handling is improved.

[0370] 4.9 Fifth Variation Next, we will describe a semiconductor memory device 3L according to a fifth modification of the fourth embodiment. This semiconductor memory device 3L differs from the fourth modification of the fourth embodiment in that a mode table tblM is used as the memory mode information. The circuit configuration and planar layout of the memory cell array 10L are the same as those of the fourth modification of the fourth embodiment. The following will focus on the differences from the fourth modification of the fourth embodiment.

[0371] 4.9.1 Mode Table In this modified example, the mode table tblM is used as the memory mode information, similar to the third modified example in the fourth embodiment.

[0372] 4.9.2 Writing Operation The writing operation of the semiconductor memory device 3L according to the fifth modified example of the fourth embodiment will now be described. Figure 46 is a flowchart showing an example of the writing operation of the semiconductor memory device 3L according to this modified example.

[0373] For example, when a write operation is initiated, the memory controller 2 selects a storage mode for the selected block BLK based on the write data and updates the mode flag flgM corresponding to the selected block BLK in the mode table tblM (S421).

[0374] Next, the memory controller 2 determines whether the selected storage mode is the normal mode (S422).

[0375] If the selected memory mode is normal mode (S422_Yes), the memory controller 2 instructs the semiconductor memory device 3L to perform the first write operation. Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S423). When the first write operation is completed, the write operation ends.

[0376] On the other hand, if the selected memory mode is high read endurance mode (S422_No), the memory controller 2 instructs the semiconductor memory device 3K to perform a first write operation and a second write operation. Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S424). Next, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S425). When the second write operation is completed, the write operation is terminated.

[0377] 4.9.3 Read Operation The read operation of the semiconductor memory device 3L according to the fifth modification of the fourth embodiment will now be described. The read operation of the semiconductor memory device 3L according to this modification is the same as the read operation described in the third modification of the fourth embodiment.

[0378] 4.9.4 Effects of this modified example This modified example achieves the same effects as the fourth modified example of the fourth embodiment.

[0379] 5. Fifth Embodiment Next, we will describe the semiconductor memory device 3M according to the fifth embodiment. The semiconductor memory device 3M according to this embodiment differs from the fourth modification of the fourth embodiment in that it has a calculation function. The following description will focus on the differences from the fourth modification of the fourth embodiment.

[0380] 5.1 Configuration of Semiconductor Memory Devices The configuration of the semiconductor memory device 3M according to the fifth embodiment will be explained with reference to Figure 47. Figure 47 is a block diagram showing an example of the configuration of a memory system 1M including the semiconductor memory device 3M according to the fifth embodiment.

[0381] As shown in Figure 47, the semiconductor memory device 3M further includes an arithmetic module 17.

[0382] The arithmetic module 17 is a module that performs various arithmetic operations using data stored in the memory cell transistor MT. The sequencer 13 controls the arithmetic module 17.

[0383] 5.2 Configuration of the Arithmetic Module The configuration of the arithmetic module 17 will be explained using Figure 48. Figure 48 is a block diagram showing an example of the configuration of the arithmetic module 17. Figure 48 also shows the memory cell array 10 and the bit line BL.

[0384] As shown in Figure 48, the arithmetic module 17 includes a plurality of registers 18 and a plurality of arithmetic circuits 19.

[0385] Register 18 stores data received from the memory cell transistor MT in the memory cell array 10, as well as data from arithmetic processing. Register 18 includes multiple latch circuits. Data is stored in each latch circuit.

[0386] The arithmetic circuit 19 is a circuit that performs various arithmetic operations. These operations include, for example, addition, subtraction, and comparison.

[0387] Multiple NAND strings NS, registers 18, and arithmetic circuits 19 within each block BLK are connected to the same bit line BL.

[0388] Each block BLK in the memory cell array 10 is either a high-read-tolerance BLK or a normal BLK. Reference data, such as operation specification data, is stored in the NAND string NS within the high-read-tolerance BLK. Operation specification data is data that specifies the operation to be performed; for example, "1" specifies an addition operation, and "0" specifies a subtraction operation. Input / output data is stored in the NAND string NS within the normal BLK.

[0389] 5.3 Arithmetic Processing The calculation processing performed by the arithmetic module 17 of the semiconductor memory device 3M according to the fifth embodiment will now be described. Figure 49 is a flowchart showing an example of the calculation processing performed by the arithmetic module 17 of the semiconductor memory device 3M according to this embodiment.

[0390] For example, when the memory controller 2 receives a request for arithmetic processing from an external source, the memory controller 2 instructs the semiconductor memory device 3M to execute the arithmetic processing.

[0391] Next, the sequencer 13 controls the arithmetic module 17 based on instructions received from the memory controller 2. The arithmetic module 17 then executes the arithmetic processing.

[0392] More specifically, the arithmetic circuit 19 obtains the operation specification data from the NAND string NS in the high read-tolerant BLK (S501).

[0393] Next, the arithmetic circuit 19 normally acquires input / output data from the NAND string NS within BLK (S502).

[0394] Next, the arithmetic circuit 19 performs calculations based on the calculation specification data of the NAND string NS in the high read-tolerance BLK and the input / output data of the NAND string NS in the normal BLK. For example, the arithmetic circuit 19 performs calculations using the input / output data based on the calculation content specified by the calculation specification data (S503).

[0395] Next, the arithmetic circuit 19 stores the calculation result RES1 obtained from the calculation process in a NAND string NS within the normal BLK (S504). For example, the arithmetic circuit 19 stores the calculation result RES1 in another NAND string NS within the normal BLK. The calculation result RES1 may also be output to the outside of the memory system 1M via the memory controller 2.

[0396] Next, the arithmetic circuit 19 executes a pre-specified algorithmic processing based on the calculation result RES1 (S505).

[0397] Next, the arithmetic circuit 19 updates the reference data of the NAND string NS in the high read-tolerant BLK based on the execution result RES2 (S506). For example, the arithmetic circuit 19 updates the data of the NAND string NS in the high read-tolerant BLK based on the execution result RES2.

[0398] 5.4 Configuration of the AI ​​(Artificial Intelligence) Module The memory system 1M, including the semiconductor memory device 3M according to the fifth embodiment, is applicable to, for example, an AI module. Figure 50 is a block diagram showing an example of the configuration of an AI module incorporating the memory system 1M, including the semiconductor memory device 3M according to the fifth embodiment.

[0399] As shown in Figure 50, the AI ​​module 4 is, for example, a chip on which AI is implemented. The AI ​​module 4 includes, for example, a GPU (Graphics Processing Unit) 5 and a memory system 1M.

[0400] The GPU5 includes a CPU (Central Processing Unit)6 and multiple DRAMs (Dynamic Random Access Memory)7. The GPU5 is connected to the memory system 1M.

[0401] CPU6 is, for example, a general-purpose CPU. CPU6 performs various processes. CPU6 is connected to multiple DRAMs7.

[0402] DRAM7 is, for example, working memory. For instance, DRAM7 holds a large amount of data used in generative AI. In the example in Figure 50, it is shown that GPU5 contains three DRAM7s, but the number of DRAM7s in GPU5 does not have to be three.

[0403] For example, the CPU 6 sends a processing request to the memory system 1M. When the memory system 1M receives the processing request, the processing is performed by the arithmetic module 17 of the semiconductor memory device 3M.

[0404] 5.5 Effects of this embodiment According to this embodiment, the same effects as the fourth modified example of the fourth embodiment are achieved.

[0405] Furthermore, Large Language Models (LLMs) used in generative AI perform machine learning on large amounts of data to generate results. Also, AI modules, for example, require a large amount of data to be stored internally in DRAM due to low transfer rates with external storage.

[0406] The semiconductor memory device 3M according to this embodiment further includes an arithmetic module 17. The arithmetic module 17 includes a plurality of registers 18, each connected to one of the bit lines BL, and a plurality of arithmetic circuits 19, each connected to one of the bit lines BL. In addition, each of the plurality of NAND strings NS in the high read-tolerance BLK is connected to one of the bit lines BL. In the normal BLK, each of the plurality of NAND strings NS is connected to one of the bit lines BL.

[0407] Because of the above configuration, as shown with reference to Figure 49, for example, reference data such as calculation specification data can be stored in the high read-tolerance BLK, and input / output data can be stored in the normal BLK. It also has calculation capabilities. Therefore, it can perform calculation processing while holding a large amount of reference data and input / output data.

[0408] 6. Others As described above, the semiconductor memory device (3) according to the embodiment comprises a plurality of memory strings (NS) arranged spaced apart from each other in a first direction (Z). Each of the plurality of memory strings (NS) includes a semiconductor layer (22 (CPS)) extending in a second direction (Y) intersecting the first direction (Z), a first string (NSa) arranged on the first side surface of the semiconductor layer (22) in a third direction (X) intersecting the first direction (Z) and the second direction (Y), and a second string (NSb) arranged on the second side surface of the semiconductor layer (22) in the third direction (X). Each of the first strings (NSa) includes a first selection transistor (ST1a) and a plurality of first memory cell transistors (MT0e~MT7e) arranged spaced apart from each other in the second direction (Y), with the semiconductor layer (22) as the channel. The second string (NSb) includes a plurality of first transistors (TR0~TR7) and a second selection transistor (ST2a), each having a semiconductor layer (22) as a channel and being spaced apart from each other in the second direction (Y).

[0409] It should be noted that the embodiments are not limited to the forms described above, and various modifications are possible.

[0410] The above embodiments and modifications may be combined to the extent possible. For example, the second modification of the third embodiment may be combined with the first modification of the third embodiment. The structure shown in Figure 17 in the second modification of the second embodiment may be applied to the second to fifth modifications of the fourth embodiment and the fifth embodiment. The fifth embodiment may be combined with the fourth embodiment or any of the first, second, third, and fifth modifications of the fourth embodiment.

[0411] Furthermore, the flowchart described in the above embodiment allows for rearranging the order of processing as much as possible.

[0412] In the third embodiment, the string flgS in block BLK was used, and in the first modification of the third embodiment, the string table tblS was used. However, instead of these, a string flag flgS may be added to FAT.

[0413] In the second and fourth modifications of the fourth embodiment, the mode flgM within block BLK was used, and in the third and fifth modifications of the fourth embodiment, the mode table tblM was used. However, instead of these, a mode flag flgM may be added to FAT.

[0414] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0415] 1...Memory system, 2...Memory controller, 3...Semiconductor memory device, 4...AI module, 5...GPU, 6...CPU, 7...DRAM, 10...Memory cell array, 11...Command register, 12...Address register, 13...Programmable logic controller, 14...Driver module, 15...Raw decoder module, 16...Sense amplifier module, 17...Arithmetic module, 18...Register, 19...Arithmetic circuit, 20...Substrate, 21...Insulator layer, 22...Semiconductor layer, 23...Insulator layer, 30...Conductive film, 31...Insulator film, 32...Charge storage film, 33...Insulator film, 34...Insulator, 40...Conductive film, 41...Insulator film, 50...Conductive film, 51...Insulator film, 60...Conductive film, 61...Semiconductor film, CPS...Semiconductor, INS...Insulator, CGP, SGP, TRP...Conductive pillar, MS...Memory structure, BC...Contact plug, LBI...Wiring

Claims

1. Each of these is a multiple memory string, spaced apart from one another in the first direction. Equipped with, Each of the aforementioned plurality of memory strings is A semiconductor layer extending in a second direction intersecting the first direction, A first string is arranged on the first side surface of the semiconductor layer in a third direction intersecting the first and second directions, A second string arranged on the second side surface of the semiconductor layer in the third direction and Includes, Each of the first strings includes a first selection transistor and a plurality of first memory cell transistors, each having the semiconductor layer as a channel and arranged spaced apart from each other in the second direction. Each of the second strings includes a plurality of first transistors and second selection transistors, each having the semiconductor layer as a channel and arranged spaced apart from each other in the second direction. Semiconductor memory device.

2. Each of the plurality of first transistors in the second string has the same structure as the first selection transistor and the second selection transistor. The semiconductor memory device according to claim 1.

3. During the read operation, cell current is not supplied to any of the multiple first memory cell transistors in the first string other than the selected first memory cell transistor. Among the plurality of first transistors in the second string, one or more first transistors located near the selected first memory cell transistor are not supplied with cell current, while the remaining first transistors are supplied with cell current. The semiconductor memory device according to claim 1.

4. Each of these is a set of memory strings, each of which is spaced apart from the others in the first direction within each of the multiple blocks. Equipped with, Each of the aforementioned plurality of memory strings is A semiconductor layer extending in a second direction intersecting the first direction, A first string is arranged on the first side surface of the semiconductor layer in a third direction intersecting the first and second directions, A second string arranged on the second side surface of the semiconductor layer in the third direction and Includes, Each of the first strings includes a first selection transistor and a plurality of first memory cell transistors, each having the semiconductor layer as a channel and arranged spaced apart from each other in the second direction. The second string includes a plurality of second memory cell transistors and second selection transistors, each of which has the semiconductor layer as a channel and is spaced apart from each other in the second direction. The data is written to either the first string or the second string. Semiconductor memory device.

5. The string on which the aforementioned data is written is switched in block units. The semiconductor memory device according to claim 4.

6. The string on which the aforementioned data is written is periodically switched. The semiconductor memory device according to claim 5.

7. The string to which the aforementioned data is written is switched each time a write operation is performed on the selected block. The semiconductor memory device according to claim 6.

8. A predetermined data is written to either the first string or the second string. The semiconductor memory device according to claim 4.

9. The aforementioned predetermined data is data at the write level in SLC. The semiconductor memory device according to claim 8.

10. Each of these is a set of memory strings, each of which is spaced apart from the others in the first direction within each of the multiple blocks. Equipped with, Each of the aforementioned plurality of memory strings is A semiconductor layer extending in a second direction intersecting the first direction, A first string is arranged on the first side surface of the semiconductor layer in a third direction intersecting the first and second directions, A second string arranged on the second side surface of the semiconductor layer in the third direction and Includes, Each of the first strings includes a first selection transistor and a plurality of first memory cell transistors, each having the semiconductor layer as a channel and arranged spaced apart from each other in the second direction. The second string includes a plurality of second memory cell transistors and second selection transistors, each of which has the semiconductor layer as a channel and is spaced apart from each other in the second direction. In the first block, where the storage mode is set to the first mode, the write data is written to either the first string or the second string, and in the second block, where the storage mode is set to the second mode, the write data is written to both the first string and the second string. Semiconductor memory device.

11. Among the aforementioned plurality of blocks, a fixed block is designated as the first mode. The semiconductor memory device according to claim 10.

12. Based on the number of times the data of the selected block is accessed, the boundary position between the first block and the second block within the plurality of blocks is changed. The semiconductor memory device according to claim 10.

13. If the number of read operations for the data in the second block exceeds a first threshold within a certain period of time, the storage mode of the second block is switched to the first mode. If there are no read operations for the data in the first block within a certain period of time, the storage mode of the first block is switched to the second mode. The semiconductor memory device according to claim 12.

14. During a write operation, the storage mode of the selected block is specified. The semiconductor memory device according to claim 10.

15. Each of the plurality of blocks stores a first flag as information indicating whether the storage mode of the selected block is designated as the first mode or the second mode. The first flag is updated during the write operation. The semiconductor memory device according to claim 14.

16. The semiconductor memory device according to claim 14, The memory controller that controls the aforementioned semiconductor storage device Equipped with, The memory controller includes a first table as information indicating whether the storage mode of the selected block is designated as the first mode or the second mode, and updates the first table during a write operation. Memory system.

17. Each of the plurality of blocks has multiple bit lines connected to one of the plurality of memory strings contained in each of the plurality of blocks, Computation module and Furthermore, The aforementioned calculation module is Each of the multiple registers is connected to one of the bit lines, Each of these is connected to one of the bit lines, and Includes, Each of the arithmetic circuits performs arithmetic processing based on the first data in the first memory string in the first block and the second data in the second memory string in the second block. The semiconductor memory device according to claim 10.

18. Each of the arithmetic circuits executes the arithmetic process using the second data based on the calculation content specified by the first data. The semiconductor memory device according to claim 17.

19. The arithmetic circuit stores the result of the arithmetic process in the third memory string within the second block. The semiconductor memory device according to claim 17.

20. The arithmetic circuit executes a predetermined algorithmic process based on the result of the arithmetic process, and updates the first data of the first memory string in the first block based on the result of the algorithmic process. The semiconductor memory device according to claim 17.

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