Program verification techniques for memory devices

Abstract

This invention provides a method for performing programming operations in a memory device and a memory device itself. [Solution] The memory device 100 includes a memory array 126 having a memory block having a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings. The memory device also includes a control circuit 110 having a programming circuit that programs the memory cells of a selected word line from the plurality of word lines into a plurality of data states in a plurality of program loops including programming pulses and verification operations. The circuit does not lock out a set of the plurality of NAND strings during at least one of the verification operations. The NAND strings of the set include at least some of the memory cells of the selected word line that have completed programming so that electricity conducts through the NAND strings of the set during sensing.

Description

Technical Field

[0001] (Field of the Invention) The present disclosure generally relates to improved program verification techniques for countering the effects of CELSRC bounce.

[0002] (Related Art) Semiconductor memories are widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile memories or volatile memories. Non-volatile memories enable information to be stored and retained even when the non-volatile memory is not connected to a power source, such as a battery.

[0003] A NAND memory device includes a chip having a plurality of memory blocks, each of the memory blocks including an array of memory cells arranged in a plurality of word lines. Programming the memory cells of a word line to hold data is typically performed in a plurality of program loops, each of the program loops including the application of a programming pulse to the control gate of the word line and a verification operation for sensing the threshold voltage of the programmed memory cells. Data is sensed both during the programming operation and during subsequent read operations. There continues to be a need for improved sensing techniques to improve the reliability of the sensing operations.

Summary of the Invention

[0004] One aspect of the present disclosure relates to a method for performing a programming operation in a memory device. The method proceeds to the step of preparing a memory block including a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings. The method proceeds to the step of programming a memory cell of a selected word line from the plurality of word lines into a plurality of data states in a plurality of program loops. The programming loop includes a programming pulse and a verification operation. In at least one of the program loops, during the verification operation, the method proceeds to the step of not locking out a set of the plurality of NAND strings. The set of NAND strings includes at least some of the memory cells of the selected word line that have completed programming so that electricity is conducted through the set of NAND strings during sensing.

[0005] According to another aspect of the present disclosure, the programmed data states include a plurality of earlier data states associated with a relatively lower threshold voltage range and a plurality of later data states associated with a relatively higher threshold voltage range.

[0006] According to yet another aspect of this disclosure, during the programming of multiple late data states, a step is taken in which the set of NAND strings is not locked out so that electricity is conducted through the set of NAND strings during detection.

[0007] According to yet another aspect of this disclosure, a programmed plurality of data states comprises seven programmed data states, and a plurality of late data states comprises three of the seven programmed data states.

[0008] According to a further aspect of this disclosure, the set of NAND strings includes NAND strings coupled to memory cells of all but one of the programmed data states that have been programmed.

[0009] According to further aspects of this disclosure, the memory device further includes a source line, which is set to approximately 0 volts (zero volt, 0V) during detection.

[0010] According to a further aspect of the present disclosure, the method further includes the step of applying a verification voltage to a selected word line during at least one verification operation of the program loop.

[0011] Another aspect of the present disclosure relates to a memory device including a memory block having a plurality of word lines and a plurality of memory cells arranged in a plurality of NAND strings. The memory device also includes a circuit configured to program a memory cell of a selected word line from the plurality of word lines into a plurality of data states in a plurality of program loops, including a programming pulse and a verification operation. The circuit is configured not to lock out a set of the plurality of NAND strings during at least one of the verification operations. The set of NAND strings includes at least some of the memory cells of the selected word line that have completed programming so that electricity conducts through the set of NAND strings during sensing.

[0012] According to another aspect of the present disclosure, the programmed data states include a plurality of earlier data states associated with a relatively lower threshold voltage range and a plurality of later data states associated with a relatively higher threshold voltage range.

[0013] According to yet another aspect of this disclosure, the circuit is configured not to lock out a set of multiple NAND strings during the programming of multiple late data states.

[0014] According to yet another aspect of this disclosure, a programmed plurality of data states comprises seven programmed data states, and a plurality of late data states comprises three of the seven programmed data states.

[0015] According to a further aspect of this disclosure, the set of NAND strings includes NAND strings coupled to memory cells of all but one of the programmed data states that have been programmed.

[0016] According to further aspects of this disclosure, the memory device further includes a source line, and during detection, the circuit sets the source line to approximately 0 volts (0V).

[0017] According to yet another aspect of this disclosure, during at least one verification operation of the program loop, the circuit applies a verification voltage to a selected word line.

[0018] Another aspect of the present disclosure relates to a device including a memory block having a plurality of word lines and a plurality of memory cells arranged in a plurality of NAND strings. The device also includes programming means for programming a memory cell of a selected word line from the plurality of word lines into a plurality of data states in a plurality of program loops, including a programming pulse and a verification operation. The programming means is configured not to lock out a first set of the plurality of NAND strings, the first set of NAND strings containing at least some of the memory cells of the selected word line that has been programmed, during at least one of the verification operations. The programming means is also configured to conduct electricity through the first set of NAND strings and through a second set of NAND strings containing the memory cells of the selected word line that is being programmed.

[0019] According to yet another aspect of this disclosure, the programmed data states include a plurality of earlier data states associated with a relatively lower threshold voltage range and a plurality of later data states associated with a relatively higher threshold voltage range.

[0020] According to yet another aspect of the present disclosure, the programming means is configured not to lock out a set of a plurality of NAND strings during the programming of a plurality of late data states.

[0021] According to a further aspect of the present disclosure, the plurality of programmed data states includes seven programmed data states, and the plurality of late data states includes three of the seven programmed data states.

[0022] According to yet a further aspect of the present disclosure, the first set of NAND strings includes NAND strings coupled to memory cells of all but one of the programmed data states that have completed programming.

[0023] According to yet a further aspect of the present disclosure, the apparatus further includes a source line, and during sensing, the programming means sets the source line to approximately 0 volts (0V).

Brief Description of the Drawings

[0024] A more detailed description will be set forth below with reference to the exemplary embodiments shown in the accompanying drawings. It is to be understood that these drawings show only exemplary embodiments of the present disclosure and are not to be regarded as limiting the scope of the present disclosure. The present disclosure will be described and explained with additional specificity and detail through the use of the accompanying drawings. [Figure 1A] It is a block diagram of an exemplary memory device. [Figure 1B] It is a block diagram of an exemplary control circuit. [Figure 1C] It is a block diagram of an exemplary circuit of the memory device of FIG. 1A. [Figure 2] It shows a block of memory cells of an exemplary two-dimensional configuration of the memory array of FIG. 1A. [Figure 3A] It shows a cross-sectional view of an exemplary floating gate memory cell in a NAND string. [Figure 3B]A cross-sectional view of an exemplary floating-gate memory cell in a NAND string is shown. [Figure 4A] A cross-sectional view of an exemplary charge trap memory cell in a NAND string is shown. [Figure 4B] A cross-sectional view of an exemplary charge trap memory cell in a NAND string is shown. [Figure 5] An exemplary block diagram of the sense block SB1 of FIG. 1 is shown. [Figure 6A] A perspective view of a set of blocks of an exemplary three-dimensional configuration of the memory array of FIG. 1 is shown. [Figure 6B] An exemplary cross-sectional view of a portion of one of the blocks of FIG. 6A is shown. [Figure 6C] A plot of the memory hole diameter in the stack of FIG. 6B is shown. [Figure 6D] An enlarged view of the region 622 of the stack of FIG. 6B is shown. [Figure 7A] A top view of an exemplary word line layer WL0 of the stack of FIG. 6B is shown. [Figure 7B] A top view of an exemplary upper dielectric layer DL116 of the stack of FIG. 6B is shown. [Figure 8] The threshold voltage distribution of a page of memory cells programmed to 1 bit per memory cell (SLC) is shown. [Figure 9] The threshold voltage distribution of a page of memory cells programmed to 3 bits per memory cell (TLC) is shown. [Figure 10] A waveform of the voltage applied to a selected word line during an exemplary programming operation is shown. [Figure 11] A schematic diagram of a selected NAND string during an exemplary sensing operation is shown. [Figure 12] A plot of the sense node voltage versus time during an exemplary sensing operation is shown. [Figure 13] A schematic diagram of an exemplary memory block including a plurality of NAND strings during a sensing operation is shown. [Figure 14]This schematic diagram illustrates the voltages applied to multiple word lines in a memory block during an exemplary negative detection operation. [Figure 15] This schematic diagram illustrates the voltages applied to multiple word lines in a memory block during an exemplary positive detection operation. [Figure 16] This is a threshold voltage distribution plot of two sets of memory cells programmed into a data state, one set of memory cells programmed using positive sensing during the verification operation, and the other set programmed using negative sensing during the verification operation. [Figure 17A] This is a threshold voltage distribution plot of multiple memory cells programmed to 3 bits per memory cell (TLC) during programming of the S6 data state by one type of programming operation. [Figure 17B] This is a threshold voltage distribution plot of multiple memory cells programmed into the TLC during the S6 data state read operation. [Figure 18] This is a flowchart including steps for programming a memory device according to an exemplary embodiment of the present disclosure. [Figure 19A] This is a threshold voltage distribution plot of multiple memory cells programmed into a TLC during programming of the S6 data state by a programming operation of an exemplary embodiment. [Figure 19B] This is a threshold voltage distribution plot of multiple memory cells programmed into the TLC during the S6 data state read operation. [Modes for carrying out the invention]

[0025] This disclosure relates, in general, to program verification techniques that prevent a specific NAND string coupled to a memory cell that has already been programmed from being locked out during detection. This allows CELSRC bounces occurring during positive detection to exhibit a more consistent pattern in both verification and read operations. This consistency improves the overall reliability of the data programmed into the memory cell. These techniques are discussed in more detail below.

[0026] Figure 1A is a block diagram of an exemplary memory device 100 configured to program memory cells in the word lines of a memory block using the sensing technique of the present disclosure. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks SB1, SB2, ... SBp (sensing circuits) that enable pages of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable storage card) as one or more memory dies 108. Commands and data are transferred between a host 140 and the controller 122 via a data bus 120 and between the controller and one or more memory dies 108 via wiring 118.

[0027] The memory structure 126 may be two-dimensional or three-dimensional. The memory structure 126 may comprise one or more arrays of memory cells, including a three-dimensional array. The memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed on (and not on) a single substrate, such as a wafer, without an intervening substrate. The memory structure 126 may include any type of non-volatile memory monolithically formed at one or more physical levels of an array of memory cells having active regions disposed on a silicon substrate. The memory structure 126 may be a non-volatile memory device having a circuit associated with the operation of a memory cell, where this associated circuit is on or within the substrate.

[0028] The control circuit 110 works in cooperation with the read / write circuit 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of the memory operations.

[0029] The memory area 113 may be provided, for example, for programming parameters. Programming parameters may include a program voltage, a program voltage bias, a location parameter indicating the location of a memory cell, a contact line connector thickness parameter, a verification voltage, and the like. The location parameter may indicate the location of a memory cell within the entire array of NAND strings, the location of a memory cell as one within a particular group of NAND strings, the location of a memory cell on a particular plane, and the like. The contact line connector thickness parameter may indicate the contact line connector, the substrate or material on which the contact line connector is formed, and the like.

[0030] The on-chip address decoder 114 provides an address interface between the address used by the host or memory controller and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltage supplied to the word and bit lines during memory operation. The power control module 116 may include drivers for the word lines, SGS and SGD transistors, and source lines. The sense block may include a bit line driver in one method. The SGS transistor is a selection gate transistor at the source end of the NAND string, and the SGD transistor is a selection gate transistor at the drain end of the NAND string.

[0031] In some embodiments, some of the components can be combined. In various designs, one or more components other than the memory structure 126 (either individually or in combination) may be considered as at least one control circuit configured to perform the operations described herein. For example, the control circuit may include any one of the following, or a combination thereof: control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sense blocks SBb, SB2..., SBp, read / write circuit 128, controller 122, etc.

[0032] The control circuit 150 may include a programming circuit 151 configured to perform a programming and verification operation for one set of memory cells, the set of memory cells including a memory cell assigned to represent one data state out of a plurality of data states and a memory cell assigned to represent another data state out of a plurality of data states, and the programming and verification operation includes a plurality of programming and verification iterations, in which the programming circuit performs programming for one selected word line, and then the programming circuit applies a verification signal to the selected word line. The control circuit 150 may also include a counting circuit 152 configured to obtain a count of memory cells that have passed the verification test for one data state. The control circuit 150 may also include a determination circuit 153 configured to determine whether the programming operation is complete based on the amount by which the count exceeds a threshold.

[0033] For example, Figure 1B is a block diagram of an exemplary control circuit 150 comprising a programming circuit 151, a counting circuit 152, and a determination circuit 153.

[0034] The off-chip controller 122 may include a processor 122c, memory devices such as ROM 122a and RAM 122b, an error-correction code (ECC) engine 245, and a lockout engine 246. The ECC engine can correct some read errors caused by the upper tail of the Vt distribution becoming too high. However, in some cases, uncorrectable errors may exist. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0035] The memory devices 122a and 122b contain code, such as an instruction set, and the processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, the processor 122c may access code from the memory device 126a of the memory structure 126, such as reserved areas of memory cells in one or more word lines. For example, the controller 122 may use the code to access the memory structure 126 for programming operations, read operations, and erase operations. The code may include boot code and control code (e.g., an instruction set). The boot code is software that initializes the controller 122 during the boot or startup process and enables the controller 122 to access the memory structure 126. The code can be used by the controller 122 to control one or more memory structures 126. When powered on, the processor 122c fetches the boot code from ROM 122a or memory device 126a for execution, and the boot code initializes system components and loads the control code into RAM 122b. Once loaded into RAM122b, the control code is executed by processor 122c. The control code includes drivers for performing basic tasks such as memory control and allocation, instruction processing prioritization, and I / O port control.

[0036] In general, control codes may include instructions for performing the functions described herein, including steps in the flowchart further discussed below, and for providing voltage waveforms, including those further discussed below. For example, as illustrated in Figure 1C, control circuits 110, controller 122, 150, and / or any other circuits are configured / programmed to perform programming operations using specific NAND string lockout techniques. In step 160, data states S1 to Sn-1 are programmed without using specific lockout techniques. In step 161, during the verification of data states Sn to S7, all Er to Sn-1 memory cells are not locked out (electrically conductive) except for one of their data states. These techniques are discussed in more detail below.

[0037] In one embodiment, the host is a computing device (e.g., a laptop, desktop, smartphone, tablet, or digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, or solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0038] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0039] Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0040] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistive switching memory elements such as anti-fuse or phase-change materials, and optionally steering elements such as diodes or transistors. As a further non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that include charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0041] Multiple memory elements can be configured so that they are connected in series, or so that each element is individually accessible. As a non-limiting example, flash memory devices with a NAND configuration (NAND memory) typically include memory elements connected in series. A NAND string is an example of a set of transistors connected in series, comprising memory cells and SG transistors.

[0042] A NAND memory array may be configured such that the array consists of multiple memory strings, each string comprising multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured such that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements may be configured in other ways. Semiconductor memory elements located in and / or on a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0043] In a two-dimensional memory structure, semiconductor memory elements are arranged on a single plane or at the level of a single memory device. Typically, in a two-dimensional memory structure, memory elements are arranged on a plane (e.g., an xy-direction plane) that extends substantially parallel to the principal surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of memory elements are formed, or a carrier substrate attached to the memory elements after they have been formed. In non-limiting examples, the substrate may include semiconductors such as silicon.

[0044] Memory elements may be arranged in an ordered array, such as multiple rows and / or columns, at the level of a single memory device. However, memory elements may be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0045] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular to the main plane of the substrate, and the x and y directions are substantially parallel to the main plane of the substrate).

[0046] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory devices. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns substantially perpendicular to the main plane of the substrate, i.e., extending in the y-direction) each having multiple memory elements. The columns may have a three-dimensional arrangement of memory elements in a two-dimensional configuration, e.g., arranged in the xy-plane and having elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0047] As a non-restrictive example, in a three-dimensional memory array of NAND strings, memory elements may be joined together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be joined together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned where some NAND strings contain memory elements within a single memory level, and others contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0048] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. In a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on layers of memory device levels beneath the array. However, adjacent memory device level layers in a monolithic three-dimensional memory array may be shared, or there may be intervening layers between the memory device levels.

[0049] In this case as well, the two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0050] Figure 2 illustrates memory blocks 200, 210 of an exemplary two-dimensional memory cell configuration of the memory array 126 of Figure 1. The memory array 126 can contain many such blocks 200, 210. Each exemplary block 200, 210 includes several NAND strings and respective bit lines shared between blocks, e.g., BL0, BL1, ... Each NAND string is connected at one end to a drain-side selection gate (SGD), and the control gate of the drain-side selection gate is connected via a common SGD line. The NAND strings are connected at their other ends to source-side selection gates (SGS), and the source-side selection gates (SGS) are connected to a common source line 220. Between the SGS and SGD, there are 112 word lines, e.g., WL0 to WL111. In some embodiments, a memory block may contain more or fewer word lines than 112. For example, in some embodiments, a memory block may contain 164 word lines. In some cases, dummy word lines that do not contain user data can be used in the memory array adjacent to the selection gate transistor, or between specific data word lines. Such dummy word lines can shield edge data word lines from certain edge effects.

[0051] One type of non-volatile memory that can be provided in a memory array is a floating-gate memory, such as the type shown in Figures 3A and 3B. However, other types of non-volatile memory can also be used. As will be discussed in more detail below, in another example shown in Figures 4A and 4B, a charge-trap memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A triple-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductor substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a restricted region. This stored charge then causes a detectable change in the threshold voltage of a portion of the cell's channel. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration in which a doped polycrystalline silicon gate extends over a portion of the memory cell channel to form distinct selective transistors.

[0052] Another approach uses NROM cells. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over a channel between the source and drain diffusion regions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0053] Figure 3A illustrates cross-sectional views of exemplary floating-gate memory cells 300, 310, and 320 in a NAND string. In this figure, the bit line or NAND string direction is towards the back of the page, and the word line direction is from left to right. As an example, word line 324 extends across the NAND strings, each containing channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is located in a different NAND string. An interlayer polydielectric (IPD) layer 328 is also illustrated. Control gates 302, 312, and 322 are part of the word line. A cross-sectional view along the contact line connector 329 is provided in Figure 3B.

[0054] The control gates 302, 312, and 322 enclose the floating gates 304, 314, and 321, increasing the surface contact area between the control gates 302, 312, and 322 and the floating gates 304, 314, and 321. This results in a higher coupling ratio, which leads to a higher IPD capacitance and makes programming and erasing easier. However, as NAND memory devices shrink, the spacing between adjacent cells 300, 310, and 320 decreases, so there is little space left between two adjacent floating gates 302, 312, and 322 for the control gates 302, 312, and 322 and the IPD layer 328.

[0055] As an alternative, flat or planar memory cells 400, 410, 420 have been developed, as shown in Figures 4A and 4B, in which the control gates 402, 412, 422 are flat or planar, i.e., the control gate does not enclose the floating gate, and the only contact with the charge storage layer 428 is from above the charge storage layer 428. In this case, there is no advantage to having a high floating gate. Instead, the floating gate can be made very thin. Furthermore, the floating gate can be used to store charge, or a thin charge trap layer can be used to trap charge. This technique can avoid the problem of ballistic electron transport, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0056] Figure 4A shows a cross-sectional view of exemplary charge trap memory cells 400, 410, and 420 in a NAND string. This figure is a word line direction of memory cells 400, 410, and 420, including flat control gates and charge trap regions, as a two-dimensional example of memory cells 400, 410, and 420 in the memory cell array 126 of Figure 1. Charge trap memory can be used in NOR and NAND flash memory devices. This technique uses an insulator such as a SiN film to store electrons, in contrast to floating-gate MOSFET technology which uses a conductor such as doped polycrystalline silicon to store electrons. As an example, word line 424 extends and spreads across the NAND string, including the respective channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are the IPD layer 428, charge trap layers 404, 414, 421, polycrystalline silicon layers 405, 415, 425, and tunnel layers 409, 407, 408. Each charge trap layer 404, 414, 421 extends continuously in its respective NAND string. The planar shape of the control gate can be made thinner than that of a floating gate. Additionally, memory cells can be placed closer to each other.

[0057] Figure 4B illustrates a cross-sectional view of the structure of Figure 4A along the contact wire connector 429. The NAND string 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ... 435, and an SGD transistor 436. The passages in the IPD layer 428 in the SGS transistor 431 and the SGD transistor 436 allow the control gate layer 402 and the floating gate layer to communicate. For example, the control gate 402 and the floating gate layer may be polycrystalline silicon, and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be a stack of nitride (N) and oxide (O), such as a non-non-on configuration.

[0058] A NAND string may be formed on a substrate comprising a p-type substrate region 455, an n-type well 456, and a p-type well 457. The p-type well has n-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 formed therein. The channel voltage Vch may be applied directly to the channel region of the substrate.

[0059] Figure 5 illustrates an exemplary block diagram of sense block SB1 in Figure 1. In one approach, the sense block comprises multiple sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different subsets of bit lines may be sensed using different sense blocks. This allows the processing load associated with the sense circuits to be shared and processed by the respective processors in each sense block. For example, a sense circuit controller 560 in SB1 can communicate with a set of sense circuits and latches. The sense circuit controller 560 may include a precharge circuit 561 that supplies voltage to each sense circuit to set the precharge voltage. In one possible approach, the voltage is supplied independently to each sense circuit, for example, via a data bus and a local bus. In another possible approach, a common voltage is supplied to each sense circuit simultaneously. The sense circuit controller 560 may also include a precharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code executable by the processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, and 553b associated with the sense circuits 550a, 551a, 552a, and 553a, setting bit values ​​in the latches, and providing voltages to set precharge levels to the sense nodes of the sense circuits 550a, 551a, 552a, and 553a. Further illustrative details of the sense circuit controller 560 and the sense circuits 550a, 551a, 552a, and 553a are provided below.

[0060] In some embodiments, a memory cell may include a flag register containing a set of latches that store flag bits. In some embodiments, the number of flag registers may correspond to the number of data states. In some embodiments, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of a flag bit may modify the associated logic of the device, such as an address decoding circuit, so that a specified block of the cell is selected. Bulk operations (such as an erase operation) may be performed using the flags set in the flag registers, or using a combination of the flag register and an address register, as in implicit addressing, or alternatively, by direct addressing using the address register alone.

[0061] Figure 6A is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of Figure 1. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3, which are memory cells (storage elements), and a peripheral region 604 having circuits used by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuits may include voltage drivers 605 that can be connected to the control gate layers of blocks BLK0, BLK1, BLK2, and BLK3. In one method, control gate layers of common height in blocks BLK0, BLK1, BLK2, and BLK3 are driven in common. The substrate 601 can also hold the circuits beneath blocks BLK0, BLK1, BLK2, and BLK3 together with one or more lower metal layers patterned into conductive paths to carry the signals of the circuits. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in the intermediate region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned with conductive paths for carrying circuit signals. Each block BLK0, BLK1, BLK2, BLK3 contains a stack region of memory cells where alternating levels of the stack represent word lines. In one possible method, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides from which vertical contacts extend upward to the upper metal layer, forming connections to the conductive paths. Although four blocks BLK0, BLK1, BLK2, BLK3 are illustrated as an example, two or more blocks extending in the x and / or y directions can be used.

[0062] In one possible method, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0063] Figure 6B illustrates an exemplary cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, and BLK3 in Figure 6A. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers include data word line layers (word lines) WL0 to WL111, as well as two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL116. Furthermore, a region of the stack 610 comprising NAND strings NS1 and NS2 is illustrated. Each NAND string contains memory holes 618, 619 filled with material that forms memory cells adjacent to the word line. Region 622 of the stack 610 is shown in detail in Figure 6D and will be discussed in further detail below. The dielectric layer may have a variable thickness such that some of the conductive layers may be closer to or further away from adjacent conductive layers. The thickness of the dielectric layer affects the "on-pitch," a factor in memory density. Specifically, a smaller on-pitch allows for more memory cells in a given area, but may compromise reliability.

[0064] The stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source end 613 at the bottom 614 of the stack and a drain end 615 at the top 616 of the stack 610. Contact line connectors (e.g., slits such as metal-filled slits) 617, 620 may be periodically provided across the stack 610 as interconnects extending through the stack 610, such as for connecting a source line to a specific contact line on the stack 610. The contact line connectors 617, 620 may be used during the formation of a word line and then filled with metal. A portion of a bit line BL0 is also illustrated. A conductive via 621 connects the drain end 615 to BL0.

[0065] Figure 6C illustrates a plot of memory hole diameters in the stack of Figure 6B. The vertical axis is positionally aligned with the stack in Figure 6B and illustrates the width (wMH), e.g., diameter, of memory holes 618 and 619. The word line layers WL0 to WL111 in Figure 6A are repeated as an example, at their respective heights z0 to z111 in the stack. In such memory devices, memory holes etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25 to 30 is common. Memory holes may have a circular cross-section. Due to the etching process, the memory hole width may vary along the length of the hole. Typically, the diameter gradually decreases from the top to the bottom of the memory hole; that is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, there is a slight narrowing at the top of the hole near the selected gate, causing the diameter to widen slightly before the gradual decrease from top to bottom of the memory hole.

[0066] Figure 6D illustrates an enlarged view of region 622 of stack 610 in Figure 6B. Memory cells are formed at different levels of the stack at the intersection of the word line layer and the memory hole. In this example, SGD transistors 680, 681 are located on top of dummy memory cells 682, 683 and data memory cell MC. Several layers can be deposited along the sidewalls (SW) of the memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., pillars formed by the material within the memory hole 630) may include a charge trap layer or film 663, a tunnel layer 664, a polycrystalline silicon body or channel 665, and a dielectric core 666, such as SiN or other nitride. The word line layer may include a high-k material 660 of blocking oxide / block, a metal barrier 661, and a conductive metal such as tungsten as a control gate. For example, control gates 690, 691, 692, 693, 694 are provided. In this example, all layers except the metal are located within the memory hole 630. In other methods, some of the layers may be control gate layers. Additional pillars are similarly formed within different memory holes. The pillars can form columnar active areas (AA) of the NAND string.

[0067] When a memory cell is programmed, electrons accumulate in a portion of the charge trap layer associated with the memory cell. These electrons are drawn from the channel through the tunnel layer into the charge trap layer. The threshold voltage Vt of the memory cell increases proportionally to the amount of accumulated charge. During a sensing operation, the threshold voltage Vt is detected or measured. During an erasing operation, the electrons return to the channel.

[0068] Each of the memory holes 630 may be filled with a plurality of annular layers, including a blocking oxide layer, a charge trapping layer 663, a tunnel layer 664, and a channel layer. The core region of each memory hole 630 is filled with body material, and the plurality of layers are located between the core region and the word line layer in each memory hole 630. In some cases, the charge trapping layer 663 and the tunnel layer 664 are annular in shape. In other cases, these layers are semicircular in shape, as will be discussed in more detail below.

[0069] Since the channel length is not formed on the substrate, the NAND string can be considered to have a floating body channel. Furthermore, the NAND string is provided by multiple word line layers stacked vertically and separated from each other by dielectric layers.

[0070] Figure 7A illustrates an exemplary top view of the word line layer WL0 of the stack 610 in Figure 6B. As mentioned, a three-dimensional memory device may comprise a stack of alternating conductive and dielectric layers. The conductive layers provide control gates for the SG transistors and memory cells. The layer used for the SG transistors is the SG layer, and the layer used for the memory cells is the word line layer. Furthermore, memory holes are formed in the stack and filled with charge trapping material and channel material. As a result, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0071] A block BLK in a three-dimensional memory device can be divided into subblocks, each subblock comprising a NAND string group having common SGD control lines. Furthermore, the word line layer within a block can be region-divided. Each region resides in its respective subblock and can extend between contact line connectors (e.g., slits) periodically formed in the stack to process the word line layer during the memory device manufacturing process. This processing may include replacing the sacrificial material of the word line layer with metal. Generally, the distance between contact line connectors should be relatively small, taking into account the limits of the distance the etchant can move laterally to remove the sacrificial material and the distance the metal can move to fill the gaps created by the removal of the sacrificial material. For example, the distance between contact line connectors may allow for several rows of memory holes between adjacent contact line connectors. The layout of memory holes and contact line connectors should also take into account the limit on the number of bit lines that can extend across the region while each bit line connects to a different memory cell. After processing the word line layer, the contact line connectors can optionally be filled with metal to provide interconnects that penetrate the stack.

[0072] In this example, there are four rows of memory holes between adjacent contact line connectors. Here, a row is a group of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are arranged in an alternating pattern to increase the density of memory holes. The word line layer or word line is divided into regions WL0a, WL0b, WL0c, and WL0d, each connected by a contact line 713. In one technique, the last region of the word line layer in one block can be connected to the first region of the word line layer in the next block. The contact line 713 is connected to a voltage driver for the word line layer. Region WL0a has exemplary memory holes 710, 711 along the contact line 712. Region WL0b has exemplary memory holes 714, 715. Region WL0c has exemplary memory holes 716, 717. Region WL0d has exemplary memory holes 718, 719. The memory holes are also shown in Figure 7B. Each memory hole can be part of its respective NAND string. For example, memory holes 710, 714, 716, and 718 may be part of the NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0073] Each circle represents a cross-section of a memory hole in the word line layer or SG layer. Exemplary circles shown with dashed lines represent memory cells provided by the material within the memory hole and by adjacent word line layers. For example, memory cells 720 and 721 are located in WL0a, memory cells 724 and 725 are in WL0b, memory cells 726 and 727 are in WL0c, and memory cells 728 and 729 are in WL0d. These memory cells are at a common height in the stack.

[0074] Contact wire connectors (e.g., slits such as metal-filled slits) 701, 702, 703, and 704 may be located between and adjacent to the edges of regions WL0a to WL0d. Contact wire connectors 701, 702, 703, and 704 provide conductive paths from the bottom to the top of the stack. For example, source wires at the bottom of the stack may be connected to conductive wires on top of the stack, and these conductive wires may be connected to voltage drivers in the peripheral region of the memory device.

[0075] Figure 7B illustrates a top view of the upper dielectric layer DL116, an example of the stack in Figure 6B. The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to its respective voltage driver. This allows simultaneous programming of a set of memory cells in one region of the word line layer, with each memory cell located in its respective NAND string connected to its respective bit line. A voltage can be set on each bit line during each programming, sensing, or erasing operation.

[0076] Region DL116a has exemplary memory holes 710, 711 along contact line 712, which coincides with bit line BL0. Several bit lines extend over the memory holes and connect to them, as indicated by the "X" symbol. BL0 connects to a set of memory holes including memory holes 711, 715, 717, and 719. Another exemplary bit line BL1 connects to a set of memory holes including memory holes 710, 714, 716, and 718. Contact line connectors (slits such as metal-filled slits, for example) 701, 702, 703, and 704 from Figure 7A are also illustrated to extend vertically through the stack. The bit lines may be numbered BL0 through BL23 in the x-direction along DL116.

[0077] Different subsets of bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in adjacent rows of cells adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in adjacent rows of cells adjacent to the first row at the left edge.

[0078] Memory cells in a memory block can be programmed to store one or more bits of data in multiple data states, each data state being associated with its own threshold voltage Vt range and its respective bit or bit sequence. For example, Figure 8 shows the threshold voltage Vt distribution for a group of memory cells programmed according to a 1-bit per memory cell (SLC) storage scheme. In the SLC storage scheme, there are two total data states, including an erase state (Er) and a single programmed data state (S1). Figure 9 illustrates the threshold voltage Vt distribution for a 3-bit per cell (TLC) storage scheme, which includes a total of eight data states: the erase state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Each programmed data state (S1-S7) is associated with its respective verification voltage (Vv1-Vv7) used during the verification portion of the programming operation. Similarly, each programmed data state is associated with a unique read voltage that may be the same as or different from its respective verification voltage. Other storage schemes are also available, such as 2 bits per cell with 4 data states (MLC), 4 bits per cell with 16 data states (QLC), or 5 bits per cell with 32 data states (PLC). The QLC storage scheme includes an erase state Er and 15 programmed data states (S1 to S15).

[0079] Programming memory cells is performed string by string and word by word, from one side of the memory block (source or drain) to the other side. In other words, the strings of the first word line (e.g., four strings) are all programmed sequentially, and then this is repeated for the second word line, then the third word line, and so on. Typically, programming memory cells in a selected word line to hold multiple bits per memory cell (e.g., MLC, TLC, or QLC) involves multiple programming loops, starting with the memory cells in an erase data state and increasing the threshold voltage Vt of those memory cells to an appropriate voltage range associated with each intended data state of the memory cell. Each programming loop includes both a programming pulse and a verification operation. Figure 10 shows waveform 1000 of the voltage applied to the selected word line during an exemplary programming operation to program the memory cells in a selected word line to hold more bits per memory cell (e.g., TLC or QLC). As shown, each program loop includes a programming pulse (hereinafter referred to as a VPGM pulse) and one or more verification pulses, depending on which data state is programmed in that particular program loop. For simplicity, a square waveform is shown for each pulse, but other shapes such as multilevel or sloped shapes are possible.

[0080] In this example, the pulse train uses Incremental Step Pulse Programming (ISPP), where the VPGM pulse voltage steps up or increases in each successive program loop. More specifically, the pulse train contains VPGM pulses whose amplitude increases stepwise with each successive program loop by the program voltage step size (dVPGM). A new pulse train begins with a VPGM pulse at the starting voltage VPGMU and ends with a final VPGM pulse that does not exceed the maximum allowable voltage. The exemplary pulse train 1000 includes a series of VPGM pulses 1001-1018 applied to the control gate of a selected word line to program a memory cell in that word line, with the amplitude increasing by the program voltage step size dVPGM between pulses.

[0081] Based on the target data state being verified in each program loop, one or more verification pulses 1020-1036 are provided after each VPGM pulse. The verification voltages may be the voltages Vv1-Vv7 shown in Figure 9 during TLC programming. Simultaneously with the application of the verification voltages, a sensing operation is performed to determine whether a particular memory cell in a selected word line has a threshold voltage Vt that is above the verification voltage Vv associated with its intended data state, by sensing the current through the NAND string containing the memory cells. If a memory cell passes verification, the programming of that memory cell is complete, and further programming of that memory cell is prohibited (or locked out) for all remaining program loops by applying a prohibition voltage to the bit lines coupled to the memory cell simultaneously with the VPGM pulse, and by skipping verification for those memory cells. During the bit scan operation, the memory device determines whether the programming of one or more of the data states is complete. Programming proceeds until all (or a sufficient number) memory cells in the selected word line pass verification for the intended state of the memory cells (in which case the programming passes), or until a predetermined maximum number of program loops are exceeded (in which case the programming fails).

[0082] Referring to Figures 11 and 12, during a detection operation (e.g., program verification or read), the drain-side sense node SEN of the memory block is charged to a predetermined charge voltage. A reference voltage VCG (e.g., Vv1 to Vv7 in Figure 9 during verification) is applied to the control gate of the selected word line WLn. Simultaneously, all memory cells in the NAND string, except for the memory cells of the selected word line, are "turned on" (made conductive) by applying a path voltage VREAD or VREADK to the unselected word lines. A relatively high path voltage VREADK is applied to the pair of adjacent word lines WLn-1 and WLn+1 directly adjacent to the selected word line WLn, and a relatively low path voltage VREAD is applied to all other unselected word lines in the memory block. The sense node SEN is then discharged through the NAND string for the sense time T_Sense. Since all but one of the memory cells in the selected word line WLn are turned on by the pass voltages VREAD, VREADK, the discharge current ICELL through the NAND string is primarily determined by the threshold voltage Vt of the detected selected memory cell. More specifically, the discharge current is determined by whether the threshold voltage Vt is greater than or less than the reference voltage VCG applied to the selected word line WLn during this process. At discharge time T_Sense, the voltage on the sense node SEN is detected by the sensing circuit and compared to the sense voltage V_Sense, which is the threshold voltage Vt of the sensing transistor. If the threshold voltage Vt of the detected memory cell is higher than the reference voltage VCG, the selected memory cell is "off," conducting a very small / negligible current and resulting in only a slight discharge of the SEN node voltage, thereby maintaining a higher voltage on the sense node compared to V_Sense. If the threshold voltage Vt of the detected selected memory cell is lower than the reference voltage VCG, the memory cell is "on," conducting a larger discharge current and resulting in a sense node bias lower than V_Sense. Through this process, it is determined whether the threshold voltage Vt of the memory cell is above or below the reference voltage VCG.This process can be repeated for each programmed data state.

[0083] Figure 13 illustrates the structure of a memory device. For example, Figure 13 shows multiple memory strings (e.g., NAND strings) connected to a common BSL layer or cell source (CELSRC) layer of a memory device. The source nodes of the NAND strings are connected to the CELSRC. As further shown in Figure 13, the nodes connecting the memory holes to the sense amplifiers SA are bit lines BL, and during detection (verification or readout), cell current ICELL flows from each sense amplifier SA to the CELSRC layer. The CELSRC driver drives the CELSRC layer from both sides of the node. As a result, during detection, when current ICELL flows to the CELSRC layer through many bit lines, the voltage at each point around the CELSRC layer can fluctuate. More specifically, during detection, the CELSRC voltage may be lowest adjacent to the connection with the CELSRC driver and highest at the central location between the CELSRC drivers.

[0084] The variable voltage across the CELSRC layer caused by current in a NAND string affects the magnitude of ICELL for those same currents in the NAND string. If left uncorrected, this adjustment to ICELL can cause sensing problems by making a particular memory cell appear to have a different threshold voltage Vt than it actually does. More specifically, when the CELSRC voltage increases where a NAND string is connected, the gate-source level Vgs and drain-source level Vds of the memory cells in that NAND string decrease. The decrease in Vgs and Vds reduces ICELL for the current flowing through the NAND string, thereby making a selected memory cell appear as if it is non-conducting or has a higher threshold voltage Vt than it actually does. This phenomenon is illustrated in Figure 13 and occasionally causes CELSRC bounce, which results in a threshold voltage shift (Vt shift). In this figure, the CELSRC gradient is the coefficient of the IR drop (represented as resistance in Figure 13) from the center to the edge of the CELSRC layer. CELSRC bounce and gradient cause detection errors because Vgs and Vds across the NAND string are smaller for cells with higher CELSRC voltages. Since the voltage of the CELSRC layer varies at different locations, memory cells in various NAND strings are detected inconsistently.

[0085] Referring to Figure 14, one detection technique, sometimes known as "negative detection," can be employed to reduce the Vt shift caused by CELSRC bounce. Negative detection involves applying a positive voltage VCELSRC (e.g., VCELSRC=1V) to the CELSRC driver during the detection operation and biasing (increasing) the bit line voltage VBL by the same voltage VCELSRC. The reference voltage VCG and path voltages VREAD and VREADK are also increased by the same positive voltage VCELSRC. Increasing all of these voltages by VCELSRC reduces the voltage fluctuation at the base of the NAND strings across the entire memory block. However, negative detection results in the use of high-current ICCs because all voltages are set to high levels due to the bias. Performance is also compromised because it takes additional time to drive these components to the increased voltage levels.

[0086] Figure 15 illustrates an alternative sensing technique known as "positive sensing." In positive sensing, a very low voltage (e.g., 0 or approximately 0 volts, VSS) is applied to the CELSRC layer during sensing, and no additional bias voltage is applied to the bit line voltage VBL, reference voltage VCG (e.g., any of the verification voltages Vv1-Vv7 illustrated in Figure 9), or pass voltages VREAD, VREADK. As a result, the magnitude of the voltages applied to these components is reduced compared to negative sensing. Therefore, the voltage at which the word line and bit line need to ramp up is reduced, thereby resulting in a reduction in peak current and average current Icc. Additionally, positive sensing eliminates the need to ramp up and ramp down the CELSRC bias, thereby reducing ramp-up and settling times and improving performance compared to negative sensing where all other variables are constant. Thus, positive sensing generally offers improved performance, reduced current usage, and reduced power consumption compared to negative sensing.

[0087] One problem associated with positive sensing is the occurrence of large CELSRC bounces in the preceding program loop for each data state Sn (e.g., any of S1-S7). This is due to the fact that most of the memory cells programmed into data state Sn are conductive, allowing current to flow through many of the NAND strings. This results in relatively high CELSRC bounces, which may cause some memory cells programmed into data state Sn to pass verification too quickly, i.e., before the threshold voltage Vt of the memory cell exceeds the verification voltage Vvn. This phenomenon is illustrated in Figure 16, where reference numerals 1600a and 1600b illustrate the threshold voltage Vt distribution of multiple memory cells programmed into data state Sn using positive sensing, and reference numerals 1602a and 1602b illustrate the threshold voltage Vt distribution of multiple memory cells programmed into the same data state Sn using negative sensing. As shown, the lower tail of the positive detection distribution 1602b extends below the detection level Vvn because some memory cells incorrectly passed the detection too early. One technique to mitigate this problem is to shift the detection level upward during the positive detection to prevent memory cells from passing the detection too early.

[0088] However, positive detection can lead to other problems. During program verification, the number of conductive NAND strings is lower compared to during a typical read operation. This is especially true for higher data states. This is due to the lockout of NAND strings associated with unprogrammed data states during program verification. For example, in TLC programming, regardless of which particular data state Sn is programmed, only about one-eighth (1 / 8) of the NAND strings can be conductive during any given detection operation. In contrast, during reads, the number of locked-out NAND strings is generally lower for earlier data states (e.g., data states S1, S2, and S3) and higher for later data states (e.g., data states S5, S6, and S6). For example, Figure 17A illustrates the threshold voltage Vt distribution of multiple memory cells programmed into the TLC during program verification of the S6 data state, and Figure 17B illustrates the threshold voltage Vt distribution of multiple programmed memory cells during read of the S6 data state. In both of these figures, solid lines illustrate memory cells coupled to conductive (unlocked) NAND strings, and dashed lines illustrate memory cells coupled to non-conductive (locked) NAND strings. As illustrated, substantially more memory cells (and the NAND strings associated with these memory cells) conduct electricity during read operations than during program verification. Therefore, the CELSRC bounce is similar during program verification and read operations in the lower data state, and changes more significantly during program verification and read operations in the higher data state.

[0089] To make CELSRC bounces more consistent during verification and reading across all programmed data states, according to one aspect of this disclosure, a selective non-lockout programmed verification technique is employed such that approximately the same number of NAND strings conduct during both programmed verification and reading, contributing to CELSRC bounces for positive detection. This has been shown to improve reliability and reduce the number of failed bits during reading.

[0090] Figure 18 includes a flowchart 1800 illustrating the steps for programming a selected word line memory according to an exemplary embodiment of the present disclosure. These steps may be performed by a controller, a processor or processing device or any other circuit that executes instructions stored in memory, and / or other circuits described herein that are specifically configured / programmed to perform the following steps.

[0091] The process begins with step 1802, which involves programming an initial data state. Specifically, the initial data state Sn is a predetermined data state in which the selective non-lockout verification technique begins, with data states S1 to Sn-1. A positive sensing scheme is used during the verification operation of the program loop for programming the S1 to Sn-1 data states. In an exemplary embodiment, data state Sn is the S5 data state of the TLC storage scheme (illustrated in Figure 9). In some other embodiments, data state Sn in this step may be the S4, S6, or S7 data state.

[0092] In step 1804, programming for the Sn data state begins with the application of a VPGM pulse to the selected word line. In step 1806, verification of the data state Sn begins. In step 1808, memory cells from data state Sn+1 to the highest data state are locked out, and memory cells programmed to one data state below the selected data state Sn are also locked out. During subsequent sensing operations, no current flows through the NAND string containing the locked-out memory cells. In contrast, current flows through the NAND string containing the unlocked memory cells during subsequent sensing operations. In the exemplary embodiment of Figure 19A, the programmed data state Sn is S6, and data states S7 and S2 are locked out. Memory cells in the other data states Er, S1, S3, S4, and S5 are not locked out.

[0093] In step 1810, a sensing operation is performed on memory cells programmed with data state Sn, and the threshold voltage Vt of these programmed memory cells is compared with the verification voltage Vvn associated with the Sn data state. The sensing operation is a positive sensing operation, which means that the source line is set to approximately 0 volts (0V) while the sense node is discharged. All NAND strings that are not locked out conduct electricity during the sensing operation. The number of memory cells that fail verification is then counted and compared with a predetermined threshold to determine whether the programming of the Sn data state is complete.

[0094] In decision step 1812, it is determined whether the verification of the Sn data state has passed. If the answer in decision step 1812 is "no", then in step 1814, the programming voltage VPGM is increased incrementally by the step size dVPGM, i.e., VPGM = VPGM + dVPGM. Another VPGM pulse is then applied to the selected word line, and the process returns to step 1806.

[0095] If the answer in decision step 1812 is "yes", the process proceeds to decision step 1816. In decision step 1816, it is determined whether the data state Sn is the last data state to be programmed, for example, S7 in the case of TLC. If the answer in decision step 1816 is "no", in step 1818, the programmed data state Sn is advanced incrementally, i.e., Sn = Sn + 1. In step 1820, the programming voltage VPGM is increased incrementally by the step size dVPGM, i.e., VPGM = VPGM + dVPGM. Then, a VPGM pulse is applied to the selected word line. Then, the process returns to step 1806.

[0096] If the answer in decision step 1816 is "yes", the programming operation is completed in step 1822.

[0097] Figure 19A illustrates the threshold voltage Vt distribution of programmed memory cells during programming of data state S6, and Figure 19B illustrates the threshold voltage Vt distribution of multiple programmed memory cells during reading of data state S6. In both of these figures, solid lines indicate memory cells coupled with conducting (unlocked) NAND strings, and dashed lines indicate memory cells coupled with locked-out (non-conducting) NAND strings during detection. As illustrated, according to the technique of this disclosure, approximately the same number of memory cells conduct during both program verification and reading of the S6 data state. Specifically, in both of these operations, about three-quarters (3 / 4) of the NAND string conduct. Therefore, the CELSRC bounce is similar both during program verification and reading. According to the technique of this disclosure, the same occurs for other data states among the later data states, e.g., S5 and S7 data states.

[0098] As illustrated in Figures 19A and 19B, the technique of the present disclosure also enables the use of substantially the same reference voltage VCG during both program verification and reading of late data states.

[0099] In this specification, various terms are used to refer to specific system components. Different companies may refer to the same or similar components by different names, and this description is not intended to distinguish components that have different names but no different functions. To the extent that the various functional units described in the following disclosures are referred to as “modules,” such characterization is intended not to unduly limit the range of potential implementation mechanisms. For example, a “module” may be implemented as a hardware circuit, including a customized very large-scale integrated circuit (VLSI) circuit or gate array, or a ready-made semiconductor including logic chips, transistors, or other discrete components. In further examples, a module may be implemented in a programmable hardware device, such as a field programmable gate array (FPGA), programmable array logic, or programmable logic device. Furthermore, a module may also be implemented, at least in part, by software executed by various types of processors. For example, a module may include segments of executable code that constitute one or more physical or logical blocks of computer instructions that translate into objects, processes, or functions. Furthermore, the executable portions of such modules do not need to be physically located together; rather, they may be stored in different locations and, when executed together, comprise an identified module and comprise different instructions that accomplish the stated purpose of that module. Executable code may consist of only one instruction or multiple instruction sets and may be distributed across different code segments, between different programs, or across several memory devices. In a modular implementation of software or partial software, the software portion may be stored in one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatus, or devices, or any preferred combination thereof.Generally, for the purposes of this disclosure, a computer-readable and / or executable storage medium may consist of any tangible and / or non-temporary medium capable of containing and / or storing a program for use by or in connection with an instruction execution system, apparatus, processor, or device.

[0100] Similarly, for the purposes of this disclosure, the term “component” may consist of any tangible, physical, and non-transient devices. For example, a component may take the form of a hardware logic circuit consisting of a customized VLSI circuit, gate array, or other integrated circuit, or it may consist of a ready-made semiconductor including a logic chip, transistor, or other discrete component, or any other suitable mechanical and / or electronic device. In addition, a component may be implemented in a programmable hardware device, such as a field-programmable gate array (FPGA), programmable array logic, or programmable logic device. Furthermore, a component may consist of one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices, which form an electrical communication configuration with one or more other components via a conductor, such as a printed circuit board (PCB). Thus, the modules defined above may, in certain embodiments, be embodied by components or implemented as components, and in some cases, the terms module and component may be used interchangeably.

[0101] Where the term “circuit” is used herein, it includes one or more electrical and / or electronic components that constitute one or more conductive paths that enable the flow of electric current. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, circuit components may provide a return path for current. In contrast, in an open-loop configuration, the circuit components within it may still be considered to form a circuit, even though they do not include a return path for current. For example, an integrated circuit is referred to as a circuit whether or not the integrated circuit is coupled to ground (as a return path for current). In certain exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include customized VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, and may also include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In further examples, a circuit may comprise one or more silicon-based integrated circuit devices or other discrete electrical devices, such as chips, dies, die planes, and packages, that form an electrical communication configuration with one or more other components, for example, via the conductors of a printed circuit board (PCB). The circuit can also be implemented as a composite circuit with respect to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, the circuit comprises a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Thus, a module as defined above may, in a particular embodiment, be embodied by a circuit or implemented as a circuit.

[0102] It will be understood that exemplary embodiments disclosed herein may consist of one or more microprocessors and specific stored computer program instructions that control one or more microprocessors to implement some, most, or all of the functions disclosed herein, together with certain non-processor circuits and other elements. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or by one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), where each function or some combination of certain functions is implemented as custom logic. Combinations of these methods may also be used. Furthermore, the following references to “controller” shall be defined to include individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and / or processors with control software, or combinations thereof.

[0103] In addition, the terms “couple,” “coupled,” or “couples” as used herein are intended to mean either a direct connection or an indirect connection. Thus, when a first device is coupled to or is coupled to a second device, the connection may be a direct connection or an indirect connection via other devices (or components) and connectors.

[0104] With regard to the use of terms such as “an embodiment,” “one embodiment,” “exemplary embodiment,” “specific embodiment,” or other similar terms in this specification, these terms are intended to indicate that a particular feature, structure, function, operation, or characteristic described in relation to an embodiment is found in at least one embodiment of this disclosure. Accordingly, the appearance of phrases such as “in one embodiment,” “in an embodiment,” and “exemplary embodiment” may all refer to the same embodiment, but not necessarily; rather, unless otherwise expressly specified, they mean “one or more embodiments, but not all.” Furthermore, the terms “comprising,” “having,” and “including,” and their variations, are used in an open-ended manner and should therefore be interpreted as “including, but not limited to,” unless otherwise expressly specified. Also, an element preceded by “comprises…a” does not, without further constraint, exclude the existence of additional identical elements in a process, method, system, article, or apparatus of the subject matter that includes that element.

[0105] The terms “a,” “an,” and “the” also mean “one or more” unless otherwise explicitly specified. For example, “a processor” programmed to perform various functions means one processor programmed to perform any and all functions, or two or more processors collectively programmed to perform each of various functions. In addition, the phrase “at least one of A and B” as used herein and / or in the following claims, where A and B are variables indicating a particular object or attribute, means, like the phrase “and / or,” a selection of A or B, or both A and B. Where there are three or more variables in a phrase, it is defined herein as including one of the variables, any one of the variables, any combination (or partial combination) of any of the variables, and all of the variables.

[0106] Furthermore, as used herein, the terms “about” or “approximately” apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to (e.g., having the same function or result as) the stated value. In certain cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0107] In addition, no enumerated list of items described herein implies that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless otherwise expressly specified. Furthermore, the term “set” as used herein shall be interpreted as meaning “one or more,” and in the case of “set,” unless otherwise expressly specified, it shall be interpreted according to set theory as meaning “one or more,” “ones or more,” and / or multiples of “ones or mores.”

[0108] The above detailed description is provided for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosure to the exact form. Many modifications and variations are possible in light of the above description. The embodiments described have been selected to best illustrate the principles of the Art and its practical applications, thereby enabling those skilled in the art to best utilize the Art in various embodiments and with various modifications suitable for specific intended uses. The scope of the Art is defined by the claims appended herein.

Claims

1. A method for performing programming operations in a memory device, The steps include preparing a memory block containing multiple memory cells arranged in multiple word lines and multiple NAND strings, A plurality of program loops, wherein each program loop includes a programming pulse and a verification operation, the step of programming the memory cell of a selected word line among the plurality of word lines into a plurality of data states, A method comprising the step of not locking out the set of NAND strings during the verification operation, the set of NAND strings, which includes at least some of the memory cells of the selected word lines that have been programmed so that electricity is conducted through the set of NAND strings during detection.

2. The method according to claim 1, wherein the programmed plurality of data states include a plurality of earlier data states associated with a relatively low threshold voltage range and a plurality of later data states associated with a relatively high threshold voltage range.

3. The method according to claim 2, wherein the step of not locking out the set of NAND strings so that electricity is conducted through the set of NAND strings during detection is performed during the programming of the plurality of late data states.

4. The method according to claim 3, wherein the programmed plurality of data states include seven programmed data states, and the plurality of late data states include three of the seven programmed data states.

5. The method according to claim 1, wherein the set of NAND strings comprises the NAND strings coupled to the memory cell for all but one of the programmed data states for which programming has been completed.

6. The method according to claim 1, further comprising a source wire, wherein the source wire is set to approximately 0 volts (0V) during detection.

7. The method according to claim 1, further comprising the step of applying a verification voltage to the selected word line during at least one of the verification operations in the program loop.

8. A memory block containing multiple memory cells arranged in multiple word lines and multiple NAND strings, A circuit comprising a plurality of program loops including programming pulses and verification operations, wherein during at least one of the verification operations, the memory cell of a selected word line among the plurality of word lines is programmed to a plurality of data states, and the circuit is A memory device comprising a set of a plurality of NAND strings, wherein the set of NAND strings is configured not to lock out the set of a plurality of NAND strings, including at least some of the memory cells of the selected word lines which have been programmed so that electricity is conducted through the set of NAND strings during detection.

9. The memory device according to claim 8, wherein the programmed plurality of data states include a plurality of earlier data states associated with a relatively low threshold voltage range and a plurality of later data states associated with a relatively high threshold voltage range.

10. The memory device according to claim 9, wherein the circuit is configured not to lock out the set of the plurality of NAND strings during the programming of the plurality of late data states.

11. The memory device according to claim 9, wherein the programmed plurality of data states include seven programmed data states, and the plurality of late data states include three of the seven programmed data states.

12. The memory device according to claim 8, wherein the set of NAND strings comprises the NAND strings coupled to the memory cell for all but one of the programmed data states for which programming has been completed.

13. The memory device according to claim 8, further comprising a source line, wherein during detection, the circuit sets the source line to approximately 0 volts (0V).

14. The memory device according to claim 8, wherein the circuit applies a verification voltage to the selected word line during at least one of the verification operations in the program loop.

15. A memory block containing multiple memory cells arranged in multiple word lines and multiple NAND strings, A plurality of program loops including a programming pulse and a verification operation, comprising: a programming means for programming the memory cell of a selected word line among the plurality of word lines into a plurality of data states during at least one of the verification operations, wherein the programming means A first set of the plurality of NAND strings, wherein the NAND strings of the first set do not lock out the first set of the plurality of NAND strings, which includes at least some of the memory cells of the selected word lines that have completed programming, A device configured to conduct electricity through a first set of NAND strings and through a second set of NAND strings including the memory cells of the programmed selected word lines.

16. The apparatus according to claim 15, wherein the programmed plurality of data states include a plurality of earlier data states associated with a relatively low threshold voltage range and a plurality of later data states associated with a relatively high threshold voltage range.

17. The apparatus according to claim 16, wherein the programming means is configured not to lock out the set of the plurality of NAND strings during the programming of the plurality of late data states.

18. The apparatus according to claim 16, wherein the programmed plurality of data states include seven programmed data states, and the plurality of late data states include three of the seven programmed data states.

19. The apparatus according to claim 15, wherein the first set of NAND strings comprises the NAND strings coupled to the memory cells of all but one of the programmed data states for which programming has been completed.

20. The apparatus according to claim 15, further comprising a source line, wherein during detection, the programming means sets the source line to approximately 0 volts (0V).

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