Glass through-vias with multilayer organic / inorganic liners for integrated circuit device packages

Abstract

The present invention provides an apparatus, system, and method for preventing mechanical failures caused by high stress on conductive features of glass through-vias from a glass substrate. [Solution] An IC die package comprising glass 210 in which conductive features such as glass through vias are embedded within the glass, wherein the embedded features include metallization separated from the glass by an intervening multilayer liner 424 comprising both an organic material layer 427 and an inorganic material layer 425. In exemplary embodiments, the organic material has a low Young's modulus to accommodate internal stress between the glass and the metallization. The inorganic material layer of the liner is a metal nitride or a nitride such as silicon nitride and may be in direct contact with the glass. The multilayer material stack may further include another inorganic material layer that is in contact with the metallization and seals the organic material layer.

Description

[Background technology]

[0001] In electronics manufacturing, IC packaging is a stage in semiconductor device manufacturing where an IC, monolithically manufactured on a chip (or die), is assembled into a "package," such as a package substrate or printed circuit board, which protects the IC chip from physical damage and enables it to communicate with other packaged IC chips and / or scaled host components. Multiple chips can be assembled simultaneously, for example, into a multi-die package (MCP).

[0002] When an IC package undergoes multiple processing steps involving temperature and pressure loading, different materials within the package behave differently from each other, potentially leading to a deformation known as "package warp." For example, relatively rigid package substrate cores made of bulk glass have been sought as a low-warp alternative to organic resin-based cores. However, glass substrates have significantly lower CTEs than conventional organic copper-clad core- or coreless substrates for IC die package architectures. When conductive features such as through-glass vias (TGVs) are formed within a glass substrate, the glass can be subjected to high stresses associated with the embedded conductive features. These high stresses can potentially lead to mechanical failure and reduce the yield of IC device packages. [Brief explanation of the drawing]

[0003] The subject matter described herein is presented as an example and is not intended to be limited by the accompanying drawings. For the sake of brevity and clarity of the illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, where appropriate, reference labels are repeated between drawings to indicate corresponding or similar elements. The drawings are as follows:

[0004] [Figure 1] This is a flowchart of a method for forming an IC device package structure, which includes an IC die coupled to a glass preform containing glass through-vias (TGVs) lined with a multilayer stack comprising at least an inorganic material layer and an organic material layer, according to several embodiments.

[0005] [Figure 2] This is a cross-sectional view of an IC device package structure that, according to several embodiments, unfolds to include a TGV opening when one or more operations in the method shown in Figure 1 are performed. [Figure 3] This is a cross-sectional view of an IC device package structure that, according to several embodiments, unfolds to include a TGV opening when one or more operations in the method shown in Figure 1 are performed.

[0006] [Figure 4A] This is a cross-sectional view of a workpiece including an IC device package structure that unfolds to include a multilayer material stack lining the TGV opening when one or more operations in the method shown in Figure 1 are performed, according to several embodiments. [Figure 4B] This is a cross-sectional view of a workpiece including an IC device package structure that unfolds to include a multilayer material stack lining the TGV opening when one or more operations in the method shown in Figure 1 are performed, according to several embodiments. [Figure 4C] This is a cross-sectional view of a workpiece including an IC device package structure that unfolds to include a multilayer material stack lining the TGV opening when one or more operations in the method shown in Figure 1 are performed, according to several embodiments.

[0007] [Figure 5A] This is a cross-sectional view of an IC device package structure that, according to several embodiments, unfolds to include a metallized TGV when one or more operations in the method shown in Figure 1 are performed. [Figure 5B] This is a cross-sectional view of an IC device package structure that, according to several embodiments, unfolds to include a metallized TGV when one or more operations in the method shown in Figure 1 are performed.

[0008] [Figure 6] This is a cross-sectional view of an IC device package structure that, according to several embodiments, unfolds to include multiple IC dies interconnected by an electrical routing structure built on the surface of a glass core including a TGV when one or more operations in the method shown in Figure 1 are performed. [Figure 7] This is a cross-sectional view of an IC device package structure that, according to several embodiments, unfolds to include multiple IC dies interconnected by an electrical routing structure built on the surface of a glass core including a TGV when one or more operations in the method shown in Figure 1 are performed. [Figure 8] This is a cross-sectional view of an IC device package structure that, according to several embodiments, unfolds to include multiple IC dies interconnected by an electrical routing structure built on the surface of a glass core including a TGV when one or more operations in the method shown in Figure 1 are performed.

[0009] [Figure 9] This figure shows a system including an IC device package structure, as shown in Figure 8, which is attached to a host component using solder features, according to several embodiments.

[0010] [Figure 10] This figure shows a mobile computing platform and a data server machine employing a device package structure including a TGV having a multilayer liner, according to several embodiments.

[0011] [Figure 11] This is a functional block diagram of an electronic computing device according to several embodiments. [Modes for carrying out the invention]

[0012] Embodiments are described with reference to the accompanying drawings. Specific configurations and arrangements are shown and discussed in detail, but this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of this specification. Those skilled in the art will also see that the techniques and / or arrangements described herein can be employed in a variety of other systems and applications not described in detail herein.

[0013] In the following detailed description, references are made to the accompanying drawings, which form part of this specification and illustrate exemplary embodiments. Furthermore, it should be understood that other embodiments may be utilized and structural and / or logical modifications may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references, such as top, bottom, apex, bottom, etc., may be used simply to facilitate the description of features in the drawings. Accordingly, the following detailed description should not be interpreted restrictively, and the scope of the claimed subject matter is defined solely by the attached claims and their equivalents.

[0014] Numerous details are provided in the following description. However, it will be apparent to those skilled in the art that embodiments may be carried out without these specific details. In some cases, well-known methods and devices are shown in block diagram form rather than in detail, in order to avoid obscuring the embodiments. Throughout this specification, references to “one embodiment,” “one embodiment,” or “several embodiments” mean that certain features, structures, functions, or characteristics described in relation to that embodiment are included in at least one embodiment. Therefore, occurrences of the phrases “in one embodiment,” “in one embodiment,” or “in several embodiments” in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment, provided that the certain features, structures, functions, or characteristics associated with these two embodiments are not mutually exclusive.

[0015] As used herein and in the appended claims, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context explicitly indicates otherwise. As used herein, the term "and / or" will also be understood to refer to and encompass any and all possible combinations of one or more of the associated enumerated items.

[0016] The terms “joined” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. These terms are not intended to be synonymous with each other. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with one another. “Joined” may be used to indicate that two or more elements are in direct or indirect (with other intervening elements between them) physical or electrical contact with one another, and / or that two or more elements cooperate or interact with one another (e.g., as causally related).

[0017] As used herein, the terms “over,” “under,” “between,” and “on” refer to the relative position of one component or material to another component or material where such a physical relationship is noteworthy. For example, in the context of materials, one material or layer covering or beneath another material may be in direct contact with it, or may have one or more intervening materials or layers. Furthermore, one material between two materials or layers may be in direct contact with both materials / layers, or may have one or more intervening materials / layers. In contrast, a first material or layer “on” a second material or layer is in direct contact with that second material / layer. Similar distinctions are made in the context of component assemblies.

[0018] Throughout this description and as used in the claims, a list of items connected by the terms “at least one of” or “one or more of” may mean any combination of the terms being enumerated. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0019] Unless otherwise specified in the specific context of use, the term “mostly” means more than 50% or more than half. For example, a composition that is mostly the first component means that more than half of the composition is the first component (e.g., <50 at.%). The term “primarily” means the most abundant or largest portion. For example, a composition that is primarily the first component means that the composition contains more of the first component than any other component. A composition that is primarily the first and second component means that the composition contains more of both the first and second components than any other component. The term “substantially” means that only accidental variation exists. For example, a composition that is substantially the first component means that the composition may further contain <1% of any other component. A composition that is substantially the first and second component means that the composition may further contain <1% of any other component that replaces either the first or second component.

[0020] Integrated circuit (IC) device package structures including a glass core having embedded metallization such as through-glass vias (TGVs) are described herein. An electrical routing structure including redistribution layer (RDL) metallization may be constructed on at least one surface of the glass and electrically coupled to the embedded metallization within the glass. An IC die may be further assembled to the routing structure. In exemplary embodiments, the embedded metallization within the glass is lined with a multilayer material stack including both inorganic and organic material layers. The multilayer liner may not be present in the metal features of the routing structure.

[0021] The lower layer of the multilayer liner may be an inorganic material and, in exemplary embodiments where the inorganic material is in direct contact with the glass, may provide strong adhesion to the bulk glass surface. The upper layer of the multilayer stack may be an organic material and may have a low modulus of elasticity (e.g., Young's) that can accommodate (i.e., buffer) the internal stresses that accumulate between the glass and the via metallization deposited on the TGV (e.g., covering the intervening multilayer liner). As described below, the multilayer TGV liner may further include a capping layer that seals the underlying organic material layer. The sealant may, for example, limit outgassing of the organic material and / or physically protect the organic material, which may be significantly softer than the sealant. The sealant may promote adhesion between the liner and the TGV metallization.

[0022] A variety of manufacturing methods may be employed to form an IC device package structure having one or more of the features described herein. Figure 1 shows a flow chart of Method 101 for forming an IC device package structure comprising an IC die bonded to a bulk glass layer including glass through vias (TGVs) lined with a multilayer material stack, according to one of several embodiments. Method 101 begins at input 110, where a workpiece containing glass of a certain thickness is received. The workpiece may be prepared upstream of Method 101 and may be in a large panel format, wafer format, or similar. In addition to glass, the workpiece received at input 110 may contain one or more materials on which electrical routing structures can be formed.

[0023] Figure 2 is a cross-sectional view of an exemplary package substrate core 201 including glass 210. The IC device package structure may be advantageously manufactured on glass 210 because the control of flatness and / or thickness for the glass preform may be better than that of a starting substrate based on organic material (e.g., epoxy), and the cost can be significantly lower than that of single-crystal material (e.g., silicon). Glass 210 may be harder than conventional core materials such as copper-clad laminate (CCL). Glass 210 is a solid bulk material layer that may be pre-formed into any shape in plan view (e.g., xy plane) suitable for a packaging workpiece, such as a rectangle. Glass 210 has a thickness T0 that may vary with mounting, for example, to limit warping and, at the same time, to maintain sufficient thinness to allow the formation of through-vias at the smallest possible pitch due to the surface flatness of glass 210. In exemplary embodiments, the thickness T0 is advantageously 50 μm to 2000 μm. Organic adhesives and / or other organic materials may not be present in the glass 210. The glass 210 is, advantageously, a bulk material of substantially homogeneous composition, in contrast to composite materials that may simply contain glass fillers (particles) and / or glass fibers in a binder (e.g., epoxy). While the glass 210 is substantially amorphous in some embodiments, it may also have other forms or microstructures, such as polycrystalline (e.g., nanocrystalline). Thus, the glass 210 may be a rectangular prism volume, distinct from, for example, a “prepreg” containing glass fibers having a diameter in the range of 5 μm to 20 μm embedded in a resin organic material, typically such as epoxy.

[0024] Glass 210 may include a material containing silicon and oxygen. Glass 210 preferably consists mostly of silicon and oxygen. In some embodiments, Glass 210 contains at least 23 percent silicon and at least 26 percent oxygen by weight (i.e., wt.%). Glass 210 may further include one or more additives, such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In Glass 210, the weight percentage of silicon is at least 0.5% (e.g., between about 0.5% and 50%) and may be between about 1% and 48%. For example, if Glass 210 is specifically fused silica, the weight percentage of silicon may be about 47%. In some embodiments where Glass 210 contains at least 23 wt.% of Si, Glass 210 contains at least 26 wt.% of O. The additives in Glass 210 may form suboxides (A2O), monoxides (AO), dioxides (AO2), trioxides (ABO3), and mixtures thereof. For example, Glass 210 is AlO x (e.g., Al2O3), BO x (e.g., B2O3), MgO x (e.g., MgO), CaO x (e.g., CaO), SrO x (e.g., SrO), BaO x (e.g., BaO), SnO x (e.g., SnO2), NaO x (e.g., Na2O), KO x (e.g., K2O), PO x (e.g., P2O3), ZrO x (e.g., ZrO2), LiO x (e.g., Li2O), TiO x (e.g., TiO2), or ZnO xIt may contain (for example, ZnO2). In some specific examples, glass 210 further contains at least 5 wt.% Al. Therefore, depending on the chemical composition, glass 210 may be called, for example, silica, fused silica, aluminosilicate, soda-lime glass, soda-lime silica, boroflote glass, lead borate glass, borosilicate, or aluminoborosilicate.

[0025] Although not shown, one or more material layers may cladd either or both of the front glass surface 241 or the back glass surface 242, thereby making the glass 210 a bulk or core layer of the multilayer substrate. An example cladding material is silicon nitride (SiN x ) or silicon oxynitride (SiO x N y This includes inorganic materials such as ). In other embodiments, a silicon layer (polycrystalline or monocrystalline) may cladd one or both sides of the glass 210. An organic material layer, such as a polymer dielectric material, may also cladd one or more sides of the glass 210. Thus, the glass 210 is advantageously substantially free of organic material (e.g., without adhesive), but the IC die package workpiece may further contain organic material within the substrate containing the glass 210.

[0026] Returning to Figure 1, Method 101 continues in block 120, where features (e.g., recesses and / or through holes) are formed in the glass. The features may be manufactured by any process known to be suitable for bulk glass. In some embodiments, block 120 includes laser ablation, a glass etching process (laser-assisted, or otherwise), or any other technique known to be suitable for forming features (e.g., holes) through the thickness of the glass received in input 110 at a desired diameter and feature pitch.

[0027] Figure 3 shows an exemplary embodiment illustrating a process for forming a substantially symmetrical bifacial hole, resulting in a through-hole 320 having a tapered (e.g., x-dimension) transverse width W that is substantially symmetrical with respect to the longitudinal z-axis (defined by a dashed line), but is maximized at each of the glass surfaces 241 and 242. The through-hole 320 has a minimum transverse width W that is half the thickness T0 or proximal to the center plane of the glass 210. The maximum width W may vary depending on the implementation. On the other hand, in some examples, the maximum width W is 100 μm or less, and favorably less than 50 μm. Thus, the aspect ratio (T0: maximum width W) of the through-hole 320 may vary in an exemplary aspect ratio range of 10:1 to 20:1.

[0028] In some embodiments where the glass 210 has a thickness T0 of at least 500 μm, the through-holes 320 have a minimum lateral pitch P of 200 μm or less, preferably 100 μm or less. The symmetrical taper shown in Figure 3 illustrates a bilateral through-hole formation process, but a single-sided asymmetric through-hole embodiment is also possible. Although a through-hole is shown in Figure 3, a blind hole or recess that does not completely penetrate the thickness T0 may be manufactured on one or more of the glass surfaces 241 or 242. The through-hole 320 (or blind hole) may have any shape in the plan view (xy) plane, such as substantially circular, rectangular, or any other arbitrary polygon. The plan view shape of the through-hole or blind hole may vary over the thickness T0.

[0029] Returning to Figure 1, Method 101 is followed by the implementation of a multi-process module 124, where a multilayer liner is formed on the sidewalls of a feature pre-formed in the bulk glass. The multi-process module 124 includes at least one inorganic material deposit 125 and at least one organic material deposit 127. Either deposit 125 or 127 may precede the other, and in exemplary embodiments, the inorganic material deposit 125 precedes the organic material deposit 127. As further shown in Figure 1, the multi-process module 124 advantageously further includes a encapsulant deposit 129, which is advantageously performed following the organic material deposit 127. Through the implementation of the multi-process module 124, stresses arising from a linear thermal expansion coefficient (CTE) mismatch between, for example, the bulk glass and the conductive material that will subsequently be deposited in the openings formed in the glass can be mitigated. The magnitude of the accumulated stress can vary depending on the implementation, for example, in relation to the thermal load on the feature geometry and package structure, and therefore the implementation of the multi-process module 124 can also vary. For example, the inorganic and / or organic material composition may vary, and / or the thickness of the inorganic material layer and / or organic material layer may vary, and / or the deposition technique may vary, depending on the magnitude of the stress accumulated in a particular IC package structure.

[0030] In particular, the multi-process module 124 may be implemented as a separate, discontinuous (ex-situ) process operation, or as multiple phases of an integrated (in-situ) process operation. In an advantageous embodiment, the multi-process module 124 is a completely "dry" process that avoids any "wet" deposition techniques. Dry deposition techniques can easily form thin films of material on the sidewalls of features with high aspect ratios (e.g., above 10:1), while wet deposition techniques may only be suitable for lower aspect ratios (e.g., 5:1 to 7:1).

[0031] The inorganic material deposition 127 includes the deposition of at least one layer of inorganic material. In exemplary embodiments, the inorganic material deposition 127 includes a deposition process that provides high thickness conformability, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In an example further shown in Figure 4A, the inorganic material layer 425 is deposited to cover the glass surfaces 241, 242 and the sidewalls 321 of the opening 320. Figure 4A shows the maximum thickness T on surfaces 241, 242. max The minimum thickness T on the side wall 321 proximal to the glass centerline at half the thickness T0. min It exhibits substantially conformal deposition, which is within 10%. In an alternative embodiment in which the inorganic material layer 425 is deposited using a deposition process that is less conformal than CVD or ALD, such as a physical vapor deposition (PVD) process, the inorganic material layer 425 has a thickness T proximal to the surfaces 241, 242. max Thickness T proximal to the glass centerline, at least 20% lower than min It may have the following: Thickness T of the inorganic material layer 425. max / T min This can vary depending on the implementation, but in an exemplary embodiment, the minimum thickness T min The thickness is at least 10 nm, and preferably less than 1 μm, to limit, for example, the effect of the multilayer liner on the electrical resistance of the through vias. In the shown embodiment, which is highly conformal, the inorganic material layer 425 is T max Sufficient non-zero T (e.g., 20nm to 200nm) min To ensure this, it may be thinner (e.g., T) than in the case of non-conformal embodiments which may be thicker (e.g., about 1 μm). min and T max Both are between 20nm and 200nm.

[0032] As shown in Figure 4A, the inorganic material layer 425 is in direct contact with the glass 210, and in such embodiments, the inorganic material layer 425 advantageously contains only trace levels of carbon, if present, less than 1.0 wt%. In further embodiments, the inorganic material layer 425 contains nitrogen. Functional groups containing nitrogen (e.g., nitrides) can have particularly good adhesion to the glass surface, reducing the risk of the liner delaminating from the glass 210. Nitride functional groups can also promote good adhesion to subsequently deposited organic material layers. In some embodiments, the inorganic material layer 425 further contains silicon, advantageously silicon nitride (SiN3N4), one example being stoichiometric composition Si3N4. x ) may be. In some embodiments, the inorganic material layer 425 contains oxygen in combination with both silicon and nitrogen (for example, SiO x N y ), or in the absence of nitrogen, one example being SiO2 in stoichiometric composition (e.g., SiO2 x ), including. Optionally, one or more metals may be present in the inorganic material layer 425. Exemplary metals include Ti (e.g., TiN). x , TiO x , TiO x N y ,TiSi x ,TiSi x O y N z ), Ta (for example, TaN x TaO x TaO x N y , TaSi x , TaSi x O y N z ), or W (for example, WN x WO x WO x N y , WSi x , WSi x O y N z ) may include one or more of the following. Other metals (e.g., com Al, Sn, Sc, In, or Au), and their nitrides, oxides, silicides, or silicates are also possible.

[0033] Returning to Figure 1, Method 101 proceeds to organic material deposition 127. Organic material deposition 127 may include any deposition technique known to be suitable for the material composition. In some embodiments, one or more of spray coating, dip coating, or inkjet printing may be used to deposit one or more layers of organic material, for example, as a liquid, gel, or sol-gel. In other embodiments, self-assembly techniques (e.g., driven by surface charge) may be employed to form the organic material layer. Following wet coating, the organic material may be cured. Note that it may be difficult to wet deposit the organic material in a manner that ensures the sidewalls of high aspect ratio features are completely covered, and in some advantageous embodiments, organic material deposition 127 may use a dry process, which may be a vapor deposition technique. In one example, an initiated chemical vapor deposition (iCVD) process deposits a polymer material on the sidewalls of an opening, for example, in direct contact with a pre-deposited inorganic material. Generally, in iCVD techniques, monomers are deposited on the surface of a workpiece, and non-thermally activated initiator radicals activate the monomers, initiating a polymerization reaction on the surface. Such techniques offer the opportunity to graft polymers directly onto pre-deposited inorganic materials. It is also possible to leave dangling bonds on the top surface of the organic material, providing bonding sites for subsequent material layers that can improve adhesion to the organic material.

[0034] Figure 4B shows an example where the organic material layer 427 is deposited on the inorganic material layer 425. As shown in Figure 4B, the organic material layer 427 is in direct contact with the inorganic material layer 425. The organic material layer 427 also has a maximum thickness T on surfaces 241 and 242. max , and minimum thickness T on the side wall 321 min It may have a thickness T. max and T minDepending on the variation between these, the inorganic material layer 425 can be described as more or less conformal. In some embodiments, the organic material layer 427 is less conformal than the inorganic material layer 425 (i.e., T max This is a larger amount of T for the organic material layer 427. min (larger than ). In some cases, the inorganic material layer 425 has a thickness variation of 20% or less, while the organic material layer 427 has a thickness variation of more than 25%.

[0035] Thickness T of organic material layer 427 max / T min This can vary depending on the implementation, but in an exemplary embodiment, the minimum thickness T min This is greater than that of the inorganic material layer 425. As further shown in the enlarged cross-sectional view of the sidewall 321, the inorganic material layer 425 has a thickness T1 along a direction perpendicular to the sidewall surface of the glass 210. Along this same direction, the organic material layer 427 has a thickness T2 that is several hundred nanometers greater than the thickness T1. In some advantageous embodiments, the thickness T2 is 0.5 μm to 5 μm. The greater thickness of the organic material layer 427 is advantageous, for example, to accommodate stress due to strain over a thickness T2.

[0036] In exemplary embodiments, the organic material layer 427 has a lower modulus of elasticity than the inorganic material layer 425. While in some cases this ratio can be directly measured for thin films, the reference to modulus of elasticity herein is also applicable to bulk materials having substantially the same chemical composition and microstructure as thin films. Therefore, even if the modulus of elasticity of the inorganic material layer 425 and / or the organic material layer 427 cannot be directly measured, materials of substantially the same composition and microstructure may be formed to a somewhat larger thickness to which ratio measurement is applicable. Unless otherwise evidence is found, it is presumed that the ratio associated with such a bulk thickness will closely match that of a thin film of substantially the same composition and microstructure.

[0037] In exemplary embodiments, the organic material layer 427 is a material having an elastic modulus of less than 110 GPa. The inventors have found that materials with elastic moduli significantly above this threshold (e.g., 120 GPa) may not adequately accommodate internal stress, and that less compliant materials may be prone to delamination when deposited in pores extending through low CTE materials (e.g., glass). Therefore, some embodiments of the organic material layer 427 may have an elastic modulus of less than 100 GPa, and more preferably less than 90 GPa.

[0038] In further embodiments, the organic material layer 427 is a material having a relatively low (linear) coefficient of thermal expansion (e.g., <20 ppm / K) compatible with the CTE of silica glass (e.g., 4 ppm / K to 9 ppm / K). In some exemplary embodiments, the organic material layer 427 may have a CTE in the range of 3 ppm / K to 20 ppm / K, more specifically in the range of 5 ppm / K to 12 ppm / K. In some cases, the CTE can be measured directly for the organic material layer 427, but the reference for the CTE is also applicable to bulk materials having substantially the same chemical composition and microstructure as the material layer 427. Therefore, even if the CTE of the organic material layer 427 is not directly measurable, a material with substantially the same composition and microstructure may be formed to a larger thickness to which the CTE measurement is applicable. Unless otherwise proven, it is presumed that the CTE associated with such a bulk thickness will closely match that of a thin film with substantially the same composition and microstructure.

[0039] The composition of the organic material layer 427 may vary depending on the deposition technique and may be determined, for example, by one or more of FTIR, Raman spectroscopy, AFM, AFM-IR, TEM, XPS, or X-EDS. For example, films deposited by iCVD may be identified by their initiator content, since the polymer chains are initiated and terminated / capped by initiator radicals. Therefore, the monomer / initiator ratio determined by XPS or FTIR may be useful. Generally, the organic material layer 427 may contain at least one of trifluoromethyl groups, carbonyl groups, sulfonyl groups, or ester groups, all of which may be detected, for example, by FTIR or XPS.

[0040] In some embodiments, the organic material layer 427 includes polytetrafluoroethylene (PTFE), poly(glycidyl methacrylate) (PGMA), poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), or poly(1H,1H,2H,2H-perfluorodecyl acrylate (pPFDA)). Such materials may be deposited by iCVD using an initiator such as tert-butyl peroxide (TBPO) in the case of PGMA or perfluorobutanesulfonyl fluoride (PBSF) in the case of PTFE.

[0041] In some other embodiments, the organic material layer 427 includes a cationic polymer electrolyte such as a π-conjugated oligomer or polymer. In some embodiments, the organic material layer 427 is one or more of poly(diallyldimethylammonium chloride) or polyethyleneimine (PEI). The organic material layer 427 may also include, or alternatively, anionic polymer electrolytes such as polystyrene sulfonate or sulfonated polysulfone.

[0042] Returning to Figure 1, method 101 is followed by encapsulant deposition 129, which may complete the multi-process module 124. The encapsulant deposition 129 may coat a pre-deposited organic material, for example, reducing outgassing of the polymer material and / or improving adhesion with subsequently deposited metals. In some exemplary embodiments, the encapsulant deposition 129 includes an atomic layer deposition (ALD) or CVD process. In the example shown in Figure 4C, the encapsulant material layer 429 is deposited on the organic material layer 427. In this example, the encapsulant material layer 429 is in direct contact with the organic material layer 427. The encapsulant material layer 429 has a maximum thickness T on surfaces 241, 242. max , and minimum thickness T on the side wall 321 min The conformality of the sealing material layer 429 is such that the thickness T max and T min It is a function of variation between . In some embodiments, the sealing material layer 429 is less conformal than the organic material layer 427 (i.e., T max T is obtained in a larger amount for the organic material layer 427 than for the sealing material layer 429. min (larger than). In some examples, the sealing material layer 429 has a thickness T max and T min There is a thickness variation of less than 10% between them.

[0043] The thickness of the sealing material layer 429 may vary depending on the mounting configuration, but in an exemplary embodiment, the minimum thickness T min The thickness may be less than that of the organic material layer 427 and less than that of the inorganic material layer 425. The sealing material layer has a thickness T3, as further shown in the enlarged cross-sectional view of the side wall 321, where the inorganic material layer 425 has a thickness T1 and the organic material layer 427 has a thickness T2. In some advantageous embodiments, the thickness T3 is 1 nm to 20 nm. The multilayer liner 424 may then include an inorganic material layer 425 having a thickness T1 of 20 nm to 500 nm, an organic material layer 427 having a thickness T2 of 0.5 μm to 5 μm, and a sealing material layer 429 having a thickness T3 of 1 nm to 20 nm.

[0044] In an exemplary embodiment, the encapsulant material layer 429 has a higher modulus of elasticity than the organic material layer 427. In an exemplary embodiment, the encapsulant material layer 429 is a material having a modulus of elasticity exceeding 120 GPa. This higher modulus of elasticity can physically protect the softer organic material layer 127 below during subsequent processing.

[0045] The composition of the encapsulant material layer 429 can vary depending on the deposition technique and may also be determined through one or more of FTIR, Raman spectroscopy, AFM, AFM-IR, TEM, XPS, or X-EDS. In an exemplary embodiment, the encapsulant material layer 429 is an inorganic material (e.g., containing trace levels of carbon below 1.0 wt%). In some embodiments, the encapsulant material layer 429 contains nitrogen. Functional groups containing nitrogen (e.g., nitrides) can have particularly good adhesion to organic materials, reducing the risk of the encapsulant material layer 429 peeling from the organic material layer 427. In some embodiments, the encapsulant material layer 429 contains metal, in combination with nitrogen or in the absence of nitrogen. Exemplary metals and their nitrides include Ti (TiN x ), Ta (TaN x ), or W (WN x ). In some embodiments, the encapsulant material layer 429 also contains oxygen, in combination with one or more of metal and nitrogen or in the absence of one or more of metal and nitrogen (e.g., TiO x , TiO x N y , TaO x , TaO x N y , WO x , WO x N y ). The encapsulant material layer 429 also contains silicon, for example, in combination with at least one of oxygen, nitrogen, or metal (e.g., TiSi x , TiSi x O y N z , TaSi x , TaSi x O y N z , WSi x , WSix O y N z ) may be included. Other metals (e.g., Al, Sn, Sc, In, or Au), and their nitrides, oxides, silicides, or silicates are also possible.

[0046] After forming the multilayer liner, method 101 is followed by metal deposition 130, where at least partially conductive metallization fills the lined openings or recesses in the glass. In an exemplary embodiment, metal deposition 130 includes deposition of a seed metal and subsequent deposition of a fill metal. In some embodiments, the seed metal layer is deposited directly on the encapsulant material of the underlying multilayer liner. Metals present in the underlying encapsulant material layer can ensure good adhesion of the seed metal. In some embodiments, the seed metal is deposited using an ALD process, which is advantageous when the aspect ratio of the openings in the glass exceeds 10:1 after deposition of the liner. Alternatively, the seed metal may be deposited using a PVD process instead if greater seed layer non-conformality is acceptable. Following the seed metal deposition, one or more fill metals (e.g., mostly copper) may be deposited (e.g., electroplated) on the surface of the seed metal layer. The seed metal and / or fill metal may each have a significantly higher elastic modulus and / or CTE than at least one layer of the underlying liner. For example, fill metallization that is mostly Cu may be expected to have an elastic modulus of approximately 130 GPa and a CTE of 16 ppm / K to 17 ppm / K.

[0047] FIG. 5A shows an example where the seed metal layer 530A is deposited directly on the encapsulant material layer 429. The seed metal layer 530A may be of any chemical composition known to be suitable as a seed layer for an electrodeposition process, e.g., having a suitable conductivity. In embodiments where the encapsulant material layer 429 contains metal, the seed metal layer 530A contains a different metal from the encapsulant material layer 429. The seed metal layer 530A may include, for example, other than Ti, Ta, or W, and in some embodiments, the seed metal layer 530A is mostly Cu.

[0048] As shown in the enlarged view of Figure 5A, the seed metal layer 530A has a thickness T4 along the direction of thickness T1 to T3. The thickness T4 may be, for example, within the same range as thickness T3 (e.g., 1 nm to 20 nm), and in some embodiments, may be at least 5 nm along the sidewall 321 proximal to the centerline of the glass thickness T0. The conformality of the seed metal material layer 530A may vary depending on the deposition technique, with the seed metal layer thickness T4 being lower along the sidewall 321v proximal to the centerline of the glass thickness T0 in the case of less conformal deposition processes such as PVD. Figure 5B further illustrates the plating of the filler metal 530B onto the seed metal layer 530A. As shown in the enlarged view, even when the seed metal layer 530A and the filler metal 530B have substantially the same composition (e.g., both are mostly Cu), the interface may be evident in the TEM image, revealing that the seed metal layer 530A has a different microstructure from the filler metal 530B. For example, the seed metal layer 530A may have a smaller particle size (e.g., 5 nm to 20 nm particle diameter) than the filler metal 530B (e.g., >25 nm particle diameter).

[0049] Returning to Figure 1, Method 101 follows TGV completion 135, where, for example, one or more layers of filling metallization, seed metallization, and / or liner material are planarized to remove plating overburden from the front and back sides of the glass. In the example shown in Figure 6, the filling metallization 530B and seed metal layer 530A have been removed from surfaces 241, 242, leaving conductive TGV 635. Alternatively, the workpiece shown in Figure 6 may be obtained through a chemical metal etching process, with or without incorporating mechanical wear. In the example shown, the encapsulant material layer 429 and organic material layer 427 have also been removed from surfaces 241, 242, exposing the inorganic material layer 425. In other embodiments, the inorganic material layer 425 may also be removed, exposing the glass 210 on surfaces 241, 242.

[0050] Returning to Figure 1, Method 101 continues in block 140, where an electrical routing structure is constructed on one or more surfaces of the glass prior to its assembly with one or more IC dies. The electrical routing structure may be electrically coupled to the TGV and may include, for example, one or more levels of metallization features embedded in any suitable dielectric material. The electrical routing structure formed in block 140 may interconnect one or more IC dies with each other and / or couple one or more of the IC dies to the TGV. Thus, the metallization feature pitch of the routing structure is advantageously minimized in the case of the highest interconnection density. Before or after the formation of the routing structure, the glass substrate may be fixed to a handle or carrier having any suitable composition and of any suitable thickness, for embodiments herein are not limited thereto.

[0051] In the example shown in Figure 7, the routing structure 780A is constructed over surface 241. Another routing structure 780B may similarly be constructed over surface 242. Routing structure 780B is shown with a dashed line to emphasize that double-sided construction is optional. The routing structure 780A (780B) includes one or more levels of RDL metallization features 782 embedded within one or more layers of the dielectric material 781. The RDL metallization features 782 may include one or more metals, one example being that is mostly copper. At least some of the RDL metallization features 782 are preferably for electrically bridging two or more IC dies together, having the finest metallization lines, i.e., spaced feature pitches (e.g., <3 μm lines and spacing) that can be directly patterned in the case of the flatness of the glass 210. The routing structure 780A may include metallization features 782 that interconnect multiple IC dies to a conductive TGV 635. In some examples where the TGV635 includes a multilayer liner 424 according to the embodiments herein, at least the organic material layer 427 is absent in the metallization feature 782. Depending on the embodiment, the dielectric material 781 may be any of, for example, a molded compound, a spin-on material, or a dry film laminate material. The dielectric material 781 may be introduced into the cast in a wet / uncured state and then dried / cured. Alternatively, the dielectric material 781 may be introduced as a semi-cured dry film that is fully cured following its coating over the glass 210. The composition of the dielectric material 781 may vary depending on the implementation. In some advantageous embodiments, the dielectric material 781 is an organic dielectric, e.g., an epoxy resin, phenolic glass, or a resin film, e.g., a GX series film (ABF) commercially available from Ajinomoto Fine-Techno Co., Inc. The dielectric material 781 may contain an epoxy resin (for example, a novolac acrylate such as epoxyphenol novolac (EPN) or epoxy cresol novolac (ECN)).In some specific examples, the dielectric material 781 is a bisphenol A epoxy resin, for example, containing epichlorohydrin. In other examples, the dielectric material 781 includes an aliphatic epoxy resin.

[0052] Returning to Figure 1, method 101 may continue in block 150, where at least one IC die is assembled to the workpiece, more specifically to the electrical routing structure. Each IC die assembled in block 150 may contain any electrical circuit, one example being a logic circuit containing a logic gate. The IC dies assembled in block 150 may also contain any photonic circuit suitable for detecting, emitting, or processing (e.g., filtering, multiplexing, and demultiplexing) optical signals.

[0053] In the example shown in Figure 8, IC dies 891-894 are assembled as the first die of the same-packaging multi-die IC device package structure 801 to interconnect their interfaces within the uppermost metallization level of the routing structure 780A. IC dies 891-894 may be directly bonded to the routing structure 780A. Alternatively, IC dies 891-894 may be electrically coupled through an intervening electrical interconnect (not shown), which may include, for example, solder of any suitable composition. In the example shown, IC dies 891-893 are each flip chips mounted with the integrated circuit within each die located proximal to the front surface 241. IC die 894, on the other hand, includes a through-die via 899, with the integrated circuit located distal to the package substrate surface 241.

[0054] Each of the IC dies 891-894 may be a fully functional ASIC, or it may be a chiplet or tile with more limited functionality that assists the functionality of one or more other IC dies that are part of the same multi-die device. The chiplet or tile may be any of the following, for example, a wireless radio circuit, a microprocessor core, an electronic memory circuit, a floating-point gate array (FPGA), a power management and / or power supply circuit, or it may include a MEMS device. In some examples, one or more of the IC dies 891-894 include one or more banks of active repeater circuits to improve a multi-die interconnect (e.g., a network-on-chip architecture). In other examples, one or more of the IC dies 891-894 include a clock generator circuit or a temperature sensing circuit. In other examples, one or more of the IC dies 891-894, together with the other IC dies 891-894, include logic circuits that implement a multi-chiplet aggregated logic circuit (e.g., a mesh network-on-chip architecture). In some specific examples, at least one of the IC dies 891-894 includes a microprocessor core circuit that includes, for example, one or more shift registers.

[0055] IC dies 891-894 advantageously include field-effect transistors (FETs) having a device pitch of 80 nm or less. The FETs may be of any architecture (e.g., planar, unplanar, single-gate, multi-gate, stacked nanosheet, etc.). In some embodiments, the FET terminals have a feature pitch of less than 30 nm. In addition, or in alternative forms, IC dies 891-894 may include active devices other than FETs. For example, IC dies 891-894 may include electronic memory structures such as magnetic tunnel junctions (MTJs), capacitors, or similar.

[0056] IC dies 891-894 may include one or more IC die metallization levels embedded within an insulator. The IC die metallization features may have any composition with sufficient conductivity, but in exemplary embodiments, the IC die metallization features are predominantly copper (Cu). In other examples, the metallization features may be predominantly non-Cu, but not limited to, predominantly Ru, or predominantly W, etc. The best of the metallization features within IC dies 891-894 may have a feature pitch ranging, for example, from 100 nm to several microns.

[0057] Returning to Figure 1, Method 101 is completed, where the assembled device package structure is further mounted to a suitable host component at Output 160. Figure 9 shows an exemplary system 901, which includes one device package structure 801 mounted to a host component 905 using an interconnect 911, according to several embodiments. In the exemplary embodiment, the interconnect 911 is a solder (e.g., SAC) microbump, but other interconnect features are also possible. In some embodiments, the host component 905 is mostly silicon. The host component 905 may include one or more alternative materials known to be suitable as an interposer or package substrate (e.g., epoxy preform, cored or coreless laminate board, etc.). The host component 905 may include a printed circuit board (PCB). The host component 905 may include one or more metallized redistribution levels (not shown) embedded in a dielectric material. The host component 905 may include one or more IC dies embedded inside.

[0058] The host component 905 may include interconnects 920, indicated by dashed lines. Each interconnect 920 may include any solder (balls, bumps, etc.) suitable for a given host board architecture (e.g., surface mount FR4). Similarly, one or more heat spreaders and / or heat sinks 950 may be further coupled to the device package structure 801, as indicated by dashed lines, which may be advantageous, for example, if the IC dies 891-894 include one or more CPU cores or other circuits of similar power density. Any package dielectric 940, such as a molding material, may surround the sidewalls of the IC dies 891-894. Although not shown, the package dielectric 940 may be back-polished so that the heat spreaders / sinks 950 can make closer contact with the IC dies 891-894.

[0059] Figure 10 shows a data server machine 1006 employing a mobile computing platform 1005 and an IC device package having a TGV including a multilayer liner, as described elsewhere in this specification, for example. The server machine 1006 may be any commercial server including any number of high-performance computing platforms, for example, arranged in a rack and networked together for electronic data processing, as described elsewhere in this specification, for example, including system 901 in an exemplary embodiment. The mobile computing platform 1005 may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1005 may be any of the following: a tablet, a smartphone, a laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), an integrated system 1010, and a battery 1015.

[0060] As further shown in Figure 10, system 901 may be coupled to one or more power management integrated circuits (PMICs) or RF integrated circuits (RFICs) including wideband RF (wireless) transmitters and / or receivers. The PMIC has an input coupled to battery 1015 and an output that provides current to other functional modules, as it can perform battery power regulation, DC-to-DC conversion, etc. As further shown, in exemplary embodiments, the RFIC has outputs coupled to an antenna (not shown) to implement any of several wireless standards or protocols, including, but not limited to, Wi-Fi® (IEEE 802.11 family), WiMAX® (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, and their derivatives, as well as any other wireless protocols designated as 3G, 4G, and later.

[0061] Figure 11 is a block diagram of a cryogenic computing device 1100 according to several embodiments. For example, one or more components of the computing device 1100 may include any of the devices or structures discussed elsewhere in this specification. Although several components are shown in Figure 11 as being included in the computing device 1100, any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the computing device 1100 may be mounted on one or more printed circuit boards (e.g., a motherboard). In some embodiments, various of these components may be manufactured on a single system-on-a-chip (SoC) die. In addition, in various embodiments, the computing device 1100 may include interface circuits for coupling with one or more components, rather than including one or more of the components shown in Figure 11. For example, the computing device 1100 may not include the display device 1103, but rather may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1103 can be coupled.

[0062] The computing device 1100 may include processing devices 1101 (e.g., one or more processing devices). As used herein, the terms processing device or processor refer to a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1101 may include memory 1121, communication device 1122, refrigeration / active cooling device 1123, battery / power regulation device 1124, logic 1125, interconnect 1126, thermal regulation device 1127, and hardware security device 1128.

[0063] The processing device 1101 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices.

[0064] The processing device 1101 may include a memory 1102, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory: DRAM), non-volatile memory (e.g., read-only memory: ROM), flash memory, solid-state memory, and / or a hard drive. In some embodiments, a memory 1121 includes a memory that shares a die with the processing device 1101. This memory may be used as a cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-M RAM).

[0065] The computing device 1100 may include a thermal control / refrigeration device 1106. The thermal control / refrigeration device 1106 may maintain the processing device 1101 (and / or other components of the computing device 1100) at a predetermined low temperature during operation. This predetermined low temperature may be any temperature discussed elsewhere in this specification.

[0066] In some embodiments, the computing device 1100 may include a communication chip 1107 (e.g., one or more communication chips). For example, the communication chip 1107 may be configured to manage wireless communication for data transfer to and from the computing device 1100. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium.

[0067] The communication chip 1107 may implement any wireless standard or protocol, including, but is not limited to, the Institute for Electrical and Electronic Engineers (IEEE) standards, including the Long-Term Evolution (LTE) Project, along with Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), and any modifications, updates, and / or revisions (e.g., the Advanced LTE Project, the Ultramobile Broadband (UMB) Project (also known as "3GPP®2")), etc.). The communication chip 1107 may operate in accordance with the Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1107 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).The communication chip 1107 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and later. The computing device 1100 may include an antenna 1113 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0068] The computing device 1100 may include a battery / power circuit 1108. The battery / power circuit 1108 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling the components of the computing device 1100 to an energy source separate from the computing device 1100 (e.g., AC line power).

[0069] The computing device 1100 may include a display device 1103 (or a corresponding interface circuit as discussed above). The display device 1103 may include any visual indicator such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0070] The computing device 1100 may include an audio output device 1104 (or a corresponding interface circuit as discussed above). The audio output device 1104 may include any device that generates an audible indicator, such as a speaker, headset, or earbuds.

[0071] The computing device 1100 may include an audio input device 1110 (or a corresponding interface circuit as discussed above). The audio input device 1110 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output).

[0072] The computing device 1100 may include a global positioning system (GPS) device 1109 (or a corresponding interface circuit as described above). The GPS device 1109 may communicate with a satellite-based system and receive the location of the computing device 1100, as is known in the art.

[0073] The computing device 1100 may include another output device 1105 (or a corresponding interface circuit as discussed above). Examples include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0074] The computing device 1100 may include another input device 1111 (or a corresponding interface circuit as discussed above). Examples include an accelerometer, gyroscope, compass, imaging device, keyboard, cursor control device, e.g., mouse, stylus, touchpad, barcode reader, Quick Response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0075] The computing device 1100 may include a security interface device 1112. The security interface device 1112 may include any device that provides security measures for the computing device 1100, such as intrusion detection, biometric validation, security coding or decryption, access list management, malware detection, or spyware detection.

[0076] The computing device 1100, or a subset of its components, may have any suitable form factor, such as a handheld or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA®), ultramobile personal computer, etc.), desktop computing device, server or other network-connected computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device.

[0077] While certain features described herein are explained with reference to various implementations, this explanation is not intended to be constrained. Therefore, various modifications of the implementations described herein, and other implementations, are obvious to those skilled in the art and are considered to be within the spirit and scope of this disclosure.

[0078] It will be recognized that the disclosure is not limited to the embodiments described and can be implemented with modifications and changes without departing from the scope of the appended claims. For example, the embodiments described above may include specific combinations of features as further provided below.

[0079] In the first example, the apparatus comprises a substrate having glass; a plurality of holes extending through the glass; metallization within the holes; and a liner located within the holes and between the metallization and the glass. The liner has an organic material between two layers of inorganic material.

[0080] In the second example, for any of the first examples, the organic material has an elastic modulus of less than 100 GPa.

[0081] In the third example, for any of the first or second examples, the organic material has a coefficient of thermal expansion (CTE) of less than 25 ppm / K.

[0082] In the fourth example, for any of the third examples, the modulus of elasticity is less than 90 GPa, and the CTE is at least 8 ppm / K.

[0083] In the fifth example, for any of the second to fourth examples, the organic material has a layer thickness greater than the layer thickness of at least one of the inorganic material layers.

[0084] In the sixth example, for any of the first to fifth examples, the organic material includes polytetrafluoroethylene (PTFE), poly(glycidyl methacrylate) (PGMA), poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), or poly(1H,1H,2H,2H-perfluorodecyl acrylate (pPFDA), poly(diallyldimethylammonium chloride) or polyethyleneimine (PEI), polystyrene sulfonate, or sulfonated polysulfone.

[0085] In the seventh example, for any of the first to sixth examples, the organic material is in contact with a first inorganic material layer between the glass and the organic material, and the organic material is in contact with a second inorganic material layer between the metallization and the organic material.

[0086] In the eighth example, with respect to any of the seventh examples, the first inorganic material layer comprises at least one of nitrogen, metal, silicon, or oxygen.

[0087] In the ninth example, the first inorganic material layer is in contact with the glass in any of the seventh to eighth examples.

[0088] In the tenth example, the second inorganic material layer is in contact with the metallization in any of the seventh to ninth examples.

[0089] In the 11th example, for any of the 7th to 10th examples, the second inorganic material layer contains a metal.

[0090] In the twelfth example, for any of the eleventh examples, the second inorganic material layer comprises the metal and nitrogen.

[0091] In the 13th example, for the 11th and 12th examples, the first inorganic material layer and the second inorganic material layer each have a thickness of less than 200 nm.

[0092] In the 14th example, the system comprises a plurality of integrated circuit (IC) dies electrically coupled to a first metallization feature on a first surface of a substrate having glass; a plurality of holes extending through the glass; and metallization within the holes. The metallization electrically couples the first metallization feature to a second metallization feature on a second surface of the glass. The substrate comprises a liner having at least one inorganic material layer in contact with at least one organic material layer, the liner being within the holes and between the metallization and the glass.

[0093] In the 15th example, for any of the 14th examples, the organic material is not present in the first metallization feature.

[0094] In the 16th example, in any of the 14th to 15th examples, the system further comprises an electrical routing structure on the first surface of the glass, the routing structure having the first metallization feature and an organic dielectric material, the plurality of holes extending from the routing structure to a second surface of the glass, and the routing structure electrically coupling the metallization in the holes to at least one of the IC dies.

[0095] In the 17th example, the organic material has an elastic modulus of less than 90 GPa and a coefficient of thermal expansion of at least 8 ppm / K. The organic material has a thickness of at least 500 nm.

[0096] In the 18th example, the method comprises the steps of receiving a workpiece containing glass, forming through-holes in the glass, and depositing a liner on the sidewalls of the holes and covering the glass surface between the through-holes. The step of depositing the liner includes depositing a first inorganic material layer to cover the sidewalls using a first vapor deposition process, depositing an organic material layer to cover the first inorganic material layer using a second vapor deposition process, and depositing a second inorganic material layer to cover the organic material layer using a third vapor deposition process. The method further comprises forming metallization within the holes and covering the liner.

[0097] In the 19th example, for any of the 18th examples, the second deposition process includes initiation chemical deposition (iCVD).

[0098] In the 20th example, for any of the 18th to 19th examples, the first and third deposition processes include atomic layer deposition (ALD).

[0099] However, the embodiments described above are not limited thereto, and in various implementations, the embodiments may include the execution of only a subset of such features, the execution of different orders of such features, the execution of different combinations of such features, and / or the execution of additional features beyond those explicitly enumerated. Accordingly, the scope of this disclosure should be determined by reference to the appended claims, together with the entire scope of equivalents to which such claims are granted. [Other possible items] [Item 1] A substrate containing glass; Multiple holes extending through the glass; Metallization in the aforementioned plurality of pores; and A liner located within the plurality of pores and between the metallization and the glass, wherein the liner has an organic material between two inorganic material layers. A device equipped with the following features. [Item 2] The apparatus according to item 1, wherein the organic material has an elastic modulus of less than 100 GPa. [Item 3] The apparatus according to item 2, wherein the organic material has a coefficient of thermal expansion (CTE) of less than 25 ppm / K. [Item 4] The apparatus according to item 3, wherein the modulus of elasticity is less than 90 GPa and the CTE is at least 8 ppm / K. [Item 5] The apparatus according to item 2, wherein the organic material has a layer thickness greater than the layer thickness of at least one of the inorganic material layers. [Item 6] The apparatus according to item 5, wherein the organic material comprises polytetrafluoroethylene (PTFE), poly(glycidyl methacrylate) (PGMA), poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), or poly(1H,1H,2H,2H-perfluorodecyl acrylate (pPFDA), poly(diallyldimethylammonium chloride) or polyethyleneimine (PEI), polystyrene sulfonate, or sulfonated polysulfone. [Item 7] The apparatus according to item 1, wherein the organic material is in contact with a first inorganic material layer between the glass and the organic material, and the organic material is in contact with a second inorganic material layer between the metallization and the organic material. [Item 8] The apparatus according to item 7, wherein the first inorganic material layer comprises at least one of nitrogen, metal, silicon, or oxygen. [Item 9] The apparatus according to item 8, wherein the first inorganic material layer is in contact with the glass. [Item 10] The apparatus according to item 9, wherein the second inorganic material layer is in contact with the metallization. [Item 11] The apparatus according to item 10, wherein the second inorganic material layer includes a metal. [Item 12] The apparatus according to item 11, wherein the second inorganic material layer includes the metal and nitrogen. [Item 13] The apparatus according to item 11, wherein the first inorganic material layer and the second inorganic material layer each have a thickness of less than 200 nm. [Item 14] Multiple integrated circuit (IC) dies electrically coupled to a first metallization feature on a first surface of a glass substrate; Multiple holes extending through the glass; Metallization within the plurality of holes, the metallization electrically coupling the first metallization feature to a second metallization feature on the second surface of the glass; and A liner having at least one inorganic material layer in contact with at least one organic material layer, the liner being located within the plurality of pores and between the metallization and the glass, A system that includes these features. [Item 15] The system described in item 14, wherein the organic material is not present in the first metallization feature. [Item 16] The system according to item 15, further comprising an electrical routing structure on the first surface of the glass, the routing structure having the first metallization feature and an organic dielectric material, the plurality of holes extending from the routing structure to the second surface of the glass, and the routing structure electrically coupling the metallization in the plurality of holes to at least one of the IC dies. [Item 17] The system according to item 14, wherein the organic material has an elastic modulus of less than 90 GPa and a thermal expansion coefficient of at least 8 ppm / K, and the organic material has a thickness of at least 500 nm. [Item 18] The stage where the workpiece, including the glass, is received; A step of forming a through hole in the glass; A step of depositing a liner on the side walls of the holes and covering the glass surface between the through holes, wherein the step of depositing the liner is: A step of depositing a first inorganic material layer so as to cover the side wall using a first deposition process; A step of depositing an organic material layer so as to cover the first inorganic material layer using a second deposition process; and A third step involves depositing a second inorganic material layer over the organic material layer using a third deposition process. Having; and The step of forming metallization within the hole and covering the liner. A method that includes [a certain feature]. [Item 19] The second deposition process is the method described in item 18, comprising initiation chemical vapor deposition (iCVD). [Item 20] The first and third deposition processes are the method described in item 19, wherein the first and third deposition processes include atomic layer deposition (ALD).

Claims

1. A substrate containing glass; Multiple holes extending through the glass; Metallization in the plurality of holes; and A liner located within the plurality of pores and between the metallization and the glass, wherein the liner has an organic material between two inorganic material layers. A device equipped with the following features.

2. The apparatus according to claim 1, wherein the organic material has an elastic modulus of less than 100 GPa.

3. The apparatus according to claim 1 or 2, wherein the organic material has a coefficient of thermal expansion (CTE) of less than 25 ppm / K.

4. The apparatus according to claim 3, wherein the elastic modulus of the organic material is less than 90 GPa, and the CTE is at least 8 ppm / K.

5. The apparatus according to claim 1 or 2, wherein the organic material has a layer thickness greater than the layer thickness of at least one of the inorganic material layers.

6. The apparatus according to claim 1 or 2, wherein the organic material comprises polytetrafluoroethylene (PTFE), poly(glycidyl methacrylate) (PGMA), poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), or poly(1H,1H,2H,2H-perfluorodecyl acrylate (pPFDA), poly(diallyldimethylammonium chloride) or polyethyleneimine (PEI), polystyrene sulfonate, or sulfonated polysulfone.

7. The apparatus according to claim 1 or 2, wherein the organic material is in contact with a first inorganic material layer between the glass and the organic material, and the organic material is in contact with a second inorganic material layer between the metallization and the organic material.

8. The apparatus according to claim 7, wherein the first inorganic material layer comprises at least one of nitrogen, metal, silicon, or oxygen.

9. The apparatus according to claim 8, wherein the first inorganic material layer is in contact with the glass.

10. The apparatus according to claim 9, wherein the second inorganic material layer is in contact with the metallization.

11. The apparatus according to claim 10, wherein the second inorganic material layer includes a metal.

12. The apparatus according to claim 11, wherein the second inorganic material layer comprises the metal and nitrogen.

13. The apparatus according to claim 11, wherein the first inorganic material layer and the second inorganic material layer each have a thickness of less than 200 nm.

14. Multiple integrated circuit (IC) dies electrically coupled to a first metallization feature on a first surface of a glass substrate; Multiple holes extending through the glass; Metallization within the plurality of holes, the metallization electrically coupling the first metallization feature to a second metallization feature on the second surface of the glass; and A liner having at least one inorganic material layer in contact with at least one organic material layer, the liner being located within the plurality of pores and between the metallization and the glass, A system equipped with these features.

15. The system according to claim 14, wherein the at least one organic material layer is not present in the first metallization feature.

16. The system according to claim 14 or 15, further comprising an electrical routing structure on the first surface of the glass, the electrical routing structure having the first metallization feature and an organic dielectric material, the plurality of holes extending from the electrical routing structure to the second surface of the glass, and the electrical routing structure electrically coupling the metallization in the plurality of holes to at least one of the IC dies.

17. The system according to claim 14 or 15, wherein the at least one organic material layer has an elastic modulus of less than 100 GPa.

18. The system according to claim 14 or 15, wherein the at least one organic material layer has a coefficient of thermal expansion (CTE) of less than 25 ppm / K.

19. The system according to claim 14 or 15, wherein the at least one organic material layer has an elastic modulus of less than 90 GPa and a thermal expansion coefficient of at least 8 ppm / K, and the at least one organic material layer has a thickness of at least 500 nm.

20. The system according to claim 14 or 15, wherein the at least one organic material layer comprises polytetrafluoroethylene (PTFE), poly(glycidyl methacrylate) (PGMA), poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), or poly(1H,1H,2H,2H-perfluorodecyl acrylate (pPFDA), poly(diallyldimethylammonium chloride) or polyethyleneimine (PEI), polystyrene sulfonate, or sulfonated polysulfone.

21. The system according to claim 14 or 15, wherein the liner has an organic material between two inorganic material layers.

22. The stage where you receive the workpiece, including the glass; A step of forming a through hole in the glass; A step of depositing a liner on the side walls of the through holes and covering the glass surface between the through holes, wherein the step of depositing the liner is: A step of depositing a first inorganic material layer so as to cover the side wall using a first deposition process; A step of depositing an organic material layer so as to cover the first inorganic material layer using a second deposition process; and A third step involves depositing a second inorganic material layer over the organic material layer using a third deposition process. Having; and The step of forming metallization within the through hole and covering the liner. A method that includes [a certain feature].

23. The method according to claim 22, wherein the second deposition process includes initiated chemical deposition (iCVD).

24. The method according to claim 22 or 23, wherein the first deposition process and the third deposition process include atomic layer deposition (ALD).

25. The method according to claim 22 or 23, further comprising the step of forming an electrical routing structure on a first surface of the glass, wherein the electrical routing structure includes interconnect metallization features in an organic dielectric material, and the through-holes extend from the electrical routing structure to a second surface of the glass.

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