Method and structure of multilayer-filled glass through-vias (TGVs)

Abstract

This invention provides a structure and method for multilayer-filled glass through-vias (TGVs) within a glass core. [Solution] The glass core includes a plurality of glass through vias (TGVs), each TGV having a side wall, and within each TGV is a multilayer filler material, the multilayer filler material characterized by a layer of copper conforming to the side wall and at least one layer of nickel-iron alloy within the copper layer. The nickel-iron alloy may be inva. The multilayer filler material includes a material and arrangement of materials that approximate a desired or target coefficient of thermal expansion (CTE) relative to the glass core.

Description

Technical Field

[0001] In various semiconductor devices, a glass core is implemented in a multilayer substrate. Electrical communication through the glass core is often facilitated by glass through-vias (TGVs) filled with copper. The copper, glass, and organic substrates that can be adhered may each exhibit different coefficients of thermal expansion (CTE). In an assembled structure, stress is applied to the glass core due to the CTE mismatch, and cracking may occur. Therefore, improved methods and structures for filling TGVs are desired.

Brief Description of the Drawings

[0002] [Figure 1] Simplified cross-sectional views of glass through-vias according to various embodiments are provided.

[0003] [Figure 2] Various exemplary stages of fabricating multilayer-filled glass through-vias in a glass core according to various embodiments are shown. [Figure 3] Various exemplary stages of fabricating multilayer-filled glass through-vias in a glass core according to various embodiments are shown. [Figure 4] Various exemplary stages of fabricating multilayer-filled glass through-vias in a glass core according to various embodiments are shown.

[0004] [Figure 5] Exemplary further fabrication and assembly processes of embodiments as described below are shown. [Figure 6] Exemplary further fabrication and assembly processes of embodiments as described below are shown.

[0005] [Figure 7] Exemplary methods of multilayer-filled glass through-vias according to various embodiments are shown.

[0006] [Figure 8] This is a top view of a wafer and die that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0007] [Figure 9] This is a simplified side cross-sectional view showing the implementation of an integrated circuit on a die, which may be included in various embodiments, according to any of the embodiments disclosed herein.

[0008] [Figure 10] This is a side cross-sectional view of a microelectronic assembly that may include any of the embodiments disclosed herein.

[0009] [Figure 11] This is a block diagram of an exemplary electrical device, which may include any of the embodiments disclosed herein. [Modes for carrying out the invention]

[0010] Semiconductor packages may include multilayer substrates having a "glass core" or with layers of glass sandwiched between them. The glass layers have perforations (also called through-vias or glass through-vias (TGVs)) that penetrate them to accommodate the routing of electrical signals between the silicon substrates on their upper and lower surfaces. The glass layers provide mechanical / directional stability and rigidity to the semiconductor package and can increase routing density. However, the mismatch in the coefficient of thermal expansion (CTE) of copper used in TGVs (Cu CTE is approximately 17 parts per million (ppm)) and the coefficient of thermal expansion of glass (the CTE of glass ranges from approximately 2 to 10 ppm), as well as the brittle nature of glass, continue to present technical challenges in fabrication and operation.

[0011] Some solutions involve filling the TGV with low CTE materials (i.e., materials with a lower CTE than copper). However, low CTE materials tend to have poor conductivity, which unfavorably limits performance and power density.

[0012] Embodiments described herein provide a technical solution to this technical problem in the form of multilayer-filled glass through vias. As used herein, “multilayer” means that at least two different materials are physically layered within the cavity of the TGV. In embodiments, copper and inva are layered within the TGV. As described above, the copper has a CTE of 17 ppm. The copper also has a resistivity of 1.7 ohms / cm and a Young's modulus of 120 GPa. Inva (NiFe) is an alloy containing nickel and iron, one common form being Fe 0.64 Ni 0.36 NiFe has a CTE of 0.4 ppm ± 20%, a resistivity of 80 ohms / cm, and a Young's modulus of 140 GPa. Since Young's modulus is a measure of stress per unit strain, a higher Young's modulus means that the component is more brittle. NiFe has a significantly better CTE and improved rigidity compared to copper, but its much higher resistivity limits its practical applications. Advantageously, the embodiment overcomes the limitation of the high resistivity of inva by layering inva with copper.

[0013] The structures and methods described herein can be readily detected by SEM and / or TEM imaging to reveal the layered structure of the materials described herein. These concepts are further developed below.

[0014] In the following, exemplary embodiments are described in conjunction with the following drawings, where similar reference numerals indicate similar elements. Unless otherwise noted, the drawings are not necessarily to scale, but may depend on the spatial orientation and relative positioning of the features. As can be understood, certain terms such as “ceiling” and “floor,” as well as “upper,” “uppermost,” “lower,” “above,” “below,” “bottom,” and “top,” refer to directions based on viewing the drawings from which the references are made. Furthermore, terms such as “front,” “back,” “rear,” “side,” “vertical,” and “horizontal” may describe the orientation and / or position of parts of a component within a frame, consistent but arbitrary in the references, as revealed by referring to the text describing the component under discussion and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0015] As used herein, the term “adjacent” refers to layers or components that are in direct physical contact with each other, with no layers or components between them. For example, layer X adjacent to layer Y refers to a layer that is in direct physical contact with layer Y. In contrast, as used herein, the terms “located on” (or, in the context of a first layer or component located on a second layer or component, “located under,” “located above / over,” or “located next to”) include (i) configurations in which the first layer or component is directly physically attached to (i.e., adjacent to) the second layer, and (ii) components and configurations in which the first layer or component is attached to (e.g., coupled to) the second layer or component via one or more intervening layers or components.

[0016] The following detailed description is not intended to limit the uses and applications of the disclosed technology. Novel embodiments may be apparent to be implemented without any of the details described herein. For simplicity, well-known structures and devices may be shown in the form of block diagrams to facilitate their explanation.

[0017] Figures 1–6 contain numerous repeating objects. Unless otherwise noted, similar objects, whether labeled or not, are intended to perform the same function or be the same feature across multiple images. Furthermore, while the objects in Figures 1–6 are not to scale, the various relationships and orientations shown in the images are intentional, as described herein.

[0018] Figure 1 provides a simplified cross-sectional view of an embodiment of a conformally plated glass through-via. The glass layer 102, or "glass core," may be patterned with a plurality of through-holes, also referred to as glass through-vias (TGVs). Embodiments 100 and 130 show one of at least one TGV that may be present in the glass layer 102. The glass layer 102 has an upper surface 101 and a lower surface 103. The glass layer 102 may have a thickness 113 (Z height) in the range of 20 microns + / - 10% to 2 millimeters + / - 10%.

[0019] The glass layer 102 may include glass (the glass used herein may be an alkali-free alkaline earth borosilicate glass such as glass containing aluminum, oxygen, boron, silicon, and alkaline earth metals (e.g., beryllium, magnesium, calcium, strontium, barium, radium such as glass containing SiO2, Al2O3, B2O3, and MgO)), or photosensitive glass (glass that can be photo-processed or photo-structured). In some embodiments, the photosensitive glass may be a glass belonging to the lithium silicate family of glasses (e.g., glass containing lithium, silicon, and oxygen) containing metal particles such as gold, silver, or other suitable metal particles. In some embodiments, the glass layer 102 or the glass core may include a plurality of glass sheets bonded together with an adhesive layer.

[0020] At least one through-hole or glass through-via (TGV) is formed in the glass layer 102 (at 802). The through-hole extends downward from the upper surface 101 to the lower surface 103 as shown and has an axis orthogonal to the upper surface. The TGV is a volume for removing glass and filling it with a conductive filling material, which will be described in more detail below. The through-hole is characterized by continuous sidewalls 105 associated with a first diameter 110-1, 110-3 at the upper surface 101 and a first diameter 110-2, 110-4 at the lower surface 103, and the axis of the through-hole is substantially perpendicular to the upper surface 101 of the glass layer 102 (and also substantially perpendicular to the lower surface 103), where substantially perpendicular is defined as 90 degrees + / - 5 degrees. Embodiment 100 shows an ideal cylindrical TGV where the through-hole has a continuous first diameter 110-1 from the upper surface 101 to the lower surface 103 (in other words, the first diameter 110-1 is equal to the first diameter 110-2).

[0021] In reality, the shape of the TGV reflects the technology used to create it. When creating through-holes using a laser etching process, the top surface 101 is laser-etched to approximately the midpoint of the glass layer 102 in the Z direction, and the bottom surface 103 is similarly laser-etched to the midpoint. The side walls 105 have a perceptible taper towards the midpoint. The midpoint can be in the range of + / - 15% of the middle between the top surface 101 and the bottom surface 103. In this image, the taper is exaggerated for illustrative purposes; at the midpoint, as shown in embodiment 130, the TGV has a second diameter 114 that is smaller than the first diameter (note that the figure is not to scale but is reliable as a general spatial relationship). In an embodiment, the second diameter is at least 10% smaller than the first diameter.

[0022] Therefore, depending on the etching process, it is possible to obtain a TGV with a somewhat hourglass-shaped profile where the through-hole narrows as the side wall 105 is traced towards the midpoint. In this scenario, the slope or taper of the side wall can be defined by an angle 120 measured radially around the axis from the top surface towards the midpoint, and similarly, it can be measured radially around the axis from the bottom surface 103 towards the midpoint. This hourglass shape can potentially affect the power density and performance.

[0023] In an embodiment, there may be a conductive liner layer 104 (also referred to as a "seed layer") within the through-hole, and the liner layer 104 is added at 706. The liner layer 104 is conformal to the side wall 105 of the cavity 106 / 136. The conductive liner layer 104 is continuous from the top surface 101 to the bottom surface 103. The liner layer 104 does not completely fill the TGV, which means that after depositing the conductive liner layer 104, a portion of the cavity 106 and cavity 136 remains open from the top surface 101 to the bottom surface 103.

[0024] The liner layer 104 may be added using a chemical vapor deposition (CVD) process, also known as plating. In some embodiments, the conductive layer 104 can be very thin, such as 20 nanometers ± 5 nanometers. In various embodiments, such as Embodiment 100 and Embodiment 130, the thickness of the liner layer 104 at any given point along the sidewall can be between 20 nanometers - 5 nanometers and 200 nanometers + 5 nanometers. The thickness of the conductive layer 104 depends on the method used to deposit the conductive layer 104. In various embodiments, the material of the liner layer 104 includes titanium. In other embodiments, the material of the liner layer 104 may be nickel, aluminum, chromium, silver, gold, cobalt, or any other conductive material.

[0025] Continuing with Figure 1, Figures 2 and 3 are simplified cross-sectional views of various exemplary stages of fabricating multilayer-filled glass through vias according to various embodiments. Figures 4 to 6 are simplified cross-sectional views of various exemplary uses of multilayer-filled glass through vias according to various embodiments. In Figures 2 onward, for the purpose of simplifying the images, the vertical sidewalls of the TGV are shown (for example, as shown in Embodiment 100 having a cavity 106). Figure 7 shows an exemplary method 700 of a multilayer-filled glass through via.

[0026] Image 200 shows the glass layer 202 or glass core before the creation of the TGV and cavity. In various embodiments, the glass layer 202 may be a reconfigured wafer with a glass core, an entire uncut panel, or a diced panel.

[0027] In embodiments where the panel is manufactured in a single step, the length X of the glass layer and the corresponding length Y (defining the region from top to bottom or in a plan view) may be within the range of a first length (e.g., X) in the range of 10 mm to 700 mm and a second length (e.g., Y) in the range of 10 mm to 700 mm, where the first length is perpendicular to the second length. The compositions of the glass 202 / 302 / 402 / 502 / 602 are described above in relation to Figure 1.

[0028] Figure 230 shows through holes or TGVs created within the glass layer 202 (in 702). As described above, the laser alters the chemical properties of the glass, allowing for etching away of areas where slopes or tapers may occur, as described in relation to Embodiment 130. In Figure 230, a first TGV 232-1 / 332-1 and a second TGV 232-2 / 332-2 are shown. In practice, TGVs 232-1 and 232-2 may be two of a plurality of TGVs. An optional cavity 234 / 334 may also be created at this stage. The optional cavity 234 may be large enough (e.g., minimum diameter) to house an IC die or other components in a later fabrication stage. In various embodiments, the optional cavity 234 / 334 may have a diameter in the range of 1 to 30 millimeters.

[0029] As shown in Figure 250, at 706, a conductive liner layer 104 / 204 is added and is indicated using a thicker line than the boundary of glass 202 in Figure 230. In various embodiments, the conductive liner layer 104 / 204 is adjacent to glass 102 / 202 as shown. Liner layer 204 is adjacent to glass 202.

[0030] In 708, a manufacturing process is selected for creating a multilayer-filled TGV. Specifically, in 708, a processing method is selected for filling the TGV with multiple layers of copper and inva "sandwiched" together. The first optional choice is called pulsed plating or switched potential plating. Using pulsed plating, one electroplating solution or electroplating bath is used. This bath contains an excess of Ni and Fe, so that when a layer of glass is immersed in the electroplating solution, the deposition of copper (Cu) during the deposition of NiFe is limited by mass transfer. As used herein, "excess" means that the electroplating solution is approximately 60-90% NiFe. Then, by switching the voltage potential or turning off the current, it becomes possible for the more noble copper (Cu) to replace NiFe and form a copper-rich layer. Using this optional choice, the "sandwich" of inva and copper, which is the multilayer-filling material, can be electrochemically deposited from a single electrolytic cell.

[0031] A second optional choice is to create two separate electroplating solutions, one using copper and the other using Inva. When a layer of glass is immersed in the copper (Cu) electroplating solution, a layer of copper can be electrodeposited. The copper bath generally contains copper, sulfuric acid, several organic chemicals, accelerators, brightness inhibitors, and some specialized materials. This copper electroplating bath yields a filler material consisting mainly of copper. After the layer of copper has been deposited, a layer of Inva can be electrodeposited. The Inva electroplating solution may contain nickel and iron atoms.

[0032] In the embodiment shown in Figure 3, only one through-hole TGV232-1 / TGV332-1 is shown for the purpose of discussing multilayer filling. At 710, the process selected at 708 is performed, and the TGV is filled with multiple alternating (or "sandwiched") layers of copper (slanted black lines to the right) and inva (dark gray), as shown in Embodiments 300, 350, and 370. In other words, the cavity 106 and / or cavity 136 are filled with a filler material comprising at least one copper layer and at least one inva layer adjacent to each other, with one copper layer of the at least one copper layer adjacent to the sidewall and conforming with the sidewall. As used herein, the verb “filling” means distributing a sufficient amount of filler material into the upper surface 101 and the lower surface 103 to enable electrical communication or a continuous electrical path between them, and a TGV filled with filler material has filler material distributed sufficiently within the cavity to enable electrical communication between the upper surface 101 and the lower surface 103.

[0033] The thickness of the copper and NiFe layers, as well as the number of copper and NiFe layers, can be modified to meet customer and / or application needs. Figure 3 shows some non-limiting examples. In Embodiment 300, the breakout dashed line shows a plan view or top view 333 of the TGV332-1. A layer of copper with a thickness of 336 conforms to the sidewall of the TGV332-1. Inside the copper layer is a layer of inva with a thickness of 338. In the top view 333, in this non-limiting example, the diameter of the inva is equal to its thickness of 338, as the center / core of the TGV is filled with inva. In a side view (or cross-sectional view of ZX), this may be described as a first copper layer conforming to sidewall 105-1, followed by an Inva layer, and further a second copper layer conforming to sidewall 105-2; however, as will be understood by those skilled in the art, the sidewalls are actually continuous, and therefore, in a top view (or XY view), this may appear as a first copper ring conforming to sidewall 105 having a thickness of 336, followed by a concentric ring of an alloy containing nickel and iron (e.g., Inva) having a diameter equal to a thickness of 338, where the multiple copper layers and Inva layers together "fill" the TGV and jointly provide an electrical path from top to bottom as described above.

[0034] In Embodiment 350, the dashed lines outside the figure indicate a plan view or top view 353 of the TGV332-1. A layer of copper having a thickness of 356 conforms with the side wall 105 of the TGV332-1. Inside the copper layer is a layer of inva having a thickness of 358, and inside the layer of inva is another layer of copper having a thickness of 360. In the top view 353, in this non-limiting example, the core of the TGV is filled with copper, so the diameter of the copper core or center is equal to the shown copper thickness 360. In a side view (or cross-sectional view of ZX), this may be described as a first copper layer conforming to sidewall 105-1, followed by an Inva layer having a thickness of 358, followed by a second copper layer having a thickness of 360, followed by a second Inva layer having a thickness of 358, followed by a third copper layer conforming to sidewall 105-2 and having a thickness of 356; however, in a top view (or XY view), this may appear as a first ring containing copper with a thickness of 356 conforming to sidewall 105, this first ring concentrically surrounding a second ring containing Inva with a thickness of 358, the second ring concentrically surrounding another ring of copper / copper core having a diameter equal to a thickness of 360, and the multiple copper layers and Inva layers working together to "fill" the TGV, providing an electrical path from top to bottom as described above.

[0035] Embodiment 370 extends the concepts developed in Embodiments 300 and 350. In Embodiment 370, the TGV332-1 is filled with a filler material 372, which includes the multilayer filler described herein. More specifically, in Embodiment 370, a layer of copper conforms with the side wall 105 of the TGV332-1. Inside the layer of copper is a layer of inva, followed by another layer of copper, followed by another layer of inva, and so on.

[0036] The diameter of the TGV can vary depending on the thickness of the glass core 202 / 302. In a non-limiting example, a 100-micron glass core may have a 30-micron TGV. The thickness of the layers in a TGV filled with multiple layers is adjusted accordingly. Furthermore, as the diameter of the TGV increases (e.g., from 100 microns to 3000 microns), the layer thickness can vary further, and there may be considerable variation in layer thickness. It should be noted that the thickness of individual layers is not precise; rather, the TGV consists of multiple layers of these materials.

[0037] In the first non-limiting example, in Embodiment 300, the copper layer or copper ring may have a thickness 336 of 5 to 10 microns + / - 10%, and the Invacore (or layer of an alloy containing nickel and iron) may have a thickness 338 of 5 to 10 microns + / - 10%, thereby filling a TGV with a diameter of 30 microns + / - 10%. In another example, for a TGV with a diameter of 30 microns, the thicknesses of the layers represented by thicknesses 336 and 338 may vary between 5 microns and 20 microns.

[0038] In a second non-limiting example, in embodiment 350, the copper core may have a minimum thickness 360 (or minimum diameter) of 5 microns + / - 10%, and the inner thickness 358 may be in the range of 1 to 50 microns. The copper thickness 356 may be in the range of 10 nanometers to 200 nanometers.

[0039] In 712, as shown in Embodiment 350, chemical mechanical polishing (CMP) may be performed in Embodiment 300 to remove the seed layer and any filler material on the surface and expose the glass surface 101 / 103.

[0040] The implementation of the embodiments can be identified by visually inspecting TEM or SEM images of a cross-sectional view of the filled TGV, as shown in embodiments 300 and 350, and in combination with compositional analysis of the filling material, to detect the multilayer filled TGV described herein.

[0041] As shown in Figure 400, the embodiment may undergo further semiconductor manufacturing processes, such as constructing one or more layers of semiconductor substrate on the upper surface (e.g., 404) or lower surface (e.g., 406) of embodiment 350 in 714. Continuing this simplified example, Figure 500 and the multi-die assembly 600 show embodiment 350 mounted on or sandwiched within a semiconductor substrate, where the semiconductor substrate may be described as follows: semiconductor substrate 504 / 604 includes one or more dielectric layers 508 / 608 with redistribution layers (RDL) or conductive traces 528 / 628 and vias 526 / 626 patterned therein on the upper surface of embodiment 350, and semiconductor substrate 506 / 606 includes one or more dielectric layers 508 / 608 with redistribution layers (RDL) or conductive traces 528 / 628 and vias 526 / 626 patterned therein on the lower surface of embodiment 350.

[0042] The dielectric material 508 / 608 can be any insulating material such as suitable nitrides or oxides, including SiOx, silicon dioxide (SiO2), SiOxNy, carbon-doped silicon dioxide (also known as C-doped SiO2, CDO, or organosilicate glass, and is a material containing silicon, oxygen, and carbon), fluorine-doped silicon dioxide (also known as fluorosilicate glass, and is a material containing F-doped SiO2, fluorine, silicon, and oxygen), and hydrogen-doped silicon dioxide (a material containing H-doped SiO2, silicon, oxygen, and hydrogen). In some embodiments, the dielectric layer includes a photo-imageable dielectric (PID). In some embodiments, the dielectric material includes an Ajinomoto Build-Up film (ABF), which is a material comprising an organic resin matrix having different types of fillers (e.g., silica fillers of different sizes or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk) and / or dielectric loss tangent (insertion loss) (Df)).

[0043] It should be noted that the optional cavity 334 may initially be filled with filler material. In practice, this filler material from the optional cavity 432 may be removed by laser drilling or ablation, for example, so that integrated circuits or components can be placed and electrically connected within it when constructing a system or package assembly. Some non-exclusive examples of ICs and components that may be placed in the cavity 432 include memory or high-bandwidth memory, trench capacitors, central processing units, optical integrated circuits, and graphics processing units.

[0044] The conductive material used in RDL trace 628 and via 626 may include a metal (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or a combination thereof) or another suitable conductive material.

[0045] The optional cavity 334 is left open and filled with an IC, PIC, or other component, and electrically mounted to 510 / 610 and 512 / 612 as known in the art. As intended, the multilayer filled through-glass vias within the glass core 502 provide via landings and contacts and electrical paths from the upper surface 503 / 603 of the substrate to the lower surface 505 / 605 of the substrate.

[0046] Figure 6 shows an exemplary multi-die assembly 600 in which the first and second ICs are mounted on the top surface 603 and solder is applied to openings created for them on the bottom surface 605. Die IC1 and IC2 may be unpackaged integrated circuit dies and may instead be referred to as chips, chiplets, chip complexes, or chiplet complexes. While the terms die, chip, and chiplet may be used interchangeably, the term chiplet may be used to refer to an integrated circuit die that implements a subset of the functionality of a larger integrated circuit component. Although the chiplets are shown in the figure as having uniform dimensions, in reality the dimensions (lateral dimensions and thickness) and shape of chiplets may vary from chiplet to chiplet; furthermore, chiplets may also vary by type / function (e.g., computation, memory, I / O, power management (control of power supply and / or power supply to components)).

[0047] In the subsequent manufacturing stage, dies IC1 and IC2 may be stabilized within a capsule material such as a molding compound, dielectric material, metal, ceramic, plastic, or a combination thereof. Underfill may also be used beneath IC1 and IC2 to surround solder bumps. Various underfill materials can be used; generally, they are (electrically) nonconductive and reduce thermomechanical stress. The underfill material may take the form of a liquid prepolymer with fillers such as silica, alumina, or boron nitride. The underfill may be cured to solidify it.

[0048] Furthermore, as part of the thermal management solution, a thermal conduction layer interface material (TIM) (not shown) may be arranged across the capsule material and / or across the die. The TIM may be any preferred material such as a silver particle-filled thermal compound, thermal grease, phase change material, indium foil, or graphite sheet. The thermal management solution may be a conformal solution that corresponds to differences in the height of the integrated circuit die for which the thermal management solution provides cooling. For example, the thermal management solution may include a substantially planar cooling component having a TIM of varying thickness between the cooling component and the integrated circuit die. In another example, the cooling component is non-planar, and the profile of the cooling component may vary with the thickness of the integrated circuit die for which the cooling component provides cooling. In such embodiments, the TIM may have a substantially uniform thickness between the cooling component and the integrated circuit die of varying thickness. The thermal management solution may also include an integrated heat spreader.

[0049] Accordingly, various non-limiting embodiments of the structure and method of multilayer-filled TGV have been described. The embodiments, as described and illustrated herein, are not limited to the chemical identity and planar depiction of the filler materials and exhibit clear features in SEM images. The following description provides additional details and context regarding various dies and various package assemblies and device configurations that can be created based on or using the provided embodiments.

[0050] Figure 8 is a top view of a wafer 800 and a die 802 that may be included in any of the embodiments disclosed herein. The wafer 800 may be made of a semiconductor material and may include one or more dies 802 formed on the surface of the wafer 800. After the fabrication of the integrated circuit components on the wafer 800 is complete, the wafer 800 may undergo a fragmentation process in which the dies 802 are separated from each other to provide individual “chips” or to be destined for packaged integrated circuit components. An individual die 802 containing integrated circuit components may include one or more transistors (e.g., part of transistor 940 in Figure 9 discussed below), support circuits for transferring electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 800 or die 802 may include memory devices (random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, and conductive-bridging RAM (CBRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Furthermore, multiple devices may be combined on a single die 802. For example, a memory array formed by multiple memory devices may be formed on the same die 802 as a processor unit (e.g., processor unit 1102 in Figure 11) or other logic configured to store information in the memory devices or execute instructions stored in the memory array. In some embodiments, the die 802 may be mounted on a wafer 800 containing other dies, and the wafer 800 is subsequently pulverized; this manufacturing procedure is referred to as the die-to-wafer assembly technique.

[0051] Figure 9 is a side cross-sectional view of an integrated circuit 900 that may be included in any of the embodiments disclosed herein. One or more of the integrated circuits 900 may be included in one or more dies 802 (Figure 8). The integrated circuit 900 may be formed on a die substrate 902 (e.g., wafer 800 in Figure 8) and may be included in a die (e.g., die 802 in Figure 8).

[0052] The die substrate 902 may be a semiconductor substrate constructed from a semiconductor material system including, for example, a system (or a combination of both) of n-type or p-type materials. The die substrate 902 may include, for example, a crystalline substrate formed using a Burk silicon or silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 902 may be formed using alternative materials, which may or may not be combined with silicon, and which include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 902. While several examples of materials on which the die substrate 902 may be formed are described herein, any material capable of functioning as the basis for the integrated circuit 900 may be used. The die substrate 902 may be part of a slicing die (for example, die 802 in Figure 8) or a wafer (for example, wafer 800 in Figure 8).

[0053] The integrated circuit 900 may include one or more device layers 904 disposed on the die substrate 902. The device layer 904 may include features of one or more transistors 940 (e.g., metal oxide semiconductor field-effect transistors: MOSFETs) formed on the die substrate 902. The transistors 940 may include, for example, one or more source and / or drain (S / D) regions 920, a gate 922 for controlling the flow of current between the S / D regions 920, and one or more S / D contacts 924 for transferring electrical signals to and from the S / D regions 920.

[0054] The gate 922 may be formed of at least two layers: a gate dielectric and a gate electrode. The gate dielectric layer may consist of one or more layers stacked together. One or more layers may consist of silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric material. High-k dielectric material may consist of elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, and zinc lead niobate. In some embodiments, an annealing process is performed on the gate dielectric, which can improve its quality when high-k materials are used.

[0055] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 940 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a filler metal layer. Furthermore, metal layers may be included for other purposes, such as barrier layers.

[0056] For PMOS transistors, the metals that can be used for the gate electrode are, but are not limited, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, the metals that can be used for the gate electrode are, but are not limited, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0057] In some embodiments, when viewed as a cross-section of the transistor 940 along the source-channel-drain direction, the gate electrode may include a U-shaped structure comprising a bottom portion substantially parallel to the surface of the die substrate 902 and two sidewall portions substantially perpendicular to the top surface of the die substrate 902. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 902 and not comprising sidewall portions substantially perpendicular to the top surface of the die substrate 902. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on the tops of one or more planar non-U-shaped layers.

[0058] In some embodiments, pairs of sidewall spacers may be formed on opposing sides of the gate stack so as to surround the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and include deposition and etching processes. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0059] The S / D region 920 can be formed within the die substrate 902 adjacent to the gate 922 of individual transistors 940. The S / D region 920 can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic are ion-implanted into the die substrate 902 to form the S / D region 920. An annealing process may follow the ion implantation process to activate the dopants and further diffuse them into the die substrate 902. In the latter process, the die substrate 902 may first be etched to form a recess at the location of the S / D region 920. An epitaxial deposition process may then be performed to fill the recess with the material used to fabricate the S / D region 920. In some packaging configurations, the S / D region 920 can be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 920 may be formed using one or more alternating semiconductor materials such as germanium or Group III-V materials or alloys. In further embodiments, one or more layers of metals and / or metal alloys may be used to form the S / D region 920.

[0060] Electrical signals, such as power and / or input / output (I / O) signals, can be transferred to and from devices on device layer 904 (e.g., transistors 940) through one or more interconnect layers (shown as interconnect layers 906-910 in Figure 9) located on device layer 904. For example, conductive features of device layer 904 (e.g., gates 922 and S / D contacts 924) can be electrically coupled to interconnect structures 928 of interconnect layers 906-910. One or more interconnect layers 906-910 can form a metallization stack (also referred to as the "ILD stack") 919 of the integrated circuit 900.

[0061] The interconnect structure 928 may be arranged within interconnect layers 906-910 to transfer electrical signals according to a variety of designs; in particular, the arrangement is not limited to the specific configuration of the interconnect structure 928 shown in Figure 9. Although a certain number of interconnect layers 906-910 are shown in Figure 9, embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than those shown.

[0062] In some embodiments, the interconnect structure 928 may include lines 928a and / or vias 928b filled with a conductive material such as metal. Lines 928a may be arranged to transfer electrical signals in a plane substantially parallel to the surface of the die substrate 902 on which the device layer 904 is formed. For example, lines 928a may transfer electrical signals in the direction inward and outward of a page, and / or across a page. Vias 928b may be arranged to transfer electrical signals in a plane substantially perpendicular to the surface of the die substrate 902 on which the device layer 904 is formed. In some embodiments, vias 928b may electrically couple lines 928a of different interconnect layers 906-910 together.

[0063] As shown in Figure 9, interconnect layers 906-910 may include dielectric material 926 disposed between interconnect structures 928. In some embodiments, the dielectric material 926 disposed between interconnect structures 928 in different interconnect layers 906-910 may have different compositions; in other embodiments, the composition of the dielectric material 926 between different interconnect layers 906-910 may be the same. Device layer 904 may include dielectric material 926 disposed between the transistor 940 and the bottom layer of the metallization stack. The dielectric material 926 contained in device layer 904 may have a different composition from the dielectric material 926 contained in interconnect layers 906-910; in other embodiments, the composition of the dielectric material 926 in device layer 904 may be the same as the dielectric material 926 contained in any one of interconnect layers 906-910.

[0064] A first interconnect layer 906 (referred to as metal 1 or "M1") may be formed directly on the device layer 904. As shown, in some embodiments, the first interconnect layer 906 may include lines 928a and / or vias 928b. Lines 928a of the first interconnect layer 906 may be coupled to contacts of the device layer 904 (e.g., S / D contacts 924). Vias 928b of the first interconnect layer 906 may be coupled to lines 928a of the second interconnect layer 908.

[0065] A second interconnect layer 908 (referred to as metal 2 or "M2") may be formed directly above the first interconnect layer 906. In some embodiments, the second interconnect layer 908 may include vias 928b to connect lines of the interconnect structure 928 of the second interconnect layer 908 with lines 928a of the third interconnect layer 910. Although lines 928a and vias 928b are structurally depicted using lines within individual interconnect layers for clarity, lines 928a and vias 928b may be structurally and / or materially continuous in some embodiments (e.g., filled simultaneously during a dual damascene process).

[0066] A third interconnect layer 910 (referred to as metal 3 or "M3") (and additional interconnect layers as desired) may be formed in succession on the second interconnect layer 908 according to similar techniques and configurations described in relation to the second interconnect layer 908 or the first interconnect layer 906. In some embodiments, "higher" (i.e., further from the device layer 904) interconnect layers in the metallization stack 919 of the integrated circuit 900 may be thicker than the lower interconnect layers in the metallization stack 919, and the lines 928a and vias 928b in the higher interconnect layers may be thicker than those in the lower interconnect layers.

[0067] The integrated circuit 900 may include a solder resist material 934 (e.g., polyimide or similar material) formed on interconnect layers 906-910 and one or more conductive contacts 936. In Figure 9, the conductive contacts 936 are shown to take the form of bonding pads. The conductive contacts 936 may be electrically coupled to an interconnect structure 928 and configured to transfer electrical signals from transistors 940 to an external device. For example, solder joints may be formed on one or more conductive contacts 936 to mechanically and / or electrically couple the integrated circuit die containing the integrated circuit 900 to another component (e.g., a printed circuit board). The integrated circuit 900 may include additional or alternative structures for transferring electrical signals from interconnect layers 906-910; for example, the conductive contacts 936 may include other similar features (e.g., posts) for transferring electrical signals to an external component.

[0068] In some embodiments where the integrated circuit 900 is a double-sided die, the integrated circuit 900 may include another metallization stack (not shown) on the opposing side of the device layer 904. This metallization stack may include a plurality of interconnect layers, as discussed above with reference to interconnect layers 906-910, to provide conductive paths (including, for example, conductive wires and vias) between the device layer 904 and conductive contact 936 and additional conductive contacts (not shown) on the opposing side of the integrated circuit 900.

[0069] In other embodiments where the integrated circuit 900 is a double-sided die, the integrated circuit 900 may include one or more through-silicon vias (TSVs) that penetrate the die substrate 902; these TSVs may create contact with the device layer 904 and provide a conductive path between the device layer 904 and the conductive contact 936 and additional conductive contacts (not shown) on opposing sides of the integrated circuit 900. In some embodiments, TSVs extending through the substrate may be used to transfer power and ground signals from the conductive contact 936 to the conductive contacts on opposing sides of the integrated circuit 900 to the transistor 940 and any other components integrated into the integrated circuit 900 die, and a metallization stack 919 may be used to transfer I / O signals from the conductive contact 936 to the transistor 940 and any other components integrated into the integrated circuit 900 die.

[0070] Multiple integrated circuits 900 can be stacked with one or more TSVs within individual stacked devices, providing connections between any one of the devices in the stack and any of the other devices. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM die may provide connections between the individual HBM and base integrated circuit dies. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may have fine-pitched solder bumps (microbumps).

[0071] Figure 10 is a side cross-sectional view of a microelectronic assembly 1000, which may include any of the embodiments disclosed herein. The microelectronic assembly 1000 includes a plurality of integrated circuit components arranged on a circuit board 1002 (which may be a motherboard, system board, mainboard, etc.). The microelectronic assembly 1000 may include components arranged on a first surface 1040 and an opposing second surface 1042 of the circuit board 1002; generally, components may be arranged on one or both of surfaces 1040 and 1042.

[0072] In some embodiments, the circuit board 1002 may be a printed circuit board (PCB) comprising a plurality of metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each individual metal layer has conductive traces. One or more of the metal layers may be formed with a desired circuit pattern to transfer electrical signals (optionally, in conjunction with other metal layers) between components coupled to the circuit board 1002. In other embodiments, the circuit board 1002 may be a non-PCB substrate. The microelectronic assembly 1000 shown in Figure 10 includes a package-on-interposer structure 1036 coupled to a first surface 1040 of the circuit board 1002 by a coupling component 1016. The coupling component 1016 can electrically and mechanically couple the package-on-interposer structure 1036 to the circuit board 1002 and may include solder balls (as shown in Figure 10), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female parts of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0073] The package-on-interposer structure 1036 may include an integrated circuit component 1020 coupled to the interposer 1004 by a coupling component 1018. The coupling component 1018 can take any preferred form for applications such as those discussed above with reference to the coupling component 1016. Although a single integrated circuit component 1020 is shown in Figure 10, multiple integrated circuit components may be coupled to the interposer 1004. In fact, additional interposers may be coupled to the interposer 1004. The interposer 1004 may provide an intervening substrate used to bridge the circuit board 1002 and the integrated circuit component 1020.

[0074] The integrated circuit component 1020 may be a packaged or unpackaged integrated circuit component comprising one or more integrated circuit dies (e.g., die 802 in Figure 8, integrated circuit 900 in Figure 9) and / or one or more other suitable components.

[0075] An unpackaged integrated circuit component 1020 includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly mounted to the interposer 1004. In embodiments in which the integrated circuit component 1020 includes multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). In addition to comprising one or more processor units, the integrated circuit component 1020 may comprise additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may reside on the same integrated circuit die as the processor units, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies may be referred to as “chiplets.” In embodiments in which the integrated circuit component includes multiple integrated circuit dies, interconnections between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate, or a combination thereof. Packaged multi-die integrated circuit components may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0076] The interposer 1004 may spread connections to a wider pitch or re-transfer connections to different connections. For example, the interposer 1004 may couple an integrated circuit component 1020 to a set of ball grid array (BGA) conductive contacts of coupling component 1016 for coupling to a circuit board 1002. In the embodiment shown in Figure 10, the integrated circuit component 1020 and the circuit board 1002 are mounted on opposing sides of the interposer 1004; in other embodiments, the integrated circuit component 1020 and the circuit board 1002 may be mounted on the same side of the interposer 1004. In some embodiments, three or more components may be interconnected by the interposer 1004.

[0077] In some embodiments, the interposer 1004 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1004 may be formed of polymer materials such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin containing inorganic fillers, ceramic material, or polyimide. In some embodiments, the interposer 1004 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1004 may include, but is not limited to, metal interconnects 1008 and vias 1010, including through vias 1010-1 (extending from a first surface 1050 of the interposer 1004 to a second surface 1054 of the interposer 1004), blind vias 1010-2 (extending from the first or second surface 1050 or 1054 of the interposer 1004 to an internal metal layer), and embedded vias 1010-3 (connecting the internal metal layer).

[0078] In some embodiments, the interposer 1004 may comprise a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first surface of the silicon interposer to an opposing second surface of the silicon interposer. In some embodiments, the interposer 1004 comprising a silicon interposer may further comprise one or more routing layers for routing connections from the first surface of the interposer 1004 to the opposing second surface of the interposer 1004.

[0079] The interposer 1004 may further include embedded devices 1014, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. Multiple more complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 1004. The package-on-interposer structure 1036 may take any form of package-on-interposer structure known in the art.

[0080] The integrated circuit assembly 1000 may include an integrated circuit component 1024 coupled to the first surface 1040 of the circuit board 1002 by a coupling component 1022. The coupling component 1022 may take any form of the embodiments discussed above with reference to the coupling component 1016, and the integrated circuit component 1024 may take any form of the embodiments discussed above with reference to the integrated circuit component 1020.

[0081] The integrated circuit assembly 1000 shown in Figure 10 includes a package-on-package structure 1034 coupled to a second surface 1042 of a circuit board 1002 by a coupling component 1028. The package-on-package structure 1034 may include integrated circuit components 1026 and 1032, which are coupled together by a coupling component 1030 such that integrated circuit component 1026 is positioned between the circuit board 1002 and integrated circuit component 1032. The coupling components 1028 and 1030 may take any form of the embodiment of the coupling component 1016 discussed above, and the integrated circuit components 1026 and 1032 may take any form of the embodiment of the integrated circuit component 1020 discussed above. The package-on-package structure 1034 may be configured according to any package-on-package structure known in the art.

[0082] Figure 11 is a block diagram of an exemplary electrical device 1100, which may include one or more embodiments disclosed herein. For example, any preferred components of the electrical device 1100 may include a microelectronic assembly 1000, an integrated circuit component 1020, an integrated circuit 900, an integrated circuit die 802, or one or more of the structures disclosed herein. While several components are shown in Figure 11 as being included in the electrical device 1100, one or more of these components may be omitted or duplicated if appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1100 may be mounted on one or more motherboards, mainboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-a-chip (SoC) die. In various embodiments, the electrical device 3000 is enclosed by or integrated with a housing.

[0083] Furthermore, in various embodiments, the electrical device 1100 may not include one or more of the components shown in Figure 11, but may include interface circuits for coupling one or more components. For example, the electrical device 1100 may not include the display device 1106, but may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1106 can be coupled. In another set of examples, the electrical device 1100 may not include the audio input device 1124 or the audio output device 1108, but may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1124 or the audio output device 1108 can be coupled.

[0084] The electrical device 1100 may include one or more processor units 1102 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1102 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Thus, the processor unit may be referred to as XPU (or xPU).

[0085] The electrical device 1100 may include a memory 1104 which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard drives). In some embodiments, the memory 1104 may include a memory located on the same integrated circuit die as the processor unit 1102. This memory may be used as a cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random-access memory (eDRAM) or spin-transfer torque magnetic random-access memory (STT-MRAM).

[0086] In some embodiments, the electrical device 1100 may comprise one or more processor units 1102 that are heterogeneous or asymmetrical to other processor units 1102 in the electrical device 1100. Various differences may exist between the processor units 1102 in the system in terms of architecture, microarchitecture, thermal, power consumption characteristics, and a spectrum of advantages metrics, including similar ones. These differences can effectively be expressed as asymmetrical and heterogeneous between the processor units 1102 in the electrical device 1100.

[0087] In some embodiments, the electrical device 1100 may include communication components 1112 (e.g., one or more communication components). For example, the communication components 1112 may manage wireless communication for data transfer to and from the electrical device 1100. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation over a non-solid medium. The term “wireless” does not imply that the associated device is not wired, although in some embodiments it may not be.

[0088] The communication component 1112 may implement any of several wireless standards or protocols, including, but not limited to, Wi-Fi® (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and Institute for Electrical and Electronic Engineers (IEEE) standards, including the Long-Term Evolution (LTE) project with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra-Mobile Broadband (UMB) project (also known as "3GPP®2")). Broadband radio access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX® networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability tests for the IEEE 802.16 standard. The communication component 1112 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1112 may operate in accordance with GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1112 may operate in accordance with Code Division Multiplexing (CDMA), Time Division Multiplexing (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G and beyond.In other embodiments, the communication component 1112 may operate according to several other radio protocols. The electrical device 1100 may include an antenna 1122 for facilitating and / or receiving other radio communications (such as AM or FM radio transmissions).

[0089] In some embodiments, the communication component 1112 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet® standard). As mentioned above, the communication component 1112 may include multiple communication components. For example, the first communication component 1112 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth®, and the second communication component 1112 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1112 may be dedicated to wireless communications, and the second communication component 1112 may be dedicated to wired communications.

[0090] The electrical device 1100 may include a battery / power circuit 1114. The battery / power circuit 1114 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 1100 to an energy source separate from the electrical device 1100 (e.g., AC line power).

[0091] The electrical device 1100 may include a display device 1106 (or the corresponding interface circuit discussed above). The display device 1106 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0092] The electrical device 1100 may include an audio output device 1108 (or the corresponding interface circuit discussed above). The audio output device 1108 may include any embedded or wired or wireless external device that generates an audible indicator, such as a speaker, headset, or earphone.

[0093] The electrical device 1100 may include an audio input device 1124 (or a corresponding interface circuit as discussed above). The audio input device 1124 may include an optionally embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output). The electrical device 1100 may include a Global Navigation Satellite System (GNSS) device 1118 (or a corresponding interface circuit as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1118 may communicate with a satellite-based system and determine the geographical location of the electrical device 1100 based on information received from one or more GNSS satellites, as is known in the art.

[0094] The electrical device 1100 may include another output device 1110 (or the corresponding interface circuit discussed above). Examples of other output devices 1110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0095] The electrical device 1100 may include another input device 1120 (or the corresponding interface circuit discussed above). Examples of other input devices 1120 may include an accelerometer, gyroscope, compass, image capture device (e.g., a planar or stereoscopic camera), cursor control devices such as a trackball, trackpad, touchpad, keyboard, or mouse, stylus, touchscreen, proximity sensor, microphone, barcode reader, Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoelectric fingertip plethysmography) sensor, electrocutaneous reaction sensor, any other sensor, or radio frequency identification (RFID) reader.

[0096] The electrical device 1100 may have any desired form factor, such as handheld or mobile electrical devices (e.g., mobile phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, 2-in-1 convertible computers, portable all-in-one computers, netbooks, ultrabooks, personal digital assistants (PDAs®), ultra-mobile personal computers, portable gaming consoles, etc.), desktop electrical devices, servers, rack-level computing solutions (e.g., blade, tray, or thread computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, stationary gaming consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., vehicles, smart home appliances, home electronic products or equipment, computing systems that are part of manufacturing equipment). In some embodiments, the electrical device 1100 may be any other electronic device that processes data. In some embodiments, the electrical device 1100 may comprise a plurality of separate physical components. In various embodiments, depending on the range of devices that the electrical device 1100 may be, in some embodiments the electrical device 1100 may be referred to as a computing device or computing system.

[0097] While at least one embodiment is presented in the detailed description above, it should be understood that a vast number of variations exist. It should also be understood that the disclosed embodiments are merely examples and are not intended to limit in any way the scope, applicability, or configuration of this disclosure. Rather, the detailed description above provides those skilled in the art with a convenient roadmap for implementing embodiments of the disclosed embodiments. Various changes can be made to the function and arrangement of the elements without departing from the scope of this disclosure, as described in the appended claims and their legal equivalents.

[0098] As used herein, the term “electronic component” may refer to an active electronic circuit (e.g., a processing unit, memory, storage device, FET) or a passive electronic circuit (e.g., a resistor, inductor, capacitor).

[0099] As used herein, the term “integrated circuit component” may refer to an electronic component made of semiconductor material for performing a function. An integrated circuit (IC) component may include any computing system component described or referred to herein, or one or more of any other computing system components such as a processor unit (e.g., a system-on-a-chip (SoC) processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, memory, or a network interface controller, and may include one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0100] An unexclusive example of an unpackaged integrated circuit component includes a single monolithic integrated circuit die; such die may include solder bumps attached to contacts on the die. When presented on a die, solder bumps or other conductive contacts may enable the die to be directly mounted to a printed circuit board (PCB) or other substrate.

[0101] A non-limiting example of a packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, where the integrated circuit dies and the package substrate are encapsulated in a casing material such as metal, plastic, glass, or ceramic. Often, the casing includes an integrated heat spreader (IHS); packaged integrated circuit components often have bumps, lead pins, or pins attached to the package substrate (either directly or by wires that attach the bumps, lead pins, or pins to the package substrate) for mounting the packaged integrated circuit component to a printed circuit board (or motherboard or base board) or another component.

[0102] As used herein, terms such as “embodiments,” “various embodiments,” “several embodiments,” and similar terms indicate that some embodiments may have some, all, or none of the features described in other embodiments. “First,” “second,” “third,” and similar terms describe a common subject and indicate various instances of the same subject being referenced; unless specifically stated, they do not imply a given sequence, in any way, such as temporally or spatially, in ranking, or in any other manner. In patent application terminology, “connected” refers to elements that are in direct physical or electrical contact with one another, and “coupled” refers to elements that cooperate or interact with one another, and coupled elements may or may not be in direct physical or electrical contact. Furthermore, terms such as “comprising,” “including,” “having,” and similar terms are used synonymously to indicate non-exclusive inclusion.

[0103] As used in this application and in the claims, any list of items linked by the terms "at least one of" or "one or more of" may mean any combination of the enumerated terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B and C. Similarly, the phrase "one or more of A, B, and C" may mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0104] When used in this application and claims, the phrase "each of" or "each of" following a list of items that are described or expressed to have characteristics, features, etc. means that all items in the list have the expressed or expressed characteristics, features, etc. For example, the phrase "each of A, B, or C includes a sidewall" or "each of A, B, or C includes a sidewall" means that A includes a sidewall, B includes a sidewall, and C includes a sidewall.

[0105] Any theory of operation, scientific principle, or other theoretical explanation presented herein with reference to the apparatus or method of this disclosure is provided for the purpose of better understanding and is not intended to be a limitation of scope. The apparatus and method of the appended claims are not limited to those apparatus and method that operate in the manner described by such theory of operation.

[0106] The following examples relate to additional embodiments of the technology disclosed herein.

[0107] Embodiment 1 is a device comprising: a layer of glass having an upper surface and a lower surface; a through hole formed in the glass layer, the through hole having a side wall; a layer of copper conforming to the side wall; and a layer of an alloy containing nickel and iron located within the through hole and adjacent to the copper layer, wherein the copper layer and the layer of the alloy containing nickel and iron together provide an electrical path from the upper surface to the lower surface.

[0108] Example 2 includes the subject matter of Example 1, wherein the nickel and iron alloy has Fe0.64 Ni0.36.

[0109] Example 3 includes the subject matter of Example 1, wherein the nickel-iron alloy has a coefficient of thermal expansion (CTE) of 0.4 parts per million (PPM) + / - 20%.

[0110] Example 4 includes the subject of Example 1, wherein the copper layer has a thickness of 10 microns + / - 10%, and the alloy layer containing nickel and iron has a thickness of 10 microns + / - 10%.

[0111] Example 5 includes the subject matter of Example 1,

[0112] The copper layer is one of a plurality of copper layers; the nickel and iron alloy layer is one of a plurality of nickel and iron alloy layers; and in the cross-sectional view of the through hole, the plurality of copper layers and the plurality of nickel and iron alloy layers appear alternately.

[0113] Example 6 includes the subject matter of Example 1, wherein the copper layer is one of a plurality of copper layers; the nickel and iron alloy layer is one of a plurality of nickel and iron alloy layers; and in the plan view of the through hole, the plurality of copper layers and the plurality of nickel and iron alloy layers appear alternately in a concentric ring.

[0114] Example 7 includes the subject matter of Example 1, wherein the glass layer has a thickness in the range of 20 microns + / - 10% to 2 millimeters + / - 10%.

[0115] Example 8 comprises the subject matter of Example 1, further comprising: another layer of copper sandwiched within the layer of the nickel and iron alloy; and the copper layer, the layer of nickel and iron alloy, and the other layer of copper together provide an electrical path from the upper surface to the lower surface.

[0116] Example 9 includes the subject matter of Example 1 and further comprises a liner layer containing titanium having a thickness of 20 nanometers + / - 5 nanometers between the copper layer and the sidewall.

[0117] Example 10 is a package assembly comprising: a first semiconductor substrate including a plurality of dielectric layers and a redistribution layer therein; conductive vias in the first semiconductor substrate, the conductive vias electrically connected to the redistribution layer and exposed on the lower surface of the first semiconductor substrate; a layer of glass attached to the lower surface of the first semiconductor substrate, the glass layer having a plurality of through-glass vias (TGVs), each TGV having a sidewall; a multilayer filler material in the plurality of TGVs, wherein the multilayer filler material is characterized by a conformal copper layer and at least one layer of an alloy containing nickel and iron in the sidewall; and a second semiconductor substrate attached to the lower surface of the glass layer, wherein the conductive vias are electrically coupled to the multilayer filler material in one of the plurality of through-glass vias.

[0118] Example 11 includes the subject matter of Example 10 and further comprises an integrated circuit die mounted on the upper surface of the first semiconductor substrate; and an electrical path from the integrated circuit die through one of the plurality of glass through vias to the lower surface of the glass layer.

[0119] Example 12 includes the subject matter of Example 11, wherein the electrical path further extends to the solder opening on the lower surface of the second semiconductor substrate.

[0120] Example 13 includes the subject matter of Example 11, wherein the integrated circuit die is a first integrated circuit die, and a second integrated circuit die is mounted on the upper surface of the first semiconductor substrate; the first integrated circuit die is operably communicating with the second integrated circuit die; and further comprises a motherboard mounted on the lower surface of the second semiconductor substrate.

[0121] Example 14 includes the subject matter of Example 11 and further comprises a capsule material superimposed on the first integrated circuit die and the second integrated circuit die.

[0122] Example 15 includes the subject matter of Example 10, wherein the nickel and iron alloy has Fe 0.64 Ni 0.36.

[0123] Example 16 is a method comprising the steps of: creating a plurality of through holes in a glass layer having an upper and lower surface, wherein the through holes are characterized by their respective side walls; preparing an electroplating solution containing copper; immersing the glass layer in the electroplating solution to conformally plate the side walls with copper; and forming a layer of an alloy containing nickel and iron within the copper-plated side walls.

[0124] Example 17 comprises the subject matter of Example 16, further comprising the steps of: creating another electroplating solution containing the nickel and iron alloy; and forming the layer of the nickel and iron alloy within the copper-plated sidewall, the step of immersing the glass layer having the copper-plated sidewall in the other electroplating solution.

[0125] Example 18 includes the subject matter of Example 16, further comprising the steps of adding nickel atoms and iron atoms to the electroplating solution; and forming the layer of the nickel and iron alloy within the copper-plated sidewall, wherein the electroplating solution includes a pulsed electroplating method or a switched electroplating method, and the nickel atoms, the iron atoms, and the copper.

[0126] Example 19 includes the subject matter of Example 16, wherein the nickel and iron alloy has Fe0.64 Ni0.36.

[0127] Example 20 includes the subject matter of Example 16 and further comprises the steps of: polishing the upper and lower surfaces to expose the glass layer; adding a first semiconductor substrate having a redistribution layer therein to the upper surface; adding a second semiconductor substrate having a redistribution layer therein to the lower surface; mounting an integrated circuit die to the upper surface of the first semiconductor substrate; and creating at least one electrical path from the integrated circuit die through glass vias to the lower surface of the second semiconductor substrate. [Other possible items] [Item 1] A layer of glass having an upper and lower surface; A through hole is formed in the glass layer, and the through hole has a side wall; The side wall and a conformal layer of copper; and A layer of an alloy containing nickel and iron, located within the through hole and adjacent to the copper layer; Equipped with, Here, the copper layer and the alloy layer containing nickel and iron work together to provide an electrical path from the upper surface to the lower surface. Device. [Item 2] The apparatus according to item 1, wherein the nickel and iron alloy has Fe0.64 Ni0.36. [Item 3] The apparatus according to item 1, wherein the nickel and iron-containing alloy has a coefficient of thermal expansion (CTE) of 0.4 parts per million (PPM) + / - 20%. [Item 4] The apparatus according to item 1, wherein the copper layer has a thickness of 10 microns + / - 10%, and the alloy layer containing nickel and iron has a thickness of 10 microns + / - 10%. [Item 5] The aforementioned copper layer is one of several copper layers; The layer of the nickel and iron alloy is one of a plurality of layers of the nickel and iron alloy; and The apparatus according to item 1, wherein in the cross-sectional view of the through hole, the plurality of copper layers and the plurality of alloys containing nickel and iron appear alternately. [Item 6] The aforementioned copper layer is one of several copper layers; The layer of the nickel and iron alloy is one of a plurality of layers of the nickel and iron alloy; and The apparatus according to item 1, wherein in a plan view of the through hole, the plurality of copper layers and the plurality of alloys containing nickel and iron appear alternately in a concentric ring. [Item 7] The apparatus according to item 1, wherein the glass layer has a thickness in the range of 20 microns + / - 10% to 2 millimeters + / - 10%. [Item 8] Another layer of copper sandwiched within the aforementioned layer of the nickel and iron alloy; and The apparatus according to item 1, further comprising the copper layer, the nickel and iron alloy layer, and the other copper layer together providing an electrical path from the upper surface to the lower surface. [Item 9] The apparatus according to item 1, further comprising a liner layer containing titanium having a thickness of 20 nanometers + / - 5 nanometers between the copper layer and the side wall. [Item 10] A first semiconductor substrate comprising multiple dielectric layers and a redistribution layer therein; Conductive vias in the first semiconductor substrate, the conductive vias are electrically connected to a redistribution layer and are exposed on the lower surface of the first semiconductor substrate; A layer of glass is attached to the lower surface of the first semiconductor substrate, the glass layer having a plurality of glass through vias (TGVs), each TGV having a side wall; The multilayer filling material in the plurality of TGVs, wherein the multilayer filling material is characterized by a conformal copper layer and at least one layer of nickel and iron alloy on the sidewalls; A second semiconductor substrate attached to the lower surface of the glass layer; Here, the conductive via is electrically coupled to the multilayer packing material within one of the plurality of glass through vias. A package assembly comprising the following features. [Item 11] An integrated circuit die mounted on the upper surface of the first semiconductor substrate; and The package assembly according to item 10, further comprising an electrical path from the integrated circuit die through one of the plurality of glass through vias to the lower surface of the glass layer. [Item 12] The package assembly according to item 11, wherein the electrical path further extends to the solder opening on the lower surface of the second semiconductor substrate. [Item 13] The aforementioned integrated circuit die is a first integrated circuit die, A second integrated circuit die mounted on the upper surface of the first semiconductor substrate; Here, the first integrated circuit die is operably communicating with the second integrated circuit die; and The package assembly described in item 11, further comprising a motherboard mounted on the underside of the second semiconductor substrate. [Item 14] The package assembly according to item 11, further comprising a capsule material superimposed on the first integrated circuit die and the second integrated circuit die. [Item 15] The package assembly according to item 10, wherein the nickel and iron alloy has Fe0.64 Ni0.36. [Item 16] A step of generating multiple through-holes in a glass layer having an upper and lower surface, wherein each through-hole is characterized by its own side wall; The step of preparing an electroplating solution containing copper; and The steps include: immersing the glass layer in the electroplating solution to conformally plate the side walls with copper; and The step of forming a layer of alloy containing nickel and iron within the copper-plated side wall. A method for providing this. [Item 17] The step of preparing another electroplating solution containing the aforementioned nickel-iron alloy; and The step of forming the layer of the nickel and iron alloy within the copper-plated sidewall includes the step of immersing the glass layer having the copper-plated sidewall in the other electroplating solution. The method described in item 16, further comprising: [Item 18] The step of adding nickel atoms and iron atoms to the electroplating solution; and The step of forming the layer of the alloy containing nickel and iron within the copper-plated sidewall includes a pulsed plating method or a switched electroplating method, and the electroplating solution containing the nickel atoms, the iron atoms, and the copper. The method described in item 16, further comprising: [Item 19] The method according to item 16, wherein the nickel and iron alloy has Fe0.64 Ni0.36. [Item 20] A step of polishing the upper and lower surfaces in order to expose the glass layer; The step of adding a first semiconductor substrate having a redistribution layer to the upper surface; The step of adding a second semiconductor substrate having a redistribution layer to the lower surface; The step of mounting an integrated circuit die on the upper surface of the first semiconductor substrate; and The step of creating at least one electrical path from the integrated circuit die through glass vias to the underside of the second semiconductor substrate. The method described in item 16, further comprising:

Claims

1. A layer of glass having an upper and lower surface; A through hole formed in the glass layer, the through hole having a side wall; The side wall and a conformal layer of copper; and A layer of alloy containing nickel and iron located within the through hole and adjacent to the copper layer; Equipped with, Here, the copper layer and the alloy layer containing nickel and iron work together to provide an electrical path from the upper surface to the lower surface. Device.

2. The apparatus according to claim 1, wherein the nickel and iron alloy comprises Fe0.64 Ni0.

36.

3. The apparatus according to claim 1 or 2, wherein the nickel and iron alloy has a coefficient of thermal expansion (CTE) of 0.4 parts per million (PPM) ±20%.

4. The apparatus according to claim 1 or 2, wherein the copper layer has a thickness of 10 microns ± 10%, and the alloy layer containing nickel and iron has a thickness of 10 microns ± 10%.

5. The aforementioned copper layer is one of several copper layers; The layer of the nickel and iron alloy is one of a plurality of layers of the nickel and iron alloy; and The apparatus according to claim 1 or 2, wherein in the cross-sectional view of the through hole, the plurality of copper layers and the plurality of alloys containing nickel and iron appear alternately.

6. The aforementioned copper layer is one of several copper layers; The layer of the nickel and iron alloy is one of a plurality of layers of the nickel and iron alloy; and The apparatus according to claim 1 or 2, wherein in a plan view of the through hole, the plurality of copper layers and the plurality of alloys containing nickel and iron appear alternately in a concentric ring.

7. The apparatus according to claim 1 or 2, wherein the glass layer has a thickness in the range of 20 microns ±10% to 2 millimeters ±10%.

8. Another layer of copper sandwiched within the aforementioned layer of the nickel and iron alloy; and The apparatus according to claim 1 or 2, further comprising the copper layer, the nickel and iron alloy layer, and the other copper layer together providing an electrical path from the upper surface to the lower surface.

9. The apparatus according to claim 1 or 2, further comprising a liner layer containing titanium having a thickness of 20 nanometers ± 5 nanometers between the copper layer and the side wall.

10. A first semiconductor substrate comprising multiple dielectric layers and a redistribution layer therein; Conductive vias in the first semiconductor substrate, the conductive vias are electrically connected to a redistribution layer and are exposed on the lower surface of the first semiconductor substrate; A layer of glass is attached to the lower surface of the first semiconductor substrate, the glass layer having a plurality of glass through vias (TGVs), each TGV having a side wall; The multilayer filler material in the plurality of TGVs, wherein the multilayer filler material is characterized by a conformal copper layer and at least one layer of nickel and iron alloy on the sidewalls; A second semiconductor substrate attached to the lower surface of the glass layer; Here, the conductive via is electrically coupled to the multilayer packing material within one of the plurality of glass vias. A package assembly comprising the following features.

11. An integrated circuit die mounted on the upper surface of the first semiconductor substrate; and The package assembly according to claim 10, further comprising an electrical path from the integrated circuit die through one of the plurality of glass through vias to the lower surface of the glass layer.

12. The package assembly according to claim 11, wherein the electrical path further extends to the solder opening on the lower surface of the second semiconductor substrate.

13. The aforementioned integrated circuit die is a first integrated circuit die, A second integrated circuit die mounted on the upper surface of the first semiconductor substrate; Here, the first integrated circuit die is operably communicating with the second integrated circuit die; and The package assembly according to claim 11 or 12, further comprising a motherboard mounted on the lower surface of the second semiconductor substrate.

14. The package assembly according to claim 13, further comprising a capsule material superimposed on the first integrated circuit die and the second integrated circuit die.

15. The package assembly according to any one of claims 10 to 12, wherein the nickel and iron alloy comprises Fe0.64 Ni0.

36.

16. A step of generating multiple through-holes in a glass layer having an upper surface and a lower surface, wherein each through-hole is characterized by its own side wall; The step of preparing an electroplating solution containing copper; and The steps include: immersing the glass layer in the electroplating solution to conformally plate the side walls with copper; and The step of forming a layer of alloy containing nickel and iron within the copper-plated side wall. A method for providing this.

17. A step of preparing another electroplating solution containing the aforementioned nickel and the aforementioned iron alloy; and The step of forming the layer of the nickel and iron alloy within the copper-plated sidewall includes the step of immersing the glass layer having the copper-plated sidewall in the other electroplating solution. The method according to claim 16, further comprising:

18. The step of adding nickel atoms and iron atoms to the electroplating solution; and The step of forming the layer of the alloy containing nickel and iron within the copper-plated sidewall includes a pulsed plating method or a switched electroplating method, and the electroplating solution containing the nickel atoms, the iron atoms, and the copper. The method according to claim 16 or 17, further comprising:

19. The method according to claim 16 or 17, wherein the nickel and iron alloy has Fe0.64 Ni0.

36.

20. A step of polishing the upper and lower surfaces in order to expose the glass layer; The step of adding a first semiconductor substrate having a redistribution layer to the upper surface; The step of adding a second semiconductor substrate having a redistribution layer to the lower surface; The step of mounting an integrated circuit die on the upper surface of the first semiconductor substrate; and The step of creating at least one electrical path from the integrated circuit die through glass vias to the lower surface of the second semiconductor substrate. The method according to claim 16 or 17, further comprising:

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