control system

Abstract

The present invention provides a control system capable of determining whether or not a semiconductor device is in an abnormal state. [Solution] The FPGA 30 of the control system includes a delay time measurement circuit 46 (time measurement unit) that outputs a PWM (output signal) to a GDM (gate driver module, drive circuit device) that drives a SiC (semiconductor element), receives a Sync (input signal) based on the PWM from the GDM, and measures the time from when the PWM is output until the Sync is received, and a redundancy abnormality determination circuit 47 (determination unit) that determines that the SiC is in an abnormal state if the measurement result by the delay time measurement circuit 46 is outside a predetermined range of a certain period of time. When the number of occurrences of the abnormal state reaches 5 (a predetermined number of times), the redundancy abnormality determination circuit 47 determines that the abnormal state has occurred consecutively and is a redundancy abnormality, and if it determines that it is a redundancy abnormality, it outputs redundancy abnormality information indicating that it is a redundancy abnormality to the upper CPU 12a (a part separate from the determination unit).

Description

Technical Field

[0001] The present invention relates to a control system.

Background Art

[0002] Patent Document 1 discloses a technique using a gate driver, an IGBT module, or the like.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a technique such as Patent Document 1, a technique capable of determining whether a semiconductor element is in an abnormal state is desired. <​​​​​​​​​​​​​Solution 1: The control system of this solution comprises a time measurement unit that outputs an output signal to a drive circuit device that drives a semiconductor element, receives an input signal based on the output signal from the drive circuit device, and measures the time from when the output signal is output until the input signal is received, and a determination unit that determines that the semiconductor element is in an abnormal state if the measurement result by the time measurement unit is outside a predetermined range of time.

[0008] According to this solution, it is possible to determine whether or not a semiconductor element is in an abnormal state by comparing the time difference between the output signal and the input signal with a predetermined fixed time.

[0009] Solution 2: The control system of this solution is characterized in that, in any of the solutions described above, the determination unit determines that the occurrence of the abnormal state is a redundant abnormality in which the abnormal state has occurred consecutively when the number of occurrences of the abnormal state reaches a predetermined number of times.

[0010] According to this solution, the determination unit determines that a condition is redundant when the number of occurrences of an abnormal state reaches a predetermined number of times. Therefore, cases where an abnormal state is determined to occur only once by chance due to false detection, etc., can be excluded from the determination of a redundant abnormality.

[0011] Solution 3: The control system of this solution is characterized in that, in any of the solutions described above, when the determination unit determines that there is a redundancy anomaly, it outputs redundancy anomaly information indicating that there is a redundancy anomaly to a part other than the determination unit.

[0012] According to this solution, if the determination unit determines that a redundancy anomaly has occurred, it outputs the redundancy anomaly information to a part separate from the determination unit, so that the other part can use the redundancy anomaly information to perform control.

[0013] Solution 4: The control system of this solution is a control system characterized in that, in any of the solutions described above, the determination unit does not determine the abnormal state when the current state of the semiconductor element is in a special state.

[0014] According to this solution, the determination unit does not determine an abnormal state when the current state of the semiconductor element is in a special state. Therefore, compared to a control method that uniformly determines an abnormal state, the reliability of the determination can be improved.

[0015] Solution 5: The control system of this solution is characterized in that, in any of the solutions described above, the number of occurrences of the abnormal state is initialized when the system transitions from the abnormal state to a normal state that is not an abnormal state.

[0016] According to this solution, the number of occurrences of an abnormal state is reset when the system transitions from an abnormal state to a normal state. Therefore, when the system transitions to a normal state, the redundancy abnormality check can be restarted from the beginning.

[0017] Solution 6: The control system of this solution is characterized in that, in any of the solutions described above, the number of occurrences of the abnormal state is not initialized if the abnormal state is not determined.

[0018] According to this solution, the number of occurrences of an abnormal state is not reset if an abnormal state is not detected. Therefore, even if an abnormal state is not detected by chance only once due to a false detection or other reason, the redundancy abnormality detection can be continued.

[0019] Solution 7: The control system of this solution is characterized in that, in any of the solutions described above, there are multiple semiconductor elements, and the redundant abnormal information is information that aggregates the states of the multiple semiconductor elements.

[0020] According to this solution, since the redundant abnormal information includes the information aggregating the information of a plurality of semiconductor elements, sufficient information can be output even when the number of terminals for outputting information is small.

[0021] Solution 8: In the control system of this solution, in any of the above solutions, there are a plurality of the semiconductor elements, and the redundant abnormal information is information including all the states of the plurality of semiconductor elements, which is a control system characterized thereby.

[0022] According to this solution, since the redundant abnormal information includes all the information of a plurality of semiconductor elements, all the information of the plurality of semiconductor elements can be output.

Advantages of the Invention

[0023] According to the present invention, it is possible to determine whether a semiconductor element is in an abnormal state.

Brief Description of the Drawings

[0024] [Figure 1] It is a diagram showing the control system 10 of the embodiment. [Figure 2] It is a diagram showing the configuration of the power switching device. [Figure 3] It is a diagram showing the outline of the control system 10. [Figure 4] It is a diagram showing the first configuration example (transmission of maximum value of redundant abnormal information) of the three-parallel feedback control. [Figure 5] It is a diagram showing the second configuration example (straight transmission of redundant abnormal information) of the three-parallel feedback control. [Figure 6] It is a diagram showing the details of the control system 10. [Figure 7] It is a diagram showing the configuration of the internal circuit of the FPGA. [Figure 8] It is a diagram showing the details of the delay detection circuit. [Figure 9] It is a diagram showing the details of the delay time measurement circuit. [Figure 10] It is a diagram showing the details of the redundant abnormality determination circuit. [Figure 11] This diagram shows the control method for the control valid signal. [Figure 12] This diagram shows the details of the maximum value determination circuit. [Modes for carrying out the invention]

[0025] Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows a control system 10 of an embodiment. Figure 1(A) shows the overall configuration of the control system 10, and Figure 1(B) shows the dotted line portion of Figure 1(A) and the details of the circuits connected thereto. As shown in Figure 1(A), the control system 10 comprises a power supply 11, a control board 12, three-phase power switching devices 13, 14, and 15, three coils 16, and a motor 17. The three-phase power switching devices 13, 14, and 15 are each composed of two power switching devices shown above and below.

[0026] In the control system 10, the control board 12 operates using power from the power supply 11, and the control board 12 drives the motor 17 by gate-controlling three-phase power switching devices 13, 14, and 15, thereby driving the motor 17 with three coils 16. Although the control system 10 drives the motor 17, it may also be a circuit that drives devices other than the motor 17.

[0027] In Figure 1(A), the dotted line portion usually only requires one power switching device, but if the current is insufficient, multiple power switching devices may be connected in parallel. The control system 10 of this embodiment can be used when connecting multiple power switching devices in parallel in such a situation.

[0028] As shown in Figure 1(B), SiC1, SiC2, and SiC3, which function as power switching devices, are connected in parallel. SiC (SiC device) is a power semiconductor (semiconductor element, power device) that uses silicon carbide semiconductor, which is a compound.

[0029] Each SiC is connected to a GDM (Gate Driver Module), and the GDM is connected to an FPGA (Field Programmable Gate Array, time measurement unit, judgment unit) 30. Specifically, SiC1 is connected to the first GDM 20a, and the first GDM 20a is connected to the FPGA 30. SiC2 is connected to the second GDM 20b, and the second GDM 20b is connected to the FPGA 30. SiC3 is connected to the third GDM 20c, and the third GDM 20c is connected to the FPGA 30.

[0030] The FPGA 30 receives PWM input from the control board 12 (higher-level control unit, higher-level CPU). FPGA30 outputs PWM1 to the first GDM20a, and Sync1 is input from the first GDM20a. FPGA30 outputs PWM2 to the second GDM20b, and Sync2 is input from the second GDM20b. FPGA30 outputs PWM3 to the third GDM20c, and Sync3 is input from the third GDM20c. PWM (Pulse Width Modulation) is a signal that uses a square wave pulse to control electrical components, etc. Sync (Synchronization) is a signal used to synchronize the operation timing between various devices (synchronization signal).

[0031] The first GDM20a outputs Vgs1 to SiC1, and Vdsps1 is input from SiC1. The second GDM20b outputs Vgs2 to SiC2, and Vdsps2 is input from SiC2. The third GDM20c outputs Vgs3 to SiC3, and Vdsps3 is input from SiC3. SiC1, SiC2, and SiC3 output Ids1, Ids2, and Ids3, respectively. Vgs is the gate-source voltage. Vdsps is the voltage between the driver source and power source of the SiC4 terminal device. Ids is the current flowing from the drain to the source.

[0032] Although not specifically shown in the diagram, Ids1 output by SiC1 is also input to the first GDM20a, Ids2 output by SiC2 is also input to the second GDM20b, and Ids3 output by SiC3 is also input to the third GDM20c. Each GDM is equipped with a Sync detection circuit (first Sync detection circuit to third Sync detection circuit), which detects Sync based on Vdsps (potential difference between the driver source and the power source) and Ids input to the Sync detection circuit, and can output Sync1, 2, and 3 to FPGA30.

[0033] The circuit that transmits PWM to FPGA30, along with the first GDM20a, second GDM20b, and third GDM20c, can be implemented as part of the control board 12's functions. On the other hand, FPGA30 can be implemented as a separate function from the control board 12.

[0034] Figure 2 shows the configuration of a power switching device. In this embodiment, a four-terminal power switching device is used. For example, the SCT3040KR (manufactured by ROHM Co., Ltd.) can be used as the four-terminal power switching device. The four terminals are drain T1, gate T2, driver source T3, and power source T4. The potential difference (Vdsps, etc.) between the driver source T3 and power source T4 can be used as a control element.

[0035] Generally, the Ls of power switching devices ranges from a few nH to over ten nH, and dI D When / dt reaches several A / ns, the electromotive force V exceeds 10V. L Vdsps is V L By making the "Sync detection circuit" highly sensitive using the same signal, it becomes possible to detect the initial operation of Id. To balance the current division when power switching devices are connected in parallel, each signal can be controlled to match the timing of the Vdsps signal.

[0036] Figure 3 shows an overview of the control system 10. As shown in Figure 3(A), a gate signal (e.g., PWM) is output from the FPGA to the GDM at a constant period, and a Sync signal corresponding to the gate signal is input to the FPGA. When the SiC is in a normal state, the Sync signal is input to the FPGA within a certain time range from the output of the gate signal. On the other hand, when the SiC is in an abnormal state, the Sync signal is input to the FPGA outside of that certain time range from the output of the gate signal. The control system 10 determines whether the SiC is in a normal or abnormal state by monitoring the delay time of the Sync signal.

[0037] Next, we will explain the control flow for each gate signal from (1) to (10). In the gate signal (1), the Sync signal is input to FPGA30 within a certain time range. Therefore, the abnormal state determination is "normal state", the redundant abnormality consecutive count counter (number of times the abnormal state has occurred) is "0", and the redundant abnormality determination is Low (not redundant abnormal). Note that, except for the gate signal (6), the control enable signal is High. In the gate signal of (2), the Sync signal is input to FPGA30 outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "1", and the redundant abnormal state determination is Low. In the gate signal of (3), the Sync signal is input to FPGA30 within a certain time range. Therefore, the abnormal state determination is "normal state", the redundant abnormal consecutive count counter is "0", and the redundant abnormal state determination is Low. The redundant abnormal consecutive count counter (number of occurrences of abnormal state) is initialized when the system transitions from an abnormal state to a normal state.

[0038] In the gate signal of (4), the Sync signal is input to FPGA30 outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "1", and the redundant abnormal state determination is Low. In the gate signal (5), the Sync signal is input to FPGA30 outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "2", and the redundant abnormal determination is Low. In the gate signal of (6), the Sync signal is input to FPGA30 outside the specified time range, but since the control enable signal is Low, no abnormal condition is detected. Thus, FPGA30 does not detect abnormal conditions when the SiC is under low current (the current state is a special state, and the control enable signal is Low) (detection unit). In addition, the redundant abnormal consecutive count counter (number of abnormal conditions) is not initialized if no abnormal condition is detected.

[0039] In the gate signal of (7), the Sync signal is input to the FPGA outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "3 times", and the redundant abnormal state determination is Low. In the gate signal (8), the Sync signal is input to the FPGA outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "4 times", and the redundant abnormal state determination is Low. In the gate signal of (9), the Sync signal is input to the FPGA outside of the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "5 times", and the redundant abnormal state determination is High. In gate signal (10), the Sync signal is input to the FPGA outside the specified time range. Therefore, the abnormal state determination is "abnormal state". In this case, the redundant abnormal consecutive count counter may be updated to "6 times" or remain at "5 times". The redundant abnormal state determination is High.

[0040] Figure 3(B) shows an example of how to determine an abnormal state. As shown in the upper and middle gate signal and Sync signal waveforms of Figure 3(B), when the SiC is functioning correctly, a Sync signal is input from the GDM to the FPGA within a certain time range (with a certain delay time) in response to the gate signal output from the FPGA to the GDM (see arrow X1). However, increasing the input capacitance increases the delay time of the Sync signal relative to the gate signal (see arrow X2). Also, as the SiC temperature rises, the delay time of the Sync signal relative to the gate signal decreases (see arrow X3).

[0041] The Sync abnormal state determination range is represented by the waveform shown in the lower part of Figure 3(B). When the Sync signal rises while this waveform is Low, it is determined to be in a normal state, and when the Sync signal rises while this waveform is High, it is determined to be in an abnormal state. In other words, the FPGA determines that the SiC is in a normal state when the Sync signal is input in range Y1 (arrow X1), and determines that the SiC is in an abnormal state when the Sync signal is input in range Y2 or range Y3 (arrows X2 and X3).

[0042] Next, two configuration examples of the control system 10 will be described. The control system 10 can adopt one of the following configuration examples.

[0043] Figure 4 shows a first example of a 3-parallel feedback control configuration (maximum value transmission of redundant abnormal information). In the first configuration example, the upper-level CPU 12a and FPGA 30 are connected, and FPGA 30 is connected to each GDM. There are "U-phase," "V-phase," and "W-phase" GDMs, and each phase has "1st," "2nd," and "3rd" GDMs. In addition, each GDM is described including the high-side (H: Highside, Hside) and low-side (L: Lowside, Lside).

[0044] For example, the "U-phase 1st GDM H / L" (20-1) includes two gate driver modules: one for driving the first row of high-side SiC (UH1) for the U-phase, and another for driving the first row of low-side SiC (UL1) for the U-phase. The "U-phase 2nd GDM H / L" (20-2) also includes two gate driver modules: one for driving the second row of high-side SiC (UH2) for the U-phase, and another for driving the second row of low-side SiC (UL2) for the U-phase. Furthermore, the "U-phase 3rd GDM H / L" (20-3) includes two gate driver modules: one for driving the third row of high-side SiC (UH3) for the U-phase, and another for driving the third row of low-side SiC (UL3) for the U-phase. Furthermore, this relationship also applies to the "V-phase" components: "V-phase 1st GDM H / L" (20-4), "V-phase 2nd GDM H / L" (20-5), and "V-phase 3rd GDM H / L" (20-6), as well as the "W-phase" components: "W-phase 1st GDM H / L" (20-7), "W-phase 2nd GDM H / L" (20-8), and "W-phase 3rd GDM H / L" (20-9). Therefore, there are a total of 18 GDMs (9 (20-1 to 20-9) × 2 (high-side and low-side)), and correspondingly, there are also 18 SiCs.

[0045] The higher-end CPU 12a outputs PWM and stop command information (2 bits) for 2x3 phases (6 phases in total) of high-side and low-side PWM to FPGA 30, and FPGA 30 inputs redundant error information (2 bits). FPGA30 outputs PWM (PWMU1~3 H / L, PWMV1~3 H / L, PWMW1~3 H / L) to each GDM20-1~20-9, and Sync (SyncU1~3 H / L, SyncV1~3 H / L, SyncW1~3 H / L) is input from each GDM20-1~20-9.

[0046] In the first configuration example, a maximum redundancy anomaly information transmission method is employed. This method transmits the maximum value of the number of redundancies on each side of each phase. In this embodiment, the 18 SiCs are divided into 6 groups, with 3 SiCs arranged in each group. The first group G1 is the U-phase H-side group (UH1, UH2, UH3), the second group G2 is the U-phase L-side group (UL1, UL2, UL3), the third group G3 is the V-phase H-side group (VH1, VH2, VH3), the fourth group G4 is the V-phase L-side group (VL1, VL2, VL3), the fifth group G5 is the W-phase H-side group (WH1, WH2, WH3), and the sixth group G6 is the W-phase L-side group (WL1, WL2, WL3). The maximum value of the number of redundancies is then the maximum value of the 6 groups.

[0047] For example, if all SiCs are in a normal state, the number of redundant anomalies will be "0". Also, if one SiC in group 1 G1 is in an abnormal state and the SiCs in the other groups are in a normal state, the number of redundant anomalies will be "1". Furthermore, if one SiC in group 1 G1 is in an abnormal state, two SiCs in group 2 G2 are in an abnormal state, and the SiCs in the other groups are in a normal state, the number of redundant anomalies will be "2". Also, if one SiC in group 1 G1 is in an abnormal state, two SiCs in group 2 G2 are in an abnormal state, three SiCs in group 3 G3 are in an abnormal state, and the SiCs in the other groups are in a normal state, the number of redundant anomalies will be "3". Furthermore, if all SiCs are in an abnormal state, the number of redundant anomalies will be "3".

[0048] The number of redundant anomalies is then stored in the redundancy anomaly information and output to the upper CPU 12a. The redundancy anomaly information is 2 bits of information, and the content of the information is as follows: "00: Normal, 01: 1 device anomaly, 10: 2 devices anomaly, 11: 3 devices anomaly". Normal indicates that all SiCs are in a normal state (redundancy anomaly count = 0), 1 device anomaly indicates that one SiC is redundantly anomaly (redundancy anomaly count = 1), 2 device anomalies indicate that two SiCs are redundantly anomaly (redundancy anomaly count = 2), and 3 device anomalies indicate that three SiCs are redundantly anomaly (redundancy anomaly count = 3).

[0049] Thus, the redundancy anomaly information in the first configuration example is information that aggregates the states of multiple SiCs.

[0050] The stop command information is 2 bits of information, and the content of the information is as follows: "00: No stop, 01: Stop 1 device, 10: Stop 2 devices, 11: Stop 3 devices". No stop means that the SiC will not be stopped, 1 device stop means that one SiC will be stopped, 2 device stop means that two SiCs will be stopped, and 3 device stop means that three SiCs will be stopped.

[0051] Figure 5 shows a second example of a 3-parallel feedback control configuration (straight transmission of redundant abnormal information). The second configuration example differs from the first configuration example only in the section on redundant error information. Since the other parts are identical to the first configuration example, their explanation is omitted. The redundancy anomaly information is 18 bits of information, and the content of the information is "UH1 / 2 / 3, UL1 / 2 / 3, VH1 / 2 / 3, VL1 / 2 / 3, WH1 / 2 / 3, WL1 / 2 / 3". For example, if "UH1" is "0", it means that the first column of SiC on the high side for the U phase is normal, and if "UH1" is "1", it means that the first column of SiC on the high side for the U phase is redundant and anomaly. Similarly, if "UH2" is "0", it means that the second column of SiC on the high side for the U phase is normal, and if "UH2" is "1", it means that the first column of SiC on the high side for the U phase is redundant and anomaly. Furthermore, if "UH3" is "0", it means that the third column of SiC on the high side for the U phase is normal, and if "UH3" is "1", it means that the first column of SiC on the high side for the U phase is redundant and anomaly. The same applies to "UL", "VH", "VL", "WH", and "WL".

[0052] Thus, the redundancy anomaly information in the second configuration example includes information that encompasses the states of all multiple SiCs.

[0053] Figure 6 shows the details of the control system 10. The higher-end CPU 12a outputs 2x3 phases of PWM (PWMU phase Hside, PWMU phase Lside, PWMV phase Hside, PWMV phase Lside, PWMW phase Hside, PWMW phase Lside) to the FPGA 30.

[0054] In FPGA30, each PWM input from the higher-level CPU12a is input to the circuit corresponding to each phase, each circuit outputs a PWM to each GDM, and each GDM inputs a Sync to each circuit. Specifically, it is as follows: The U-phase Hside circuit 40-1 receives the PWMU-phase Hside as input, outputs PWMU-phase Hside 1, 2, and 3 to the GDM (1st to 3rd GDM H for U-phase in Figure 5), and receives SyncU-phase Hside 1, 2, and 3 as input. The U-phase Lside circuit 40-2 receives the PWMU-phase Lside as input, outputs PWMU-phase Lside 1, 2, and 3 to the GDM (the 1st to 3rd GDM L for the U-phase in Figure 5), and receives SyncU-phase Lside 1, 2, and 3 as input.

[0055] The V-phase H-side circuit 40-3 receives the PWM V-phase H-side input, outputs PWM V-phase H-side 1, 2, and 3 to the GDM (V-phase 1st to 3rd GDM H in Figure 5), and receives the Sync V-phase H-side 1, 2, and 3 input. The V-phase Lside circuit 40-4 receives the PWM V-phase Lside input, outputs PWM V-phase Lside 1, 2, and 3 to the GDM (V-phase 1st to 3rd GDM L in Figure 5), and receives the Sync V-phase Lside 1, 2, and 3 input.

[0056] The W-phase H-side circuit 40-5 receives the PWM W-phase H-side input, outputs PWM W-phase H-side 1, 2, and 3 to the GDM (the 1st to 3rd GDM H for the W-phase in Figure 5), and receives the Sync W-phase H-side 1, 2, and 3 inputs. The W-phase Lside circuit 40-6 receives the PWMW-phase Lside input, outputs PWMW-phase Lside 1, 2, and 3 to the GDM (the 1st to 3rd GDM L for the W phase in Figure 5), and receives SyncW-phase Lside 1, 2, and 3 as inputs.

[0057] The initial value for the maximum redundancy abnormality is "00". The maximum redundancy abnormality can be calculated by processing in the following order: "U-phase H-side circuit 40-1" → "U-phase L-side circuit 40-2" → "V-phase H-side circuit 40-3" → "V-phase L-side circuit 40-4" → "W-phase H-side circuit 40-5" → "W-phase L-side circuit 40-6". Stop designation information is transmitted to each circuit.

[0058] Figure 7 shows the internal circuit configuration of the FPGA. The internal circuit in Figure 7 is the same as the circuits included in "U-phase H-side circuit 40-1", "U-phase L-side circuit 40-2", "V-phase H-side circuit 40-3", "V-phase L-side circuit 40-4", "W-phase H-side circuit 40-5", and "W-phase L-side circuit 40-6" in Figure 6, and can be considered a common circuit. Because it is a common circuit, "PWM1, 2, 3", "Sync1, 2, 3", "1st to 3rd GDM", etc. are indicated with common symbols.

[0059] In reality, if it is "U-phase Hside circuit 40-1", then "PWM1, 2, 3" becomes "PWMU-phase Hside1, 2, 3", "Sync1, 2, 3" becomes "SyncU-phase Hside1, 2, 3", "1st to 3rd GDM" becomes "U-phase 1st to 3rd GDM H", "Id" becomes "IdU-phase Hside", "SiC1, 2, 3" becomes "UH1, 2, 3", and "Redundancy Anomaly Judgment No. 1, 2, 3" becomes "Redundancy Anomaly Judgment No. 1, 2, 3 for U-phase Hside". These points are also true for "U-phase Lside circuit 40-2" to "W-phase Lside circuit 40-6", and for the following diagrams. Also, although SiC1, 2, and 3 are shown vertically for convenience, they are actually connected in parallel (see Figure 1).

[0060] FPGA30 (for example, U-phase H-side circuit 40-1) detects PWM with filter detection circuit 41 and outputs PWM0, generates PWM1, 2, and 3 with first delay circuit 42a, second delay circuit 42b, and third delay circuit 42c, and outputs PWM1, 2, and 3 to first GDM20a, second GDM20b, and third GDM20c.

[0061] Furthermore, Sync1, 2, and 3 are input to FPGA30 from the first GDM20a, second GDM20b, and third GDM20c, respectively, and feedback control is performed in the time difference measurement circuit 44, the delay time determination circuit 45, and the three delay circuits (first delay circuit 42a, second delay circuit 42b, and third delay circuit 42c). The time difference measurement circuit 44, the delay time determination circuit 45, and the three delay circuits are circuits that delay PWM1, 2, and 3 (output signals) based on Sync1, 2, and 3 to suppress phase variations of the gate driver and SiC and to correctly synchronize the gate driver and SiC, but these circuits can also be omitted.

[0062] Furthermore, in FPGA 30, PWM1, 2, 3 and Sync1, 2, 3 are input to the delay time measurement circuit 46, and redundancy abnormality detection circuit 47 performs redundancy abnormality detection. Note that a 250MHz 4-phase shift PLL is used in the time difference measurement circuit 44 and the delay time measurement circuit 46.

[0063] A current sensor is placed on the SiC, and the SiC current (Id) is input to the control effective range detection circuit 20d. The control effective range detection circuit 20d determines the current value, and the determination result is output as a control effective signal, which is input to the FPGA 30's time difference measurement circuit 44 and delay time measurement circuit 46. The control effective range detection circuit 20d compares a preset minimum current value with the value of Id, and if the preset minimum current value ≤ the value of Id (high current), it outputs the control effective signal as High, and if the minimum current value > the value of Id (low current), it outputs the control effective signal as Low. The control effective range detection circuit 20d can be implemented at any point in the system.

[0064] The redundancy anomaly detection circuit 47 performs a determination regarding redundancy anomalies, and redundancy anomaly determinations No. 1, 2, and 3 are output to the stop detection circuit 43. Redundancy anomaly determination No. 1 indicates whether the first column of SiC is normal or abnormal, redundancy anomaly determination No. 2 indicates whether the second column of SiC is normal or abnormal, and redundancy anomaly determination No. 3 indicates whether the third column of SiC is normal or abnormal. Redundancy anomaly determinations No. 1, 2, and 3 are, for example, 1-bit information, which can be set to "0: normal, 1: abnormal". The redundancy anomaly detection circuit 47 also outputs redundancy anomaly information (2 bits = red0 / 1 bit) to the upper CPU 12a based on redundancy anomaly determinations No. 1, 2, and 3.

[0065] The upper-level CPU 12a outputs PWM to FPGA 30 and, if necessary, outputs stop command information (2 bits = cpu0 / 1 bit) to the stop determination circuit 43 of FPGA 30.

[0066] Figure 8 shows the details of the delay detection circuit. Figure 8(A) shows the circuit configuration, and Figure 8(B) shows the timing charts for each signal. Note that the delay detection circuit may be included in the delay time measurement circuit, or it may be a separate circuit from the delay time measurement circuit.

[0067] As shown in Figure 8(A), the delay detection circuit is a circuit that receives the rising edge signals of PWM1, 2, 3, Sync1, 2, 3, and PWM0 and outputs a delayed signal. When PWM1 is input, Sync1 is input; when PWM2 is input, Sync2 is input; and when PWM3 is input, Sync3 is input.

[0068] For example, when PWM1 and Sync1 are input to the delay detection circuit, PWM1 and Sync1 are input to the clock portion of the upper and lower flip-flop circuits, respectively. Also, the rising edge of PWM0 is input as a clear signal to the upper and lower flip-flop circuits. Then, data A is output from the upper flip-flop circuit and data B is output from the lower flip-flop circuit, and by inputting the inverted data (negated data) of data A and data B into the AND circuit, a delay signal is output.

[0069] As shown in Figure 8(B), PWM1, 2, and 3 rise first, followed by Sync1, 2, and 3. In this case, when the logical AND of the inverted data of data A and data B is taken, only the portion where data A is High and data B is Low becomes High, and this is used as the length of the delay time (the length from the rising edge of data A to the rising edge of data B), and a delay signal is output.

[0070] Figure 9 shows the details of the delay time measurement circuit. Figure 9(A) shows the circuit configuration, Figure 9(B) shows the timing charts for each signal in the first example, and Figure 9(C) shows the timing charts for each signal in the second example. As shown in Figure 9(A), the delay time measurement circuit 46 is a circuit that receives a delay signal and a clock signal as inputs and outputs the delay time. The delay time measurement circuit 46 receives the delay signal shown in Figure 8, controls counters 0 to 3 with CLK0 to CLK3 generated by the PLL, and adds data 0 to data 3 using an adder circuit to measure the delay time. In addition, the delay time measurement circuit 46 uses a 250MHz 4-phase shift PLL to measure (decompose) the phase difference pulses in 1ns time.

[0071] The PLL utilizes a function (circuit) built into the FPGA. By using the PLL, the clock is increased to 250ns and a 4-phase shift is performed. This allows for the generation of a continuous clock waveform at 250MHz. CLK0 to CLK3 are waveforms shifted by 90 degrees, with CLK1 shifted by 90 degrees relative to CLK0, CLK2 shifted by 90 degrees relative to CLK1, CLK3 shifted by 90 degrees relative to CLK2, and CLK0 shifted by 90 degrees relative to CLK3. Since 250MHz corresponds to 4ns, a 90-degree shift means that each clock has a 1ns shift.

[0072] Each vertical line in Figure 9(B)(C) corresponds to 1 ns. As shown in Figure 9(B), assume that the waveform of the delay signal is high for only a short time. In this case, since the waveform of the delay signal is high only when CLK1 is high, counter 1 corresponding to CLK1 is set to 1. After that, the waveform of the delay signal becomes low, and this state continues. The values ​​counted by each counter are added together in the final adder circuit. As a result, in the example in Figure 9(B), the delay time is 1 (ns).

[0073] As shown in Figure 9(C), assume that the waveform of the delayed signal remains high for a longer period than in Figure 9(B). In this case, since the waveform of the delayed signal is high for all of CLK0 to CLK3, counters 0 to 3 corresponding to CLK0 to CLK3 count accordingly. Specifically, counter 0 corresponding to CLK0 counts 4, counter 1 corresponding to CLK1 counts 4, counter 2 corresponding to CLK2 counts 5, and counter 3 corresponding to CLK3 counts 4. After that, the waveform of the delayed signal becomes low, and this state continues. The values ​​counted by each counter are added together in the final adder circuit. Thus, in the example in Figure 9(C), the delay time is 4 + 4 + 5 + 4 = 17 (ns). Note that each counter counts up when its own clock pulse becomes high and the input signal is high.

[0074] Thus, the delay detection circuit (Figure 8) and the delay time measurement circuit (Figure 9) measure the time from when the FPGA 30 outputs a PWM (output signal) to when the GDM (drive circuit device) that drives the SiC (semiconductor element) inputs a Sync (input signal) based on the PWM from the GDM to the FPGA 30 (time measurement unit).

[0075] Figure 10 shows the details of the redundant anomaly detection circuit. Figure 10(A) shows the circuit configuration, and Figure 10(B) shows the timing chart for each signal. Note that the numbers in parentheses in Figure 10(A) correspond to the numbers in parentheses in Figure 10(B). As shown in Figure 10(A), the redundant anomaly detection circuit 47 is a circuit that receives inputs for delay time, threshold L, threshold H, delay signal, consecutive count, and anomaly release, and outputs redundant anomaly detection Nos. 1, 2, and 3. In the figure, thick lines indicate information of multiple bits, and thin lines indicate information of one bit. Also, the anomaly release input may not be provided.

[0076] When a delay time is input to the redundancy anomaly detection circuit, it is compared with a threshold L (comparison L circuit) and with a threshold H (comparison H circuit). If the delay time is less than the threshold L, or if the delay time is greater than the threshold H, the result of each comparison circuit becomes 1. The two comparison results are input to the OR circuit, and the result of the OR circuit (2) is input as is to the upper OR circuit, and the inverted data is input to the lower OR circuit.

[0077] Furthermore, when a delay signal is input to the redundancy anomaly detection circuit, after the delay signal is delayed (delay circuit), the falling edge of the delay signal is detected (falling edge detection circuit), and the result of the falling edge detection (1) is input to the upper and lower logical AND circuits. The result of the upper logical AND circuit (4) is input to the counter circuit that manages the redundancy anomaly consecutive counter. In the next comparison circuit, the value of the redundancy anomaly consecutive counter (5) is compared with the number of consecutive occurrences, and if the redundancy anomaly consecutive counter ≥ the number of consecutive occurrences, 1 is stored in the hold circuit. The information stored in the hold circuit (6) is output as redundancy anomaly determination No. 1, 2, and 3. In this embodiment, the number of consecutive occurrences is set to 5, but it may be 2 to 4, or 6 or more. Note that when the second configuration example shown in Figure 5 (straight transmission of redundancy anomaly information) is adopted, redundancy anomaly determination No. 1, 2, and 3 are output to the higher-level CPU.

[0078] The delay time at the top of Figure 10(A) is generated based on the delay signal, as shown in Figure 9(A). However, since this delay time passes through the adder circuit in Figure 9(A), the L / H comparison circuit, OR circuit, AND circuit in Figure 10(A), etc., a certain amount of delay is expected between the output of "Counter 0 / 1 / 2 / 3" in Figure 9(A) and the input of "Counter Circuit (Redundant Abnormal Consecutive Count Counter)" in Figure 10(A). On the other hand, the delay signal in Figure 10(A) is input at the same timing as in Figure 9(A), so no delay is expected. In order to synchronize the delay time and the timing of the delay signal, the delay circuit to which the delay signal in Figure 10(A) is input is a circuit that delays the delay signal considering the delay time caused by the comparison circuit L / H, OR circuit, AND circuit, etc. in Figure 10(A). Note that the delay time of the delay circuit in Figure 10(A) varies depending on the circuit configuration, so it can be set to any desired time. If the circuit configuration does not cause any delay, it is also possible to omit the delay circuit in Figure 10(A).

[0079] On the other hand, the result of the lower AND circuit (3) and the error clear are input to the OR circuit and used as data to clear the value of the redundant error continuous counter. The error clear is also used as data to clear the value of the hold circuit. The error clear can be output to the FPGA by the higher-level CPU at any time (for example, when the value of the hold circuit is reset).

[0080] As shown in Figure 10(B), when a PWM signal is output from the FPGA, a Sync signal is input to the FPGA. This generates a delayed signal pulse. The delay time is the time from the rising edge of the delayed signal to the rising edge of the delayed signal. (1) rises on the falling edge of the delayed signal. If (1) is High and (2) is Low, it is a normal state, so (3) becomes High and the redundancy error consecutive count counter is reset (0 (=n0)). On the other hand, if (1) is High and (2) is High, it is an abnormal state, so (4) becomes High and the redundancy error consecutive count counter is incremented. When the redundancy error consecutive count counter (5) reaches "5 (=n5)", the redundancy error judgments No. 1, 2, and 3 (6) corresponding to the SiC determined to be redundant become High. The momentary Low state of (2) is due to the PWM rising edge resetting the signal.

[0081] Thus, the redundant anomaly detection circuit (Figure 10) determines that the SiC is in an abnormal state if the delay time (measurement result by the time measurement unit) is outside a predetermined range of time (determination unit). Furthermore, the redundant anomaly detection circuit (Figure 10) determines that if the number of occurrences of the abnormal state reaches 5 (a predetermined number of times), it is a redundant anomaly where the abnormal state has occurred consecutively (determination unit).

[0082] In the control system 10 of this embodiment, when the SiC is functioning normally, the Sync delay time relative to the PWM is approximately 115 ns. Therefore, the range of normal operation is set to be the delay time plus or minus 5 ns. Within a predetermined time range, this can be 110 ns to 120 ns, and outside this predetermined time range, it can be 109 ns or less, or 121 ns or more. These values ​​are merely examples and can be changed as appropriate according to the system specifications. Whether the system is within or outside the predetermined time range can be determined by setting threshold values ​​L and H to values ​​corresponding to the predetermined time range. Threshold values ​​L and H realize the waveform of the Sync abnormal state determination range shown in Figure 3(B). The reason why the waveform of the first period in Figure 10(B)(2) is not the same as the waveform shown in Figure 3(B) is that the Sync is within the predetermined time range (the SiC is functioning normally), so the data in (2) becomes 0 in the first OR circuit.

[0083] Figure 11 shows the control method for the control enable signal. Figure 11(A) shows the first method, and Figure 11(B) shows the second method. Either method may be adopted. As shown in Figure 11(A), the first method involves inputting the control enable signal to the delay detection circuit. In the first method, the control enable signal can be input to the part of the delay detection circuit (see Figure 8) where the rising edge of PWM0 is input. Specifically, the inverted data of the rising edge of PWM0 and the control enable signal is input to the OR circuit. As a result, when the control enable signal is low (when the SiC is low power), the delay signal is not output, and consequently, abnormal condition detection is not performed.

[0084] As shown in Figure 11(B), the second method involves inputting the control enable signal to the redundant anomaly detection circuit. In the second method, the control enable signal can be input to the upper and lower AND gates of the redundant anomaly detection circuit (see Figure 10). As a result, when the control enable signal is low (when the SiC is low power), the redundant anomaly consecutive count counter is not incremented, and consequently, the anomaly state is not detected.

[0085] Figure 12 shows the details of the maximum value determination circuit. Figure 12(A) shows the circuit configuration, and Figure 12(B) shows the processing flow. Note that the maximum value determination circuit may be included in the redundant anomaly detection circuit, or it may be a separate circuit from the redundant anomaly detection circuit.

[0086] As shown in Figure 12(A), the maximum value determination circuit is a circuit that receives redundancy anomaly determinations No. 1, 2, and 3, and an input value (initial value is 00), and outputs an output value (ultimately redundancy anomaly information).

[0087] In the first two adder circuits, the redundancy anomaly detections No. 1, 2, and 3 are added together, and a 2-bit "add" value is output. An example of the "add" output is shown below. (Example 1) Redundancy Anomaly Detection No. 1 = 0 Redundancy abnormality judgment No2=0 Redundancy abnormality judgment No.3=0 counter=00

[0088] (Example 2) Redundancy Anomaly Detection No. 1 = 0 Redundancy abnormality judgment No2=1 Redundancy abnormality judgment No.3=0 add=01

[0089] (Example 3) Redundancy Anomaly Detection No. 1 = 1 Redundancy abnormality judgment No2=0 Redundancy abnormality judgment No.3=1 add=10

[0090] (Example 4) Redundancy Anomaly Detection No. 1 = 1 Redundancy abnormality judgment No2=1 Redundancy abnormality judgment No.3=1 add=11

[0091] The value `add` is stored in data A, and the input value is stored in data B. A comparison circuit then compares data A and data B. If data A > data B, the comparison result is 0, and if not, the comparison result is 1. The comparison result, `add`, and the input value are input to the multiplexer. If the comparison result is 0 (A > B), `add` is selected as the output value, and if the comparison result is 1 (otherwise), the input value is selected as the output value.

[0092] Then, as shown in Figure 12(B), this process is carried out in the following order: "U-phase H-side circuit 40-1" → "U-phase L-side circuit 40-2" → "V-phase H-side circuit 40-3" → "V-phase L-side circuit 40-4" → "W-phase H-side circuit 40-5" → "W-phase L-side circuit 40-6". The initial value of the input (initial value of the maximum value for redundancy error judgment) is "00", but the input value from the second time onward becomes the output value of the previous process, and finally, 2 bits of redundancy error information (red0 / 1 bit) is generated and output to the higher-level CPU.

[0093] Note that the maximum value determination circuit shown in Figure 12 is necessary when adopting the first configuration example (redundant anomaly information maximum value transmission) shown in Figure 4, but is not necessary when adopting the second configuration example (redundant anomaly information straight transmission) shown in Figure 5. In the case of the second configuration example, as soon as the redundant anomaly determinations No. 1, 2, and 3 shown in Figure 10 are output, that information can be directly output to the higher-level CPU.

[0094] Thus, when the redundancy anomaly detection circuit (Figure 10) or the maximum value detection circuit (Figure 12) determines that there is a redundancy anomaly, it outputs redundancy anomaly information indicating that there is a redundancy anomaly to the higher-level CPU (a separate part from the detection unit, a control unit higher than the FPGA) (detection unit).

[0095] As described above, this embodiment has the following advantages. (1) According to this embodiment, it is possible to determine whether or not the SiC (semiconductor element) is in an abnormal state by comparing the delay time (time difference) of the PWM (output signal) and Sync (input signal) with a predetermined fixed time.

[0096] (2) According to this embodiment, the redundancy abnormality determination circuit (Figure 10) determines that a system is redundant when the number of occurrences of an abnormal state reaches five (a predetermined number of times). Therefore, cases where an abnormal state is determined to occur only once by chance due to false detection, etc., can be excluded from the redundancy abnormality determination.

[0097] (3) According to this embodiment, if the redundancy abnormality determination circuit (Figure 10) or the maximum value determination circuit (Figure 12) determines that there is a redundancy abnormality, it outputs the redundancy abnormality information to the higher-level CPU (a part separate from the determination unit), so that the higher-level CPU 12a can use the redundancy abnormality information to perform control.

[0098] (4) According to this embodiment, the redundant abnormality detection circuit (Figure 10) does not perform an abnormality detection when the SiC is under low current (when the current state of the semiconductor element is in a special state, or when Sync may become unstable). Therefore, compared to a control method that uniformly performs an abnormality detection, the reliability of the detection can be improved.

[0099] (5) According to this embodiment, the redundant abnormality consecutive count counter (number of occurrences of abnormal state) is initialized when the system transitions from an abnormal state to a normal state, so when the system transitions to a normal state, the redundancy abnormality determination can be restarted from the beginning.

[0100] (6) According to this embodiment, the redundant abnormality consecutive count counter (number of occurrences of abnormal conditions) is not initialized when an abnormal condition is not determined. Therefore, even if a situation occurs where an abnormal condition is not determined once or multiple times by chance due to false detection or the like, the redundancy abnormality determination can be continued.

[0101] (7) According to the first configuration example of this embodiment (Figure 4), the redundant abnormal information includes the maximum number of the six groups of SiC (information aggregating information from multiple semiconductor elements), so sufficient information can be output even if the number of terminals for outputting information is small.

[0102] (8) According to the second configuration example of this embodiment (Figure 5), the redundant abnormal information includes all the information of the 18 SiCs (information of multiple semiconductor elements), so all the information of the 18 SiCs can be output.

[0103] (9) The FPGA30 operates at a maximum frequency of several hundred MHz, so the time measurement resolution is several nanoseconds. Therefore, it is difficult to measure delay times with a resolution greater than the operating frequency (less than 4 ns). In this embodiment, a circuit is provided that improves the resolution (a circuit capable of measuring delay time with a resolution of 1 nsec) by using a PLL (phase-locked loop) circuit configuration.

[0104] [Transformed form] The present invention can be implemented in various ways without being limited to the embodiments described above. (1) The output signal was explained using the PWM example, but other signals may also be used. The input signal was explained using the Sync example, but other signals may also be used. (2) Although the SiC was described using a 4-terminal example, a 3-terminal SiC may also be used. If a 3-terminal SiC is used and the terminals of the driver source T3 are eliminated, a shunt resistor can be placed next to the coil 16 or motor 17, and the waveform of the shunt resistor can be used to output a waveform (input signal) to the FPGA that replaces the Sync signal.

[0105] (3) The determination unit may determine that a redundant abnormality has occurred when the number of occurrences of the abnormal condition reaches one, or it may output a message to that effect to a part other than the determination unit when the number of occurrences of the abnormal condition reaches one. The part other than the determination unit was explained in the example of the upper CPU 12a, but it may be any part of the FPGA 30. (4) The FPGA (determination unit) may not output the abnormal state or redundancy abnormality to a part other than the determination unit, but may use the abnormal state or redundancy abnormality within the FPGA to perform control.

[0106] (5) The determination unit may determine an abnormal state even if the current state of the semiconductor device is in a special state. The special state is not limited to low current, but may also be high current. The special state may be a state in which the current state of the SiC is within or outside a predetermined range of a certain value. (6) The number of occurrences of an abnormal state does not need to be reset if the system transitions from an abnormal state to a normal state. The number of occurrences of an abnormal state may be reset if no abnormal state check is performed.

[0107] (7) The content of the redundant anomaly information is arbitrary. The redundant anomaly information only needs to include information on at least one semiconductor device. The redundant anomaly information does not need to be output. (8) The determination result of the determination unit may be stored without being output, or it may be monitored by an external device.

[0108] (9) Some explanations have been omitted regarding rising edge, falling edge, PWM, and Sync, but the control content of one process can be modified to suit the control content of other processes and reused. (10) In addition, the structures and circuit configurations shown in the embodiments are merely preferred examples, and various elements can be added to the basic structure, some components can be replaced, or some components can be deleted. [Explanation of Symbols]

[0109] 10 Control Systems 11 Power supply 12 Control board 12a Upper CPU 13, 14, 15 Power switching devices 16 coils 17 Motor 20a 1st GDM 20b 2nd GDM 20c 3rd GDM 20d Control effective range detection circuit 20-1 1st GDM H / L for U phase 20-2 2nd GDM H / L for U phase 20-3 3rd GDM H / L for U phase 20-4 1st GDM H / L for V phase 2nd GDM H / L for 20-5 V phase 20-6 3rd GDM H / L for V phase 20-7 1st GDM H / L for W phase 20-8 2nd GDM H / L for W phase 20-9 3rd GDM H / L for W phase 30 FPGA 40-1 U phase Hside circuit 40-2 U phase Lside circuit 40-3 V phase Hside circuit 40-4 V phase Lside circuit 40-5 W phase Hside circuit 40-6 W phase Lside circuit 41 Filter detection circuit 42a First delay circuit 42b Second delay circuit 42c Third delay circuit 43 Stop judgment circuit 44 Time difference measurement circuit 45 Delay Time Determination Circuit 46 Delay Time Measurement Circuit 47 Redundant abnormality judgment circuit

Claims

1. A time measurement unit that outputs an output signal to a drive circuit device that drives a semiconductor element, receives an input signal based on the output signal from the drive circuit device, and measures the time from when the output signal is output until the input signal is received, A determination unit determines that the semiconductor element is in an abnormal state if the measurement result from the time measurement unit is outside a predetermined range of time, A control system equipped with the following features.

2. In the control system according to claim 1, The control system is characterized in that the determination unit determines, when the number of occurrences of the abnormal state reaches a predetermined number of times, that the abnormal state is a redundant abnormality in which the abnormal state has occurred consecutively.

3. In the control system according to claim 2, The control system is characterized in that, when the determination unit determines that a redundancy abnormality has occurred, it outputs redundancy abnormality information indicating that a redundancy abnormality has occurred to a part other than the determination unit.

4. In the control system according to claim 1, The control system is characterized in that the determination unit does not determine the abnormal state when the current state of the semiconductor element is in a special state.

5. In the control system according to claim 2, A control system characterized in that the number of occurrences of the abnormal state is reset when the system transitions from the abnormal state to a normal state that is not an abnormal state.

6. In the control system according to claim 2, A control system characterized in that the number of occurrences of the abnormal state is not reset if the abnormal state is not determined.

7. In the control system according to claim 3, There are multiple semiconductor elements, The control system is characterized in that the redundant abnormal information is information that aggregates the states of multiple semiconductor elements.

8. In the control system according to claim 3, There are multiple semiconductor elements, The control system is characterized in that the redundant abnormal information includes information that contains the states of all of the semiconductor elements.

Images