control system

Abstract

This invention provides a control system that can reduce the degradation of semiconductor devices. [Solution] The control system is a control system that controls multiple SiCs (semiconductor elements). In the control system, the higher-level CPU generates stop command information regarding the stopping of multiple SiCs. The FPGA (stop determination circuit 43, switching unit) operates the SiCs by switching which SiC to stop at regular intervals according to the stop command information. The stop determination circuit 43 is a circuit that determines which SiC to stop and stops the PWM output corresponding to the SiC that has been determined to stop, thereby stopping the SiC. If there is a redundant SiC, the FPGA will prioritize stopping the redundant SiC. When the FPGA stops a SiC, it will not stop the SiCs that are currently being driven. The FPGA can make the driving modes of the high-side SiCs and low-side SiCs different even with the same stop command information.

Description

Technical Field

[0001] The present invention relates to a control system.

Background Art

[0002] Patent Document 1 discloses a technology using a gate driver, an IGBT module, or the like.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a technology such as Patent Document 1, a technology capable of reducing the deterioration of semiconductor elements is desired.

[0005] Therefore, the present invention provides a control system capable of reducing the deterioration of semiconductor elements.

Means for Solving the Problems

[0006] The present invention employs the following solutions to solve the above problems. Note that the following solutions and the wording in parentheses are merely examples, and the present invention is not limited thereto. Further, the present invention can be an invention including at least one of the invention-specific matters shown in the following solutions. Furthermore, elements limiting the invention-specific matters can be added to the invention-specific matters shown in the following solutions to make them subordinate concepts, and elements limiting the invention-specific matters can also be deleted to make them superordinate concepts.

[0007] Solution 1: The control system of this solution is a control system for controlling a plurality of semiconductor elements, comprising: a stop command information generation unit that generates stop command information for stopping the plurality of semiconductor elements; and a switching unit that switches the semiconductor elements to be stopped at regular intervals according to the stop command information and operates the plurality of semiconductor elements.

[0008] According to this solution, by switching between semiconductor elements that are stopped at regular intervals to operate multiple semiconductor elements, the amount of time that semiconductor elements are not operating can be increased compared to a method in which all semiconductor elements are kept running continuously. As a result, the degradation of semiconductor elements can be reduced.

[0009] Solution 2: The control system of this solution comprises, in any of the solutions described above, a drive circuit device for driving the semiconductor element, a time measurement unit that outputs an output signal to the drive circuit device, receives an input signal based on the output signal from the drive circuit device, and measures the time from when the output signal is output until the input signal is received, and a determination unit that determines that the semiconductor element is in an abnormal state if the measurement result by the time measurement unit is outside a predetermined range of a certain period of time, wherein the determination unit determines that the abnormal state is a redundant abnormality if the number of occurrences of the abnormal state reaches a predetermined number of times, and the switching unit, if there is a semiconductor element in a redundant abnormality, preferentially stops the semiconductor element in a redundant abnormality.

[0010] According to this solution, if there is a redundant or faulty semiconductor element, the redundant or faulty semiconductor element is stopped preferentially, allowing the faulty location to be stopped quickly, and as a result, the degradation of the semiconductor element can be reduced.

[0011] Solution 3: The control system of this solution is a control system characterized in that, in any of the solutions described above, the switching unit does not stop the semiconductor element that is in operation when stopping the semiconductor element.

[0012] According to this solution, since the semiconductor element in operation is not stopped, it is possible to avoid situations in which the semiconductor element in operation is suddenly stopped, resulting in the generation of unintended pulses.

[0013] Solution 4: The control system of this solution is characterized in that, in any of the solutions described above, the semiconductor element includes high-side and low-side semiconductor elements, and the switching unit is capable of making the driving modes of the high-side semiconductor element and the low-side semiconductor element different, even with the same stop command information.

[0014] According to this solution, even with the same stop command information, it is possible to make the driving modes of the high-side semiconductor element and the low-side semiconductor element different, thereby enabling flexible control according to the occurrence of redundancy abnormalities. [Effects of the Invention]

[0015] According to the present invention, a control system that can reduce the degradation of semiconductor elements can be provided. [Brief explanation of the drawing]

[0016] [Figure 1] This is a diagram showing the control system 10 of the embodiment. [Figure 2] This diagram shows the configuration of a power switching device. [Figure 3] This is a diagram illustrating the overview of the control system 10. [Figure 4] This figure shows a first example of parallel feedback control (maximum value transmission of redundant abnormal information). [Figure 5] This figure shows a second example of parallel feedback control (straight transmission of redundant abnormal information). [Figure 6] This is a diagram showing the details of the control system 10. [Figure 7] This is a diagram showing the internal circuitry of an FPGA. [Figure 8]It is a diagram showing the details of the delay detection circuit. [Figure 9] It is a diagram showing the details of the delay time measurement circuit. [Figure 10] It is a diagram showing the details of the redundant abnormality determination circuit. [Figure 11] It is a diagram showing the control method of the control enable signal. [Figure 12] It is a diagram showing the details of the maximum value determination circuit. [Figure 13] It is a diagram showing the details of the stop determination circuit. [Figure 14] It is a diagram showing the operation content of the FPGA. [Figure 15] It is a diagram showing the details of the determination circuit. [Figure 16] It is a diagram showing the details of the pattern generation circuit and the like. [Figure 17] It is a diagram for explaining two counters used in the pattern generation circuit. [Figure 18] It is a diagram showing the details of counter 2. [Figure 19] It is a diagram showing the details of counter 3. [Figure 20] It is a diagram showing the operation of the stop command information. [Figure 21] It is a diagram showing an operation example of simulation 1. [Figure 22] It is a diagram showing an operation example of simulation 2. [Figure 23] It is a diagram showing an operation example of simulation 3. [Figure 24] It is a diagram showing an operation example of simulation 4. [Figure 25] It is a diagram showing the relationship between the current and time of SiC. [Figure 26] It is a block diagram showing the details of the control board.

Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 1 shows a control system 10 of an embodiment. Figure 1(A) shows the overall configuration of the control system 10, and Figure 1(B) shows the dotted line portion of Figure 1(A) and the details of the circuits connected thereto. As shown in Figure 1(A), the control system 10 comprises a power supply 11, a control board 12, three-phase power switching devices 13, 14, and 15, three coils 16, and a motor 17. The three-phase power switching devices 13, 14, and 15 are each composed of two power switching devices shown above and below.

[0018] In the control system 10, the control board 12 operates using power from the power supply 11, and the control board 12 drives the motor 17 by gate-controlling three-phase power switching devices 13, 14, and 15, thereby driving the motor 17 with three coils 16. Although the control system 10 drives the motor 17, it may also be a circuit that drives devices other than the motor 17.

[0019] In Figure 1(A), the dotted line portion usually only requires one power switching device, but if the current is insufficient, multiple power switching devices may be connected in parallel. The control system 10 of this embodiment can be used when connecting multiple power switching devices in parallel in such a situation.

[0020] As shown in Figure 1(B), SiC1, SiC2, and SiC3, which function as power switching devices, are connected in parallel. SiC (SiC device) is a power semiconductor (semiconductor element, power device) that uses silicon carbide semiconductor, which is a compound. Control system 10 is a control system that controls multiple SiCs (multiple semiconductor elements).

[0021] Each SiC is connected to a GDM (Gate Driver Module), and the GDM is connected to an FPGA (Field Programmable Gate Array, time measurement unit, judgment unit, switching unit) 30. Specifically, SiC1 is connected to the first GDM 20a, and the first GDM 20a is connected to the FPGA 30. SiC2 is connected to the second GDM 20b, and the second GDM 20b is connected to the FPGA 30. SiC3 is connected to the third GDM 20c, and the third GDM 20c is connected to the FPGA 30.

[0022] The FPGA 30 receives PWM input from the control board 12 (higher-level control unit, higher-level CPU). FPGA30 outputs PWM1 to the first GDM20a, and Sync1 is input from the first GDM20a. FPGA30 outputs PWM2 to the second GDM20b, and Sync2 is input from the second GDM20b. FPGA30 outputs PWM3 to the third GDM20c, and Sync3 is input from the third GDM20c. PWM (Pulse Width Modulation) is a signal that uses a square wave pulse to control electrical components, etc. Sync (Synchronization) is a signal used to synchronize the operation timing between various devices (synchronization signal).

[0023] The first GDM20a outputs Vgs1 to SiC1, and Vdsps1 is input from SiC1. The second GDM20b outputs Vgs2 to SiC2, and Vdsps2 is input from SiC2. The third GDM20c outputs Vgs3 to SiC3, and Vdsps3 is input from SiC3. SiC1, SiC2, and SiC3 output Ids1, Ids2, and Ids3, respectively. Vgs is the gate-source voltage. Vdsps is the voltage between the driver source and power source of the SiC4 terminal device. Ids is the current flowing from the drain to the source.

[0024] Although not specifically shown in the diagram, Ids1 output by SiC1 is also input to the first GDM20a, Ids2 output by SiC2 is also input to the second GDM20b, and Ids3 output by SiC3 is also input to the third GDM20c. Each GDM is equipped with a Sync detection circuit (first Sync detection circuit to third Sync detection circuit), which detects Sync based on Vdsps (potential difference between the driver source and the power source) and Ids input to the Sync detection circuit, and can output Sync1, 2, and 3 to FPGA30.

[0025] The circuit that transmits PWM to FPGA30, along with the first GDM20a, second GDM20b, and third GDM20c, can be implemented as part of the control board 12's functions. On the other hand, FPGA30 can be implemented as a separate function from the control board 12.

[0026] Figure 2 shows the configuration of a power switching device. In this embodiment, a four-terminal power switching device is used. For example, the SCT3040KR (manufactured by ROHM Co., Ltd.) can be used as the four-terminal power switching device. The four terminals are drain T1, gate T2, driver source T3, and power source T4. The potential difference (Vdsps, etc.) between the driver source T3 and power source T4 can be used as a control element.

[0027] Generally, the Ls of power switching devices ranges from a few nH to over ten nH, and dI D When / dt reaches several A / ns, the electromotive force V exceeds 10V. L Vdsps is V L By making the "Sync detection circuit" highly sensitive using the same signal, it becomes possible to detect the initial operation of Id. To balance the current division when power switching devices are connected in parallel, each signal can be controlled to match the timing of the Vdsps signal.

[0028] Figure 3 shows an overview of the control system 10. As shown in Figure 3(A), a gate signal (e.g., PWM) is output from the FPGA to the GDM at a constant period, and a Sync signal corresponding to the gate signal is input to the FPGA. When the SiC is in a normal state, the Sync signal is input to the FPGA within a certain time range from the output of the gate signal. On the other hand, when the SiC is in an abnormal state, the Sync signal is input to the FPGA outside of that certain time range from the output of the gate signal. The control system 10 determines whether the SiC is in a normal or abnormal state by monitoring the delay time of the Sync signal.

[0029] Next, we will explain the control flow for each gate signal from (1) to (10). In the gate signal (1), the Sync signal is input to FPGA30 within a certain time range. Therefore, the abnormal state determination is "normal state", the redundant abnormality consecutive count counter (number of times the abnormal state has occurred) is "0", and the redundant abnormality determination is Low (not redundant abnormal). Note that, except for the gate signal (6), the control enable signal is High. In the gate signal of (2), the Sync signal is input to FPGA30 outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "1", and the redundant abnormal state determination is Low. In the gate signal of (3), the Sync signal is input to FPGA30 within a certain time range. Therefore, the abnormal state determination is "normal state", the redundant abnormal consecutive count counter is "0", and the redundant abnormal state determination is Low. The redundant abnormal consecutive count counter (number of occurrences of abnormal state) is initialized when the system transitions from an abnormal state to a normal state.

[0030] In the gate signal of (4), the Sync signal is input to FPGA30 outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "1", and the redundant abnormal state determination is Low. In the gate signal (5), the Sync signal is input to FPGA30 outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "2", and the redundant abnormal determination is Low. In the gate signal of (6), the Sync signal is input to FPGA30 outside the specified time range, but since the control enable signal is Low, no abnormal condition is detected. Thus, FPGA30 does not detect abnormal conditions when the SiC is under low current (the current state is a special state, and the control enable signal is Low) (detection unit). In addition, the redundant abnormal consecutive count counter (number of abnormal conditions) is not initialized if no abnormal condition is detected.

[0031] In the gate signal of (7), the Sync signal is input to the FPGA outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "3 times", and the redundant abnormal state determination is Low. In the gate signal (8), the Sync signal is input to the FPGA outside the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "4 times", and the redundant abnormal state determination is Low. In the gate signal of (9), the Sync signal is input to the FPGA outside of the specified time range. Therefore, the abnormal state determination is "abnormal state", the redundant abnormal consecutive count counter is "5 times", and the redundant abnormal state determination is High. In gate signal (10), the Sync signal is input to the FPGA outside the specified time range. Therefore, the abnormal state determination is "abnormal state". In this case, the redundant abnormal consecutive count counter may be updated to "6 times" or remain at "5 times". The redundant abnormal state determination is High.

[0032] Figure 3(B) shows an example of how to determine an abnormal state. As shown in the upper and middle gate signal and Sync signal waveforms of Figure 3(B), when the SiC is functioning correctly, a Sync signal is input from the GDM to the FPGA within a certain time range (with a certain delay time) in response to the gate signal output from the FPGA to the GDM (see arrow X1). However, increasing the input capacitance increases the delay time of the Sync signal relative to the gate signal (see arrow X2). Also, as the SiC temperature rises, the delay time of the Sync signal relative to the gate signal decreases (see arrow X3).

[0033] The Sync abnormal state determination range is represented by the waveform shown in the lower part of Figure 3(B). When the Sync signal rises while this waveform is Low, it is determined to be in a normal state, and when the Sync signal rises while this waveform is High, it is determined to be in an abnormal state. In other words, the FPGA determines that the SiC is in a normal state when the Sync signal is input in range Y1 (arrow X1), and determines that the SiC is in an abnormal state when the Sync signal is input in range Y2 or range Y3 (arrows X2 and X3).

[0034] Next, two configuration examples of the control system 10 will be described. The control system 10 can adopt one of the following configuration examples.

[0035] Figure 4 shows a first example of a 3-parallel feedback control configuration (maximum value transmission of redundant abnormal information). In the first configuration example, the upper-level CPU 12a and FPGA 30 are connected, and FPGA 30 is connected to each GDM. There are "U-phase," "V-phase," and "W-phase" GDMs, and each phase has "1st," "2nd," and "3rd" GDMs. In addition, each GDM is described including the high-side (H: Highside, Hside) and low-side (L: Lowside, Lside).

[0036] For example, the "U-phase 1st GDM H / L" (20-1) includes two gate driver modules: one for driving the first row of high-side SiC (UH1) for the U-phase, and another for driving the first row of low-side SiC (UL1) for the U-phase. The "U-phase 2nd GDM H / L" (20-2) also includes two gate driver modules: one for driving the second row of high-side SiC (UH2) for the U-phase, and another for driving the second row of low-side SiC (UL2) for the U-phase. Furthermore, the "U-phase 3rd GDM H / L" (20-3) includes two gate driver modules: one for driving the third row of high-side SiC (UH3) for the U-phase, and another for driving the third row of low-side SiC (UL3) for the U-phase. Furthermore, this relationship also applies to the "V-phase" components: "V-phase 1st GDM H / L" (20-4), "V-phase 2nd GDM H / L" (20-5), and "V-phase 3rd GDM H / L" (20-6), as well as the "W-phase" components: "W-phase 1st GDM H / L" (20-7), "W-phase 2nd GDM H / L" (20-8), and "W-phase 3rd GDM H / L" (20-9). Therefore, there are a total of 18 GDMs (9 (20-1 to 20-9) × 2 (high-side and low-side)), and correspondingly, there are also 18 SiCs.

[0037] The higher-end CPU 12a outputs PWM and stop command information (2 bits) for 2x3 phases (6 phases in total) of high-side and low-side PWM to FPGA 30, and FPGA 30 inputs redundant error information (2 bits). FPGA30 outputs PWM (PWMU1~3 H / L, PWMV1~3 H / L, PWMW1~3 H / L) to each GDM20-1~20-9, and Sync (SyncU1~3 H / L, SyncV1~3 H / L, SyncW1~3 H / L) is input from each GDM20-1~20-9.

[0038] The upper-level CPU 12a generates stop command information for stopping multiple SiCs (stop command information generation unit). The FPGA 30 (stop determination circuit) switches which SiC to stop at regular intervals (every 10ms to 10s) according to the stop command information, thereby operating multiple SiCs (switching unit).

[0039] In the first configuration example, a maximum redundancy anomaly information transmission method is employed. This method transmits the maximum value of the number of redundancies on each side of each phase. In this embodiment, the 18 SiCs are divided into 6 groups, with 3 SiCs arranged in each group. The first group G1 is the U-phase H-side group (UH1, UH2, UH3), the second group G2 is the U-phase L-side group (UL1, UL2, UL3), the third group G3 is the V-phase H-side group (VH1, VH2, VH3), the fourth group G4 is the V-phase L-side group (VL1, VL2, VL3), the fifth group G5 is the W-phase H-side group (WH1, WH2, WH3), and the sixth group G6 is the W-phase L-side group (WL1, WL2, WL3). The maximum value of the number of redundancies is then the maximum value of the 6 groups.

[0040] For example, if all SiCs are in a normal state, the number of redundant anomalies will be "0". Also, if one SiC in group 1 G1 is in an abnormal state and the SiCs in the other groups are in a normal state, the number of redundant anomalies will be "1". Furthermore, if one SiC in group 1 G1 is in an abnormal state, two SiCs in group 2 G2 are in an abnormal state, and the SiCs in the other groups are in a normal state, the number of redundant anomalies will be "2". Also, if one SiC in group 1 G1 is in an abnormal state, two SiCs in group 2 G2 are in an abnormal state, three SiCs in group 3 G3 are in an abnormal state, and the SiCs in the other groups are in a normal state, the number of redundant anomalies will be "3". Furthermore, if all SiCs are in an abnormal state, the number of redundant anomalies will be "3".

[0041] The number of redundant anomalies is then stored in the redundancy anomaly information and output to the upper CPU 12a. The redundancy anomaly information is 2 bits of information, and the content of the information is as follows: "00: Normal, 01: 1 device anomaly, 10: 2 devices anomaly, 11: 3 devices anomaly". Normal indicates that all SiCs are in a normal state (redundancy anomaly count = 0), 1 device anomaly indicates that one SiC is redundantly anomaly (redundancy anomaly count = 1), 2 device anomalies indicate that two SiCs are redundantly anomaly (redundancy anomaly count = 2), and 3 device anomalies indicate that three SiCs are redundantly anomaly (redundancy anomaly count = 3).

[0042] Thus, the redundancy anomaly information in the first configuration example is information that aggregates the states of multiple SiCs.

[0043] The stop command information is 2 bits of information, and the content of the information is as follows: "00: No stop, 01: Stop 1 device, 10: Stop 2 devices, 11: Stop 3 devices". No stop means that the SiC will not be stopped, 1 device stop means that one SiC will be stopped, 2 device stop means that two SiCs will be stopped, and 3 device stop means that three SiCs will be stopped.

[0044] Figure 5 shows a second example of a 3-parallel feedback control configuration (straight transmission of redundant abnormal information). The second configuration example differs from the first configuration example only in the section on redundant error information. Since the other parts are identical to the first configuration example, their explanation is omitted. The redundancy anomaly information is 18 bits of information, and the content of the information is "UH1 / 2 / 3, UL1 / 2 / 3, VH1 / 2 / 3, VL1 / 2 / 3, WH1 / 2 / 3, WL1 / 2 / 3". For example, if "UH1" is "0", it means that the first column of SiC on the high side for the U phase is normal, and if "UH1" is "1", it means that the first column of SiC on the high side for the U phase is redundant and anomaly. Similarly, if "UH2" is "0", it means that the second column of SiC on the high side for the U phase is normal, and if "UH2" is "1", it means that the first column of SiC on the high side for the U phase is redundant and anomaly. Furthermore, if "UH3" is "0", it means that the third column of SiC on the high side for the U phase is normal, and if "UH3" is "1", it means that the first column of SiC on the high side for the U phase is redundant and anomaly. The same applies to "UL", "VH", "VL", "WH", and "WL".

[0045] Thus, the redundancy anomaly information in the second configuration example includes information that encompasses the states of all multiple SiCs.

[0046] Figure 6 shows the details of the control system 10. The higher-end CPU 12a outputs 2x3 phases of PWM (PWMU phase Hside, PWMU phase Lside, PWMV phase Hside, PWMV phase Lside, PWMW phase Hside, PWMW phase Lside) to the FPGA 30.

[0047] In FPGA30, each PWM input from the higher-level CPU12a is input to the circuit corresponding to each phase, each circuit outputs a PWM to each GDM, and each GDM inputs a Sync to each circuit. Specifically, it is as follows: The U-phase Hside circuit 40-1 receives the PWMU-phase Hside as input, outputs PWMU-phase Hside 1, 2, and 3 to the GDM (1st to 3rd GDM H for U-phase in Figure 5), and receives SyncU-phase Hside 1, 2, and 3 as input. The U-phase Lside circuit 40-2 receives the PWMU-phase Lside as input, outputs PWMU-phase Lside 1, 2, and 3 to the GDM (the 1st to 3rd GDM L for the U-phase in Figure 5), and receives SyncU-phase Lside 1, 2, and 3 as input.

[0048] The V-phase H-side circuit 40-3 receives the PWM V-phase H-side input, outputs PWM V-phase H-side 1, 2, and 3 to the GDM (V-phase 1st to 3rd GDM H in Figure 5), and receives the Sync V-phase H-side 1, 2, and 3 input. The V-phase Lside circuit 40-4 receives the PWM V-phase Lside input, outputs PWM V-phase Lside 1, 2, and 3 to the GDM (V-phase 1st to 3rd GDM L in Figure 5), and receives the Sync V-phase Lside 1, 2, and 3 input.

[0049] The W-phase H-side circuit 40-5 receives the PWM W-phase H-side input, outputs PWM W-phase H-side 1, 2, and 3 to the GDM (the 1st to 3rd GDM H for the W-phase in Figure 5), and receives the Sync W-phase H-side 1, 2, and 3 inputs. The W-phase Lside circuit 40-6 receives the PWMW-phase Lside input, outputs PWMW-phase Lside 1, 2, and 3 to the GDM (the 1st to 3rd GDM L for the W phase in Figure 5), and receives SyncW-phase Lside 1, 2, and 3 as inputs.

[0050] The initial value for the maximum redundancy abnormality is "00". The maximum redundancy abnormality can be calculated by processing in the following order: "U-phase H-side circuit 40-1" → "U-phase L-side circuit 40-2" → "V-phase H-side circuit 40-3" → "V-phase L-side circuit 40-4" → "W-phase H-side circuit 40-5" → "W-phase L-side circuit 40-6". Stop designation information is transmitted to each circuit.

[0051] Figure 7 shows the internal circuit configuration of the FPGA. The internal circuit in Figure 7 is the same as the circuits included in "U-phase H-side circuit 40-1", "U-phase L-side circuit 40-2", "V-phase H-side circuit 40-3", "V-phase L-side circuit 40-4", "W-phase H-side circuit 40-5", and "W-phase L-side circuit 40-6" in Figure 6, and can be considered a common circuit. Because it is a common circuit, "PWM1, 2, 3", "Sync1, 2, 3", "1st to 3rd GDM", etc. are indicated with common symbols.

[0052] In reality, if it is "U-phase Hside circuit 40-1", then "PWM1, 2, 3" becomes "PWMU-phase Hside1, 2, 3", "Sync1, 2, 3" becomes "SyncU-phase Hside1, 2, 3", "1st to 3rd GDM" becomes "U-phase 1st to 3rd GDM H", "Id" becomes "IdU-phase Hside", "SiC1, 2, 3" becomes "UH1, 2, 3", and "Redundancy Anomaly Judgment No. 1, 2, 3" becomes "Redundancy Anomaly Judgment No. 1, 2, 3 for U-phase Hside". These points are also true for "U-phase Lside circuit 40-2" to "W-phase Lside circuit 40-6", and for the following diagrams. Also, although SiC1, 2, and 3 are shown vertically for convenience, they are actually connected in parallel (see Figure 1).

[0053] FPGA30 (for example, U-phase H-side circuit 40-1) detects PWM with filter detection circuit 41 and outputs PWM0, generates PWM1, 2, and 3 with first delay circuit 42a, second delay circuit 42b, and third delay circuit 42c, and outputs PWM1, 2, and 3 to first GDM20a, second GDM20b, and third GDM20c.

[0054] Furthermore, Sync1, 2, and 3 are input to FPGA30 from the first GDM20a, second GDM20b, and third GDM20c, respectively, and feedback control is performed in the time difference measurement circuit 44, the delay time determination circuit 45, and the three delay circuits (first delay circuit 42a, second delay circuit 42b, and third delay circuit 42c). The time difference measurement circuit 44, the delay time determination circuit 45, and the three delay circuits are circuits that delay PWM1, 2, and 3 (output signals) based on Sync1, 2, and 3 to suppress phase variations of the gate driver and SiC and to correctly synchronize the gate driver and SiC, but these circuits can also be omitted.

[0055] Furthermore, in FPGA 30, PWM1, 2, 3 and Sync1, 2, 3 are input to the delay time measurement circuit 46, and redundancy abnormality detection circuit 47 performs redundancy abnormality detection. Note that a 250MHz 4-phase shift PLL is used in the time difference measurement circuit 44 and the delay time measurement circuit 46.

[0056] A current sensor is placed on the SiC, and the SiC current (Id) is input to the control effective range detection circuit 20d. The control effective range detection circuit 20d determines the current value, and the determination result is output as a control effective signal, which is input to the FPGA 30's time difference measurement circuit 44 and delay time measurement circuit 46. The control effective range detection circuit 20d compares a preset minimum current value with the value of Id, and if the preset minimum current value ≤ the value of Id (high current), it outputs the control effective signal as High, and if the minimum current value > the value of Id (low current), it outputs the control effective signal as Low. The control effective range detection circuit 20d can be implemented at any point in the system.

[0057] The redundancy anomaly detection circuit 47 performs a determination regarding redundancy anomalies, and redundancy anomaly determinations No. 1, 2, and 3 are output to the stop detection circuit 43. Redundancy anomaly determination No. 1 indicates whether the first column of SiC is normal or abnormal, redundancy anomaly determination No. 2 indicates whether the second column of SiC is normal or abnormal, and redundancy anomaly determination No. 3 indicates whether the third column of SiC is normal or abnormal. Redundancy anomaly determinations No. 1, 2, and 3 are, for example, 1-bit information, which can be set to "0: normal, 1: abnormal". The redundancy anomaly detection circuit 47 also outputs redundancy anomaly information (2 bits = red0 / 1 bit) to the upper CPU 12a based on redundancy anomaly determinations No. 1, 2, and 3.

[0058] The upper-level CPU 12a outputs PWM to FPGA 30 and, if necessary, outputs stop command information (2 bits = cpu0 / 1 bit) to the stop determination circuit 43 of FPGA 30.

[0059] Figure 8 shows the details of the delay detection circuit. Figure 8(A) shows the circuit configuration, and Figure 8(B) shows the timing charts for each signal. Note that the delay detection circuit may be included in the delay time measurement circuit, or it may be a separate circuit from the delay time measurement circuit.

[0060] As shown in Figure 8(A), the delay detection circuit is a circuit that receives the rising edge signals of PWM1, 2, 3, Sync1, 2, 3, and PWM0 and outputs a delayed signal. When PWM1 is input, Sync1 is input; when PWM2 is input, Sync2 is input; and when PWM3 is input, Sync3 is input.

[0061] For example, when PWM1 and Sync1 are input to the delay detection circuit, PWM1 and Sync1 are input to the clock portion of the upper and lower flip-flop circuits, respectively. Also, the rising edge of PWM0 is input as a clear signal to the upper and lower flip-flop circuits. Then, data A is output from the upper flip-flop circuit and data B is output from the lower flip-flop circuit, and by inputting the inverted data (negated data) of data A and data B into the AND circuit, a delay signal is output.

[0062] As shown in Figure 8(B), PWM1, 2, and 3 rise first, followed by Sync1, 2, and 3. In this case, when the logical AND of the inverted data of data A and data B is taken, only the portion where data A is High and data B is Low becomes High, and this is used as the length of the delay time (the length from the rising edge of data A to the rising edge of data B), and a delay signal is output.

[0063] Figure 9 shows the details of the delay time measurement circuit. Figure 9(A) shows the circuit configuration, Figure 9(B) shows the timing charts for each signal in the first example, and Figure 9(C) shows the timing charts for each signal in the second example. As shown in Figure 9(A), the delay time measurement circuit 46 is a circuit that receives a delay signal and a clock signal as inputs and outputs the delay time. The delay time measurement circuit 46 receives the delay signal shown in Figure 8, controls counters 0 to 3 with CLK0 to CLK3 generated by the PLL, and adds data 0 to data 3 using an adder circuit to measure the delay time. In addition, the delay time measurement circuit 46 uses a 250MHz 4-phase shift PLL to measure (decompose) the phase difference pulses in 1ns time.

[0064] The PLL utilizes a function (circuit) built into the FPGA. By using the PLL, the clock is increased to 250ns and a 4-phase shift is performed. This allows for the generation of a continuous clock waveform at 250MHz. CLK0 to CLK3 are waveforms shifted by 90 degrees, with CLK1 shifted by 90 degrees relative to CLK0, CLK2 shifted by 90 degrees relative to CLK1, CLK3 shifted by 90 degrees relative to CLK2, and CLK0 shifted by 90 degrees relative to CLK3. Since 250MHz corresponds to 4ns, a 90-degree shift means that each clock has a 1ns shift.

[0065] Each vertical line in Figure 9(B)(C) corresponds to 1 ns. As shown in Figure 9(B), assume that the waveform of the delay signal is high for only a short time. In this case, since the waveform of the delay signal is high only when CLK1 is high, counter 1 corresponding to CLK1 is set to 1. After that, the waveform of the delay signal becomes low, and this state continues. The values ​​counted by each counter are added together in the final adder circuit. As a result, in the example in Figure 9(B), the delay time is 1 (ns).

[0066] As shown in Figure 9(C), assume that the waveform of the delayed signal remains high for a longer period than in Figure 9(B). In this case, since the waveform of the delayed signal is high for all of CLK0 to CLK3, counters 0 to 3 corresponding to CLK0 to CLK3 count accordingly. Specifically, counter 0 corresponding to CLK0 counts 4, counter 1 corresponding to CLK1 counts 4, counter 2 corresponding to CLK2 counts 5, and counter 3 corresponding to CLK3 counts 4. After that, the waveform of the delayed signal becomes low, and this state continues. The values ​​counted by each counter are added together in the final adder circuit. Thus, in the example in Figure 9(C), the delay time is 4 + 4 + 5 + 4 = 17 (ns). Note that each counter counts up when its own clock pulse becomes high and the input signal is high.

[0067] Thus, the delay detection circuit (Figure 8) and the delay time measurement circuit (Figure 9) measure the time from when the FPGA 30 outputs a PWM (output signal) to when the GDM (drive circuit device) that drives the SiC (semiconductor element) inputs a Sync (input signal) based on the PWM from the GDM to the FPGA 30 (time measurement unit).

[0068] Figure 10 shows the details of the redundant anomaly detection circuit. Figure 10(A) shows the circuit configuration, and Figure 10(B) shows the timing chart for each signal. Note that the numbers in parentheses in Figure 10(A) correspond to the numbers in parentheses in Figure 10(B). As shown in Figure 10(A), the redundant anomaly detection circuit 47 is a circuit that receives inputs for delay time, threshold L, threshold H, delay signal, consecutive count, and anomaly release, and outputs redundant anomaly detection Nos. 1, 2, and 3. In the figure, thick lines indicate information of multiple bits, and thin lines indicate information of one bit. Also, the anomaly release input may not be provided.

[0069] When a delay time is input to the redundancy anomaly detection circuit, it is compared with a threshold L (comparison L circuit) and with a threshold H (comparison H circuit). If the delay time is less than the threshold L, or if the delay time is greater than the threshold H, the result of each comparison circuit becomes 1. The two comparison results are input to the OR circuit, and the result of the OR circuit (2) is input as is to the upper OR circuit, and the inverted data is input to the lower OR circuit.

[0070] Furthermore, when a delay signal is input to the redundancy anomaly detection circuit, after the delay signal is delayed (delay circuit), the falling edge of the delay signal is detected (falling edge detection circuit), and the result of the falling edge detection (1) is input to the upper and lower logical AND circuits. The result of the upper logical AND circuit (4) is input to the counter circuit that manages the redundancy anomaly consecutive counter. In the next comparison circuit, the value of the redundancy anomaly consecutive counter (5) is compared with the number of consecutive occurrences, and if the redundancy anomaly consecutive counter ≥ the number of consecutive occurrences, 1 is stored in the hold circuit. The information stored in the hold circuit (6) is output as redundancy anomaly determination No. 1, 2, and 3. In this embodiment, the number of consecutive occurrences is set to 5, but it may be 2 to 4, or 6 or more. Note that when the second configuration example shown in Figure 5 (straight transmission of redundancy anomaly information) is adopted, redundancy anomaly determination No. 1, 2, and 3 are output to the higher-level CPU.

[0071] The delay time at the top of Figure 10(A) is generated based on the delay signal, as shown in Figure 9(A). However, since this delay time passes through the adder circuit in Figure 9(A), the L / H comparison circuit, OR circuit, AND circuit in Figure 10(A), etc., a certain amount of delay is expected between the output of "Counter 0 / 1 / 2 / 3" in Figure 9(A) and the input of "Counter Circuit (Redundant Abnormal Consecutive Count Counter)" in Figure 10(A). On the other hand, the delay signal in Figure 10(A) is input at the same timing as in Figure 9(A), so no delay is expected. In order to synchronize the delay time and the timing of the delay signal, the delay circuit to which the delay signal in Figure 10(A) is input is a circuit that delays the delay signal considering the delay time caused by the comparison circuit L / H, OR circuit, AND circuit, etc. in Figure 10(A). Note that the delay time of the delay circuit in Figure 10(A) varies depending on the circuit configuration, so it can be set to any desired time. If the circuit configuration does not cause any delay, it is also possible to omit the delay circuit in Figure 10(A).

[0072] On the other hand, the result of the lower AND circuit (3) and the error clear are input to the OR circuit and used as data to clear the value of the redundant error continuous counter. The error clear is also used as data to clear the value of the hold circuit. The error clear can be output to the FPGA by the higher-level CPU at any time (for example, when the value of the hold circuit is reset).

[0073] As shown in Figure 10(B), when a PWM signal is output from the FPGA, a Sync signal is input to the FPGA. This generates a delayed signal pulse. The delay time is the time from the rising edge of the delayed signal to the rising edge of the delayed signal. (1) rises on the falling edge of the delayed signal. If (1) is High and (2) is Low, it is a normal state, so (3) becomes High and the redundancy error consecutive count counter is reset (0 (=n0)). On the other hand, if (1) is High and (2) is High, it is an abnormal state, so (4) becomes High and the redundancy error consecutive count counter is incremented. When the redundancy error consecutive count counter (5) reaches "5 (=n5)", the redundancy error judgments No. 1, 2, and 3 (6) corresponding to the SiC determined to be redundant become High. The momentary Low state of (2) is due to the PWM rising edge resetting the signal.

[0074] Thus, the redundant anomaly detection circuit (Figure 10) determines that the SiC is in an abnormal state if the delay time (measurement result by the time measurement unit) is outside a predetermined range of time (determination unit). Furthermore, the redundant anomaly detection circuit (Figure 10) determines that if the number of occurrences of the abnormal state reaches 5 (a predetermined number of times), it is a redundant anomaly where the abnormal state has occurred consecutively (determination unit).

[0075] In the control system 10 of this embodiment, when the SiC is functioning normally, the Sync delay time relative to the PWM is approximately 115 ns. Therefore, the range of normal operation is set to be the delay time plus or minus 5 ns. Within a predetermined time range, this can be 110 ns to 120 ns, and outside this predetermined time range, it can be 109 ns or less, or 121 ns or more. These values ​​are merely examples and can be changed as appropriate according to the system specifications. Whether the system is within or outside the predetermined time range can be determined by setting threshold values ​​L and H to values ​​corresponding to the predetermined time range. Threshold values ​​L and H realize the waveform of the Sync abnormal state determination range shown in Figure 3(B). The reason why the waveform of the first period in Figure 10(B)(2) is not the same as the waveform shown in Figure 3(B) is that the Sync is within the predetermined time range (the SiC is functioning normally), so the data in (2) becomes 0 in the first OR circuit.

[0076] Figure 11 shows the control method for the control enable signal. Figure 11(A) shows the first method, and Figure 11(B) shows the second method. Either method may be adopted. As shown in Figure 11(A), the first method involves inputting the control enable signal to the delay detection circuit. In the first method, the control enable signal can be input to the part of the delay detection circuit (see Figure 8) where the rising edge of PWM0 is input. Specifically, the inverted data of the rising edge of PWM0 and the control enable signal is input to the OR circuit. As a result, when the control enable signal is low (when the SiC is low power), the delay signal is not output, and consequently, abnormal condition detection is not performed.

[0077] As shown in Figure 11(B), the second method involves inputting the control enable signal to the redundant anomaly detection circuit. In the second method, the control enable signal can be input to the upper and lower AND gates of the redundant anomaly detection circuit (see Figure 10). As a result, when the control enable signal is low (when the SiC is low power), the redundant anomaly consecutive count counter is not incremented, and consequently, the anomaly state is not detected.

[0078] Figure 12 shows the details of the maximum value determination circuit. Figure 12(A) shows the circuit configuration, and Figure 12(B) shows the processing flow. Note that the maximum value determination circuit may be included in the redundant anomaly detection circuit, or it may be a separate circuit from the redundant anomaly detection circuit.

[0079] As shown in Figure 12(A), the maximum value determination circuit is a circuit that receives redundancy anomaly determinations No. 1, 2, and 3, and an input value (initial value is 00), and outputs an output value (ultimately redundancy anomaly information).

[0080] In the first two adder circuits, the redundancy anomaly detections No. 1, 2, and 3 are added together, and a 2-bit "add" value is output. An example of the "add" output is shown below. (Example 1) Redundancy Anomaly Detection No. 1 = 0 Redundancy abnormality judgment No2=0 Redundancy abnormality judgment No.3=0 counter=00

[0081] (Example 2) Redundancy Anomaly Detection No. 1 = 0 Redundancy abnormality judgment No2=1 Redundancy abnormality judgment No.3=0 add=01

[0082] (Example 3) Redundancy Anomaly Detection No. 1 = 1 Redundancy abnormality judgment No2=0 Redundancy abnormality judgment No.3=1 add=10

[0083] (Example 4) Redundancy Anomaly Detection No. 1 = 1 Redundancy abnormality judgment No2=1 Redundancy abnormality judgment No.3=1 add=11

[0084] The value `add` is stored in data A, and the input value is stored in data B. A comparison circuit then compares data A and data B. If data A > data B, the comparison result is 0, and if not, the comparison result is 1. The comparison result, `add`, and the input value are input to the multiplexer. If the comparison result is 0 (A > B), `add` is selected as the output value, and if the comparison result is 1 (otherwise), the input value is selected as the output value.

[0085] Then, as shown in Figure 12(B), this process is carried out in the following order: "U-phase H-side circuit 40-1" → "U-phase L-side circuit 40-2" → "V-phase H-side circuit 40-3" → "V-phase L-side circuit 40-4" → "W-phase H-side circuit 40-5" → "W-phase L-side circuit 40-6". The initial value of the input (initial value of the maximum value for redundancy error judgment) is "00", but the input value from the second time onward becomes the output value of the previous process, and finally, 2 bits of redundancy error information (red0 / 1 bit) is generated and output to the higher-level CPU.

[0086] Note that the maximum value determination circuit shown in Figure 12 is necessary when adopting the first configuration example (redundant anomaly information maximum value transmission) shown in Figure 4, but is not necessary when adopting the second configuration example (redundant anomaly information straight transmission) shown in Figure 5. In the case of the second configuration example, as soon as the redundant anomaly determinations No. 1, 2, and 3 shown in Figure 10 are output, that information can be directly output to the higher-level CPU.

[0087] Thus, when the redundancy anomaly detection circuit (Figure 10) or the maximum value detection circuit (Figure 12) determines that there is a redundancy anomaly, it outputs redundancy anomaly information indicating that there is a redundancy anomaly to the higher-level CPU (a separate part from the detection unit, a control unit higher than the FPGA) (detection unit).

[0088] Figure 13 shows the details of the stop detection circuit. As shown in Figure 13, the stop determination circuit 43 is a circuit that receives PWM1in, 2in, 3in, redundancy abnormality (redundancy abnormality determination No. 1, 2, 3), stop command information from the higher-level CPU, and PWM0 as inputs, and outputs PWM1out, 2out, and 3out. Note that PWM1in, 2in, and 3in correspond to PWMin of the stop determination circuit 43 in Figure 7, and PWM1out, 2out, and 3out correspond to PWMout of the stop determination circuit 43 in Figure 7. The stop determination circuit 43 is a circuit that determines which SiC to stop, and stops the PWM output corresponding to the SiC that has been determined to stop, thereby stopping the SiC.

[0089] When PWM1in, 2in, and 3in are input to the stop detection circuit 43, each PWM is input to the last three OR circuits. The top OR circuit outputs PWM1out, the second OR circuit from the top outputs PWM2out, and the third OR circuit from the top outputs PWM3out.

[0090] Redundancy anomaly detections No. 1, No. 2, and No. 3 (redundancy anomaly) are input to the detection circuit, and the calculation results are input to the pattern generation circuit and the multiplexer. The stop command information (cpu0 / 1bit) is input to a latch circuit and splits into two. One data stream is input to the pattern generation circuit via the edge detection circuit and counter reference circuit. The other data stream is input to the pattern generation circuit and multiplexer via the judgment circuit. The pattern generation circuit generates a stop pattern, and the multiplexer selects a stop pattern. The selection result is held by three latch circuits.

[0091] PWM0 branches into two after an edge (rising edge) is detected by the edge detection circuit. One data stream is input to a latch circuit that receives stop command information. The other data stream is input to three latch circuits that receive the output data of the multiplexer. The data output from these three latch circuits is then input to the final OR gate.

[0092] The latch circuit on the left holds stop command information, and when the rising edge of PWM0 is detected by the edge detection circuit, it outputs the stop command information to the edge detection circuit and the judgment circuit. Meanwhile, the three latch circuits on the right hold the output data of the multiplexer, and when the rising edge of PWM0 is detected by the edge detection circuit, the output data of the multiplexer is output to the three OR circuits. The "stop command information" input from the higher-level CPU is asynchronous, so it is latched on the rising edge to synchronize with PWM0.

[0093] The last three OR gates receive PWM1in, 2in, and 3in as inputs. If the data output from the latch gate is Low, PWM1in, 2in, and 3in are output as Low PWM1out, 2out, and 3out (i.e., the PWM output is stopped, and the SiC stops). On the other hand, if the data output from the latch gate is High, PWM1in, 2in, and 3in are output as High PWM1out, 2out, and 3out (i.e., the PWM output is not stopped, and the SiC does not stop). Thus, the last three OR gates have the role of outputting PWM1out, 2out, and 3out as Low depending on the redundancy abnormality, even if PWM1in, 2in, and 3in are input as High. In addition, the PWM stop time in the counter reference circuit can be arbitrarily set between 10ms and 10s.

[0094] The edge detection circuit on the left side of Figure 13 is a circuit that detects the rising edge of PWM0. Because the PWM period of the edge detection circuit on the left side is 1 kHz to several hundred kHz (several MHz in the case of GaN (a power semiconductor using gallium nitride)), the circuit latches stop command information at the rising edge in order to synchronize with PWM0. On the other hand, the edge detection circuit on the right side of Figure 13 is a circuit that detects the rising edge of the stop command information. Depending on the content of the stop command information, the edge detection circuit on the right side may change the counter pattern from counter 2 to counter 3. In this case, the load signal of the counter is used, so the rising edge of the stop command information is used as the load signal of the counter.

[0095] Figure 14 is a diagram illustrating the operation of an FPGA. The FPGA operates based on a combination of "redundancy error count" and "CPU shutdown count." The total number of operation patterns is 4 x 4 = 16 (operation patterns 1-16). The "redundancy error count" can be a value between "0" and "3" (4 possibilities). Similarly, the "CPU shutdown count" can also be a value between "0" and "3" (4 possibilities). The FPGA's operation can be controlled by a shutdown detection circuit.

[0096] The "Redundancy Anomaly Count" corresponds to the content of the redundancy anomaly information output to the higher-level CPU. If the "Redundancy Anomaly Information" is "00: Normal", the "Redundancy Anomaly Count" will be "0". If the "Redundancy Anomaly Information" is "01: 1 Device Anomaly", the "Redundancy Anomaly Count" will be "1". If the "Redundancy Anomaly Information" is "10: 2 Device Anomalies", the "Redundancy Anomaly Count" will be "2". If the "Redundancy Anomaly Information" is "11: 3 Device Anomalies", the "Redundancy Anomaly Count" will be "3".

[0097] Furthermore, the "CPU Stop Count" corresponds to the content of the stop command information input from the higher-level CPU. If the "Stop Command Information" is "00: No Stop", the "CPU Stop Count" will be "0". If the "Stop Command Information" is "01: Stop 1 Device", the "CPU Stop Count" will be "1". If the "Stop Command Information" is "10: Stop 2 Devices", the "CPU Stop Count" will be "2". If the "Stop Command Information" is "11: Stop 3 Devices", the "CPU Stop Count" will be "3". Details of FPGA operation are as follows.

[0098] [Operation Pattern 1-4: When the number of redundant errors is 0-3 and the number of CPU shutdowns is 0] Operation: 3 parallel operation Contents: All 3 parallel processes are running. Specific example: In the case of the U-phase Hside in Figure 4, UH1, UH2, and UH3 are operated.

[0099] [Operation Pattern 5: When the number of redundant errors is 0 and the number of CPU shutdowns is 1] Operation: Counter 3 Content: Stopped "1", abnormal "0", so 3 parallel connections are stopped one column at a time. Specific example: In the case of the U-phase Hside in Figure 4, UH1, UH2, and UH3 are stopped one by one alternately.

[0100] [Operation Pattern 6: When the number of redundant errors is 1 and the number of CPU shutdowns is 1] Operation: Redundant abnormal stop Content: Since there are equal numbers of stops and abnormalities, abnormalities are always treated as stops. Specific example: In the case of the U-phase Hside in Figure 4, if UH1 is redundant and malfunctioning, UH1 is always shut down.

[0101] [Operation Pattern 7: When the number of redundant errors is 2 and the number of CPU shutdowns is 1] Operation: Counter 2 Content: Stop "1", Anomaly "2", so stop one column alternately with Anomaly 2 in parallel. Specific example: In the case of the U-phase Hside shown in Figure 4, if UH1 and UH2 are redundant and malfunctioning, one UH1 or UH2 will be shut down alternately.

[0102] [Operation Pattern 8: When the number of redundant errors is 3 and the number of CPU shutdowns is 1] Operation: Counter 3 Content: Stop "1", abnormal "3", therefore, stop one row of abnormal 3 in parallel alternately. Specific example: In the case of the U-phase Hside shown in Figure 4, if UH1, UH2, and UH3 are redundant and abnormal, then UH1, UH2, and UH3 will be shut down one by one alternately.

[0103] [Operation Pattern 9: When the number of redundant errors is 0 and the number of CPU shutdowns is 2] Operation: Counter 3 Content: Stopped "2", abnormal "0", so 3 parallel operations are stopped alternately in 2 rows. Specific example: In the case of the U-phase Hside in Figure 4, two of UH1, UH2, and UH3 are stopped alternately.

[0104] [Operation Pattern 10: When the number of redundant errors is 1 and the number of CPU shutdowns is 2] Operation: Counter 2 Content: There are 2 stops and 1 abnormality, so the abnormal column will always stop, and the remaining 2 columns will alternately stop one column at a time. Specific example: In the case of the U-phase Hside in Figure 4, if UH1 has a redundancy error, UH1 is stopped, and UH2 and UH3 are stopped one by one alternately.

[0105] [Operation Pattern 11: When the number of redundant errors is 2 and the number of CPU shutdowns is 2] Operation: Redundant abnormal stop Content: Since there are equal numbers of stops and abnormalities, abnormalities are always treated as stops. Specific example: In the case of the U-phase Hside shown in Figure 4, if UH1 and UH2 are redundant and malfunctioning, UH1 and UH2 will be shut down.

[0106] [Operation Pattern 12: When the number of redundant errors is 3 and the number of CPU shutdowns is 2] Operation: Counter 3 Content: Stop "2", abnormal "3", therefore abnormal 3 parallel stops are alternately stopped in 2 rows. Specific example: In the case of the U-phase Hside shown in Figure 4, if UH1, UH2, and UH3 are redundant and abnormal, then two of UH1, UH2, and UH3 will be shut down alternately.

[0107] [Operation Pattern 13-16: When the number of redundant errors is 0-3 and the number of CPU shutdowns is 3] Operation: 3 parallel stops Content: All 3 parallel processes have been stopped. Specific example: In the case of the U-phase Hside in Figure 4, UH1, UH2, and UH3 are shut down.

[0108] Thus, the FPGA (stop-down determination circuit) prioritizes stopping the redundant SiC (if there are both normal SiCs and redundant SiCs, it stops the redundant SiC) (switching section).

[0109] Figure 15 shows the details of the judgment circuit. Figure 15(A) shows the circuit configuration, Figure 15(B) shows the details of the stop command information, Figure 15(C) shows the details of the redundant abnormality information, and Figure 15(D) shows a conversion example. The judgment circuit in Figure 15 is the circuit that receives the redundant abnormality judgments No. 1, 2, 3, etc. from Figure 13.

[0110] As shown in Figure 15(A), the determination circuit is a circuit that takes cpu0, 1, red0, and 1 as inputs and outputs sel0 and 1. The topmost exclusive OR circuit receives cpu0 and 1 as inputs, and the result of the operation is input to the two AND circuits, which are output as sel0 and 1. The second exclusive OR gate from the top receives red0 and cpu0 as inputs. The inverted data of the calculation result is input to the AND gate above it, which then passes through the OR gate above it and is input to the AND gate above it, and is output as sel0. The third exclusive OR gate from the top receives inputs red1 and cpu1. The inverted data of the calculation result is input to the AND gate above it, which then passes through the OR gate above it and is input to the AND gate above it, and is output as sel0.

[0111] The fourth exclusive OR gate from the top receives red0 and 1 as inputs, and the result of the operation branches into three. The first result is input to the upper AND gate, passes through the upper OR gate, is input to the upper AND gate, and is output as sel0. The second result is input to the negation gate, passes through the upper and lower OR gates, is input to the upper and lower AND gates, and is output as sel0 and 1. The third result is input to the lower AND gate, passes through the lower OR gate, is input to the lower AND gate, and is output as sel1.

[0112] The fifth exclusive OR gate from the top receives red0 and cpu1 as inputs. The inverted data of the calculation result is input to the AND gate below, which then passes through the OR gate below and is input to the AND gate below that, outputting as sel1. sel0 and sel1 are used as selection data (select information) for the multiplexer.

[0113] Here, the top route in Figure 15(A) corresponds to the route where "all 3 parallel processes are running or stopped" (operation patterns 1-4, 13-16 in Figure 14). Also, the second route from the top in Figure 15(B) corresponds to the route where "number of redundant errors = number of CPU stops" (operation patterns 6, 11 in Figure 14). Furthermore, the third route from the top in Figure 15(C) is the route for using "counter 3" (operation patterns 5, 8, 9, 12 in Figure 14). Also, the fourth route from the top in Figure 15(D) is the route for using "counter 2" (operation patterns 7, 10 in Figure 14).

[0114] As shown in Figure 15(B), the stop command information consists of 2 bits, with 0 bits corresponding to CPU0 and 1 bit corresponding to CPU1.

[0115] As shown in Figure 15(C), the redundancy error information is represented by 2 bits, with 0 bits corresponding to red0 and 1 bit corresponding to red1. The redundancy error information (red0, 1) can be generated by adding redundancy errors No. 1, 2, and 3 using an adder circuit.

[0116] As shown in Figure 15(D), if "redundancy anomaly No. 1, 2, 3" = "0, 0, 0", then "red0, 1" = "0, 0", if "redundancy anomaly No. 1, 2, 3" = "0, 0, 1", then "red0, 1" = "0, 1", if "redundancy anomaly No. 1, 2, 3" = "1, 0, 1", then "red0, 1" = "1, 0", and if "redundancy anomaly No. 1, 2, 3" = "1, 1, 1", then "red0, 1" = "1, 1".

[0117] Figure 16 shows details of the pattern generation circuit, etc. The pattern generation circuit is the circuit located upstream (on the left) of the multiplexer in Figure 13. The pattern generation circuit receives stop command information cpu0, 1, redundancy anomaly judgment No.1, 2, 3, cnt2gs1, 2, 3, and cnt3gs1, 2, 3 as inputs, and processes some of the input data to produce an output.

[0118] CPU0 and CPU1 are input to the OR circuit, and the inverted data of the calculation result is input to the "00" of the top multiplexer, the "00" of the second multiplexer from the top, and the "00" of the third multiplexer from the top.

[0119] Redundancy error detection No. 1 is input to the inverting circuit (negation circuit), and the calculation result is input to "01" of the top multiplexer. cnt2gs1 inputs the original data directly into the top multiplexer, "10". cnt3gs1 inputs the original data directly into "11" of the top multiplexer.

[0120] Redundancy error detection No. 2 is input to the inverting circuit, and the calculation result is input to "01" of the second multiplexer from the top. cnt2gs2 inputs the data directly into "10" of the second multiplexer from the top. cnt3gs2 inputs the data directly into "11" of the second multiplexer from the top.

[0121] Redundancy error detection No. 3 is input to the inverting circuit, and the calculation result is input to "01" of the third multiplexer from the top. cnt2gs3 inputs the data directly into "10," the third multiplexer from the top. cnt3gs3 inputs the data directly into "11," the third multiplexer from the top.

[0122] The 2-bit select information (sel0, 1) is input to three multiplexers, and the output result from each multiplexer is selected. For example, if "sel0, 1" = "0, 0", the input value "00" of the multiplexer is output from the multiplexer. Also, if "sel0, 1" = "0, 1", the input value "01" of the multiplexer is output from the multiplexer. Furthermore, if "sel0, 1" = "1, 0", the input value "10" of the multiplexer is output from the multiplexer. And if "sel0, 1" = "1, 1", the input value "11" of the multiplexer is output from the multiplexer.

[0123] The output values ​​of the three multiplexers are then input to the AND gate, and the results of the calculation with PWM1in, 2in, and 3in are output as PWM1out, 2out, and 3out. Note that the three AND gates on the right side of Figure 16 are the same as the three AND gates on the right side of Figure 13, and the latch gate is omitted in Figure 16.

[0124] Furthermore, the redundancy anomaly determination No. 1, 2, and 3 are "anomaly: 1, normal: 0". Also, cnt2gs1, 2, and 3 use the signal of counter 2. In addition, cnt3gs1, 2, and 3 use the signal of counter 3. In this embodiment, two types of counters (counter 2 and counter 3) are used. Counter 2 represents a counter that repeats two events, and counter 3 represents a counter that repeats three events.

[0125] Figure 17 illustrates the two counters used in the pattern generation circuit. Figure 17(A) shows the circuit configuration of the counter circuit, and Figure 17(B) shows the details of counters 2 and 3. As shown in Figure 17(A), the counter circuit uses a 2-bit down counter, receiving 2-bit inputs (0-bit, 1-bit), Load, Enable, and Clock, and outputting 2-bit outputs (0-bit, 1-bit) and Carry. Note that the counter circuit may also be an up counter.

[0126] The details of the counter circuit are as follows: Load: If Load is High when the Clock starts up, InputData is output to Output. Enable: If Enable is High when Clock starts up, the countdown will begin. However, if Load is High, Load takes precedence. When Carry:OutputData is "zero", Carry is High.

[0127] As shown in the upper and lower sections of Figure 17(B), the pattern generation circuit uses two counters, Counter 2 and Counter 3. Counter 2 is a down counter that repeats "1" → "0" → "1" → "0" → ... More specifically, bit 0 of Counter 2's Output alternates between High and Low, while bit 1 of Counter 2's Output remains Low.

[0128] Counter 3 is a down counter that repeats "2" → "1" → "0" → "2" → "1" → "0" → ... More specifically, bit 0 of Counter 3's Output repeats "Low → High → Low", and bit 1 of Counter 3's Output repeats "High → Low → Low".

[0129] In counters 2 and 3, the duration for which the signal is high or low (pulse width) can be arbitrarily set between 10ms and 10s. This pulse width can be set using the counter reference circuit shown in Figure 13. The pulse width (duration) set using the counter reference circuit in Figure 13 becomes the time for stopping the PWM (the time for stopping the SiC).

[0130] Figure 18 shows the details of counter 2. Figures 18(A) and (B) show the timing charts for counter 2, cnt2gs1, 2, and 3, and Figure 18(C) shows the circuit configuration.

[0131] Figure 18(A) shows the timing chart for the case of "Redundancy Anomaly 2 (Number of Redundancy Anomalies = 2) / Stop Command 1 (Number of CPU Stops = 1)". The 0th bit of counter 2 alternates between Low and High. cnt2gs1 is a waveform (pulse) where the 0th bit of counter 2 is inverted. cnt2gs2 remains High. cnt2gs3 has the same waveform as the 0th bit of counter 2.

[0132] Figure 18(B) shows the timing chart for the case of "Redundancy Anomaly 1 (Number of Redundancy Anomalies = 1) / Stop Command 2 (Number of CPU Stops = 2)". The 0th bit of counter 2 alternates between Low and High. cnt2gs1 remains Low. cnt2gs2 is a waveform where the 0th bit of counter 2 is inverted. cnt2gs3 has the same waveform as the 0th bit of counter 2.

[0133] The circuit shown in Figure 18(C) is the circuit that realizes the operation shown in Figures 18(A) and (B). The circuit shown in Figure 18(C) is a circuit that receives bit 0 of counter 2, redundancy error judgment No. 1, 2, and 3, and operation details as input, and outputs cnt2gs1, 2, and 3.

[0134] The 0th bit of counter 2 is input to the top exclusive OR gate, and the result of the operation is input to the "1" of the top multiplexer and the third exclusive OR gate from the top. Redundancy error detection No. 1 is input to the second exclusive OR circuit from the top, and the calculation result is input to the top exclusive OR circuit and as selection data for the top multiplexer. Redundancy error detection No. 2 is input to the fourth exclusive OR circuit from the top, and the calculation result is input as selection data for the third exclusive OR circuit from the top and the second multiplexer from the top. Redundancy error detection No. 3 is input to the sixth exclusive OR circuit from the top, and the calculation result is input as selection data for the fifth exclusive OR circuit from the top and the third multiplexer from the top.

[0135] The topmost exclusive OR gate not only outputs its result to the "1" of the topmost multiplexer, but also outputs its result to the third exclusive OR gate from the top. Similarly, the third exclusive OR gate from the top not only outputs its result to the "1" of the second multiplexer from the top, but also outputs its result to the fifth exclusive OR gate from the top.

[0136] The operation is "0" in the case of "Redundancy Anomaly 2 / Stop Command 1" and "1" in the case of "Redundancy Anomaly 1 / Stop Command 2". The operation is input to the second, fourth, and sixth exclusive OR circuits from the top, and the inverted data is input to "0" of each multiplexer. Then, cnt2gs1, 2, and 3 are output from each multiplexer.

[0137] The results of each exclusive OR circuit are as follows (the same applies to Figure 19). If input A=0 and input B=0, then output O=0. If input A=0 and input B=1, then output O=1. If input A=1 and input B=0, then output O=1. If input A=1 and input B=1, then output O=0.

[0138] Figure 19 shows the details of counter 3. Figures 19(A) and (B) show the timing charts for counter 3, cnt3gs1, 2, and 3, and Figure 19(C) shows the circuit configuration.

[0139] Figure 19(A) shows the timing chart for the cases of "Redundancy Anomaly 3 (Number of Redundancy Anomalies = 3) / Stop Command 2 (Number of CPU Stops = 2)" or "Redundancy Anomaly 0 (Number of Redundancy Anomalies = 0) / Stop Command 2 (Number of CPU Stops = 2)". The 0th bit of counter 3 repeats "Low → High → Low". Each bit of counter 3 repeats the pattern "High → Low → Low". cnt3gs1 repeats "Low → Low → High". cnt3gs2 repeats "Low → High → Low". cnt3gs3 repeats "High → Low → Low".

[0140] Figure 19(B) shows the timing chart for the cases of "Redundancy Anomaly 3 (Number of Redundancy Anomalies = 3) / Stop Command 1 (Number of CPUs Stopped = 1)" or "Redundancy Anomaly 0 (Number of Redundancy Anomalies = 0) / Stop Command 1 (Number of CPUs Stopped = 1)". The 0th bit of counter 3 repeats "Low → High → Low". Each bit of counter 3 repeats the pattern "High → Low → Low". cnt3gs1 repeats "High → High → Low". cnt3gs2 repeats "High → Low → High". cnt3gs3 repeats "Low → High → High".

[0141] The circuit shown in Figure 19(C) is the circuit that realizes the operation shown in Figures 19(A) and (B). The circuit shown in Figure 19(C) is a circuit that receives the 0th bit, 1st bit, and operation details of counter 3 as input and outputs cnt3gs1, 2, and 3.

[0142] Bits 0 and 1 of counter 3 are input to the OR circuit, and the inverted data of the calculation result is input to the uppermost exclusive OR circuit. The 0th bit of counter 3 is input to the second exclusive OR circuit from the top. One bit of counter 3 is input to the third exclusive OR circuit from the top.

[0143] The operation is "0" if the error is "Redundancy Anomaly 3 / Stop Command 2" or "Redundancy Anomaly 0 / Stop Command 2", and "1" if the error is "Redundancy Anomaly 3 / Stop Command 1" or "Redundancy Anomaly 0 / Stop Command 1". The operation is input to three exclusive OR circuits. Then, cnt3gs1, 2, and 3 are output from each multiplexer.

[0144] Figure 20 shows the operation of stop command information. As shown in Figure 20, PWM0 is output in the FPGA, and PWM1in, 2in, and 3in are generated based on PWM0. Here, we assume that while PWM1in, 2in, and 3in (PWM1out, 2out, and 3out) are initially high, a stop command is input from the higher-level CPU to the FPGA (see arrow A in the diagram). In this case, the stop command information is latched (held) in the latch circuit, so PWM1out, 2out, and 3out will not stop in this state. The stop command information latch (stop command information latched by the latch circuit) becomes active on the next rising edge of PWM0, and based on the stop command information latch, for example, PWM2out stops (see arrow B in the diagram).

[0145] Thus, the FPGA (stop-determining circuit) will stop the PWM output only after the PWM output has finished, if there is a PWM output in progress. In other words, when the FPGA (stop-determining circuit) stops a SiC (semiconductor element), it will not stop a SiC that is currently being driven (switching section).

[0146] Figure 21 shows an example of the operation of Simulation 1. Simulation 1 shows an example of operation when the stop command information is "0→1→2→1→0" and all three SiCs connected in parallel are normal (redundancy error judgment No. 1=0, redundancy error judgment No. 2=0, redundancy error judgment No. 3=0).

[0147] If the stop command information is "0", PWM1out, 2out, and 3out will not stop. If the stop command information is "1", PWM1out, 2out, and 3out will stop one at a time, alternating between each other. If the stop command information is "2", then any two of the PWM1out, 2out, and 3out will stop alternately. Note that when PWM stops (stops the PWM output), it means that the corresponding SiC also stops.

[0148] Figure 22 shows an example of the operation of Simulation 2. Simulation 2 shows an example of operation when the stop command information is "0→1→2→1→0" and only the second of the three SiCs connected in parallel is abnormal (redundancy abnormality judgment No. 1=0, redundancy abnormality judgment No. 2=1, redundancy abnormality judgment No. 3=0).

[0149] If the stop command information is "0", PWM1out, 2out, and 3out will not stop. If the stop command information is "1", only PWM2out will stop. If the stop command information is "2", PWM2out will stop, while either PWM1out or PWM3out will stop alternately.

[0150] Figure 23 shows an example of the operation of Simulation 3. Simulation 3 shows an example of operation when the stop command information is "0→1→2→1→0" and the first and second SiCs among the three SiCs connected in parallel are abnormal (redundancy abnormality judgment No. 1=1, redundancy abnormality judgment No. 2=1, redundancy abnormality judgment No. 3=0).

[0151] If the stop command information is "0", PWM1out, 2out, and 3out will not stop. If the stop command information is "1", either PWM1out or PWM2out will stop alternately. If the stop command information is "2", PWM1out and 2out will stop.

[0152] Figure 24 shows an example of the operation of Simulation 4. Simulation 4 shows an example of operation when the stop command information is "0→1→2→1→0", all three parallel-connected Highside SiCs are normal (redundancy error judgment No.1=0, redundancy error judgment No.2=0, redundancy error judgment No.3=0), and the second of the three parallel-connected Lowside SiCs is abnormal (redundancy error judgment No.1=0, redundancy error judgment No.2=1, redundancy error judgment No.3=0).

[0153] [Highside] If the stop command information is "0", PWM1out, 2out, and 3out will not stop. If the stop command information is "1", PWM1out, 2out, and 3out will stop one at a time alternately. If the stop command information is "2", then any two of the PWM1out, 2out, and 3out will stop alternately.

[0154] [Lowside] If the stop command information is "0", PWM1out, 2out, and 3out will not stop. If the stop command information is "1", only PWM2out will stop. If the stop command information is "2", PWM2out will stop, while either PWM1out or PWM3out will stop alternately.

[0155] Thus, the FPGA (stop determination circuit) can make the PWM stop point different on the high-side and low-side even with the same stop command information. In other words, the SiC (semiconductor element) includes high-side and low-side SiCs, and the FPGA (stop determination circuit) can make the driving mode of the high-side SiC and the low-side SiC different even with the same stop command information (switching section).

[0156] Figure 25 shows the relationship between current and time in SiC. The solid lines in the diagram represent the actual current values, while the dashed lines represent the target current values. For example, let's consider a car with the accelerator pedal fully depressed. In this case, the target current value is represented by a dashed line, but the actual current value rises with a delay, as shown by the solid line, and reaches the target current value over time. In this case, the SiC (power device) operates in 3 parallel configurations, and the current value rises to 100%. Now, by releasing the accelerator, the SiC switches from driving in 3 parallel configurations to 2 parallel configurations (current value around 66%), and when the accelerator is pressed again, the SiC drives in 3 parallel configurations (current value 100%).

[0157] If a redundancy anomaly occurs in one row of SiCs, and the accelerator is pressed continuously in this state, the target current value would normally reach 100% (as shown by the dashed line). However, by switching the SiC drive from 3 parallel to 2 parallel based on the redundancy anomaly detection result, the current value can be reduced to 66%. This prevents the SiC with the redundancy anomaly from being continuously driven.

[0158] Figure 26 is a block diagram showing the details of the control board. The configuration of the control board is merely an example and can be freely changed according to the system specifications. The control board 12 includes an ADC (digital converter) 51 that digitally converts the current values ​​Ia and Ib between the inverter 50 and the motor 17 and the voltage value V of the inverter 50; a communication unit 53 that receives information from the speed instruction unit 52; a timer unit 54 that manages time; a motor information receiving unit 55 that receives information from the motor 17 (A phase, B phase, Z phase, etc.); an input / output unit 56 that outputs PWM signals and stop command information to the inverter 50 and receives redundant abnormal information from the inverter 50; and a control unit 57 that controls these. The inverter 50 includes the FPGA, GDM, SiC, etc. mentioned above.

[0159] The control unit 57 may generate stop command information based on redundant abnormal information input from the inverter 50, or it may generate stop command information without relying on redundant abnormal information (for example, by monitoring the status of the motor 17).

[0160] The control board 12 can minimize the total loss of the SiC (power device) included in the inverter 50. The control board 12 can minimize the total loss of the SiC by changing the number of SiCs driven according to the rotational speed and torque of the motor 17. The rotational speed and torque of the motor 17 can be calculated based on the information received by the motor information receiving unit 55. The higher-level CPU 12a, which manages the rotational speed and torque of the motor 17, calculates the total loss of the SiCs, determines the optimal number of SiCs driven, and can transmit stop command information to the FPGA (inverter 50). Upon receiving the stop command information, the FPGA can distribute the operation by switching which SiCs to stop at regular intervals. However, if there is a redundancy anomaly, it is preferable for the FPGA to prioritize stopping the SiC with the redundancy anomaly. The FPGA transmits the redundancy anomaly information to the higher-level CPU 12a, and the higher-level CPU 12a can reduce the output current to an appropriate value and then output stop command information to the FPGA. Based on the stop command information, the FPGA can stop the PWM and stop the SiCs.

[0161] As described above, this embodiment has the following advantages. (1) According to this embodiment, since multiple SiCs are operated by switching between SiCs (semiconductor elements) that are stopped at regular intervals, the amount of time that the SiCs are not operating can be increased compared to a method in which all SiCs are kept running, and as a result, the degradation of the SiCs can be reduced. Furthermore, if one SiC is kept running continuously, the SiC will degrade quickly, so by stopping the SiCs alternately, the possibility of degradation can be distributed.

[0162] (2) According to this embodiment, if there is a redundant SiC, the redundant SiC is stopped preferentially (see Figure 14), so the location where the abnormality occurred can be stopped quickly, and as a result, the degradation of the semiconductor device can be reduced.

[0163] (3) According to this embodiment, since the SiC is not stopped while in operation (see Figure 20), it is possible to avoid situations in which the SiC is suddenly stopped while in operation and unintended pulses are generated.

[0164] (4) According to this embodiment, even with the same stop command information, it is possible to make the driving modes of the high-side SiC and the low-side SiC different (see Figure 24), so that flexible control can be performed according to the occurrence of redundancy abnormalities.

[0165] (5) According to this embodiment, it is possible to determine whether or not the SiC (semiconductor element) is in an abnormal state by comparing the delay time (time difference) of the PWM (output signal) and Sync (input signal) with a predetermined fixed time.

[0166] (6) According to this embodiment, the redundancy abnormality determination circuit (Figure 10) determines that a system is redundant when the number of occurrences of an abnormal state reaches five (a predetermined number of times). Therefore, cases where an abnormal state is determined to occur only once by chance due to false detection, etc., can be excluded from the redundancy abnormality determination.

[0167] (7) According to this embodiment, when the redundancy abnormality determination circuit (Figure 10) or the maximum value determination circuit (Figure 12) determines that there is a redundancy abnormality, it outputs the redundancy abnormality information to the higher-level CPU (a part separate from the determination unit), so that the higher-level CPU 12a can use the redundancy abnormality information to perform control.

[0168] (8) According to this embodiment, the redundant abnormality detection circuit (Figure 10) does not perform an abnormality detection when the SiC is at a low current (when the current state of the semiconductor element is in a special state, or when Sync may become unstable), thus improving the reliability of the detection compared to a control method that uniformly performs an abnormality detection.

[0169] (9) According to this embodiment, the redundant abnormality consecutive count counter (number of occurrences of abnormal state) is initialized when the system transitions from an abnormal state to a normal state, so when the system transitions to a normal state, the redundancy abnormality determination can be restarted from the beginning.

[0170] (10) According to this embodiment, the redundant abnormality consecutive count counter (number of occurrences of abnormal conditions) is not initialized when an abnormal condition is not determined. Therefore, even if a situation occurs where an abnormal condition is not determined once or multiple times by chance due to false detection or the like, the redundancy abnormality determination can be continued.

[0171] (11) According to the first configuration example of this embodiment (Figure 4), the redundant abnormal information includes the maximum number of the six groups of SiC (information aggregating information from multiple semiconductor elements), so sufficient information can be output even if the number of terminals for outputting information is small.

[0172] (12) According to the second configuration example of this embodiment (Figure 5), the redundant abnormal information includes all of the information of the 18 SiCs (information of multiple semiconductor elements), so all of the information of the 18 SiCs can be output.

[0173] (13) The FPGA30 has a maximum operating frequency of several hundred MHz, so the time measurement resolution is several nanoseconds. Therefore, it is difficult to measure delay times with a resolution greater than the operating frequency (less than 4 ns). In this embodiment, a circuit is provided that improves the resolution (a circuit capable of measuring delay time with a resolution of 1 nsec) by using a PLL (phase-locked loop) circuit configuration.

[0174] [Transformed form] The present invention can be implemented in various ways without being limited to the embodiments described above. (1) The output signal was explained using the PWM example, but other signals may also be used. The input signal was explained using the Sync example, but other signals may also be used. (2) Although the SiC was described using a 4-terminal example, a 3-terminal SiC may also be used. If a 3-terminal SiC is used and the terminals of the driver source T3 are eliminated, a shunt resistor can be placed next to the coil 16 or motor 17, and the waveform of the shunt resistor can be used to output a waveform (input signal) to the FPGA that replaces the Sync signal.

[0175] (3) The determination unit may determine that a redundant abnormality has occurred when the number of occurrences of the abnormal condition reaches one, or it may output a message to that effect to a part other than the determination unit when the number of occurrences of the abnormal condition reaches one. The part other than the determination unit was explained in the example of the upper CPU 12a, but it may be any part of the FPGA 30. (4) The FPGA (determination unit) may not output the abnormal state or redundancy abnormality to a part other than the determination unit, but may use the abnormal state or redundancy abnormality within the FPGA to perform control.

[0176] (5) The determination unit may determine an abnormal state even if the current state of the semiconductor device is in a special state. The special state is not limited to low current, but may also be high current. The special state may be a state in which the current state of the SiC is within or outside a predetermined range of a certain value. (6) The number of occurrences of an abnormal state does not need to be reset if the system transitions from an abnormal state to a normal state. The number of occurrences of an abnormal state may be reset if no abnormal state check is performed.

[0177] (7) The content of the redundant anomaly information is arbitrary. The redundant anomaly information only needs to include information on at least one semiconductor device. The redundant anomaly information does not need to be output. (8) The determination result of the determination unit may be stored without being output, or it may be monitored by an external device.

[0178] (9) Some explanations have been omitted regarding rising edge, falling edge, PWM, and Sync, but the control content of one process can be modified to suit the control content of other processes and reused. (10) In addition, the structures and circuit configurations shown with reference in the embodiments are merely preferred examples, and various elements can be added to the basic structure, some configurations can be replaced, or some configurations can be deleted. Furthermore, the configuration of the control board and each circuit configuration can be changed to a different configuration.

[0179] (11) Even if there is a redundant semiconductor element, it is not necessary to prioritize the shutdown of the redundant semiconductor element. (12) When the switching unit stops a semiconductor element, it may stop a semiconductor element that is currently in operation. (13) If the stop command information is the same, the driving mode of the high-side semiconductor element and the low-side semiconductor element may be the same.

[0180] (14) The stop command information generation unit, switching unit, time measurement unit, and determination unit may be partially included in the higher-level CPU and the remainder in the FPGA. The division of each unit can be freely changed. The stop command information generation unit, switching unit, time measurement unit, and determination unit may all be included in the higher-level CPU. The stop command information generation unit, switching unit, time measurement unit, and determination unit may all be included in the FPGA. The control system may include a higher-level CPU and an FPGA, or it may be a system that includes an FPGA but does not include a higher-level CPU, or it may be a system that includes a higher-level CPU but does not include an FPGA. [Explanation of Symbols]

[0181] 10 Control Systems 11 Power supply 12 Control board 12a Upper CPU 13, 14, 15 Power switching devices 16 coils 17 Motor 20a 1st GDM 20b 2nd GDM 20c 3rd GDM 20d Control effective range detection circuit 20-1 1st GDM H / L for U phase 20-2 2nd GDM H / L for U phase 20-3 3rd GDM H / L for U phase 20-4 1st GDM H / L for V phase 2nd GDM H / L for 20-5 V phase 20-6 3rd GDM H / L for V phase 20-7 1st GDM H / L for W phase 20-8 2nd GDM H / L for W phase 20-9 3rd GDM H / L for W phase 30 FPGA 40-1 U phase Hside circuit 40-2 U phase Lside circuit 40-3 V phase Hside circuit 40-4 V phase Lside circuit 40-5 W phase Hside circuit 40-6 W phase Lside circuit 41 Filter detection circuit 42a First delay circuit 42b Second delay circuit 42c Third delay circuit 43 Stop judgment circuit 44 Time difference measurement circuit 45 Delay Time Determination Circuit 46 Delay Time Measurement Circuit 47 Redundant abnormality judgment circuit 50 Inverters 51 ADC 52 Speed ​​indicator 53 Communications Department 54 Timer section 55 Motor Information Receiving Unit 56 Input / output section 57 Control Unit

Claims

1. A control system for controlling multiple semiconductor elements, A stop command information generation unit generates stop command information relating to the stopping of the plurality of semiconductor elements, A switching unit that operates the plurality of semiconductor elements by switching the semiconductor elements that are stopped at regular intervals in accordance with the stop command information, A control system equipped with the following features.

2. In the control system according to claim 1, A drive circuit device for driving the aforementioned semiconductor element, A time measurement unit that outputs an output signal to the drive circuit device, receives an input signal based on the output signal from the drive circuit device, and measures the time from when the output signal is output until the input signal is received, The system includes a determination unit that determines that the semiconductor element is in an abnormal state if the measurement result from the time measurement unit is outside a predetermined range of time, The determination unit determines that if the number of occurrences of the abnormal state reaches a predetermined number of times, the abnormal state is a redundant abnormality in which the abnormal state occurred consecutively. The control system is characterized in that, when the switching unit has a redundant semiconductor element, it preferentially shuts down the semiconductor element with the redundant abnormality.

3. In the control system according to claim 1, The control system is characterized in that, when the switching unit stops the semiconductor element, it does not stop the semiconductor element that is currently in operation.

4. In the control system according to claim 1, The semiconductor element includes high-side and low-side semiconductor elements. The control system is characterized in that the switching unit can make the driving modes of the high-side semiconductor element and the low-side semiconductor element different, even when the same stop command information is provided.

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