Semiconductor devices and semiconductor memory devices

Abstract

To provide a semiconductor device with excellent transistor characteristics. [Solution] The semiconductor device of the embodiment comprises a first electrode, a second electrode, an oxide semiconductor layer between the first electrode and the second electrode, a gate electrode, a first insulating layer between the first electrode and the gate electrode, a second insulating layer between the gate electrode and the second electrode, and a gate insulating layer between the gate electrode, the first insulating layer, and the second insulating layer and the oxide semiconductor layer. When the thickness of the gate insulating layer between the first insulating layer and the oxide semiconductor layer is defined as the first thickness, the thickness of the gate insulating layer between the second insulating layer and the oxide semiconductor layer is defined as the second thickness, the thickness of the gate insulating layer between the first end of the gate electrode on the first electrode side and the oxide semiconductor layer is defined as the third thickness, and the thickness of the gate insulating layer between the second end of the gate electrode on the second electrode side and the oxide semiconductor layer is defined as the fourth thickness, the second thickness is greater than the first thickness, or the fourth thickness is greater than the third thickness.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device.

Background Art

[0002] An oxide semiconductor transistor that forms a channel in an oxide semiconductor layer has excellent characteristics such that the channel leakage current during the off operation is extremely small. For this reason, for example, it is possible to apply an oxide semiconductor transistor to a switching transistor of a memory cell of a Dynamic Random Access Memory (DRAM).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] 4] The problem to be solved by the present invention is to provide a semiconductor device with excellent transistor characteristics.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment comprises a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode facing the oxide semiconductor layer, a first insulating layer provided between the first electrode and the gate electrode, a second insulating layer provided between the gate electrode and the second electrode, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, between the first insulating layer and the oxide semiconductor layer, and between the second insulating layer and the oxide semiconductor layer, wherein in a first cross section parallel to a first direction connecting the first electrode and the second electrode, the first insulating layer and the oxide semiconductor layer If the thickness of the gate insulating layer in the second direction perpendicular to the first direction at the first position between the two layers is defined as the first thickness, the thickness of the gate insulating layer in the second direction at the second position between the second insulating layer and the oxide semiconductor layer is defined as the second thickness, the thickness of the gate insulating layer in the second direction at the third position between the first end of the gate electrode on the first electrode side and the oxide semiconductor layer is defined as the third thickness, and the thickness of the gate insulating layer in the second direction at the fourth position between the second end of the gate electrode on the second electrode side and the oxide semiconductor layer is defined as the fourth thickness, then the second thickness is greater than the first thickness, or the fourth thickness is greater than the third thickness. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 17] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 18] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] Schematic cross-sectional view of a comparative semiconductor device. [Figure 20] A schematic cross-sectional view showing an example of a manufacturing method for a semiconductor device in a comparative example. [Figure 21] A schematic cross-sectional view showing an example of a manufacturing method for a semiconductor device in a comparative example. [Figure 22] A schematic cross-sectional view showing an example of a manufacturing method for a semiconductor device in a comparative example. [Figure 23] A schematic cross-sectional view of a semiconductor device of a first modified example of the first embodiment. [Figure 24] A schematic cross-sectional view of a semiconductor device of a second modified example of the first embodiment. [Figure 25] A schematic cross-sectional view of a semiconductor device of a third modified example of the first embodiment. [Figure 26]Schematic cross-sectional view of the semiconductor device of the second embodiment. [Figure 27] Schematic cross-sectional view of the semiconductor device of the third embodiment. [Figure 28] Schematic cross-sectional view of the semiconductor device of the first modification of the third embodiment. [Figure 29] Schematic cross-sectional view of the semiconductor device of the second modification of the third embodiment. [Figure 30] Equivalent circuit diagram of the semiconductor memory device of the fourth embodiment. [Figure 31] Schematic cross-sectional view of the semiconductor memory device of the fourth embodiment.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.

[0008] In addition, in this specification, the terms "upper", "lower", "upper part", or "lower part" may be used for convenience. "Upper", "lower", "upper part", or "lower part" are terms indicating the relative positional relationship in the drawing and are not terms defining the positional relationship with respect to gravity.

[0009] Qualitative and quantitative analysis of the chemical composition of components constituting semiconductor devices and semiconductor memory devices described herein can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or Rutherford back-scattering spectroscopy (RBS). Furthermore, a transmission electron microscope (TEM) can be used to measure the thickness, distance between components, and grain size of components constituting semiconductor devices and semiconductor memory devices. Additionally, X-ray photoelectron spectroscopy (XPS), hard X-ray photoelectron spectroscopy (HAXPES), or electron energy loss spectroscopy (EELS) can be used to identify the constituent materials of semiconductor devices and semiconductor memory devices and to measure the relative abundance of those materials.

[0010] In this specification, "metal" refers to a general term for substances that exhibit metallic properties, and for example, metal compounds such as metal nitrides and metal carbides that exhibit metallic properties are included in the scope of "metal".

[0011] (First embodiment) The semiconductor device of the first embodiment comprises a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode facing the oxide semiconductor layer, a first insulating layer provided between the first electrode and the gate electrode, a second insulating layer provided between the gate electrode and the second electrode, and gate insulating layers provided between the gate electrode and the oxide semiconductor layer, between the first insulating layer and the oxide semiconductor layer, and between the second insulating layer and the oxide semiconductor layer. In a first cross-section parallel to the first direction connecting the first electrode and the second electrode, if the thickness of the gate insulating layer in the second direction perpendicular to the first direction at the first position between the first insulating layer and the oxide semiconductor layer is defined as the first thickness, the thickness of the gate insulating layer in the second direction at the second position between the second insulating layer and the oxide semiconductor layer is defined as the second thickness, the thickness of the gate insulating layer in the second direction at the third position between the first end of the gate electrode on the first electrode side and the oxide semiconductor layer is defined as the third thickness, and the thickness of the gate insulating layer in the second direction at the fourth position between the second end of the gate electrode on the second electrode side and the oxide semiconductor layer is defined as the fourth thickness, then the second thickness is greater than the first thickness, or the fourth thickness is greater than the third thickness.

[0012] Figures 1, 2, 3, and 4 are schematic cross-sectional views of a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view of Figure 1 at AA'. Figure 3 is a cross-sectional view of Figure 1 at BB'. Figure 4 is a cross-sectional view of Figure 1 at CC'.

[0013] In Figure 1, the vertical direction is referred to as the first direction. In Figure 1, the horizontal direction is referred to as the second direction. The second direction is perpendicular to the first direction. The first direction is the direction connecting the lower electrode 12 and the upper electrode 14.

[0014] Figure 1 is a cross-section parallel to the first direction. Figure 1 is an example of the first cross-section.

[0015] The semiconductor device of the first embodiment is a transistor 100. Transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. Transistor 100 has a gate electrode that surrounds the oxide semiconductor layer in which the channel is formed. Transistor 100 is a so-called Gate All Around (GAA) transistor. Transistor 100 is a so-called vertical transistor.

[0016] The transistor 100 comprises a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a first interlayer insulating layer 22, and a second interlayer insulating layer 24. The gate electrode 18 includes a first portion 18a and a second portion 18b. The first interlayer insulating layer 22 includes a third portion 22a and a fourth portion 22b. The second interlayer insulating layer 24 includes a fifth portion 24a and a sixth portion 24b.

[0017] The lower electrode 12 is an example of the first electrode. The upper electrode 14 is an example of the second electrode. The first interlayer insulating layer 22 is an example of the first insulating layer. The second interlayer insulating layer 24 is an example of the second insulating layer.

[0018] The lower electrode 12 is provided beneath the oxide semiconductor layer 16. The lower electrode 12 is electrically connected to the oxide semiconductor layer 16. The lower electrode 12 is in contact with the oxide semiconductor layer 16, for example. The lower electrode 12 functions as either the source electrode or the drain electrode of the transistor 100.

[0019] The lower electrode 12 is a conductor. The lower electrode 12 includes, for example, an oxide conductor. The lower electrode 12 is, for example, an oxide conductor layer.

[0020] The lower electrode 12 includes, for example, indium (In), tin (Sn), and oxygen (O). The lower electrode 12 includes, for example, indium tin oxide. The lower electrode 12 is, for example, an indium tin oxide layer.

[0021] The lower electrode 12 contains, for example, tin (Sn) and oxygen (O). The lower electrode 12 contains, for example, tin oxide. The lower electrode 12 is, for example, a tin oxide layer.

[0022] The lower electrode 12 contains, for example, a metal. The lower electrode 12 is, for example, a metal layer.

[0023] The lower electrode 12 includes, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), zinc (Zn), or tantalum (Ta). The lower electrode 12 is, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, a zinc layer, or a tantalum layer.

[0024] The lower electrode 12 may, for example, have a laminated structure of multiple conductors. The lower electrode 12 may, for example, have a laminated structure of an oxide conductor layer and a metal layer. For example, the surface of the lower electrode 12 on the side of the oxide semiconductor layer 16 is the oxide conductor layer.

[0025] The upper electrode 14 is provided on the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. The upper electrode 14 is in contact with the oxide semiconductor layer 16, for example. The upper electrode 14 functions as the source electrode or drain electrode of the transistor 100.

[0026] The upper electrode 14 is a conductor. The upper electrode 14 includes, for example, an oxide conductor. The upper electrode 14 is, for example, an oxide conductor layer.

[0027] The upper electrode 14 includes, for example, indium (In), tin (Sn), and oxygen (O). The upper electrode 14 includes, for example, indium tin oxide. The upper electrode 14 is, for example, an indium tin oxide layer.

[0028] The upper electrode 14 contains, for example, tin (Sn) and oxygen (O). The upper electrode 14 contains, for example, tin oxide. The upper electrode 14 is, for example, a tin oxide layer.

[0029] The upper electrode 14 contains, for example, a metal. The upper electrode 14 is, for example, a metal layer.

[0030] The upper electrode 14 includes, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). The upper electrode 14 is, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0031] The upper electrode 14 may, for example, have a laminated structure of multiple conductors. The upper electrode 14 may, for example, have a laminated structure of an oxide conductor layer and a metal layer. For example, the surface of the upper electrode 14 on the side of the oxide semiconductor layer 16 is the oxide conductor layer.

[0032] The lower electrode 12 and the upper electrode 14 are formed from, for example, the same material. The lower electrode 12 and the upper electrode 14 are, for example, oxide conductors containing indium (In), tin (Sn), and oxygen (O). The lower electrode 12 and the upper electrode 14 contain, for example, indium tin oxide. The lower electrode 12 and the upper electrode 14 are, for example, indium tin oxide layers.

[0033] The oxide semiconductor layer 16 is provided between the lower electrode 12 and the upper electrode 14. The oxide semiconductor layer 16 is in contact with, for example, the lower electrode 12. The oxide semiconductor layer 16 is in contact with, for example, the upper electrode 14.

[0034] A channel is formed in the oxide semiconductor layer 16 that serves as a current path when the transistor 100 is turned on.

[0035] The oxide semiconductor layer 16 is an oxide semiconductor. For example, the oxide semiconductor layer 16 is amorphous.

[0036] The oxide semiconductor layer 16 includes, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), as well as zinc (Zn) and oxygen (O). The oxide semiconductor layer 16 includes, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The oxide semiconductor layer 16 includes, for example, indium gallium zinc oxide. The oxide semiconductor layer 16 is, for example, an indium gallium zinc oxide layer.

[0037] The oxide semiconductor layer 16 includes, for example, at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W), and oxygen (O). The oxide semiconductor layer 16 includes, for example, titanium oxide, zinc oxide, or tungsten oxide. The oxide semiconductor layer 16 is, for example, a titanium oxide layer, a zinc oxide layer, or a tungsten oxide layer.

[0038] The oxide semiconductor layer 16 has a chemical composition different from, for example, the chemical composition of the lower electrode 12 and the chemical composition of the upper electrode 14.

[0039] The oxide semiconductor layer 16 contains oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 16 function as donors.

[0040] The length of the oxide semiconductor layer 16 in the first direction is, for example, 40 nm to 200 nm. The length of the oxide semiconductor layer 16 in the second direction is, for example, 10 nm to 100 nm.

[0041] The first width in the second direction (w1 in Figure 1) of the portion of the oxide semiconductor layer 16 that is in contact with the lower electrode 12 is substantially equal to, for example, the second width in the second direction (w2 in Figure 1) of the portion of the oxide semiconductor layer 16 that is in contact with the upper electrode 14.

[0042] The gate electrode 18 faces the oxide semiconductor layer 16. The gate electrode 18 is positioned such that its position coordinate in the first direction is between the position coordinates of the lower electrode 12 and the upper electrode 14 in the first direction.

[0043] As shown in Figure 2, the gate electrode 18 is provided surrounding the oxide semiconductor layer 16. The gate electrode 18 is provided around the oxide semiconductor layer 16.

[0044] The gate electrode 18 is a conductor. The gate electrode 18 is, for example, a metal, a metallic compound, or a semiconductor. The gate electrode 18 includes, for example, tungsten (W).

[0045] The length of the gate electrode 18 in the first direction is, for example, between 10 nm and 100 nm.

[0046] The gate electrode 18 includes a first portion 18a and a second portion 18b in a first cross-section parallel to the first direction. In the second direction, an oxide semiconductor layer 16 is provided between the first portion 18a and the second portion 18b.

[0047] The gate electrode 18 has a first end E1 on the lower electrode 12 side and a second end E2 on the upper electrode 14 side.

[0048] The gate insulating layer 20 is provided between the gate electrode 18 and the oxide semiconductor layer 16. As shown in Figure 2, the gate insulating layer 20 is provided surrounding the oxide semiconductor layer 16. The gate insulating layer 20 is provided between the lower electrode 12 and the upper electrode 14.

[0049] The gate insulating layer 20 is provided between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. The gate insulating layer 20 is provided between the second interlayer insulating layer 24 and the oxide semiconductor layer 16.

[0050] The gate insulating layer 20 is in contact with, for example, the lower electrode 12. The gate insulating layer 20 is in contact with, for example, the upper electrode 14. The gate insulating layer 20 is separated from, for example, the lower electrode 12. The gate insulating layer 20 is separated from, for example, the upper electrode 14.

[0051] The gate insulating layer 20 is, for example, an oxide, nitride, or oxynitride. The gate insulating layer 20 includes, for example, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride. The gate insulating layer 20 is, for example, a silicon oxide layer, an aluminum oxide layer, a titanium oxide layer, a tantalum oxide layer, a hafnium oxide layer, a silicon nitride layer, an aluminum nitride layer, or a silicon oxynitride layer.

[0052] The gate insulating layer 20 may have, for example, a multilayer structure. The thickness of the gate insulating layer 20 is, for example, 2 nm or more and 10 nm or less.

[0053] In the first cross-section, the thickness of the gate insulating layer 20 in the second direction at the first position (P1 in Figure 1) between the first interlayer insulating layer 22 and the oxide semiconductor layer 16 is defined as the first thickness (t1 in Figure 1), the thickness of the gate insulating layer 20 in the second direction at the second position (P2 in Figure 1) between the second interlayer insulating layer 24 and the oxide semiconductor layer 16 is defined as the second thickness (t2 in Figure 1), the thickness of the gate insulating layer 20 in the second direction at the third position (P3 in Figure 1) between the first end of the gate electrode 18 on the side of the lower electrode 12 (E1 in Figure 1) and the oxide semiconductor layer 16 is defined as the third thickness (t3 in Figure 1), and the thickness of the gate insulating layer 20 in the second direction at the fourth position (P4 in Figure 1) between the second end of the gate electrode 18 on the side of the upper electrode 14 (E2 in Figure 1) and the oxide semiconductor layer 16 is defined as the fourth thickness (t4 in Figure 1).

[0054] The second thickness t2 is thicker than the first thickness t1, or the fourth thickness t4 is thicker than the third thickness t3. Figure 1 illustrates the case where the second thickness t2 is thicker than the first thickness t1, and the fourth thickness t4 is thicker than the third thickness t3.

[0055] The second thickness t2 is, for example, 1.1 times or more and 1.5 times or less the first thickness t1. Also, the fourth thickness t4 is, for example, 1.1 times or more and 1.5 times or less the third thickness t3.

[0056] In transistor 100, the thickness of the gate insulating layer 20 is greater in the portion closer to the upper electrode 14 than in the portion closer to the lower electrode 12. For example, the thickness of the gate insulating layer 20 increases in the direction from the lower electrode 12 towards the upper electrode 14.

[0057] The first interlayer insulating layer 22 is provided between the lower electrode 12 and the gate electrode 18. The first interlayer insulating layer 22 includes a third portion 22a and a fourth portion 22b in a first plane. In a second direction, an oxide semiconductor layer 16 is provided between the third portion 22a and the fourth portion 22b. In a second direction, a gate insulating layer 20 is provided between the third portion 22a and the fourth portion 22b.

[0058] As shown in Figure 3, the first interlayer insulating layer 22 surrounds the gate insulating layer 20 and the oxide semiconductor layer 16.

[0059] The first interlayer insulating layer 22 is in contact with the gate insulating layer 20. The third portion 22a is in contact with the gate insulating layer 20. The fourth portion 22b is in contact with the gate insulating layer 20. The first interlayer insulating layer 22 is in contact with the lower electrode 12.

[0060] A second interlayer insulating layer 24 is provided between the gate electrode 18 and the upper electrode 14. The second interlayer insulating layer 24 includes a fifth portion 24a and a sixth portion 24b in the first plane. In the second direction, an oxide semiconductor layer 16 is provided between the fifth portion 24a and the sixth portion 24b. In the second direction, a gate insulating layer 20 is provided between the fifth portion 24a and the sixth portion 24b.

[0061] As shown in Figure 4, the second interlayer insulating layer 24 surrounds the gate insulating layer 20 and the oxide semiconductor layer 16.

[0062] The second interlayer insulating layer 24 is in contact with the gate insulating layer 20. The fifth portion 24a is in contact with the gate insulating layer 20. The sixth portion 24b is in contact with the gate insulating layer 20. The second interlayer insulating layer 24 is in contact with the upper electrode 14.

[0063] The first interlayer insulating layer 22 and the second interlayer insulating layer 24 are insulators. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 are, for example, oxides, nitrides, or oxynitrides. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 include, for example, silicon (Si) and oxygen (O). The first interlayer insulating layer 22 and the second interlayer insulating layer 24 include, for example, silicon oxide. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 are, for example, silicon oxide. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 include, for example, silicon (Si) and nitrogen (N). The first interlayer insulating layer 22 and the second interlayer insulating layer 24 include, for example, silicon nitride. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 are, for example, silicon nitride.

[0064] The first interlayer insulating layer 22 and the second interlayer insulating layer 24 may be formed of different materials.

[0065] The first distance in the second direction (d1 in Figure 1) between the portion of the third portion 22a that contacts the lower electrode 12 and the portion of the fourth portion 22b that contacts the lower electrode 12 is smaller than the second distance in the second direction (d2 in Figure 1) between the portion of the fifth portion 24a that contacts the upper electrode 14 and the portion of the sixth portion 24b that contacts the upper electrode 14. In the first plane, the outer boundary of the gate insulating layer 20 extends from the lower electrode 12 toward the upper electrode 14. The outer boundary of the gate insulating layer 20 has a so-called forward taper shape.

[0066] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0067] Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are schematic cross-sectional views showing an example of a manufacturing method for a semiconductor device according to the first embodiment. Figures 5 to 18 each show a cross-section corresponding to Figure 1. Figures 5 to 18 are diagrams showing an example of a manufacturing method for transistor 100.

[0068] The following explanation will be given using the example of a transistor 100 where the lower electrode 12 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a silicon oxide layer, and the first interlayer insulating layer 22 and the second interlayer insulating layer 24 are silicon oxide layers.

[0069] First, a first silicon oxide film 31, a tungsten film 32, and a second silicon oxide film 33 are formed on the first indium tin oxide film 30 (Figure 5). The first silicon oxide film 31, the tungsten film 32, and the second silicon oxide film 33 are formed, for example, by the Chemical Vapor Deposition (CVD) method.

[0070] The first indium tin oxide film 30 ultimately becomes the lower electrode 12. A portion of the first silicon oxide film 31 ultimately becomes the first interlayer insulating layer 22. A portion of the tungsten film 32 ultimately becomes the gate electrode 18. A portion of the second silicon oxide film 33 ultimately becomes the second interlayer insulating layer 24.

[0071] Next, an opening 34 is formed from the surface of the second silicon oxide film 33, penetrating the tungsten film 32 and the first silicon oxide film 31, and reaching the first indium tin oxide film 30 (Figure 6). The opening 34 has a forward taper shape, for example, with the opening diameter decreasing toward the first indium tin oxide film 30. The opening 34 is formed, for example, using lithography and reactive ion etching (RIE).

[0072] Next, a first silicon nitride film 35 is formed inside the opening 34 (Figure 7). The first silicon nitride film 35 is formed, for example, by the Atomic Layer Deposition (ALD) method.

[0073] Next, a second silicon nitride film 36 is formed inside the opening 34 (Figure 8). The second silicon nitride film 36 is formed, for example, by a CVD method which has lower step coverage than the ALD method. The second silicon nitride film 36 is formed such that the film thickness at the top of the opening 34 is thicker than the film thickness at the bottom of the opening 34.

[0074] Next, the first silicon nitride film 35 at the bottom of the opening 34 is etched to expose the first indium tin oxide film 30 (Figure 9). The first silicon nitride film 35 is etched using the RIE method.

[0075] When etching the first silicon nitride film 35, the surfaces of the second silicon nitride film 36 and the first silicon nitride film 35 are exposed to RIE, thus inflicting processing damage.

[0076] Next, the opening 34 is filled with a titanium nitride film 37 (Figure 10). The titanium nitride film 37 is formed, for example, by the ALD method. In a later process step, when the first silicon nitride film 35 and the second silicon nitride film 36 are removed by etching, an aluminum oxide film can be used instead of the titanium nitride film 37, provided that a selectivity ratio with silicon nitride can be ensured.

[0077] Next, the upper part of the titanium nitride film 37 is removed, leaving the titanium nitride film 37 only inside the opening 34 (Figure 11). The upper part of the titanium nitride film 37 is removed, for example, by chemical mechanical polishing (CMP).

[0078] Next, the first silicon nitride film 35 and the second silicon nitride film 36 are removed by etching (Figure 12). The titanium nitride film 37 remains in a columnar shape within the opening 34. For example, a wet etching method is used to remove the first silicon nitride film 35 and the second silicon nitride film 36.

[0079] Next, the opening 34 is filled with a third silicon oxide film 38 (Figure 13). The third silicon oxide film 38 is formed in the area where the second silicon nitride film 36 and the first silicon nitride film 35 were removed. The third silicon oxide film 38 is formed, for example, by the ALD method. Since the opening 34 has a shape that widens from the bottom to the top, the embedding of the third silicon oxide film 38 is improved. A portion of the third silicon oxide film 38 eventually becomes the gate insulating layer 20.

[0080] Next, the upper part of the third silicon oxide film 38 is removed, leaving the third silicon oxide film 38 only inside the opening 34 (Figure 14). The upper part of the third silicon oxide film 38 is removed, for example, by the CMP method.

[0081] Next, the columnar titanium nitride film 37 inside the opening 34 is removed (Figure 15). For example, a wet etching method is used to remove the titanium nitride film 37.

[0082] Next, the opening 34 is filled with an indium gallium zinc oxide film 39 (Figure 16). The indium gallium zinc oxide film 39 is formed, for example, by the ALD method. A portion of the indium gallium zinc oxide film 39 eventually becomes the oxide semiconductor layer 16.

[0083] Next, the upper part of the indium gallium zinc oxide film 39 is removed, leaving the indium gallium zinc oxide film 39 only inside the opening 34 (Figure 17). The upper part of the indium gallium zinc oxide film 39 is removed, for example, by the CMP method.

[0084] Next, a second indium tin oxide film 40 is formed on the indium gallium zinc oxide film 39 (Figure 18). The second indium tin oxide film 40 is formed, for example, by sputtering. The second indium tin oxide film 40 ultimately becomes the upper electrode 14.

[0085] By the above manufacturing method, the transistor 100 shown in Figures 1 to 4 is manufactured.

[0086] The operation and effects of the semiconductor device according to the first embodiment will be described below.

[0087] Oxide semiconductor transistors, which form channels in an oxide semiconductor layer, possess the excellent characteristic of extremely low channel leakage current during off-operation. For this reason, for example, the application of oxide semiconductor transistors to switching transistors in DRAM memory cells is being considered. Because the channel leakage current during off-operation is extremely low, applying oxide semiconductor transistors to switching transistors improves the charge retention characteristics of DRAM.

[0088] Figure 19 is a schematic cross-sectional view of a comparative example semiconductor device. Figure 19 corresponds to Figure 1 of the semiconductor device of the first embodiment.

[0089] The comparative semiconductor device is transistor 900. Transistor 900 is an oxide semiconductor transistor. Transistor 900 differs from transistor 100 of the first embodiment in that the first thickness t1, second thickness t2, third thickness t3, and fourth thickness t4 of the gate insulating layer 20 are equal. Transistor 900 also differs from transistor 100 in that the thickness of the gate insulating layer 20 in the second direction in the first cross-section is constant between the lower electrode 12 and the upper electrode 14.

[0090] Figures 20, 21, and 22 are schematic cross-sectional views showing an example of a semiconductor device manufacturing method for a comparative example. Figures 20, 21, and 22 each show a cross-section corresponding to Figure 19. Figures 20, 21, and 22 are diagrams showing an example of a manufacturing method for transistor 900.

[0091] The manufacturing method for the semiconductor device is the same as in the first embodiment until an opening 34 is formed that penetrates the tungsten film 32 and the first silicon oxide film 31 from the surface of the second silicon oxide film 33 and reaches the first indium tin oxide film 30.

[0092] Next, a silicon oxide film 42 is formed inside the opening 34 (Figure 20). The silicon oxide film 42 is formed, for example, by the ALD method. A portion of the silicon oxide film 42 will eventually become the gate insulating layer 20.

[0093] Next, the silicon oxide film 42 at the bottom of the opening 34 is etched to expose the first indium tin oxide film 30 (Figure 21). The silicon oxide film 42 is etched using the RIE method.

[0094] When etching the silicon oxide film 42, the surface of the silicon oxide film 42 is exposed to RIE, resulting in processing damage.

[0095] Subsequently, similar to the manufacturing method of the first embodiment, the opening 34 is filled with an indium gallium zinc oxide film 39, and then a second indium tin oxide film 40 is formed on top of the indium gallium zinc oxide film 39 (Figure 22).

[0096] The transistor 900 shown in Figure 19 is manufactured using the above manufacturing method.

[0097] In the manufacturing method of the comparative example transistor 900, when etching the silicon oxide film 42 at the bottom of the opening 34, the surface of the silicon oxide film 42 that will become the gate insulating layer 20 is exposed to etching, causing processing damage. As a result, for example, the reliability of the gate insulating layer 20 of the transistor 900 is reduced.

[0098] In the first embodiment of the transistor 100, the thickness of the gate insulating layer 20 is greater in the portion closer to the upper electrode 14 than in the portion closer to the lower electrode 12. By making the gate insulating layer 20 thicker in the portion closer to the upper electrode 14 than in the portion closer to the lower electrode 12, a transistor manufacturing method can be realized that improves the reliability of the gate insulating layer 20.

[0099] In the manufacturing method of the transistor 100 according to the first embodiment, a first silicon nitride film 35 and a second silicon nitride film 36 are formed inside the opening 34 (Figure 8). Then, the first silicon nitride film 35 at the bottom of the opening 34 is etched to expose the first indium tin oxide film 30 (Figure 9). At this time, the surfaces of the second silicon nitride film 36 and the first silicon nitride film 35 are exposed to RIE, and thus suffer processing damage. However, the second silicon nitride film 36 and the first silicon nitride film 35 are removed as shown in Figure 12 and are therefore not used in the gate insulating layer 20.

[0100] In the transistor 100 of the first embodiment, a third silicon oxide film 38 is formed in the region where the second silicon nitride film 36 and the first silicon nitride film 35 have been removed (Figure 13), and the third silicon oxide film 38 is used as the gate insulating layer 20. The portion of the third silicon oxide film 38 used as the gate insulating layer 20 is not exposed to RIE and is not subjected to processing damage. Therefore, the reliability of the gate insulating layer 20 of transistor 100 is improved compared to the comparative example transistor 900.

[0101] In the transistor 100 of the first embodiment, the gate insulating layer 20 is thicker in the portion closer to the upper electrode 14 than in the portion closer to the lower electrode 12. Therefore, in the manufacturing method of the transistor 100, the opening 34 used to embed the third silicon oxide film 38 has a shape that widens at the top compared to the bottom (Figure 12). This improves the embedding ability of the third silicon oxide film 38. Consequently, for example, a situation in which the third silicon oxide film 38 cannot be embedded between the gate electrode 18 and the oxide semiconductor layer 16, and the gate insulating layer 20 is not formed, can be avoided.

[0102] Furthermore, in the transistor 100 of the first embodiment, the gate insulating layer 20 closer to the upper electrode 14 is thicker than the gate insulating layer 20 closer to the lower electrode 12. Therefore, for example, the asymmetry in the on-current flowing between the lower electrode 12 and the upper electrode 14 can be adjusted depending on the direction of the current.

[0103] In transistor 100, the fourth thickness t4 of the gate insulating layer 20 between the second end E2 of the gate electrode 18 and the oxide semiconductor layer 16 is greater than the third thickness t3 of the gate insulating layer 20 between the first end E1 of the gate electrode 18 and the oxide semiconductor layer 16. Therefore, for example, the channel resistance directly below the second end E2 of the gate electrode 18 is higher than the channel resistance directly below the first end E1 of the gate electrode 18.

[0104] Furthermore, the second thickness t2 of the gate insulating layer 20 between the second interlayer insulating layer 24 and the oxide semiconductor layer 16 is greater than the first thickness t1 of the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. Therefore, the strength of the fringe electric field applied from the gate electrode 18 is weaker in the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 than in the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12. Consequently, for example, the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 is greater than the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12.

[0105] From the above perspective, when transistor 100 is in the ON state, electrons become less likely to flow, for example, from the upper electrode 14 to the lower electrode 12. In other words, when transistor 100 is in the ON state, an asymmetry in the ON current occurs, where current becomes less likely to flow, for example, from the lower electrode 12 to the upper electrode 14.

[0106] For example, there may be a difference between the contact resistance of the lower electrode 12 and the oxide semiconductor layer 16 and the contact resistance of the upper electrode 14 and the oxide semiconductor layer 16. In the ON state, electrons may flow more easily from the lower electrode 12 to the upper electrode 14. In this case, an asymmetry in the ON current occurs, making it difficult for current to flow from the upper electrode 14 to the lower electrode 12.

[0107] In the transistor 100 of the first embodiment, for example, the on-current asymmetry that can be achieved by the difference in the thickness of the gate insulating layer 20 can cancel out the on-current asymmetry caused by the contact resistance between the lower electrode 12 and the upper electrode 14 and the oxide semiconductor layer 16. Therefore, according to the transistor 100 of the first embodiment, it is possible to suppress on-current asymmetry. Furthermore, if asymmetry in the magnitude of the on-current of the transistor 100 is required, it is possible to achieve on-current asymmetry. In this way, according to the transistor 100, the on-current asymmetry can be adjusted.

[0108] As described above, according to the first embodiment, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0109] (First variation) The semiconductor device of the first modified embodiment differs from the semiconductor device of the first embodiment in that the first width in the second direction of the portion of the oxide semiconductor layer in contact with the first electrode in the first cross-section is smaller than the second width in the second direction of the portion of the oxide semiconductor layer in contact with the second electrode in the first cross-section.

[0110] Figure 23 is a schematic cross-sectional view of a semiconductor device of a first modification of the first embodiment. Figure 23 corresponds to Figure 1 of the first embodiment.

[0111] The semiconductor device of the first modification of the first embodiment is a transistor 101. The first width in the second direction (w1 in Figure 23) of the portion of the oxide semiconductor layer 16 in contact with the lower electrode 12 is smaller than the second width in the second direction (w2 in Figure 23) of the portion of the oxide semiconductor layer 16 in contact with the upper electrode 14. The width of the oxide semiconductor layer 16 increases, for example, from the lower electrode 12 toward the upper electrode 14. The oxide semiconductor layer 16 has a so-called forward taper shape.

[0112] According to the first modification of the first embodiment, transistor 101, the reliability of the gate insulating layer 20 is improved, similar to transistor 100 of the first embodiment. Furthermore, the contact area between the upper electrode 14 and the oxide semiconductor layer 16 can be made larger than the contact area between the lower electrode 12 and the oxide semiconductor layer 16. Therefore, for example, the contact resistance between the upper electrode 14 and the oxide semiconductor layer 16 can be reduced.

[0113] The fourth thickness t4 of the gate insulating layer 20 between the second end E2 of the gate electrode 18 and the oxide semiconductor layer 16 is greater than the third thickness t3 of the gate insulating layer 20 between the first end E1 of the gate electrode 18 and the oxide semiconductor layer 16. Therefore, for example, if the oxide semiconductor layer 16 does not have a tapered shape, the channel resistance directly below the second end E2 of the gate electrode 18 will be higher than the channel resistance directly below the first end E1 of the gate electrode 18. In other words, an asymmetry in channel resistance occurs. Therefore, for example, an asymmetry in on-current may occur.

[0114] According to transistor 101, the oxide semiconductor layer 16 has a forward tapered shape, which allows the area of ​​the oxide semiconductor layer 16 facing the second end E2 of the gate electrode 18 to be larger than the area of ​​the oxide semiconductor layer 16 facing the first end E1 of the gate electrode 18 in a plane perpendicular to the first direction. Therefore, the asymmetry of the channel resistance is mitigated and the asymmetry of the on-current is suppressed.

[0115] As described above, according to the first modification of the first embodiment, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized, similar to the first embodiment.

[0116] (Second variation) The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first embodiment in that the first width in the second direction of the portion of the oxide semiconductor layer in contact with the first electrode in the first cross-section is greater than the second width in the second direction of the portion of the oxide semiconductor layer in contact with the second electrode in the first cross-section.

[0117] Figure 24 is a schematic cross-sectional view of a semiconductor device of a second modification of the first embodiment. Figure 24 corresponds to Figure 1 of the first embodiment.

[0118] A semiconductor device of the second modification of the first embodiment is a transistor 102. The first width in the second direction (w1 in Figure 24) of the portion of the oxide semiconductor layer 16 in contact with the lower electrode 12 is greater than the second width in the second direction (w2 in Figure 24) of the portion of the oxide semiconductor layer 16 in contact with the upper electrode 14. The width of the oxide semiconductor layer 16 decreases, for example, from the lower electrode 12 toward the upper electrode 14. The oxide semiconductor layer 16 has a so-called reverse tapered shape.

[0119] According to the transistor 102, a second modification of the first embodiment, the reliability of the gate insulating layer 20 is improved, similar to the transistor 100 of the first embodiment. Furthermore, the contact area between the lower electrode 12 and the oxide semiconductor layer 16 can be made larger than the contact area between the upper electrode 14 and the oxide semiconductor layer 16. Therefore, for example, the contact resistance between the lower electrode 12 and the oxide semiconductor layer 16 can be reduced.

[0120] As described above, according to the second modification of the first embodiment, the reliability of the gate insulating layer 20 is improved, similar to the first embodiment, and a semiconductor device with excellent transistor characteristics is realized.

[0121] (Third variation) The semiconductor device of the third modification of the first embodiment differs from the semiconductor device of the first embodiment in that the gate insulating layer provided between the first insulating layer and the oxide semiconductor layer has a void.

[0122] Figure 25 is a schematic cross-sectional view of a semiconductor device of a third modified example of the first embodiment. Figure 25 corresponds to Figure 1 of the first embodiment.

[0123] A semiconductor device of the third modified form of the first embodiment is a transistor 103. In the transistor 103, the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16 has a void 44. The gate insulating layer 20 between the gate electrode 18 and the lower electrode 12 also has a void 44. For example, in the manufacturing method of the semiconductor device of the first embodiment, it is possible to form a void in the gate insulating layer 20 by adjusting the deposition conditions of the third silicon oxide film 38 which ultimately becomes the gate insulating layer 20.

[0124] There are no voids 44 in the gate insulating layer 20 between the second interlayer insulating layer 24 and the oxide semiconductor layer 16, and in the gate insulating layer 20 between the gate electrode 18 and the oxide semiconductor layer 16.

[0125] The second thickness t2 of the gate insulating layer 20 between the second interlayer insulating layer 24 and the oxide semiconductor layer 16 is greater than the first thickness t1 of the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. Therefore, for example, if there is no void in the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16, the strength of the fringe electric field applied from the gate electrode 18 will be weaker in the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 than in the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12.

[0126] Therefore, for example, the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 is greater than the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12. Thus, an asymmetry occurs in the parasitic resistance of the transistor.

[0127] In the third modified version of the first embodiment, transistor 103 has a gap 44 in the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. The dielectric constant of the gap is lower than, for example, the dielectric constant of oxides and nitrides. Therefore, compared to the case where there is no gap 44 in the gate insulating layer 20, the strength of the fringe electric field applied to the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12 is reduced. Therefore, for example, the difference between the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 and the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12 becomes smaller. Thus, the upper-lower asymmetry of the parasitic resistance of the transistor is suppressed.

[0128] According to the transistor 103, a third modification of the first embodiment, the reliability of the gate insulating layer 20 is improved, similar to the transistor 100 of the first embodiment. Furthermore, the presence of an air gap 44 in the gate insulating layer 20 between the gate electrode 18 and the lower electrode 12 suppresses the upper-lower asymmetry of the parasitic resistance of the transistor 103.

[0129] As described above, according to the third modification of the first embodiment, the reliability of the gate insulating layer 20 is improved, similar to the first embodiment, and a semiconductor device with excellent transistor characteristics is realized.

[0130] As described above, according to the first embodiment and its modifications, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0131] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the gate insulating layer provided between the second insulating layer and the oxide semiconductor layer, and the gate insulating layer provided between the gate electrode and the oxide semiconductor layer, contain different materials from the gate insulating layer provided between the first insulating layer and the oxide semiconductor layer. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0132] Figure 26 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. Figure 26 corresponds to Figure 1 of the first embodiment.

[0133] The semiconductor device of the second embodiment is a transistor 200. In the transistor 200, the gate insulating layer 20 provided between the second interlayer insulating layer 24 and the oxide semiconductor layer 16, and the gate insulating layer 20 provided between the gate electrode 18 and the oxide semiconductor layer 16, contain different materials from the gate insulating layer 20 provided between the first interlayer insulating layer 22 and the oxide semiconductor layer 16.

[0134] As shown in Figure 26, the first region 20a is a part of the gate insulating layer 20 provided between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. The second region 20b is a part of the gate insulating layer 20 provided between the second interlayer insulating layer 24 and the oxide semiconductor layer 16. The third region 20c is a part of the gate insulating layer 20 provided between the gate electrode 18 and the oxide semiconductor layer 16. The second region 20b and the third region 20c contain different materials from the first region 20a.

[0135] The first region 20a includes, for example, silicon nitride. The first region 20a is formed of, for example, silicon nitride. The second region 20b includes, for example, silicon oxide. The second region 20b is formed of, for example, silicon oxide. The third region 20c includes, for example, silicon oxide. The third region 20c is formed of, for example, silicon oxide.

[0136] The transistor 200 of the second embodiment can be formed, for example, in the semiconductor device manufacturing method of the first embodiment, by removing the first silicon nitride film 35 and the second silicon nitride film 36 by etching (Figure 12), while leaving a portion of the first silicon nitride film 35 in the opening 34.

[0137] For example, by including a material with a different dielectric constant in the second region 20b than in the first region 20a, the strength of the fringe electric field between the gate electrode 18 and the oxide semiconductor layer 16 can be adjusted. Therefore, for example, the difference between the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 and the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12 can be adjusted to achieve optimal transistor characteristics.

[0138] As described above, according to the second embodiment, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0139] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the gate insulating layer includes a first film provided between the gate electrode and the oxide semiconductor layer and containing a first material, and a second film provided between the first film and the oxide semiconductor layer and containing a second material different from the first material, and the gate insulating layer further includes a third film provided between the second film and the oxide semiconductor layer and containing the first material. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0140] Figure 27 is a schematic cross-sectional view of a semiconductor device according to the third embodiment. Figure 27 corresponds to Figure 1 of the first embodiment.

[0141] The semiconductor device of the third embodiment is a transistor 300. The gate insulating layer 20 of the transistor 300 includes a first film 20x, a second film 20y, and a third film 20z. The gate insulating layer 20 of the transistor 300 includes a laminated film of the first film 20x, the second film 20y, and the third film 20z.

[0142] The first film 20x and the second film 20y, and the second film 20y and the third film 20z are, for example, in contact with each other. The first film 20x and the third film 20z are, for example, physically continuous on the side of the lower electrode 12 of the gate insulating layer 20.

[0143] The first film 20x contains the first material. The second film 20y contains the second material. The third film 20z contains the first material. The first film 20x and the third film 20z contain the same material.

[0144] The first film 20x is formed from, for example, the first material. The second film 20y is formed from, for example, the second material. The third film 20z is formed from, for example, the first material. The first film 20x and the third film 20z are formed from, for example, the same material.

[0145] The first material is, for example, an oxide, nitride, or oxynitride. The first material is, for example, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride.

[0146] The second material is different from the first material. The third material is, for example, an oxide, nitride, or oxynitride. The first material is, for example, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride.

[0147] For example, the first material is a nitride and the second material is an oxide. For example, the first material is silicon nitride and the second material is silicon oxide.

[0148] The second material is, for example, a material having a higher dielectric constant than the first material. The second material is, for example, a material having a higher dielectric constant than silicon oxide. For example, the first material is silicon oxide and the second material is titanium oxide. For example, the first material is silicon nitride and the second material is titanium oxide.

[0149] If the second material has a higher dielectric constant than the first material, for example, in the first cross-section, the fifth thickness (t5 in Figure 27) of the second film 20y between the first end E1 of the gate electrode 18 and the oxide semiconductor layer 16 is thinner than the sixth thickness (t6 in Figure 27) of the second film 20y between the second end E2 of the gate electrode 18 and the oxide semiconductor layer 16.

[0150] In transistor 300, the fourth thickness t4 of the gate insulating layer 20 between the second end E2 of the gate electrode 18 and the oxide semiconductor layer 16 is greater than the third thickness t3 of the gate insulating layer 20 between the first end E1 of the gate electrode 18 and the oxide semiconductor layer 16. Therefore, for example, the channel resistance directly below the second end E2 of the gate electrode 18 is higher than the channel resistance directly below the first end E1 of the gate electrode 18.

[0151] However, in transistor 300, by making the second material a material having a higher dielectric constant than the first material, and making the fifth thickness t5 of the second film 20y thinner than the sixth thickness t6 of the second film 20y, the difference between the equivalent oxide thickness (EOT) of the gate insulating layer 20 at the fourth position P4 and the equivalent oxide thickness of the gate insulating layer 20 at the third position P3 can be reduced. Therefore, the difference between the channel resistance directly below the second end E2 of the gate electrode 18 and the channel resistance directly below the first end E1 of the gate electrode 18 can be reduced.

[0152] The transistor 300 of the third embodiment can be manufactured, for example, in the semiconductor device manufacturing method of the first embodiment, by using a multilayer film instead of the third silicon oxide film 38 when filling the opening 34 with the third silicon oxide film 38 which will ultimately become the gate insulating layer 20.

[0153] The transistor 300 of the third embodiment, like the first embodiment, has improved reliability of the gate insulating layer 20. Furthermore, the transistor characteristics of the transistor 300 are further improved by using a multilayer film for the gate insulating layer 20.

[0154] (First variation) The semiconductor device of the first modification of the third embodiment differs from the semiconductor device of the third embodiment in that the first film is separated from the first electrode.

[0155] Figure 28 is a schematic cross-sectional view of the semiconductor device of the first modified example of the third embodiment. Figure 28 corresponds to Figure 27 of the third embodiment.

[0156] The semiconductor device of the first modified example of the third embodiment is a transistor 301. The gate insulating layer 20 of the transistor 301 includes a first film 20x, a second film 20y, a third film 20z, and a fourth film 20w.

[0157] The first membrane 20x is separated from the lower electrode 12 in a first direction. The second membrane 20y is separated from the lower electrode 12 in a first direction. The third membrane 20z is separated from the lower electrode 12 in a first direction.

[0158] A fourth membrane 20w is provided between the first membrane 20x and the lower electrode 12. A fourth membrane 20w is provided between the second membrane 20y and the lower electrode 12. A fourth membrane 20w is provided between the third membrane 20z and the lower electrode 12.

[0159] The fourth film 20w includes a third material. The third material is, for example, a different material from the second material. The third material is, for example, an oxide, nitride, or oxynitride. The third material is, for example, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride.

[0160] The transistor 301 of the first modification of the third embodiment has improved reliability of the gate insulating layer 20, similar to the first embodiment. Furthermore, the transistor characteristics of the transistor 301 are further improved by using a multilayer film for the gate insulating layer 20.

[0161] (Second variation) The semiconductor device of the second modification of the third embodiment differs from the semiconductor device of the third embodiment in that the gate insulating layer does not include the third film.

[0162] Figure 29 is a schematic cross-sectional view of a semiconductor device of a second modified example of the third embodiment. Figure 29 corresponds to Figure 27 of the third embodiment.

[0163] The semiconductor device of the second modification of the third embodiment is a transistor 302. The gate insulating layer 20 of the transistor 302 includes a first film 20x and a second film 20y. Unlike the gate insulating layer 20 of the third embodiment, the gate insulating layer 20 of the transistor 302 does not include a third film 20z.

[0164] The transistor 302 of the second modification of the third embodiment has improved reliability of the gate insulating layer 20, similar to the first embodiment. Furthermore, the transistor characteristics of the transistor 302 are further improved by using a multilayer film for the gate insulating layer 20.

[0165] As described above, according to the third embodiment and its modifications, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0166] (Fourth embodiment) The semiconductor memory device of the fourth embodiment comprises the semiconductor device of the first embodiment and a capacitor electrically connected to either the first electrode or the second electrode.

[0167] The semiconductor memory device of the fourth embodiment is a semiconductor memory 400. The semiconductor memory device of the fourth embodiment is a DRAM. The semiconductor memory 400 uses the transistor 100 of the first embodiment as a switching transistor for the memory cell of the DRAM.

[0168] In the following, some descriptions that overlap with the first embodiment will be omitted.

[0169] Figure 30 is an equivalent circuit diagram of a semiconductor memory device according to the fourth embodiment. Although Figure 30 illustrates the case where there is one memory cell MC, multiple memory cell MCs may be provided, for example, in an array.

[0170] The semiconductor memory 400 comprises a memory cell MC, a word line WL, a bit line BL, and a plate line PL. The memory cell MC includes a switching transistor TR and a capacitor CA. In Figure 30, the region enclosed by the dashed line is the memory cell MC.

[0171] The word wire WL is electrically connected to the gate electrode of the switching transistor TR. The bit wire BL is electrically connected to one of the source and drain electrodes of the switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source and drain electrodes of the switching transistor TR. The other electrode of capacitor CA is connected to the plate wire PL.

[0172] Memory cells (MC) store data by accumulating electric charge in capacitors (CA). Data is written to and read by turning on a switching transistor (TR).

[0173] For example, a switching transistor TR is turned on while a desired voltage is applied to the bit line BL, and data is written to the memory cell MC.

[0174] Furthermore, for example, by turning on a switching transistor TR, the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor is detected, and data from the memory cell MC is read out.

[0175] Figure 31 is a schematic cross-sectional view of a semiconductor memory device according to the fourth embodiment. Figure 31 shows a cross-section of the memory cell MC of the semiconductor memory 400.

[0176] The semiconductor memory 400 includes a silicon substrate 10, a switching transistor TR, a capacitor CA, a lower insulating layer 50, and an upper insulating layer 52.

[0177] The switching transistor TR comprises a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a first interlayer insulating layer 22, and a second interlayer insulating layer 24.

[0178] The switching transistor TR has the same structure as the transistor 100 in the first embodiment.

[0179] Capacitor CA is provided between the silicon substrate 10 and the switching transistor TR. Capacitor CA is provided between the silicon substrate 10 and the lower electrode 12. Capacitor CA is electrically connected to the lower electrode 12. It is also possible to configure capacitor CA to be electrically connected to the upper electrode 14.

[0180] The capacitor CA comprises a cell electrode 71, a plate electrode 72, and a capacitor insulating film 73. The cell electrode 71 is electrically connected to the lower electrode 12. The cell electrode 71 is, for example, in contact with the lower electrode 12.

[0181] The cell electrode 71 and plate electrode 72 are made of, for example, titanium nitride. The capacitor insulating film 73 has a layered structure of, for example, zirconium oxide, aluminum oxide, and zirconium oxide.

[0182] The gate electrode 18 is electrically connected to, for example, a word line WL (not shown). The upper electrode 14 is electrically connected to, for example, a bit line BL (not shown). The plate electrode 72 is connected to, for example, a plate line PL (not shown).

[0183] The semiconductor memory 400 applies an oxide semiconductor transistor with extremely low channel leakage current during off-operation to the switching transistor TR. Therefore, a DRAM with excellent charge retention characteristics is realized.

[0184] Furthermore, the switching transistor TR of the semiconductor memory 400 has a highly reliable gate insulating layer 20. Therefore, the reliability of the semiconductor memory 400 is improved.

[0185] In the fourth embodiment, a semiconductor memory to which the transistor of the first embodiment is applied was described as an example, but the semiconductor memory of the embodiment of the present invention may also be a semiconductor memory to which the transistor of the second embodiment or the third embodiment is applied.

[0186] According to the semiconductor memory device of the fourth embodiment, a semiconductor memory device with excellent transistor characteristics can be realized.

[0187] In the first to third embodiments, a GAA transistor in which a gate electrode is provided surrounding an oxide semiconductor layer in which a channel is formed was described as an example. However, the transistor in the embodiment of the present invention may be, for example, a double-gate transistor in which gate electrodes are provided opposite each other in two directions of the oxide semiconductor layer in which the channel is formed, or a tri-gate transistor in which gate electrodes are provided opposite each other in three directions of the oxide semiconductor layer in which the channel is formed.

[0188] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0189] 12 Lower electrode (first electrode) 14. Upper electrode (second electrode) 16 Oxide semiconductor layer 18 Guard gate 18a Part 1 18b Part 2 20 Gate insulating layer 20x First membrane 20y Second membrane 20z Third membrane 22 First interlayer insulating layer (first insulating layer) 22a Third part 22b Part 4 24. Second interlayer insulating layer (second insulating layer) 24a Part 5 24b Part 6 44 void 100 Transistors (Semiconductor Devices) 110 Transistors (Semiconductor Devices) 120 Transistors (Semiconductor Devices) 130 Transistors (Semiconductor Devices) 200 Transistors (Semiconductor Equipment) 300 Transistors (Semiconductor Devices) 310 Transistors (Semiconductor Devices) 320 Transistors (Semiconductor Equipment) 400 Semiconductor memory (semiconductor storage device) d1 First distance d2 Second distance t1 First thickness t2 Second thickness t3 Third thickness t4 Fourth thickness t5 Fifth thickness t6 The sixth thickness w1 First width w2 Second width CA Capacitor E1 First end E2 Second end P1 First position P2 Second position P3 Third position P4, 4th position

Claims

1. The first electrode and The second electrode and An oxide semiconductor layer provided between the first electrode and the second electrode, A gate electrode facing the oxide semiconductor layer, A first insulating layer is provided between the first electrode and the gate electrode, A second insulating layer is provided between the gate electrode and the second electrode, The gate insulating layer is provided between the gate electrode and the oxide semiconductor layer, between the first insulating layer and the oxide semiconductor layer, and between the second insulating layer and the oxide semiconductor layer. In a first cross-section parallel to the first direction connecting the first electrode and the second electrode, The thickness of the gate insulating layer in a second direction perpendicular to the first direction at a first position between the first insulating layer and the oxide semiconductor layer is defined as the first thickness. The thickness of the gate insulating layer in the second direction at the second position between the second insulating layer and the oxide semiconductor layer is defined as the second thickness. The thickness of the gate insulating layer in the second direction at the third position between the first end of the gate electrode on the first electrode side and the oxide semiconductor layer is set to the third thickness. When the thickness of the gate insulating layer in the second direction at the fourth position between the second end of the gate electrode on the second electrode side and the oxide semiconductor layer is defined as the fourth thickness, A semiconductor device in which the second thickness is greater than the first thickness, or the fourth thickness is greater than the third thickness.

2. The semiconductor device according to claim 1, wherein the second thickness is greater than the first thickness, and the fourth thickness is greater than the third thickness.

3. The semiconductor device according to claim 1, wherein the second thickness is 1.1 times or more and 1.5 times or less the first thickness, or the fourth thickness is 1.1 times or more and 1.5 times or less the third thickness.

4. In the first cross-section, the gate electrode includes a first portion and a second portion. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is provided between the first portion and the second portion in the second direction.

5. The semiconductor device according to claim 1, wherein the gate electrode surrounds the oxide semiconductor layer.

6. In the first cross-section, the first insulating layer includes a third portion and a fourth portion, and in the second direction, the oxide semiconductor layer is provided between the third portion and the fourth portion. The semiconductor device according to claim 1, wherein in the first cross-section, the second insulating layer includes a fifth portion and a sixth portion, and in the second direction, the oxide semiconductor layer is provided between the fifth portion and the sixth portion.

7. The semiconductor device according to claim 6, wherein the first distance in the second direction between the portion of the third portion that contacts the first electrode and the portion of the fourth portion that contacts the first electrode is smaller than the second distance in the second direction between the portion of the fifth portion that contacts the second electrode and the portion of the sixth portion that contacts the second electrode.

8. The semiconductor device according to claim 1, wherein the first width in the second direction of the portion of the oxide semiconductor layer in contact with the first electrode in the first cross-section is smaller than the second width in the second direction of the portion of the oxide semiconductor layer in contact with the second electrode in the first cross-section.

9. The semiconductor device according to claim 7, wherein the first width in the second direction of the portion of the oxide semiconductor layer in contact with the first electrode in the first cross-section is smaller than the second width in the second direction of the portion of the oxide semiconductor layer in contact with the second electrode in the first cross-section.

10. The semiconductor device according to claim 1, wherein the first width in the second direction of the portion of the oxide semiconductor layer in contact with the first electrode in the first cross-section is greater than the second width in the second direction of the portion of the oxide semiconductor layer in contact with the second electrode in the first cross-section.

11. The semiconductor device according to claim 7, wherein the first width in the second direction of the portion of the oxide semiconductor layer in contact with the first electrode in the first cross-section is greater than the second width in the second direction of the portion of the oxide semiconductor layer in contact with the second electrode in the first cross-section.

12. The semiconductor device according to claim 1, wherein the gate insulating layer provided between the first insulating layer and the oxide semiconductor layer has a void.

13. The semiconductor device according to claim 1, wherein the gate insulating layer provided between the second insulating layer and the oxide semiconductor layer and the gate insulating layer provided between the gate electrode and the oxide semiconductor layer include materials different from the gate insulating layer provided between the first insulating layer and the oxide semiconductor layer.

14. The semiconductor device according to claim 1, wherein the gate insulating layer includes a first film provided between the gate electrode and the oxide semiconductor layer and containing a first material, and a second film provided between the first film and the oxide semiconductor layer and containing a second material different from the first material.

15. The semiconductor device according to claim 14, further comprising a third film comprising the first material and provided between the second film and the oxide semiconductor layer, wherein the gate insulating layer is provided between the second film and the oxide semiconductor layer.

16. The semiconductor device according to claim 14, wherein the dielectric constant of the second material is higher than that of the first material.

17. The semiconductor device according to claim 15, wherein the dielectric constant of the second material is higher than that of the first material.

18. The semiconductor device according to claim 17, wherein, in the first cross-section, the fifth thickness in the second direction of the second film between the first end and the oxide semiconductor layer is thinner than the sixth thickness in the second direction of the second film between the second end and the oxide semiconductor layer.

19. The semiconductor device according to claim 14, wherein the first film is separated from the first electrode.

20. The semiconductor device according to claim 1, A capacitor electrically connected to either the first electrode or the second electrode, A semiconductor memory device equipped with the following features.

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