Multilayer electronic components

Abstract

We provide highly reliable stacked electronic components. [Solution] The laminated electronic component includes a capacitance forming section including a dielectric layer 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layer in a first direction; a main body 110 including first and second surfaces facing each other in a first direction X, third and fourth surfaces facing each other in a second direction Y, and fifth and sixth surfaces connected to the first to fourth surfaces and facing each other in a third direction; external electrodes arranged on the third and fourth surfaces, respectively; and side margin sections 114 and 115 arranged on the fifth and sixth surfaces, respectively, and containing a plurality of dielectric crystal grains G1 to G3. When the average size of a plurality of dielectric crystal grains is measured in N regions (N is a constant of 2 or more) where the positions in the first direction are different from each other, for each of M cross-sections (M is an integer of 2 or more) in the first and third directions of the side margin sections where the positions in the second direction are different from each other, the standard deviation of the average size value measured M × N times is 5.3 or more and 8.3 or less.

Description

[Technical Field]

[0001] This disclosure relates to a stacked electronic component. [Background technology]

[0002] Multi-layered ceramic capacitors (MLCCs), a type of multilayer electronic component, are chip-type capacitors that are mounted on printed circuit boards of various electronic products such as liquid crystal displays (LCDs), plasma display panels (PDPs), computers, smartphones, and mobile phones to charge or discharge electricity. Due to their advantages of being small, yet guaranteeing high capacitance and being easy to mount, MLCCs are used as components in a wide range of electronic devices.

[0003] To miniaturize and increase the capacitance of MLCCs, maximizing the effective area of ​​the internal electrodes is required. Therefore, methods for maximizing the widthwise area of ​​the internal electrodes have been studied, specifically a method in which a sheet for forming side margins is attached separately to the widthwise cross-section of the laminated chip before firing. Since the microstructure of the side margins significantly affects the reliability of MLCCs, further research is needed in this area. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Korean Published Patent Gazette No. 10-2015-0135092 [Overview of the project] [Problems that the invention aims to solve]

[0005] One of the various purposes of this disclosure is to provide highly reliable stacked electronic components.

[0006] However, the purpose of this disclosure is not limited to what is described above, and this will become clearer in the course of describing specific embodiments of this disclosure. [Means for solving the problem]

[0007] A stacked electronic component according to one embodiment of the present disclosure includes a capacitance forming portion including a dielectric layer and internal electrodes arranged alternately with the dielectric layer in a first direction; a main body including first and second surfaces facing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and facing each other in a second direction, fifth and sixth surfaces connected to the first, second, third, and fourth surfaces and facing each other in a third direction; external electrodes arranged on the third and fourth surfaces, respectively; and side margin portions arranged on the fifth and sixth surfaces, respectively, and containing a plurality of dielectric crystal grains. When the average size of the plurality of dielectric crystal grains is measured in N regions (N is a constant of 2 or more) where the positions in the first direction are different from each other, for each of M cross-sections (M is an integer of 2 or more) of the side margin portions in the first and third directions where the positions in the second direction are different from each other, the standard deviation of the average size value measured M × N times may be 5.3 or more and 8.3 or less.

[0008] A multilayer electronic component according to an embodiment of the present disclosure includes a dielectric layer, a capacitance forming portion including internal electrodes alternately arranged with the dielectric layer in a first direction, a first surface and a second surface facing each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and facing each other in a second direction, a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and facing each other in a third direction, a main body, external electrodes respectively arranged on the third surface and the fourth surface, and side margin portions respectively arranged on the fifth surface and the sixth surface and including a plurality of dielectric crystal grains. When cross-sections in the first direction and the third direction cut at the 1 / 10 point, 1 / 4 point, and 1 / 2 point of the length of the side margin portion in the second direction are respectively defined as a first cross-section, a second cross-section, and a third cross-section, and the average sizes of the plurality of dielectric crystal grains measured in three first regions having different positions in the first direction in the first cross-section are defined as GS1, GS2, and GS3, the average sizes of the plurality of dielectric crystal grains measured in three second regions having different positions in the first direction in the second cross-section are defined as GS4, GS5, and GS6, and the average sizes of the plurality of dielectric crystal grains measured in three third regions having different positions in the first direction in the third cross-section are defined as GS7, GS8, and GS9, the standard deviation of the GS1 to GS9 values can be 5.3 nm or more and 8.3 nm or less.

Advantages of the Invention

[0009] Among various effects of the present disclosure, a multilayer electronic component excellent in reliability can be provided.

Brief Description of the Drawings

[0010] [Figure 1] It is a perspective view schematically showing a multilayer electronic component according to an embodiment of the present disclosure. [Figure 2] It is a perspective view schematically showing the main body and the side margin portion of FIG. 1. [Figure 3] It is a perspective view schematically showing the main body of FIG. 1. [Figure 4] It is a cross-sectional view schematically showing a cut cross-section along the line I-I' of FIG. 1. [Figure 5a] It is a cross-sectional view schematically showing a cross-section along line II-II' of FIG. 2. [Figure 5b] It is a cross-sectional view schematically showing a cross-section along line III-III' of FIG. 2. [Figure 5c] It is a cross-sectional view schematically showing a cross-section along line IV-IV' of FIG. 2. [Figure 6a] It is an image obtained by photographing the side margin portion of Comparative Example 1 with a scanning electron microscope (SEM). [Figure 6b] It is an image obtained by photographing the side margin portion of the Example with a scanning electron microscope (SEM). [Figure 6c] It is an image obtained by photographing the side margin portion of Comparative Example 2 with a scanning electron microscope (SEM). [Figure 7a] It is a graph showing the evaluation results of the moisture resistance reliability of Comparative Example 1. [Figure 7b] It is a graph showing the evaluation results of the moisture resistance reliability of the Example. [Figure 8] It is a graph showing the evaluation results of the breakdown voltage (BDV) of the Example and Comparative Example 2. [Figure 9] It is a graph showing the accelerated life distributions of the Example and Comparative Example 2.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present disclosure can be modified into several other forms, and the scope of the present disclosure is not limited to the embodiments described below. Also, the embodiments of the present disclosure are provided to more fully explain the present disclosure to ordinary technicians. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or emphasized or simplified) for clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0012] Furthermore, in order to clearly illustrate this disclosure, parts unrelated to the explanation have been omitted in the drawings, and the size and thickness of each illustrated component are shown arbitrarily for the convenience of explanation; therefore, this disclosure is not necessarily limited by the illustrations. Also, components with the same function within the scope of the same idea are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a component, it does not mean that other components are excluded, but rather that other components may be included, unless otherwise stated to the contrary.

[0013] In drawings, the first direction X can be defined as the thickness (T) direction, the second direction Y as the length (L) direction, and the third direction Z as the width (W) direction.

[0014] Multilayer electronic components Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present disclosure; Figure 2 is a schematic perspective view of the main body and side margin portion of Figure 1; Figure 3 is a schematic perspective view of the main body of Figure 1; Figure 4 is a schematic cross-sectional view of a section along line I-I' of Figure 1; Figure 5a is a schematic cross-sectional view of a section along line II-II' of Figure 2; Figure 5b is a schematic cross-sectional view of a section along line III-III' of Figure 2; Figure 5c is a schematic cross-sectional view of a section along line IV-IV' of Figure 2; and Figure 6a is a comparative example. Figure 6b is an image of the side margin of Example 1 taken with a scanning electron microscope (SEM), Figure 6c is an image of the side margin of Comparative Example 2 taken with a scanning electron microscope (SEM), Figure 7a is a graph showing the evaluation results of the moisture resistance reliability of Comparative Example 1, Figure 7b is a graph showing the evaluation results of the moisture resistance reliability of Example, Figure 8 is a graph showing the evaluation results of the dielectric breakdown voltage (BDV) of Example and Comparative Example 2, and Figure 9 is a graph showing the accelerated lifetime distribution of Example and Comparative Example 2.

[0015] Hereinafter, with reference to Figures 1 to 9, a multilayer electronic component 100 according to one embodiment of the present disclosure will be described in detail. While a multilayer ceramic capacitor will be described as an example of a multilayer electronic component, the present disclosure is not limited to this and can be applied to a variety of multilayer electronic components, such as inductors, piezoelectric elements, varistors, or thermistors.

[0016] A stacked electronic component 100 according to one embodiment of the present disclosure may include a main body 110, external electrodes 131, 132, and side margin portions 114, 115.

[0017] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process and the polishing process on the corners of the main body 110, the main body 110 may not be a perfectly straight hexahedron, but it can be substantially hexahedral.

[0018] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, a fifth surface 1, a second surface 2, a third surface 3 and a fourth surface 4 connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and facing each other in a third direction, and a fifth surface and a sixth surface 5, 6.

[0019] The main body 110 may include a capacitance forming section Ac disposed inside the main body 110, which includes a dielectric layer 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layer 111 in a first direction to form a capacitance. The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM).

[0020] The dielectric layer 111 may mainly consist of a perovskite-type compound represented by ABO3, for example. The perovskite-type compound represented by ABO3 is, for example, BaTiO3, (Ba 1-x Ca x)TiO3(0 < x < 1), Ba(Ti 1-y Ca y )O3(0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3(0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3(0 < x ≤ 0.5, 0 < y ≤ 0.5) can include one or more of them.

[0021] The internal electrodes 121 and 122 can include, for example, a first internal electrode 121 and a second internal electrode 122 that are alternately arranged in the first direction with the dielectric layer 111 interposed therebetween. The first internal electrode 121 and the second internal electrode 122 can be electrically separated from each other by the dielectric layer 111 disposed therebetween.

[0022] The first internal electrode 121 can extend to the third surface 3, the fifth surface 5, and the sixth surface 6 and be disposed spaced apart from the fourth surface 4. The first internal electrode 121 can be connected to the first external electrode 131. The second internal electrode 122 can extend to the fourth surface 4, the fifth surface 5, and the sixth surface 6 and be disposed spaced apart from the third surface 3. The second internal electrode 122 can be connected to the second external electrode 132.

[0023] The conductive metal included in the internal electrodes 121 and 122 can be one or more of Ni, Cu, Pd, Ag, Au, Pt, Sn, W, Ti, and alloys thereof, and more preferably can include Ni, but the present invention is not limited thereto.

[0024] The main body 110 can include cover portions 112 and 113 disposed on both surfaces facing each other in the first direction of the capacitance forming portion Ac.

[0025] The side margin portions 114 and 115 may be respectively disposed on the fifth surface 5 and the sixth surface 6 of the main body 110. The multilayer electronic component 100 may include a first side margin portion 114 disposed on the fifth surface 5 and a second side margin portion 115 disposed on the sixth surface 6.

[0026] The cover portions 112 and 113 and the side margin portions 114 and 115 may include, for example, a perovskite-type compound represented by ABO3 as a main component. The perovskite-type compound represented by ABO3 may be, for example, BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3 (0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x ≤ 0.5, 0 < y ≤ 0.5), and may include one or more of them.

[0027] The external electrodes 131 and 132 may be respectively disposed on the third surface 3 and the fourth surface 4 of the main body 110. The multilayer electronic component 100 may include a first external electrode 131 disposed on the third surface 3 and a second external electrode 132 disposed on the fourth surface 4. The first external electrode 131 may be disposed on the third surface 3 and extend onto a part of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6, and the second external electrode 132 may be disposed on the fourth surface 4 and extend onto a part of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6.

[0028] The type and form of the external electrodes 131 and 132 are not particularly limited and can have a multilayer structure. For example, the external electrodes 131 and 132 may include base electrode layers 131a and 132a that come into contact with the internal electrodes 121 and 122, and plating layers 131b and 132b placed on the base electrode layers 131a and 132a.

[0029] The base electrode layers 131a and 132a may be fired electrode layers containing metal and glass. The metal contained in the base electrode layers 131a and 132a may include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, and / or alloys containing these. The glass contained in the base electrode layers 131a and 132a may include, for example, one or more oxides of Ba, Ca, Zn, Al, B, and Si.

[0030] The base electrode layers 131a and 132a may consist only of fired electrode layers, but the disclosure is not limited thereto, and the base electrode layers 131a and 132a may include fired electrode layers containing metal and glass, and resin electrode layers disposed on the fired electrode layers and containing metal particles and resin.

[0031] The metal particles contained in the resin electrode layer may include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, Sn, and / or alloys containing these. The resin contained in the resin electrode layer may include, for example, one or more of epoxy resin, acrylic resin, and ethylcellulose.

[0032] The plating layers 131b and 132b may include, for example, Ni, Sn, Pd, and / or alloys containing these, and may be formed in multiple layers. The plating layers 131b and 132b may be, for example, a Ni plating layer or a Sn plating layer, or a Ni plating layer and a Sn plating layer may be formed sequentially. The plating layers 131b and 132b may include multiple Ni plating layers and / or multiple Sn plating layers.

[0033] The drawing illustrates a structure in which the stacked electronic component 100 has two external electrodes 131 and 132, but it is not limited to this, and the number and shape of the external electrodes 131 and 132 can be changed depending on the form of the internal electrodes 121 and 122 or other purposes.

[0034] The side margin portions 114 and 115 may contain multiple dielectric crystal grains G1, G2, G3, G4, G5, G6, G7, G8, and G9. The side margin portions 114 and 115 can essentially serve to protect the capacitance-forming portion Ac. By suppressing the grain growth of the multiple dielectric crystal grains G1 to G9 contained in the side margin portions 114 and 115, the density of the side margin portions 114 and 115 can be improved, thereby preventing external moisture from penetrating the capacitance-forming portion Ac and improving the reliability of the stacked electronic component 100.

[0035] To more effectively improve the reliability of the multilayer electronic component 100, it is necessary to uniformly suppress the grain growth of multiple dielectric crystal grains G1 to G9. This makes it possible to uniformly improve the density of the side margin portions 114 and 115 at different locations.

[0036] Therefore, in the stacked electronic component 100 according to one embodiment of the present disclosure, when the average size of a plurality of dielectric crystal grains G1 to G9 is measured in N regions that are different in position in the first direction for each of the M cross-sections in the first and third directions of the side margin portions 114 and 115 that are different in position in the second direction, the standard deviation of the average size value measured M × N times can satisfy the condition that M and N are integers of 2 or more.

[0037] In other words, the side margins 114 and 115 of the stacked electronic component 100 according to one embodiment of the present disclosure can satisfy a standard deviation of the average size of crystal grains measured across multiple cross-sections and multiple regions that is between 5.3 and 8.3. When the above standard deviation satisfies the above numerical range, the reliability of the stacked electronic component 100 can be effectively improved.

[0038] If the above standard deviation exceeds 8.3, grain growth of dielectric crystal grains contained in the side margin portions 114 and 115 may not be uniformly suppressed, and the BDV dispersion and lifetime characteristics of the multilayer electronic component 100 may deteriorate. If the above standard deviation is less than 5.3, grain growth of dielectric crystal grains contained in the side margin portions 114 and 115 may be excessively suppressed, resulting in an increase in pores within the side margin portions 114 and 115, which may consequently reduce the moisture resistance reliability of the multilayer electronic component 100.

[0039] The standard deviation can be calculated using the following formula 1. The standard deviation is obtained by squaring the deviations, summing them, dividing by the number of measurements, and then finding the square root of this sum. It can be said to represent the root mean square of the deviations. [Mathematical formula 1]

number

[0040] The M cross-sections mentioned above are not particularly limited, but as shown in Figures 2 and 5a-5c, they may include a first cross-section CS1 cut at 1 / 10 of the length L in the second direction of the side margin portions 114 and 115, a second cross-section CS2 cut at 1 / 4 of the length L in the second direction of the side margin portions 114 and 115, and a third cross-section CS3 cut at 1 / 2 of the length L in the second direction of the side margin portions 114 and 115.

[0041] The fact that the M cross-sections mentioned above can include the first cross-section CS1, the second cross-section CS2, and the third cross-section CS3, which are cross-sections in the first and third directions obtained by cutting the side margin portions 114 and 115 at points 1 / 10, 1 / 4, and 1 / 2 of the length L in the second direction means that the average size of the dielectric crystal grains G1 to G9 and the standard deviation of that average size value can be measured at various positions in the second direction. In other words, when the M cross-sections include the first cross-section CS1, the second cross-section CS2, and the third cross-section CS3, and the standard deviation satisfies 5.3 to 8.3, the side margin portions 114 and 115 can contain stacked crystal grains G1 to G9 that have a certain level of size uniformity regardless of their position in the second direction, thereby more effectively improving the reliability of the stacked electronic component 100.

[0042] In this disclosure, the points of 1 / 10, 1 / 4, and 1 / 2 of the length L in the second direction of the side margin portions 114 and 115 can mean points close enough that a person of ordinary skill would recognize them as points of 1 / 10, 1 / 4, and 1 / 2 of the length L in the second direction of the side margin portions 114 and 115. Therefore, considering errors in the polishing process for measurement, the 1 / 10 point can mean a point between 1 / 10 ± 1 / 50 of the length L in the second direction of the side margin portions 114 and 115, the 1 / 4 point can mean a point between 1 / 4 ± 1 / 50 of the length L in the second direction of the side margin portions 114 and 115, and the 1 / 2 point can mean a point between 1 / 2 ± 1 / 50 of the length L in the second direction of the side margin portions 114 and 115.

[0043] The above N regions are not particularly limited, but may include three regions whose positions in the first direction are different from each other.

[0044] For example, if the average sizes of multiple dielectric crystal grains G1 to G3 measured in three first regions UR1, CR1, and LR1 of the first cross section CS1, which are at different positions in the first direction, are defined as GS1, GS2, and GS3, the average sizes of multiple dielectric crystal grains G4 to G6 measured in three second regions UR2, CR2, and LR2 of the second cross section CS2, which are at different positions in the first direction, are defined as GS4, GS5, and GS6, and the average sizes of multiple dielectric crystal grains G7 to G9 measured in three third regions UR3, CR3, and LR3 of the third cross section CS3, which are at different positions in the first direction, are defined as GS7, GS8, and GS9, then the standard deviation of the above GS1 to GS9 values ​​can be between 5.3 nm and 8.3 nm. In other words, the standard deviation of the above GS1 to GS9 values ​​can represent, for example, the standard deviation among the nine average size values ​​measured at a total of nine locations.

[0045] For example, the above N regions may include the upper regions UR1, UR2, UR3, the central regions CR1, CR2, CR3, and the lower regions LR1, LR2, LR3 of the side margin portions 114, 115. Here, the central regions CR1, CR2, CR3 can correspond to the central region of the volume forming portion Ac in the first direction, the upper regions UR1, UR2, UR3 can correspond to the uppermost region of the volume forming portion Ac in the first direction, and the lower regions LR1, LR2, LR3 can correspond to the lowermost region of the volume forming portion Ac in the first direction.

[0046] In other words, the first regions UR1, CR1, and LR1 may include a first central region CR1 corresponding to the central region of the volume-forming portion Ac in the first direction, a first upper region UR1 corresponding to the uppermost region of the volume-forming portion Ac in the first direction, and a first lower region LR1 corresponding to the lowermost region of the volume-forming portion Ac in the first direction.

[0047] The second regions UR2, CR2, and LR2 may include a second central region CR2 corresponding to the central region of the volume-forming portion Ac in the first direction, a second upper region UR2 corresponding to the uppermost region of the volume-forming portion Ac in the first direction, and a second lower region LR2 corresponding to the lowermost region of the volume-forming portion Ac in the first direction.

[0048] The third regions UR3, CR3, and LR3 may include a third central region CR3 corresponding to the central region of the volume-forming portion Ac in the first direction, a third upper region UR3 corresponding to the uppermost region of the volume-forming portion Ac in the first direction, and a third lower region LR3 corresponding to the lowermost region of the volume-forming portion Ac in the first direction.

[0049] The fact that the above N regions can include upper regions UR1, UR2, UR3, central regions CR1, CR2, CR3, and lower regions LR1, LR2, LR3 means that the average size of dielectric crystal grains G1 to G9 and the standard deviation of that average size can be measured at various positions in the first direction. That is, when the above N regions include upper regions UR1, UR2, UR3, central regions CR1, CR2, CR3, and lower regions LR1, LR2, LR3, and the above standard deviation is between 5.3 and 8.3, the side margin portions 114 and 115 can contain dielectric crystal grains G1 to G9 that have a constant level of size uniformity regardless of their position in the first direction, thereby more effectively improving the reliability of the stacked electronic component 100.

[0050] On the other hand, in order to more accurately measure the average size of dielectric crystal grains G1 to G9, each of the N regions can contain more than 500 dielectric crystal grains G1 to G9. There is no particular upper limit on the number of dielectric crystal grains G1 to G9 contained in each of the N regions, but it may be, for example, 1000 or less.

[0051] The following describes an example of a method for measuring the above standard deviation. First, after removing the external electrodes 131 and 132 of the multilayer electronic component 100, the cross-sections in the first and third directions (first cross-section) are exposed by polishing the side margin portions 114 and 115 to a point 1 / 10 of the length L in the second direction. In the first cross-section CS1, a first central region CR1, a first upper region UR1, and a first lower region LR1 are defined. To prevent interference by the internal electrodes, the first regions UR1, CR1, and LR1 can be defined at a position separated from the capacitance forming portion Ac by a certain distance d1. The above d1 can be, for example, 100 nm or more and 500 nm or less. The first central region CR1 can be set to overlap the center of the capacitance forming region Ac in the first direction and in the third direction, the first upper region UR1 can be set to overlap the internal electrodes 121 and 122 located at the top with respect to the first direction and in the third direction, and the first lower region LR1 can be set to overlap the internal electrodes 121 and 122 located at the bottom with respect to the first direction and in the third direction. Next, images of the first central region CR1, the first upper region UR1, and the first lower region LR1 were obtained using a scanning electron microscope (SEM) at 50,000x magnification. Each image was designed to contain more than 500 dielectric crystal grains G1 to G3. By analyzing each image with an image analysis program, GS1 to GS3 can be calculated.

[0052] Next, the chip, which has been polished to 1 / 10 of the length L in the second direction of the side margin portions 114 and 115, is polished again to 1 / 4 of the length L in the second direction of the side margin portions 114 and 115 to expose the cross-sections in the first and third directions (second cross-section). The second central region CR2, the second upper region UR2, and the second lower region LR2 are defined in the second cross-section CS2. GS4 to GS6 can be calculated by performing the same process in the second cross-section CS2 as the method used to measure the average size of the crystal grains in the first cross-section CS1.

[0053] Next, the chip, which has been polished to a point 1 / 4 of the length L in the second direction of the side margin portions 114 and 115, is polished again to a point 1 / 2 of the length L in the second direction of the side margin portions 114 and 115 to expose the cross-sections in the first and third directions (third cross-section). The third central region CR3, the third upper region UR3, and the third lower region LR3 are defined in the third cross-section CS3. GS7 to GS9 can be calculated by performing the same process in the third cross-section CS3 as in the method used to measure the average size of the crystal grains in the first cross-section CS1.

[0054] This allows us to calculate the standard deviation of the total of nine average magnitude values ​​from GS1 to GS9. However, this disclosure is not limited thereto, and the above M×N can have various values ​​such as 3×4, 4×3, 4×4, 5×5, etc.

[0055] In one embodiment, the average size of multiple dielectric crystal grains GS2, GS5, GS8 measured in the central regions CR1, CR2, CR3 can be greater than the average size of multiple dielectric crystal grains GS1, GS3, GS4, GS6, GS7, GS9 measured in the upper regions UR1, UR2, UR3 or the lower regions LR1, LR2, LR3. That is, GS1 to GS9 can satisfy one or more of the following conditions: GS2 > GS1, GS2 > GS3, GS5 > GS4, GS5 > GS6, GS8 > GS7, and GS8 > GS9.

[0056] The dielectric crystal grains G1, G4, and G7 contained in the upper regions UR1, UR2, and UR3, and the dielectric crystal grains G3, G6, and G9 contained in the lower regions LR1, LR2, and LR3, can have their grain growth suppressed compared to the dielectric crystal grains G2, G5, and G8 contained in the central regions CR1, CR2, and CR3 due to the influence of the sintering aid diffused from the cover portions 112 and 113. As a result, one or more of the following conditions can be satisfied: GS2 > GS1, GS2 > GS3, GS5 > GS4, GS5 > GS6, GS8 > GS7, and GS8 > GS9.

[0057] However, the side margins 114 and 115 of the stacked electronic component 100 according to one embodiment of the present disclosure may include dielectric crystal grains G1 to G9 having a certain level of size uniformity regardless of their position in the first direction. As a result, the ratio of the average size GS1, GS3, GS4, GS6, GS7, GS9 of multiple dielectric crystal grains measured in the upper region UR1, UR2, UR3 or the lower region LR1, LR2, LR3 to the average size GS2, GS5, GS8 of multiple dielectric crystal grains measured in the central region CR1, CR2, CR3 may be 0.923 or more and 0.987 or less. In other words, one or more of the following conditions can be met: 0.923≦GS1 / GS2≦0.987, 0.923≦GS3 / GS2≦0.987, 0.923≦GS4 / GS5≦0.987, 0.923≦GS6 / GS5≦0.987, 0.923≦GS9 / GS8≦0.987, and 0.923≦GS9 / GS8≦0.987. When the above numerical ranges are met, the reliability of the multilayer electronic component 100 can be improved more effectively.

[0058] The average size of multiple dielectric crystal grains GS2, GS5, and GS8 measured in the central regions CR1, CR2, and CR3 can be, for example, between 200 nm and 300 nm.

[0059] On the other hand, the dielectric layer 111 and the side margin portions 114 and 115 may contain the following minor components in addition to the ABO3 main component in order to realize a stacked electronic component 100 with desired characteristics.

[0060] The minor components are described based on the number of moles of elements and can be calculated by converting them to the content of oxides or carbonates of additives added before firing. Unless there are special circumstances, the elemental content before and after firing does not have a large margin of error, and the types and content of elements contained in the dielectric layer 111 and side margin portions 114 and 115 can be measured using various measurement methods such as SEM-EDS, TEM-EDS, and STEM-EDS after firing.

[0061] As a more specific example of a method for measuring the content of each element contained in the side margins 114 and 115, an analytical sample is prepared by thinning the region corresponding to the side margins 114 and 115 of the cross-section of the multilayer electronic component 100 using a focused ion beam (FIB). Then, the surface damage layer of the thinned sample is removed using Ar ion milling, and after that, each component is mapped using an image obtained with (S)TEM-EDS and qualitative / quantitative analysis is performed. In this case, the qualitative / quantitative analysis graph of each component can be shown converted to the mass fraction (wt%), atomic percentage (at%), or mole fraction (mol%) of each element.

[0062] 1) First subcomponent The dielectric layer 111 and the side margin portions 114 and 115 may contain a first minor component comprising one or more of Dy, Y, Tb, Sc, La, Nd, Eu, Gd, Ho, Er, Yb, and Lu. This first minor component can play a role in improving the reliability of the multilayer electronic component 100. The total content of the first minor component contained in the side margin portions 114 and 115 may be, for example, 0.6 moles or more and 3.0 moles or less per 100 moles of Ti.

[0063] 2)Second subcomponent The dielectric layer 111 and the side margin portions 114 and 115 may contain a second minor component comprising one or more of Mg and Zr. The inclusion of this second minor component in the side margin portions 114 and 115 can lower the sintering temperature of the side margin portions 114 and 115 and suppress grain growth. The total content of the second minor component contained in the side margin portions 114 and 115 may be, for example, 0.1 moles or more and 3.0 moles or less per 100 moles of Ti.

[0064] 3) Third subcomponent The dielectric layer 111 and the side margin portions 114 and 115 may contain a third subcomponent comprising one or more of Mn, V, Cr, Fe, Ni, Co, and Zn. This third subcomponent is a valence-variable acceptor element and can play a role in improving the dielectric properties and high-temperature accelerated lifetime characteristics of the stacked electronic component 100.

[0065] The total content of the above-mentioned third minor component contained in the side margin portions 114 and 115 may be, for example, 0.01 moles or more and 8.0 moles or less per 100 moles of Ti.

[0066] 4) Fourth subcomponent The dielectric layer 111 and the side margin portions 114 and 115 may contain a fourth minor component comprising one or more of Si and Al. The Si can suppress grain growth of dielectric crystal grains contained in the side margin portions 114 and 115, thereby improving the density of the side margin portions 114 and 115. The Al can contribute to low-temperature densification through liquid phase formation during sintering, thereby improving the high-temperature withstand voltage characteristics of the multilayer electronic component 100.

[0067] In order to appropriately control the microstructure of the side margin portions 114 and 115, the side margin portions 114 and 115 may contain one or more of the following: Dy, Mn, Mg, V, Si, and Al, or they may contain all of Dy, Mn, Mg, V, Si, and Al.

[0068] The size of the stacked electronic component 100 is not particularly limited, however, the maximum length of the stacked electronic component 100 in the second direction can be 0.1 mm to 6.0 mm, the maximum width of the stacked electronic component 100 in the third direction can be 0.1 mm to 5.0 mm, and the maximum thickness of the stacked electronic component 100 in the first direction can be 0.05 mm to 3.5 mm.

[0069] The average thickness of the dielectric layer 111 is not particularly limited, but it may be, for example, 0.1 μm to 20 μm, 0.1 μm to 10 μm, 0.1 μm to 5 μm, 0.1 μm to 2 μm, or 0.1 μm to 0.4 μm.

[0070] The average thickness of the internal electrodes 121 and 122 is not particularly limited, but the average thickness of the internal electrodes 121 and 122 may be, for example, 0.1 μm to 3.0 μm, 0.1 μm to 1.0 μm, or 0.1 μm to 0.4 μm.

[0071] The average thickness of the dielectric layer 111 and the average thickness of the internal electrodes 121 and 122 refer to the average thickness of each dielectric layer 111 and internal electrodes 121 and 122 in the first direction. The average thickness of the dielectric layer 111 and the average thickness of the internal electrodes 121 and 122 can be measured by scanning the cross-sections of the multilayer electronic component 100 in the first and third directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the average thickness of one dielectric layer 111 can be measured by measuring its thickness at multiple points, for example, five equally spaced points in the third direction, and then calculating the average value. Similarly, the average thickness of one internal electrode 121 or 122 can be measured by measuring its thickness at multiple points, for example, five equally spaced points in the third direction, and then calculating the average value. The five equally spaced points can be specified in the capacitance forming section Ac. On the other hand, if such average values ​​are measured for 10 dielectric layers 111 and 10 internal electrodes 121 and 122, and then the average values ​​are measured, the average thickness of the dielectric layer 111 and the average thickness of the internal electrodes 121 and 122 can be further generalized.

[0072] The average thickness of the cover portions 112 and 113 is not particularly limited. The average thickness of the cover portions 112 and 113 may be, for example, 150 μm or less, 100 μm or less, 30 μm or less, or 20 μm or less. The average thickness of the cover portions 112 and 113 may be, for example, 5 μm or more, 10 μm or more, or 30 μm or more. Here, the average thickness tc of the cover portions 112 and 113 refers to the average thickness of the first cover portion 112 and the second cover portion 113, respectively.

[0073] The average thickness tc of the cover portions 112 and 113 can mean the average thickness of the cover portions 112 and 113 in the first direction, and can be the average value of the thickness in the first direction measured at five equally spaced points in the cross-section of the stacked electronic component 100 in the first and third directions.

[0074] The average thickness wm of the side margin portions 114 and 115 is not particularly limited. The average thickness wm of the side margin portions 114 and 115 can be, for example, 3 μm or more and 100 μm or less. For example, if the multilayer electronic component 100 has a size of 1005 size (length: approximately 1.0 mm, width: approximately 0.5 mm, thickness: approximately 0.5 mm) or less, the average thickness wm of the side margin portions 114 and 115 may be 3 μm or more and 25 μm or less, or for example, 14 μm or more and 20 μm or less. The average thickness wm of the side margin portions 114 and 115 refers to the average thickness of the first side margin portion 114 and the second side margin portion 115, respectively.

[0075] The average thickness tm of the side margin portions 114 and 115 can refer to the average thickness of the side margin portions 114 and 115 in the third direction, and may be the average value of the thickness in the third direction measured at five equally spaced points in the cross-sections of the multilayer electronic component 100 in the first and third directions. The average thickness tm of the side margin portions 114 and 115 can be measured, for example, in the third cross-section CS3.

[0076] The following describes an example of a method for forming a stacked electronic component 100. However, the manufacturing method of the stacked electronic component 100 is not limited to this.

[0077] First, prepare the ceramic powder for forming the dielectric layer 111. The ceramic powder may be, for example, BaTiO3, (Ba 1-x Ca x )TiO3(0 <x<1)、Ba(Ti 1-y Ca y )O3(0 <y<1)、(Ba 1-x Ca x )(Ti 1-y Zr y)O3 (0 < x < 1, 0 < y < 1), or Ba(Ti 1-y Zr y )O3 (0 < y < 1) can be included. BaTiO3 powder can be synthesized, for example, by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. As methods for synthesizing the above ceramic powder, there are, for example, the solid-phase method, the sol-gel method, the hydrothermal synthesis method, etc., but the present invention is not limited thereto. Next, after drying and pulverizing the prepared ceramic powder, an organic solvent such as ethanol, a binder such as polyvinyl butyral, and other auxiliary components are mixed to produce a ceramic slurry, and then the ceramic slurry is applied and dried on a carrier film to prepare a sheet for forming a dielectric layer.

[0078] Next, an internal electrode conductive paste containing a metal powder, a binder, an organic solvent, etc. with a predetermined thickness is printed on the sheet for forming a dielectric layer using a screen printing method or a gravure printing method, etc. to form an internal electrode pattern.

[0079] After that, the sheet for forming a dielectric layer on which the internal electrode pattern is printed is peeled off from the carrier film, and then laminated and pressure-bonded by a predetermined number of layers to form a ceramic laminate. On the upper and lower parts of the ceramic laminate, a cover part forming sheet on which no internal electrode pattern is formed may be laminated by a predetermined number of layers to form cover parts 112 and 113 after firing. After that, the above ceramic laminate is cut to have a predetermined chip size. At this time, the ends of the internal electrode pattern are exposed on both sides facing each other in the third direction of the cut chip.

[0080] Next, after attaching a sheet for forming a margin part on both sides in the third direction of the cut chip, firing can be performed to form a main body 110 and side margin parts 114 and 115. The above firing can be performed, for example, at a temperature of 1000°C or higher and 1400°C or lower for 1 hour to 3 hours in an atmosphere of 1.0% H2 / 99.0% N2 to 3.5% H2 / 96.5% N2 (H2O / H2 / N2 atmosphere).

[0081] On the other hand, the margin-forming sheet can be formed in a similar manner to the dielectric layer-forming sheet, but the types and content of the auxiliary components included in the margin-forming sheet may differ from those included in the dielectric layer-forming sheet.

[0082] The margin-forming sheet may contain the above-mentioned first to fourth minor component powders in predetermined amounts. The margin-forming sheet may contain, for example, one or more of Dy, Mn, Mg, V, Si, and Al. The above minor component powders may be added to the margin-forming sheet in the form of oxides and / or carbonates, but this disclosure is not limited thereto.

[0083] Next, external electrodes 131 and 132 are formed. For example, if the base electrode layers 131a and 132a include a fired electrode layer, the main body 110 can be dipped in a conductive paste for external electrodes containing metal powder, glass frit, binder, and organic solvent, and then the conductive paste for external electrodes can be fired at a temperature of 500°C to 900°C to form a fired electrode layer.

[0084] For example, if the base electrode layers 131a and 132a include a resin electrode layer, the main body can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then cured at a temperature of 250°C to 550°C to form the resin electrode layer.

[0085] Furthermore, electroplating and / or electroless plating may be performed to form plating layers 131b and 132b on the underlying electrode layers 131a and 132a.

[0086] (Examples) Using the manufacturing method described above, a sample chip of size 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm, thickness: approximately 0.5 mm) was prepared. Subsequently, the cross-sections in the first and third directions (first cross-section) were exposed by polishing to a point 1 / 10th of the length in the second direction of the side margin. The upper, central, and lower regions of the side margin of the first cross-section were analyzed using a scanning electron microscope (SEM) at 50,000x magnification, and the average size of the dielectric crystal grains GS1, GS2, and GS3 contained in each region was calculated. The number of crystal grains contained in each region was approximately 700 to 800.

[0087] Next, the side margin was polished to a point 1 / 4 of its length in the second direction to expose the second cross-section, and the average sizes of the dielectric crystal grains GS4, GS5, and GS6 contained in the upper, central, and lower regions of the side margin were calculated using the same method.

[0088] Next, the side margin was polished to the point halfway along its second length to expose the third cross-section, and the average sizes of the dielectric crystal grains GS7, GS8, and GS9 contained in the upper, central, and lower regions of the side margin were calculated using the same method. Finally, the standard deviations for the nine measured values ​​GS1 to GS9 were measured.

[0089] Comparative Example 1 had a standard deviation of less than 5.3, the Example satisfies the standard deviation requirement of 5.3 or more and 8.3 or less, and Comparative Example 2 had a standard deviation exceeding 8.3.

[0090] Referring to Figures 6a to 6c, it can be seen that Comparative Example 1 has a larger number of pores compared to the Example. In Figures 6a to 6c, the pores are the areas that are highlighted. Also, referring to Figure 6c, it can be seen that a large number of empty spaces appear as black. This is presumably because, in Comparative Example 2, the side margin area was not densified as in the Example.

[0091] The humidity resistance reliability of the sample chips from Comparative Example 1 and the Example was evaluated. The humidity resistance reliability evaluation was carried out for approximately 2 hours in an environment of 85°C, 85% humidity, and 1Vr for 20 sample chips each from Comparative Example 1 and the Example. Referring to Figures 7a and 7b, in the Example, there were no sample chips with decreased insulation resistance (IR), but in Comparative Example 1, there were sample chips with a sharp decrease in insulation resistance (IR). This is presumed to be because, when the standard deviation is less than 5.3, the grain growth of dielectric crystal grains contained in the side margin is excessively suppressed, resulting in the generation of a large number of pores, which reduces the humidity resistance reliability of the sample chip.

[0092] Next, dielectric breakdown voltage (BDV) evaluation and accelerated lifetime evaluation were performed for Example and Comparative Example 2. Dielectric breakdown voltage (BDV) was calculated for 40 samples each of Example and Comparative Example 2, as the voltage value at which leakage current occurred when a DC voltage was applied under conditions of current: 0.01A and measurement time: 50ms. For accelerated lifetime evaluation, the lifetime of 40 samples each of Example and Comparative Example 2 was measured under conditions of temperature of 125°C and 1.5XVr.

[0093] Referring to Figures 8 and 9, it can be seen that Comparative Example 2 exhibited degraded BDV dispersion and lifetime characteristics compared to the Example. In the case of Comparative Example 2, it is expected that the grain growth of dielectric crystal grains contained in the side margin was not uniformly suppressed, resulting in a standard deviation exceeding 8.3. This is expected to have led to a decrease in the density of the side margin, resulting in a decline in BDV dispersion and lifetime characteristics.

[0094] In other words, when the above standard deviation satisfies 5.3 to 8.3, it can be confirmed that the reliability of the multilayer electronic component is improved.

[0095] This disclosure is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims attached. Therefore, within the scope of the technical idea of ​​this disclosure as described in the claims, various forms of substitution, modification, and alteration are possible by a person with ordinary skill in the art, and these also fall within the scope of this disclosure.

[0096] Furthermore, the expression "one embodiment" does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct characteristics of each embodiment. However, the above-presented embodiments do not preclude their realization in combination with the characteristics of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, as long as there is no contradictory or contrary explanation of that matter in the other embodiment.

[0097] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and non-connected cases. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component. [Explanation of Symbols]

[0098] 100 Stacked Electronic Components 110 Main Unit 111 Dielectric layer 112, 113 Cover section 114, 115 Side margin section G1, G2, G3, G4, G5, G6, G7, G8, G9 Dielectric crystal grains CS1, CS2, CS3 cross section UR1, UR2, UR3 upper area CR1, CR2, CR3 central region LR1, LR2, LR3 lower area 121, 122 Internal electrode 131, 132 External electrode 131a, 132a Base electrode layer 131b, 132b Plating layer

Claims

1. A capacitance forming portion including a dielectric layer and internal electrodes arranged alternately with the dielectric layer in a first direction, and a body including first and second surfaces facing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and facing each other in a second direction, and fifth and sixth surfaces connected to the first, second, third and fourth surfaces and facing each other in a third direction, External electrodes arranged on the third and fourth surfaces, respectively, The fifth and sixth surfaces are respectively arranged and include side margin portions containing a plurality of dielectric crystal grains, When measuring the average size of the plurality of dielectric crystal grains in each of the M cross-sections (M is an integer of 2 or more) of the side margin portion in the first and third directions, where the positions in the second direction are different from each other, in N regions (N is an integer of 2 or more) where the positions in the first direction are different from each other, A multilayer electronic component in which the standard deviation of the average size value measured M × N times is 5.3 or more and 8.3 or less.

2. The stacked electronic component according to claim 1, wherein the M cross-sections include a first cross-section cut at a point 1 / 10 of the length of the side margin portion in the second direction, a second cross-section cut at a point 1 / 4 of the length of the side margin portion in the second direction, and a third cross-section cut at a point 1 / 2 of the length of the side margin portion in the second direction.

3. The stacked electronic component according to claim 2, wherein the N regions include the upper region, central region, and lower region of the side margin portion.

4. The stacked electronic component according to claim 3, wherein the average size of the plurality of dielectric crystal grains measured in the central region is greater than the average size of the plurality of dielectric crystal grains measured in the upper region or the lower region.

5. The stacked electronic component according to claim 3, wherein the ratio of the average size of the plurality of dielectric crystal grains measured in the upper or lower region to the average size of the plurality of dielectric crystal grains measured in the central region is 0.923 or more and 0.987 or less.

6. The stacked electronic component according to claim 3, wherein the average size of the plurality of dielectric crystal grains measured in the central region is 200 nm or more and 300 nm or less.

7. The central region corresponds to the central region in the first direction of the volume forming section, The upper region corresponds to the uppermost region in the first direction of the volume forming portion, The stacked electronic component according to claim 3, wherein the lower region corresponds to the lowest region in the first direction of the capacitance forming portion.

8. The stacked electronic component according to any one of claims 1 to 7, wherein each of the N regions contains 500 or more of the plurality of dielectric crystal grains.

9. The stacked electronic component according to any one of claims 1 to 7, wherein the side margin portion further comprises one or more of Dy, Y, Tb, Sc, La, Nd, Eu, Gd, Ho, Er, Yb, and Lu.

10. The stacked electronic component according to any one of claims 1 to 7, wherein the side margin portion further comprises one or more of Mg and Zr.

11. The stacked electronic component according to any one of claims 1 to 7, wherein the side margin portion further comprises one or more of Mn, V, Cr, Fe, Ni, Co, and Zn.

12. The multilayer electronic component according to any one of claims 1 to 7, wherein the side margin portion further comprises one or more of Si and Al.

13. A capacitance forming portion including a dielectric layer and internal electrodes arranged alternately with the dielectric layer in a first direction, and a body including first and second surfaces facing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and facing each other in a second direction, and fifth and sixth surfaces connected to the first, second, third and fourth surfaces and facing each other in a third direction, External electrodes arranged on the third and fourth surfaces, respectively, The fifth and sixth surfaces are respectively arranged and include side margin portions containing a plurality of dielectric crystal grains, The cross-sections obtained by cutting the side margin portion at points 1 / 10, 1 / 4, and 1 / 2 of its length in the second direction are designated as the first cross-section, second cross-section, and third cross-section, respectively. The average size of the plurality of dielectric crystal grains measured in three first regions of the first cross-section whose positions in the first direction are different from each other is defined as GS1, GS2, and GS3. The average size of the plurality of dielectric crystal grains measured in three second regions of the second cross-section whose positions in the first direction are different from each other is defined as GS4, GS5, and GS6. When the average size of the plurality of dielectric crystal grains measured in three third regions of the third cross-section whose positions in the first direction are different from each other is denoted as GS7, GS8, and GS9, A multilayer electronic component in which the standard deviation of the GS1 to GS9 values ​​is 5.3 nm or more and 8.3 nm or less.

14. The first region includes a first central region corresponding to the central region of the volume forming portion in the first direction, a first upper region corresponding to the uppermost region of the volume forming portion in the first direction, and a first lower region corresponding to the lowermost region of the volume forming portion in the first direction. The second region includes a second central region corresponding to the central region of the volume forming portion in the first direction, a second upper region corresponding to the uppermost region of the volume forming portion in the first direction, and a second lower region corresponding to the lowermost region of the volume forming portion in the first direction. The stacked electronic component according to claim 13, wherein the third region includes a third central region corresponding to the central region of the capacitance forming portion in the first direction, a third upper region corresponding to the uppermost region of the capacitance forming portion in the first direction, and a third lower region corresponding to the lowermost region of the capacitance forming portion in the first direction.

15. The stacked electronic component according to claim 13 or 14, wherein GS1 to GS9 satisfy one or more of the following conditions: GS2 > GS1, GS2 > GS3, GS5 > GS4, GS5 > GS6, GS8 > GS7, and GS8 > GS9.

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