Semiconductor equipment
By integrating a lateral MOSFET or bipolar transistor as an active mirror clamp element on a SiC substrate with separate signal pads, the semiconductor device addresses the issue of Schottky barriers, improving misfire control and preventing false firing.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2024-12-20
- Publication Date
- 2026-07-02
Smart Images
Figure 2026109973000001_ABST
Abstract
Description
[Technical Field]
[0001] This disclosure relates to semiconductor devices. [Background technology]
[0002] Protection design is an important element in the design of power elements. One of the factors that necessitates protection of power elements is gate voltage floating. For example, if the gate voltage rises above a predetermined value due to displacement current generated during a steep switching process, false firing occurs. The semiconductor device described in Patent Document 1 suppresses the occurrence of false firing by an active mirror clamp circuit. [Prior art documents] [Patent Documents]
[0003] [Patent Document 1] Japanese Patent Publication No. 2016-174033 [Overview of the Initiative] [Problems that the invention aims to solve]
[0004] When an active mirror clamp circuit is provided on a SiC substrate, for example, a Schottky barrier formed between the p-type SiC region formed by impurity implantation and the metal electrode can hinder the realization of ohmic contact, reducing the misfire control function of the mirror clamp circuit.
[0005] This disclosure aims to provide a semiconductor device that improves the controllability of misfiring in order to solve the above-mentioned problems. [Means for solving the problem]
[0006] The semiconductor device according to the present disclosure includes a power element, an active mirror clamp element, a gate signal pad, and an active mirror clamp signal pad. The power element is formed on a semiconductor substrate. The active mirror clamp element is a horizontal element formed on the semiconductor substrate via an insulating film. The gate signal pad is electrically connected to the gate electrode of the power element. The active mirror clamp signal pad is provided independently of the gate signal pad and is electrically connected to the control electrode of the active mirror clamp element. The first current electrode of the active mirror clamp element is electrically connected to the gate electrode of the power element. The second current electrode of the active mirror clamp element is electrically connected to one current electrode of the power element.
Effect of the Invention
[0007] According to the present disclosure, a semiconductor device with improved controllability of false arcing is provided.
[0008] The object, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.
Brief Description of the Drawings
[0009] [Figure 1] It is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 1. [Figure 2] It is a circuit diagram showing the configuration of the semiconductor device. [Figure 3] It is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 2. [Figure 4] It is a circuit diagram showing the configuration of the semiconductor device. [Figure 5] It is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 3. [Figure 6] It is a circuit diagram showing the configuration of the semiconductor device. [Figure 7] It is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 4. [Figure 8] It is a circuit diagram showing the configuration of the semiconductor device.
Best Mode for Carrying Out the Invention
[0010] <Embodiment 1> FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device 101 in Embodiment 1. FIG. 2 is a circuit diagram showing the configuration of the semiconductor device 101.
[0011] The semiconductor device 101 includes an element region A, an active mirror clamp circuit region B, and a wiring region C within one semiconductor chip. In the element region A, a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is provided as the power element 10. In the active mirror clamp circuit region B, a lateral MOSFET is provided as the active mirror clamp element 20. The active mirror clamp element 20 is a switching element different from the power element 10 and is provided within the semiconductor chip in which the power element 10 is formed. In other words, the active mirror clamp element 20 is built into the semiconductor chip in which the power element 10 is formed.
[0012] The vertical MOSFET, which is the power element 10, is formed of SiC. The vertical MOSFET includes an n-type drift layer 11, a p-type well region 12, an n-type well region 13, an n-type drain layer 14, an insulating film 15, a gate electrode 16, a source electrode 17, and a drain electrode 18. The SiC substrate is composed of an n-type drift layer 11, a p-type well region 12, an n-type well region 13, and an n-type drain layer 14. - The n-type drift layer 11 is provided on the surface side of the SiC substrate. The p-type well region 12 is provided in a part of the surface layer of the n-type drift layer 11. The n-type well region 13 is provided in a part of the surface layer of the p-type well region 12. From the surface of the SiC substrate, an n-type... + + + + - + + + + +
[0013] n- - The n-type drift layer 11 is provided on the surface side of the SiC substrate. The p-type well region 12 is provided in a part of the surface layer of the n-type drift layer 11. The n-type well region 13 is provided in a part of the surface layer of the p-type well region 12. - - + +- Type drift layer 11, p-type well region 12 and n + The type well region 13 is exposed.
[0014] The insulating film 15 is made of n that make up the surface of the SiC substrate - Type drift layer 11, p-type well region 12 and n + It is provided on the surface of the mold well region 13. The insulating film 15 of Embodiment 1 is shown in Figure 1 on the left side n + Type well region 13 and right side n + p-type well region 12 and n-type well region 13 are located between them. - It covers the mold drift layer 11. The gate electrode 16 is provided on its insulating film 15. The source electrode 17 is on the surface of the SiC substrate n + With the n in contact with the type well region 13 + It is electrically connected to the type well region 13.
[0015] n + The drain layer 14 is provided on the back side of the SiC substrate. The drain electrode 18 is located on the back side of the SiC substrate. + With the n in contact with the type drain layer 14 + The drain layer 14 is electrically connected.
[0016] Multiple cells (not shown) are regularly arranged in element region A. A vertical MOSFET is formed in each of these cells. However, the shape and arrangement of each cell are not limited to the configuration shown in Figure 1.
[0017] Active mirror clamp circuit region B includes the field oxide film 21 and the active mirror clamp element 20. The field oxide film 21 is made of n that constitute the surface of the SiC substrate. - It is provided on the mold drift layer 11.
[0018] The active mirror clamp element 20 is provided on the field oxide film 21 and is made of polysilicon. The active mirror clamp element 20 of Embodiment 1 is an N-channel enhancement type MOSFET. The N-channel enhancement type MOSFET has a p-type Poly-Si layer 22, n + It includes a poly-Si region 23, an insulating film 24, a gate electrode 25, a source electrode 26, and a drain electrode 27.
[0019] The p-type Poly-Si layer 22 is provided on the field oxide film 21. + The p-type Poly-Si region 23 is provided on a part of the surface layer of the p-type Poly-Si layer 22. Here, two n + A poly-Si region 23 is provided. The insulating film 24 is, as shown in Figure 1, on the left side n + Poly-Si region 23 and the right side n + The surface of the p-type Poly-Si layer 22 is covered between the p-type Poly-Si region 23 and the other type Poly-Si region 23. The gate electrode 25 is provided on the insulating film 24. The source electrode 26 consists of two n + The left side of the Poly-Si region 23 + It is electrically connected in contact with the Poly-Si region 23. The drain electrode 27 is on the right side n + It is electrically connected while in contact with the Poly-Si region 23.
[0020] The wiring region C includes gate voltage wiring 31, active mirror clamp circuit signal wiring 32, gate signal pad 33, and active mirror clamp signal pad 34. The gate voltage wiring 31 and active mirror clamp circuit signal wiring 32 are provided on the field oxide film 21. The gate signal pad 33 and active mirror clamp signal pad 34 are different pads but are provided within the same semiconductor chip. In other words, the active mirror clamp signal pad 34 is provided within the semiconductor chip independently of the gate signal pad 33.
[0021] The gate signal pad 33 is electrically connected to the gate electrode 16 of the power element 10 and the drain electrode 27 of the active mirror clamp element 20 via the gate voltage wiring 31. In other words, the drain electrode 27 of the active mirror clamp element 20 is electrically connected to the gate electrode 16 of the power element 10.
[0022] The active mirror clamp signal pad 34 is electrically connected to the gate electrode 25 of the active mirror clamp element 20 via the active mirror clamp circuit signal wiring 32.
[0023] Furthermore, the source electrode 26 of the active mirror clamp element 20 is electrically connected to the source electrode 17 of the power element 10. The source electrode 26 of the active mirror clamp element 20 and the source electrode 17 of the power element 10 are connected to the source terminal 19.
[0024] When semiconductor device 101 is ON, a positive bias is applied to the gate signal pad 33 and a negative bias is applied to the active mirror clamp signal pad 34. A positive bias gate voltage is applied to the gate electrode 16 of power element 10, causing power element 10 to operate. A negative bias control voltage is applied to the gate electrode 25 of active mirror clamp element 20, causing active mirror clamp element 20 to not operate.
[0025] When the semiconductor device 101 is in the off state, a negative bias is applied to the gate signal pad 33 and a positive bias is applied to the active mirror clamp signal pad 34. A control voltage of the positive bias is applied to the gate electrode 16 of the active mirror clamp element 20, causing the active mirror clamp element 20 to operate. As a result, the gate electrode 16 and source electrode 17 of the power element 10 are short-circuited via the active mirror clamp element 20, thus preventing false firing of the power element 10.
[0026] In summary, the semiconductor device 101 in Embodiment 1 includes a power element 10, an active mirror clamp element 20, a gate signal pad 33, and an active mirror clamp signal pad 34. The power element 10 is formed on a SiC substrate as a semiconductor substrate. The active mirror clamp element 20 includes a MOSFET as a lateral element formed on the semiconductor substrate via a field oxide film as an insulating film. The gate signal pad 33 is electrically connected to the gate electrode 16 of the power element 10. The active mirror clamp signal pad 34 is provided independently of the gate signal pad 33 and is electrically connected to the gate electrode 25 as a control electrode of the active mirror clamp element 20. The drain electrode 27 as the first current electrode of the active mirror clamp element 20 is electrically connected to the gate electrode 16 of the power element 10. The source electrode 26 as the second current electrode of the active mirror clamp element 20 is electrically connected to the source electrode 17 as a one-way current electrode of the power element 10.
[0027] Such a semiconductor device 101 improves the controllability of misfires. Furthermore, the active mirror clamp element 20 is formed of polysilicon on a SiC substrate. Since the active mirror clamp element 20 is not formed by impurity implantation into the SiC substrate, the problems caused by Schottky barriers between the p-type SiC region formed by impurity implantation and the metal electrode do not occur.
[0028] <Embodiment 2> Figure 3 is a cross-sectional view showing the configuration of the semiconductor device 102 in Embodiment 2. Figure 4 is a circuit diagram showing the configuration of the semiconductor device 102.
[0029] A vertical MOSFET is provided as a power element 10 in element region A. This vertical MOSFET has the same configuration as in Embodiment 1.
[0030] Active mirror clamp circuit region B includes the field oxide film 21 and the active mirror clamp element 20. The field oxide film 21 is made of n that constitute the surface of the SiC substrate.- It is provided on the mold drift layer 11.
[0031] The active mirror clamp element 20 is a switching element separate from the power element 10 and is a lateral MOSFET. The active mirror clamp element 20 is provided on the field oxide film 21 and is located within the semiconductor chip on which the power element 10 is formed. The active mirror clamp element 20 in Embodiment 2 is a P-channel depletion type MOSFET.
[0032] The P-channel depletion MOSFET is formed from polysilicon. The P-channel depletion MOSFET has an n-type Poly-Si layer 28, p + It includes a poly-Si region 29, an insulating film 24, a gate electrode 25, a source electrode 27, and a drain electrode 26.
[0033] The n-type Poly-Si layer 28 is provided on the field oxide film 21. + The n-type Poly-Si region 29 is located on a part of the surface layer of the n-type Poly-Si layer 28. Here, two p + A poly-Si region 29 is provided. The insulating film 24 is, as shown in Figure 3, p on the left side + Poly-Si region 29 and the right side p + The surface of the n-type Poly-Si layer 28 is covered between the n-type Poly-Si region 29 and the n-type Poly-Si region 29. The gate electrode 25 is provided on the insulating film 24. The source electrode 27 consists of two p + The right side of the Poly-Si region 29 + It is electrically connected in contact with the poly-Si region 29. The drain electrode 26 is on the left side p + It is electrically connected while in contact with the Poly-Si region 29.
[0034] The wiring region C includes gate voltage wiring 31 and gate signal pad 33. The gate voltage wiring 31 is provided on the field oxide film 21. The gate signal pad 33 is provided within the semiconductor chip.
[0035] The gate signal pad 33 is electrically connected to the gate electrode 16 of the power element 10, the gate electrode 25 and source electrode 27 of the active mirror clamp element 20 via the gate voltage wiring 31. In other words, the gate electrode 25 and source electrode 27 of the active mirror clamp element 20 are electrically connected to the gate electrode 16 of the power element 10.
[0036] Furthermore, the drain electrode 26 of the active mirror clamp element 20 is electrically connected to the source electrode 17 of the power element 10.
[0037] When the semiconductor device 102 is turned ON, a positive bias is applied to the gate signal pad 33. This applies a positive bias to the gate electrode 16 of the power element 10 and the gate electrode 25 of the active mirror clamp element 20. As a result of this positive bias, the power element 10 operates, but the active mirror clamp element 20 does not operate because it is a P-channel depletion type MOSFET.
[0038] When the semiconductor device 102 is in the off state, a negative bias is applied to the gate signal pad 33. This applies a negative bias to the gate electrode 25 of the active mirror clamp element 20. The active mirror clamp element 20 operates because it is a P-channel depletion type MOSFET. As a result, the gate electrode 16 and source electrode 17 of the power element 10 are short-circuited via the active mirror clamp element 20, thus preventing false firing of the power element 10.
[0039] In such a semiconductor device 102, the power supply for operating the power element 10 and the active mirror clamp element 20 is shared, eliminating the need for a separate power supply for the active mirror clamp element.
[0040] <Embodiment 3> Figure 5 is a cross-sectional view showing the configuration of the semiconductor device 103 in Embodiment 3. Figure 6 is a circuit diagram showing the configuration of the semiconductor device 103.
[0041] A vertical MOSFET is provided as a power element 10 in element region A. This vertical MOSFET has the same configuration as in Embodiment 1.
[0042] Active mirror clamp circuit region B includes the field oxide film 21 and the active mirror clamp element 20. The field oxide film 21 is made of n that constitute the surface of the SiC substrate. - It is provided on the mold drift layer 11.
[0043] The active mirror clamp element 20 is a switching element separate from the power element 10, and is a lateral bipolar transistor. The active mirror clamp element 20 is provided on the field oxide film 21 and is located within the semiconductor chip on which the power element 10 is formed.
[0044] The lateral bipolar transistor, which is the active mirror clamp element 20, is formed of, for example, polysilicon. The lateral transistor has an n-type semiconductor region 28A, p + This is a pnp transistor including a semiconductor region 29A, a base electrode 25A as a control electrode, an emitter electrode 26A as a second current electrode, and a collector electrode 27A as a first current electrode.
[0045] n-type semiconductor region 28A and p + The type semiconductor region 29A is provided on the field oxide film 21. Here, two p + A type semiconductor region 29A is provided, and the n-type semiconductor region 28A has two p + It is sandwiched between n-type semiconductor regions 29A. The base electrode 25A is provided on the n-type semiconductor region 28A. The emitter electrode 26A is provided with two p-type semiconductor regions as shown in Figure 5. + In the type semiconductor region 29A, the left side is p +It is electrically connected in contact with the type semiconductor region 29A. The collector electrode 27A is on the right side p + It is electrically connected while in contact with the semiconductor region 29A.
[0046] The active mirror clamp element 20 controls the current flowing between the emitter electrode 26A and the collector electrode 27A by a control voltage applied between the base electrode 25A and the emitter electrode 26A.
[0047] The wiring region C includes gate voltage wiring 31, active mirror clamp circuit signal wiring 32, gate signal pad 33, and active mirror clamp signal pad 34. The gate voltage wiring 31 and active mirror clamp circuit signal wiring 32 are provided on the field oxide film 21. The gate signal pad 33 and active mirror clamp signal pad 34 are different pads but are provided within the same semiconductor chip. In other words, the active mirror clamp signal pad 34 is provided within the semiconductor chip independently of the gate signal pad 33.
[0048] The gate signal pad 33 is electrically connected to the gate electrode 16 of the power element 10 and the collector electrode 27A of the active mirror clamp element 20 via the gate voltage wiring 31. In other words, the collector electrode 27A of the active mirror clamp element 20 is electrically connected to the gate electrode 16 of the power element 10.
[0049] The active mirror clamp signal pad 34 is electrically connected to the base electrode 25A of the active mirror clamp element 20 via the active mirror clamp circuit signal wiring 32.
[0050] Furthermore, the emitter electrode 26A of the active mirror clamp element 20 is electrically connected to the source electrode 17 of the power element 10.
[0051] When semiconductor device 103 is ON, a positive bias is applied to the gate signal pad 33 and a negative bias is applied to the active mirror clamp signal pad 34. A positive bias gate voltage is applied to the gate electrode 16 of power element 10, causing power element 10 to operate. A negative bias control voltage is applied to the base electrode 25A of active mirror clamp element 20, causing active mirror clamp element 20 to not operate.
[0052] When the semiconductor device 103 is in the off state, a negative bias is applied to the gate signal pad 33 and a negative bias is applied to the active mirror clamp signal pad 34. A control voltage for the negative bias is applied to the base electrode 25A of the active mirror clamp element 20, causing the active mirror clamp element 20 to operate. Through the active mirror clamp element 20, the gate electrode 16 and source electrode 17 of the power element 10 are short-circuited, thus preventing false firing of the power element 10.
[0053] Note that the power element 10 may also be a vertical IGBT (Insulated-Gate Bipolar Transistor). In that case, the n shown in Figure 5 + The drain layer 14 is p + It is replaced with a type collector layer. Also, the first main electrode 17A of the power element 10 corresponds to the emitter electrode, and the second main electrode 18A corresponds to the collector electrode. This is also applied in the earlier embodiments 1 and 2 and the later embodiment 4. When the power element 10 is an IGBT, a semiconductor device 103 that can be used in the high voltage and high current region is realized.
[0054] <Embodiment 4> Figure 7 is a cross-sectional view showing the configuration of the semiconductor device 104 in Embodiment 4. Figure 8 is a circuit diagram showing the configuration of the semiconductor device 104.
[0055] A power element 10 is provided in element region A. The power element 10 shown in Figure 7 is a vertical MOSFET. In other words, the vertical MOSFET of Embodiment 4 has the same configuration as Embodiment 1.
[0056] Active mirror clamp circuit region B includes the field oxide film 21 and the active mirror clamp element 20. The field oxide film 21 is made of n that constitute the surface of the SiC substrate. - It is provided on the mold drift layer 11.
[0057] The active mirror clamp element 20 is a switching element separate from the power element 10 and is a lateral transistor. The active mirror clamp element 20 is provided on the field oxide film 21 and is located within the semiconductor chip on which the power element 10 is formed. The lateral transistor in Embodiment 4 is a PNP transistor having the same configuration as in Embodiment 3. This embodiment can also be applied to Embodiment 1 or Embodiment 2.
[0058] In wiring region C, a chip-integrated gate resistor 35 is provided, which is associated with the gate of the power element 10. One end of the chip-integrated gate resistor 35 is connected to the collector electrode 27A of the active mirror clamp element 20. The other end of the chip-integrated gate resistor 35 is connected to the gate electrode 16 of the power element 10.
[0059] Even if a chip-integrated gate resistor 35 exists within the chip, this embodiment makes it possible to control misfires by avoiding the resistor.
[0060] This disclosure allows for the free combination of each embodiment, and enables the modification or omission of each embodiment as appropriate.
[0061] The various aspects of this disclosure are summarized below as an appendix.
[0062] (Note 1) A power element formed on a semiconductor substrate, The active mirror clamp element, which is a lateral element formed on the semiconductor substrate via an insulating film, A gate signal pad electrically connected to the gate electrode of the power element, The system includes an active mirror clamp signal pad, which is provided independently of the gate signal pad and electrically connected to the control electrode of the active mirror clamp element, The first current electrode of the active mirror clamp element is electrically connected to the gate electrode of the power element. A semiconductor device in which the second current electrode of the active mirror clamp element is electrically connected to one current electrode of the power element.
[0063] (Note 2) A power element formed on a semiconductor substrate, The system includes an active mirror clamp element which includes a P-channel depletion type lateral MOSFET formed on the semiconductor substrate via an insulating film, The gate electrode of the active mirror clamp element is electrically connected to the gate electrode of the power element. The drain electrode of the active mirror clamp element is electrically connected to the gate electrode of the power element. A semiconductor device in which the source electrode of the active mirror clamp element is electrically connected to one current electrode of the power element.
[0064] (Note 3) Furthermore, it includes a chip-integrated gate resistor, One end of the chip-integrated gate resistor is connected to the first current electrode or the drain electrode of the active mirror clamp element. The semiconductor device according to Appendix 1 or Appendix 2, wherein the other end of the chip-integrated gate resistor is connected to the gate electrode of the power element.
[0065] (Note 4) The power element is a transistor of either a vertical IGBT or a vertical MOSFET, as described in any one of the items in Appendix 1 to 3 of the semiconductor device.
[0066] (Note 5) The semiconductor device according to any one of Appendix 1, Appendix 3, or Appendix 4, wherein the active mirror clamp element is a lateral enhancement type MOSFET or a lateral bipolar transistor.
[0067] (Note 6) The semiconductor substrate on which the power element is formed is a SiC substrate, and the insulating film on the semiconductor substrate is a field oxide film. The semiconductor device according to any one of the appendices 1 to 5, wherein the active mirror clamp element is formed of polysilicon provided on the field oxide film. [Explanation of Symbols]
[0068] 10 power elements, 11 n - Type drift layer, 12 p-type well region, 13 n + Type well region, 14 n + 15 Drain layer, 16 Insulating film, 17 Electrode, 17A First main electrode, 18 Drain electrode, 18A Second main electrode, 19 Source terminal, 20 Active mirror clamp element, 21 Field oxide film, 22 p-type Poly-Si layer, 23 n + n-type Poly-Si region, 24 insulating film, 25 gate electrode, 25A base electrode, 26 source electrode (drain electrode), 26A emitter electrode, 27 drain electrode (source electrode), 27A collector electrode, 28 n-type Poly-Si layer, 28A n-type semiconductor region, 29 p + Type Poly-Si region, 29A p +Semiconductor region, 31 Gate voltage wiring, 32 Active mirror clamp circuit signal wiring, 33 Gate signal pad, 34 Active mirror clamp signal pad, 35 Chip-integrated gate resistor, 101-104 Semiconductor device, A Element region, B Active mirror clamp circuit region, C Wiring region.
Claims
1. A power element formed on a semiconductor substrate, The active mirror clamp element, which is a lateral element formed on the semiconductor substrate via an insulating film, A gate signal pad electrically connected to the gate electrode of the power element, The system includes an active mirror clamp signal pad, which is provided independently of the gate signal pad and electrically connected to the control electrode of the active mirror clamp element, The first current electrode of the active mirror clamp element is electrically connected to the gate electrode of the power element. A semiconductor device in which the second current electrode of the active mirror clamp element is electrically connected to one current electrode of the power element.
2. A power element formed on a semiconductor substrate, The active mirror clamp element includes a P-channel depletion type lateral MOSFET formed on the semiconductor substrate via an insulating film, The gate electrode of the active mirror clamp element is electrically connected to the gate electrode of the power element. The drain electrode of the active mirror clamp element is electrically connected to the gate electrode of the power element. A semiconductor device in which the source electrode of the active mirror clamp element is electrically connected to one current electrode of the power element.
3. Furthermore, it includes a chip-integrated gate resistor, One end of the chip-integrated gate resistor is connected to the first current electrode or the drain electrode of the active mirror clamp element. The semiconductor device according to claim 1 or claim 2, wherein the other end of the chip-integrated gate resistor is connected to the gate electrode of the power element.
4. The semiconductor device according to claim 1 or claim 2, wherein the power element is a transistor that is either a vertical IGBT or a vertical MOSFET.
5. The semiconductor device according to claim 1, wherein the active mirror clamp element is a lateral enhancement type MOSFET or a lateral bipolar transistor.
6. The semiconductor substrate on which the power element is formed is a SiC substrate, and the insulating film on the semiconductor substrate is a field oxide film. The semiconductor device according to claim 1 or 2, wherein the active mirror clamp element is formed of polysilicon provided on the field oxide film.