Semiconductor device and method for manufacturing a semiconductor device

Abstract

This can improve the transistor characteristics in semiconductor devices. [Solution] The semiconductor device of the embodiment includes a first electrode BE, a second electrode TE provided above the first electrode BE in a first direction perpendicular to the surface of the first electrode BE, an oxide semiconductor 40 extending in the first direction having one end in contact with the first electrode BE and the other end in contact with the second electrode TE, gate insulating films 41, 42 surrounding the side surface of the oxide semiconductor 40, and a gate electrode 23 surrounding the side surface of the gate insulating films 41, 42, wherein the gate electrode 23 includes a recess 90 provided on the surface facing the oxide semiconductor 40.

Description

Technical Field

[0006] ,

[0004] , , , , , , [Figure 1] , , , , , ,

[0005] ,

[0001] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Research and development of semiconductor devices having transistors using an oxide semiconductor for a channel have been promoted.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Embodiments for Carrying Out the Invention

[0007] Referring to FIGS. 1 to 23, the semiconductor device and the manufacturing method of the semiconductor device according to the embodiment will be described. In the following description, elements having the same function and configuration are denoted by the same reference numerals. Also, in each of the following embodiments, when components (for example, circuits, wirings, various voltages and signals, etc.) with reference numerals accompanied by numbers / letters for differentiation at the end do not need to be distinguished from each other, descriptions (reference numerals) with the numbers / letters at the end omitted are used. The drawings are schematic, and the relationship between the film thickness and the planar dimensions, the ratio of the film thicknesses of each layer, etc. may be different from the actual ones. Therefore, specific film thicknesses and dimensions should be determined in consideration of the following description. Also, there may be portions where the dimensional relationships and ratios are different between the drawings.

[0008] (Embodiment) (1) First Embodiment Referring to FIGS. 1 to 13, the semiconductor device and the manufacturing method of the semiconductor device according to the first embodiment will be described.

[0009] (a) Configuration The configuration of the semiconductor device according to the first embodiment will be described.

[0010] (a-1) Memory System The configuration of the memory system including the semiconductor device of this embodiment will be explained using Figure 1. Figure 1 is a block diagram showing an example of the configuration of the memory system including the semiconductor device of this embodiment.

[0011] The memory system 100 performs data writing and reading operations, etc., in response to commands from an external host device (not shown).

[0012] The memory system 100 includes a semiconductor device 1 and a memory controller 2.

[0013] (a-1-1) Internal configuration of semiconductor device 1 The semiconductor device 1 is a memory device that uses transistors to select the memory element to be operated on. The semiconductor device 1 stores data using, for example, capacitors as memory elements. The semiconductor device 1 is, for example, a DRAM (Dynamic Random Access Memory). The memory controller 2 controls the semiconductor device 1.

[0014] The semiconductor device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a write circuit 15, a read circuit 16, a row selection circuit 17, a column selection circuit 18, and a sense amplifier 19.

[0015] The memory cell array 11 includes multiple memory cells MC, multiple word lines WL, multiple bit lines BL, and plate lines PL. In Figure 1, one memory cell MC, one word line WL, and one bit line BL are illustrated. Each memory cell MC stores one bit of data. Each memory cell MC is connected between a corresponding bit line BL from among the multiple bit lines BL and a plate line PL. Each memory cell MC is connected to a corresponding word line WL from among the multiple word lines WL. Word lines WL are associated with rows. Bit lines BL are associated with columns. In the memory cell array 11, one memory cell MC is identified by selecting one row and one column.

[0016] The input / output circuit 12 receives a control signal CNT, a command CMD, an address ADD, and data DAT from the memory controller 2. The input / output circuit 12 sends data DAT to the memory controller 2. When data is written to the semiconductor device 1, data DAT is the written data Dw. When data is read from the semiconductor device 1, data DAT is the read data Dr.

[0017] The control circuit 13 receives a control signal CNT and a command CMD from the input / output circuit 12. Based on the control signal CNT and the command CMD, the control circuit 13 instructs the write circuit 15 to write data DAT to the memory cell array 11. Based on the control signal CNT and the command CMD, the control circuit 13 instructs the read circuit 16 to read data from the memory cell array 11. Based on the control signal CNT and the command CMD, the control circuit 13 instructs the voltage generation circuit 14 to generate various voltages.

[0018] The voltage generation circuit 14 generates various voltages used for operation of the memory cell array 11 based on instructions from the control circuit 13. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 15, the read circuit 16, the row selection circuit 17, the column selection circuit 18, and the sense amplifier 19.

[0019] The writing circuit 15 performs processing and control for writing data to the memory cell MC. The writing circuit 15 receives the write data Dw from the input / output circuit 12. The write data Dw is the data to be written to the memory cell MC that is the target of the data writing. The writing circuit 15 receives one or more voltages used in the data writing operation from the voltage generation circuit 14. Based on the control of the control circuit 13 and the write data Dw, the writing circuit 15 supplies one or more voltages used in the data writing operation to the column selection circuit 18.

[0020] The read circuit 16 performs processing and control for reading data from the memory cell MC. The read circuit 16 receives one or more voltages from the voltage generation circuit 14 that are used in the data reading operation. Based on the control of the control circuit 13, the read circuit 16 uses the voltages used in the data reading operation to determine the data stored in the memory cell MC. The determined data is supplied to the input / output circuit 12 as read data Dr.

[0021] The row selection circuit 17 receives address ADD from the input / output circuit 12. The row selection circuit 17 supplies the voltage supplied from the voltage generation circuit 14 to the memory cell array 11. This causes the row selection circuit 17 to select one word line WL associated with the row identified by address ADD.

[0022] The column selection circuit 18 receives address ADD from the input / output circuit 12. The column selection circuit 18 supplies the voltage supplied from the voltage generation circuit 14 to the memory cell array 11. As a result, the column selection circuit 18 sets the bit line BL associated with the column identified by address ADD to the selected state.

[0023] The sense amplifier 19 uses the voltage received from the voltage generation circuit 14 to amplify the voltage of the bit line BL during data readout operations in order to determine the data stored in the memory cell MC to be read.

[0024] (a-1-2) Circuit configuration of memory cell array The circuit configuration of the memory cell array 11 of the semiconductor device 1 in this embodiment will be explained using Figure 2. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 11 of the semiconductor device 1 in this embodiment.

[0025] The memory cell array 11 includes m word lines WL(WL1,...,WLm), n bit lines BL(BL1,...,BLn), and plate lines PL, where m and n are positive integers.

[0026] Each of the multiple bit lines BL is connected to, for example, m memory cells MC, which correspond to one bit line BL among multiple memory cells MC. Each of the m memory cells MC, which correspond to one bit line BL, is connected to, for example, one word line, among m word lines WL.

[0027] Each memory cell MC includes a cell capacitor CC and a cell transistor CT.

[0028] A cell transistor (CT) is a switching element (selection element) used to select the memory element to operate on. A cell transistor CT is, for example, an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the following, one of the source and drain of a cell transistor CT will be simply referred to as one end of the cell transistor CT, and the other end will be simply referred to as the other end of the cell transistor CT. One end of each cell transistor CT is connected to a bit line BL associated with the cell transistor CT. The gate of each cell transistor CT is connected to a word line WL associated with the cell transistor CT.

[0029] The semiconductor constituting part of a cell transistor (CT) includes a region (channel region) where the transistor's channel is formed. The semiconductor material includes an oxide semiconductor. When the material is composed of configuration A, the material may contain unintended impurities different from those in configuration A.

[0030] A cell capacitor CC is a capacitive element that functions as a memory element. One electrode at one end of each cell capacitor CC is connected to the other end of the cell transistor CT corresponding to the cell capacitor CC. The other electrode at the other end of each cell capacitor CC is connected to a plate wire PL. The cell capacitor CC stores data based on the charge accumulated in the node SN connected to the cell transistor CT. In the following, the node SN where the charge of the cell capacitor CC is accumulated is also called the storage node SN.

[0031] Depending on the amount of charge accumulated in the storage node SN, the state in which the memory cell MC is storing "1" data or the state in which the memory cell MC is storing "0" data is determined. In the following, as an example, the state in which the potential of the storage node SN is charged to a potential relatively higher than the potential of the plate wire PL is considered to be the state in which the memory cell MC is storing "1" data. The state in which the storage node SN is charged to a potential relatively lower than the potential of the plate wire PL is considered to be the state in which the memory cell MC is storing "0" data.

[0032] With the above configuration, in each memory cell MC, the cell capacitor CC and the cell transistor CT are connected in series between the bit line BL corresponding to the memory cell MC and the plate line PL.

[0033] (a-1-3) Planar layout of memory cell array The planar layout of the memory cell array 11 of the semiconductor device 1 of this embodiment will be explained using Figure 3. Figure 3 is a plan view showing an example of the planar layout of the memory cell array 11 of the semiconductor device 1 of this embodiment. In Figure 3, as an example, four word lines WL1,...,WL4 and four bit lines BL1,...,BL4 are shown.

[0034] In the following explanation, the X direction is approximately parallel to the substrate of the semiconductor device 1. The X direction corresponds to the extension direction of the word line WL. The Y direction is approximately parallel to the substrate of the semiconductor device 1 and perpendicular to the X direction. The Y direction corresponds to the extension direction of the bit line BL. The Z direction is approximately perpendicular to the substrate. In the Z direction, the side facing the memory cell array 11 from the substrate is called the upper side. In the Z direction, the side facing the substrate from the memory cell array 11 is called the lower side. Of the two faces of a component perpendicular to the Z direction, the upper face is called the top surface, and the lower face is called the bottom surface. A face of a component that is substantially parallel to the Z direction (a face that intersects the X and Y directions) is called a side surface.

[0035] The memory cell array 11 includes multiple pillars PI associated with multiple bit lines BL and multiple word lines WL, multiple conductors GE, and multiple upper electrodes TE.

[0036] Each pillar PI functions, for example, as a component of a cell transistor CT. If the cell transistor CT is a vertical transistor, each pillar PI contains a semiconductor that forms the channel region of the cell transistor CT.

[0037] In this embodiment, each of the multiple conductors GE functions as the gate electrode GE and word line WL of the cell transistor CT.

[0038] Figure 3 shows the sets of pillar PIs for four rows. Each of the four sets of pillar PIs in a row corresponds to a word line WL1, ..., WL4. In each row, the four pillar PIs are arranged along the X direction. In each set of pillar PIs in a row, the four pillar PIs are arranged, for example, at substantially equal intervals in the X direction. In sets of pillar PIs for two adjacent rows in the Y direction, the positions of each of the four pillar PIs in one row differ in the X direction from the positions of each of the four pillar PIs in the other row. Due to this arrangement, in sets of pillar PIs for two adjacent rows in the Y direction, the four pillar PIs in one row and the four pillar PIs in the other row are offset in the X direction. For example, the pillar PIs in odd-numbered rows are adjacent to the pillar PIs in even-numbered rows in directions that intersect the X and Y directions.

[0039] In Figure 3, the case where each of the four rows contains four pillar PIs is shown, but the number of rows with pillar PIs and the number of pillar PIs in each row are not limited to these numbers. The number of rows with pillar PIs and the number of pillar PIs in each row can be changed as appropriate.

[0040] Each pillar PI is connected to the corresponding bit line BL via the upper electrode TE. Each of the multiple bit line BLs extends along the Y direction. The multiple bit line BLs are aligned along the X direction. In the following, of bit line BL1 and bit line BL4, the side of bit line BL1 is referred to as one end in the X direction, and the side of bit line BL4 is referred to as the other end in the X direction. Each bit line BL is positioned such that, when viewed from the Z direction, it overlaps with at least a portion of one of the pillar PIs in the set of pillar PIs in each row. Each bit line BL overlaps, for example, with respect to the X direction, with respect to one end of a pillar PI contained in the row corresponding to word line WL1 or word line WL3 (contained in an odd-numbered row). Each bit line BL overlaps, for example, with respect to the X direction, with respect to the other end of a pillar PI contained in the row corresponding to word line WL2 or word line WL4 (contained in an even-numbered row).

[0041] Each bit line BL is electrically connected to each pillar PI that overlaps with the bit line BL. The number of pillar PIs that overlap with the bit line BL can be designed to be any number, depending on the number of word lines WL.

[0042] Each gate electrode GE (word line WL) extends in the X direction. Multiple gate electrode GEs are aligned in the Y direction. When viewed from the Z direction, each gate electrode GE is positioned to surround the pillar PI corresponding to that gate electrode GE. The gate electrode GE faces the side of the pillar PI.

[0043] (a-1-4) Cross-sectional structure of a memory cell array The cross-sectional structure of the memory cell array 11 of the semiconductor device 1 of the embodiment will be described using Figures 4 and 5. Figure 4 is a cross-sectional view along line IV-IV in Figure 3, showing an example of the cross-sectional structure of the memory cell array 11 of the semiconductor device 1 of the embodiment. Figure 5 is a cross-sectional view along line VV in Figure 3, showing an example of the cross-sectional structure of the memory cell array 11 of the semiconductor device 1 of the embodiment.

[0044] The memory cell array 11 includes a plurality of conductors 21-29, insulators 31-36, a plurality of oxide semiconductors 40, a plurality of gate insulating films 41, 42, and a component SLT.

[0045] An insulator 31 is provided above the substrate SUB.

[0046] The electrodes at one end of each of the multiple cell capacitors CC are provided so as to overlap with at least a portion of the insulator 31 in the Z direction. In the following, the electrodes at one end of the cell capacitor CC will also be simply referred to as the cell capacitor CC. The multiple cell capacitors CC include a conductive material. This material includes, for example, silicon (Si). An example of this material is silicon germanium. The cell capacitor CC has, for example, a columnar shape extending along the Z direction. The shape of the columnar cell capacitor CC in the XY cross-section may be, for example, circular (or elliptical) or polygonal (for example, quadrilateral).

[0047] Multiple conductors 21 are provided above multiple cell capacitors CC, corresponding to the multiple cell capacitors CC. The conductors 21 overlap with at least a portion of the insulator 31 in the Z direction. The conductors 21 include, for example, conductive oxides. The multiple conductors 21 include, for example, at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo), and oxygen (O). The conductors 21 include, for example, indium (In), tin (Sn), and oxygen (O). The conductors 21 include, for example, ITO (Indium Tin Oxide).

[0048] Multiple conductors 22 are provided below the lower surface of each conductor 21 and on the side surface of each conductor 21. The lower surface of each conductor 22 is in contact with the upper surface of the cell capacitor CC corresponding to the conductor 22.

[0049] For example, the upper surfaces of multiple conductors 21, 22 are aligned with the upper surface of the insulator 31. A pair of conductors 21, 22 that correspond to each other function as a lower electrode BE.

[0050] Insulators 32, 33, and 34 are provided in this order, moving upward, on the upper surface of insulator 31 and on the upper surfaces of the multiple conductors 21 and 22.

[0051] A cell transistor is a vertical transistor that includes an oxide semiconductor 40 as the channel region.

[0052] Each of the multiple oxide semiconductors 40 has a columnar structure. The multiple oxide semiconductors 40 are provided corresponding to the multiple lower electrodes BE (conductors 21, 22). The oxide semiconductor 40 is provided on the upper surface of the conductor 21. The lower surface of the oxide semiconductor 40 is in contact with the upper surface of the conductor 21. The oxide semiconductor 40 penetrates the insulators 32, 33, 34. The oxide semiconductor 40 contains, for example, at least one element from indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and tin (Sn). The oxide semiconductor 40 contains, for example, at least one element from indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), and zinc (Zn). The oxide semiconductor 40 contains, for example, indium-gallium-zinc oxide.

[0053] In the above configuration, a conductor 21 corresponding to the oxide semiconductor 40 is provided between the oxide semiconductor 40 and the conductor 22, which are aligned in the Z direction. In this configuration, the conductor 21 can reduce the contact resistance between the conductor 22 and the oxide semiconductor 40.

[0054] Gate insulating films 41 and 42 are provided on the side surfaces of each oxide semiconductor 40. Each gate insulating film 41 and 42 has a cylindrical structure.

[0055] The gate insulating film 41 is provided on at least a portion of the side surface of the oxide semiconductor 40. The gate insulating film 41 includes an insulator. The gate insulating film 41 includes, for example, silicon oxide, silicon oxynitride, metal oxide, or metal oxynitride. The metal contained in the metal oxide or metal oxynitride used in the gate insulating film 41 is, for example, at least one element from among aluminum (Al), hafnium (Hf), and zirconium (Zr).

[0056] The gate insulating film 42 is provided so as to cover the side surface of the gate insulating film 41. The gate insulating film 42 is provided between the gate insulating film 41 and the conductor 23. The gate insulating film 42 contains an insulator. The gate insulating film 42 contains, for example, silicon nitride, metal oxide, metal nitride, or metal oxynitride. The metal elements contained in the metal oxide, metal nitride, or metal oxynitride used in the gate insulating film 42 are, for example, at least one of aluminum (Al), hafnium (Hf), and zirconium (Zr). The gate insulating film 42 is a single layer film containing one layer containing silicon nitride, metal oxide, metal nitride, or metal oxynitride. Alternatively, the gate insulating film 42 may be a multilayer film containing two or more of silicon nitride, metal oxide, metal nitride, and metal oxynitride. In the embodiment, a structure in which two gate insulating films 41 and 42 are provided is described, but the gate insulating film 42 may not be provided.

[0057] The dimensions (film thickness) of the gate insulating films 41 and 42 along the X or Y direction are, for example, 2 nanometers (nm) or more and 10 nanometers or less.

[0058] The pairs of oxide semiconductors 40 and gate insulating films 41 and 42 that correspond to each other function as pillars PI. The oxide semiconductor 40 corresponds to the semiconductor that constitutes a part (channel region) of the cell transistor CT. For example, the upper surfaces of multiple oxide semiconductors 40 and the upper surfaces of multiple gate insulating films 41 and 42 are aligned with the upper surface of the insulator 34.

[0059] The pillar PI is provided within the hole HL2 formed in the conductor 23. The pillar PI may have a tapered shape. For example, in a tapered pillar PI, the dimension of the upper part of the pillar PI along the X direction (or Y direction) is larger than the dimension of the lower part of the pillar PI along the X direction (or Y direction). The pillar PI may also have a bowing shape in which the central part along the Z direction bulges out.

[0060] Multiple conductors 23 are provided so as to overlap at least a portion of the insulator 33 in the Z direction. The conductors 23 are wiring layers (conductive layers) that function as gate electrodes GE and word lines WL. Each of the multiple conductors 23 extends in the X direction corresponding to the gate electrodes GE. As a result, in the XZ cross-section shown in Figure 4, one conductor 23 is in contact with the side surface of multiple pillars PI aligned in the X direction. The multiple conductors 23 are aligned in the Y direction corresponding to multiple gate electrodes GE. As a result, in the YZ cross-section shown in Figure 5, the conductors 23 are in contact with the side surface of one pillar PI. The conductors 23 include, for example, tungsten (W) or titanium (Ti). Hereinafter, the conductors 23 are also referred to as wiring layers 23.

[0061] The dimensions (film thickness) of the conductor 23 in the Z direction are, for example, 30 nm or more and 50 nm or less.

[0062] The insulator 35 is provided on the upper surface of the insulator 34, the upper surfaces of the multiple oxide semiconductors 40, and the upper surfaces of the gate insulating films 41 and 42.

[0063] Multiple conductors 24 are provided so as to overlap at least a portion of the insulator 35 in the Z direction and correspond to multiple pillars PI. The conductors 24 are provided on the upper surface of the oxide semiconductor 40. The conductors 24 cover the corresponding upper surface of the oxide semiconductor 40. The conductors 24 include, for example, conductive oxides. The conductors 24 include, for example, at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo), and oxygen (O). Multiple conductors 24 include, for example, oxides of at least one element among indium (In) and tin (Sn). The conductive oxide includes, for example, at least one compound among indium tin oxide and tin oxide.

[0064] Multiple conductors 25 are provided on the upper surfaces of multiple conductors 24, corresponding to multiple conductors 24. The conductors 25 include, for example, at least one element from among titanium (Ti), tin (Sn), zinc (Zn), ruthenium (Ru), and niobium (Nb). The conductors 25 include, for example, a nitride of at least one of these elements. The conductors 25 include, for example, titanium nitride (TiN).

[0065] Multiple conductors 26 are provided on the upper surfaces of multiple conductors 25, corresponding to multiple conductors 25. The conductors 26 include, for example, tungsten (W). The upper surfaces of the multiple conductors 26 are aligned with the upper surface of the insulator 35. In the Z direction, the film thickness of the conductors 26 is, for example, thicker than the film thickness of the conductors 24 and 25.

[0066] In the configuration described above, the corresponding sets of conductors 24, 25, and 26 function as the upper electrode TE. Conductor 25 is provided to prevent metallic elements contained in conductor 26 from entering conductor 24 by diffusion. Conductor 25 can function, for example, as a barrier metal.

[0067] Multiple conductors 27 are provided on the upper surface of the insulator 35 and on the upper surfaces of the multiple conductors 26. Each conductor 27 is provided on a plurality of upper electrodes TE. Each conductor 27 is in contact with the conductor 26 of the upper electrode TE corresponding to the conductor 27. The conductors 27 extend along the Y direction. The plurality of upper electrodes TE connected to each conductor 27 correspond to a plurality of different bit lines BL. The plurality of conductors 27 are aligned in the X direction corresponding to the plurality of bit lines BL. The plurality of conductors 27 include, for example, titanium nitride (TiN).

[0068] Multiple conductors 28 are provided on the upper surfaces of multiple conductors 27. The conductors 28 include, for example, tungsten (W).

[0069] Multiple conductors 29 are provided on the upper surfaces of multiple conductors 28. The conductors 29 include, for example, titanium nitride (TiN).

[0070] In the above configuration, the conductors 27, 28, and 29 function as bit lines BL. Conductors 27 and 29 are provided to prevent metallic elements contained in conductor 28 from diffusing into the layer below conductor 27 and the layer above conductor 29. For this reason, conductors 27 and 29 can function, for example, as barrier metals. Note that conductors 27 and 29 are not required.

[0071] The insulator 36 is provided on the upper surface of the multiple conductors 29.

[0072] Multiple member SLTs are provided above the insulator 34. Each member SLT extends along the Y direction. Multiple member SLTs are aligned along the X direction. Each member SLT penetrates the conductors 27, 28, and 29. The upper surface of each member SLT is aligned with, for example, the upper surface of the insulator 36. The lower surface of each member SLT is in contact with, for example, the conductor 26. The lower surface of the member SLT only needs to reach the height of the upper surface of the insulator 35. The member SLT is an insulator such as silicon oxide. Two adjacent bit lines BL in the X direction are separated from each other by the corresponding member SLT. The two bit lines BL are insulated from each other by the member SLT.

[0073] In an XZ cross-section including word line WL1 or word line WL3, member SLT is provided so as to overlap, for example, one end of the upper electrode TE in the X direction. In an XZ cross-section including word line WL2 or word line WL4, each member SLT is provided so as to overlap, for example, the other end of each upper electrode TE in the X direction. In the XZ cross-section shown in Figure 4, an example is shown in which each member SLT is provided so as to overlap the other end of the upper electrode TE corresponding to member SLT.

[0074] In the semiconductor device 1 of this embodiment, the wiring layer (conductor) 23, which serves as the word line WL and the gate electrode GE, includes a recess 90 in the portion (region) facing the pillar PI. The recess 90 is provided on a part of the side surface of the wiring layer 23. For example, the recess 90 is provided on the upper side surface of the wiring layer 23. For example, the recess 90 is not provided on the lower side surface of the wiring layer 23. For example, the lower end of the recess 90 in the Z direction is located above the lower surface (bottom) of the wiring layer 23 and below the halfway point of the wiring layer 23 in the Z direction. For example, the upper end of the recess 90 in the Z direction is aligned with the upper position of the wiring layer 23. For example, the dimension Da in the Z direction from the bottom of the wiring layer 23 to the lower end of the recess 90 is greater than the dimension Db of the recess 90 in the X or Y direction (depth of the recess 90). The depth Db of recess 90 corresponds to the distance from the opening (opening surface) of recess 90 facing pillar PI in the X or Y direction of recess 90 to the side surface of gate electrode GE at the location of recess 90.

[0075] In Figure 4, the position where the gate electrode GE has the longest dimension in the X direction is defined as the first position, and the position where the gate electrode GE has the shortest dimension in the X direction is defined as the second position. For example, dimension Da is the dimension in the Z direction from the bottom of the wiring layer 23 to the first position. For example, dimension Db is the dimension in the X direction from the first position to the second position. For example, the first position defining dimension Da is a position below the recess 90, located at or below the lower electrode BE side end of the recess 90.

[0076] In the semiconductor device 1 of this embodiment, the oxide semiconductor 40 of the pillar PI includes a protrusion 99 in the portion facing the recess 90. The protrusion 99 projects from the side surface of the oxide semiconductor 40 in the X or Y direction. The protrusion 99 may also be treated as part of the pillar PI. The dimensions of the oxide semiconductor 40 in the X or Y direction are larger at the protrusion 99. For example, the dimensions of the oxide semiconductor 40 in the X or Y direction at the protrusion 99 are larger than the dimensions of the oxide semiconductor 40 in the X or Y direction at the bottom surface.

[0077] A portion of the gate insulating film 41, 42 is curved according to the shape of the recess 90 and the shape of the protrusion 99. For example, a portion of the gate insulating film 41, 42 is curved. The protrusion 99 is provided on the curved portion of the gate insulating film 41, 42.

[0078] Furthermore, when the recess 90 is filled by the gate insulating films 41 and 42 and the gate insulating films 41 and 42 become flat, the side surface of the oxide semiconductor 40 has a flat surface without any protrusions 99.

[0079] The semiconductor device 1 of this embodiment can improve the characteristics of a cell transistor CT through the recesses 90 of the conductor 23 and the protrusions 99 of the oxide semiconductor 40.

[0080] (b) Manufacturing method The method for manufacturing the semiconductor device 1 of this embodiment will be described with reference to Figures 6 to 13.

[0081] Figure 6 is a flowchart illustrating the manufacturing method of the semiconductor device 1 according to this embodiment. Figures 7 to 13 are cross-sectional process diagrams showing an example of the manufacturing method of the semiconductor device 1 according to this embodiment. The cross-sections shown in Figures 7 to 13 correspond to the cross-sections along the YZ plane of the semiconductor device 1 according to this embodiment. In Figures 7 to 13, the manufacturing process of the semiconductor device 1 is illustrated focusing on the region where one memory cell is formed.

[0082] <S11,S12> As shown in Figure 7, an insulator 31 is formed above the substrate SUB. Multiple memory elements CC are formed in multiple holes HL1 formed within the insulator 31. The memory elements CC are, for example, cell capacitors CC.

[0083] Multiple lower electrodes BE are formed on the upper surfaces of multiple cell capacitors CC. For example, after the conductor 22 of the lower electrode BE is formed on the upper surface of the cell capacitor CC and on the side surface of the insulator 31, the conductor 21 of the lower electrode BE is formed on the conductor 22.

[0084] <s13> As shown in Figure 8, an insulator 32 is formed on the insulator 31 and the lower electrode BE. An insulator 33 and a wiring layer 23A are formed on the insulator 32. The wiring layer 23A is processed by photolithography and etching to have a predetermined shape. The wiring layer 23A is a conductor for forming the word line WL and the gate electrode GE of the cell transistor CT. The material of the wiring layer 23A is, for example, tungsten (W) or titanium (Ti).

[0085] The insulator 34 is formed on the wiring layer 23A and the insulator 33.

[0086] A mask 80 is formed on the insulator 34. Multiple openings OP are formed within the mask 80 by photolithography and etching. The positions of the openings OP correspond to the positions where the pillars PI of the cell transistor CT are formed.

[0087] <s14> As shown in Figure 9, an etching process using a reactive gas (etching gas) 81, such as RIE (Reactive Ion Etching), is performed on the insulator 34 and the wiring layer 23A based on the pattern of the mask 80. Hereafter, the etching process using a reactive gas will also be called dry etching.

[0088] Openings are formed within the insulator 34 by dry etching.

[0089] The wiring layer 23A is etched by an ionized reactive gas 81. If the wiring layer 23A contains tungsten, the reactive gas 81 is a fluorine-based gas such as nitrogen trifluoride (NF3).

[0090] Dry etching of the wiring layer 23A is stopped before the insulator 32 beneath the wiring layer 23A is exposed.

[0091] In this embodiment, the etching process forms a groove 85 within the wiring layer 23A. The thickness D1 of the wiring layer 23A remaining below the bottom of the groove 85 (above the lower electrode BE) is 10% to 30% of the thickness D2 of the wiring layer 23A between the insulator 32 and the insulator 34. For example, if the thickness D2 of the wiring layer 23A is 30 nm to 50 nm, the thickness D1 of the wiring layer 23A below the bottom of the groove 85 is 3 nm to 15 nm.

[0092] Furthermore, if the wiring layer 23A is a titanium layer, a fluorine-based gas or a chlorine-based gas is used as the reactive gas 81.

[0093] <s15> As shown in Figure 10, after the groove 85 is formed in the wiring layer 23A, a chemical reaction treatment is performed on the wiring layer 23. A chemical reaction layer 50 is formed on the portion of the wiring layer 23 that is exposed relative to the groove 85. The chemical reaction layer 50 has an oxide layer 50A and an oxide layer 50B. The chemical reaction treatment is performed using ions 82. For example, the chemical reaction treatment is performed in the same apparatus (chamber) as the dry etching described above. For example, the chemical reaction treatment is performed within the temperature control range of the electrostatic chuck of the chamber. For example, the chemical reaction treatment is performed between 0°C and 120°C. The chemical reaction layer 50 is also called a compound layer (or simply compound) 50.

[0094] For example, oxidation treatment with oxygen ions 82 is performed on the wiring layer 23A as a chemical reaction. The exposed surface of the wiring layer 23A is oxidized by a chemical reaction with oxygen ions.

[0095] Through oxidation treatment, oxide layers 50A and 50B are formed on the exposed surface of the wiring layer 23A. Oxide layer 50A is formed within the wiring layer 23A located at the bottom of the groove 85. Oxide layer 50B is formed within the wiring layer 23A located on the side of the groove 85. If the wiring layer 23A is tungsten, then oxide layers 50A and 50B are tungsten oxide.

[0096] For example, during the oxidation process, a bias is applied to the substrate SUB. Therefore, oxygen ions are accelerated and penetrate into the wiring layer 23A almost perpendicular to its surface. Due to the high anisotropy of oxidation, the amount of oxidation in the wiring layer 23A on the sides of the groove 85 is less than the amount of oxidation in the wiring layer 23A at the bottom of the groove 85. For example, the sides of the wiring layer 23A are oxidized mainly by radical oxidizing species. The penetration depth (diffusion distance) of radical oxygen into the wiring layer 23A depends on the temperature of the substrate SUB. That is, the amount of oxidation by radical oxygen can be controlled by controlling the temperature of the substrate SUB. For example, increasing the temperature of the substrate SUB can increase the amount of oxidation in the groove 85. Furthermore, on the side surface of the wiring layer 23A, the outermost oxide layer generated by radical oxygen acts as an inhibitory layer against oxygen intrusion, preventing further oxygen penetration. Therefore, oxidation on the side surface of the wiring layer 23A stops at a certain depth. Thus, the film thickness T2 of the oxide layer 50B along the Y or X direction is smaller than the film thickness T1 of the oxide layer 50A along the Z direction.

[0097] The chemical reaction treatment for the wiring layer 23A may also be a nitriding treatment using nitrogen ions. By nitriding, nitride layers (e.g., tungsten nitride layer or titanium nitride layer) 50A, 50B are formed within the wiring layer 23A along the shape of the groove 85. The chemical reaction treatment may also be an oxynitriding treatment containing both oxygen ions and nitrogen ions.

[0098] <s16> As shown in Figure 11, in this embodiment, the oxide layers 50A and 50B are selectively removed by etching using etching solution (chemical) 83. Hereinafter, etching using etching solution will be referred to as wet etching.

[0099] For example, if the oxide layers 50A and 50B are tungsten oxide layers, solution 83 is hydrochloric acid (HCl) or trimethyl-2-hydroxyethylammonium hydroxide (TMY) solution. Similarly, if the oxide layers 50A and 50B are titanium oxide layers, solution 83 is HCl or TMY solution. Furthermore, if layers 50A and 50B are tungsten nitride or titanium nitride, HCl or TMY solution may be used for solution 83.

[0100] Removal of the oxide layer 50A forms holes HL2 within the wiring layer 23. As a result, gate electrode GE is formed within the wiring layer 23. The surface of the insulator 32 is exposed through the holes HL2. Holes HL2 are formed at the location where pillars PI are formed.

[0101] In this embodiment, the removal of the oxide layer 50B forms a recess 90 on the side surface of the wiring layer 23. The formation of the recess 90 causes the side surface of the wiring layer 23 to recede in a direction parallel to the surface of the substrate SUB (X direction or Y direction). The lower end of the recess 90 in the Z direction is located above the lower surface of the wiring layer 23. The dimension Da from the lower surface of the wiring layer 23 to the lower end of the recess 90 is greater than the depth Db of the recess 90.

[0102] <s17> The pillar PI is formed within the hole HL2 of the wiring layer 23 so that the pillar PI is electrically connected to the lower electrode BE.

[0103] As shown in Figure 12, the gate insulating film 42 is formed on the side surface of the wiring layer 23 and on the insulator 32. The gate insulating film 41 is formed on the gate insulating film 42.

[0104] As shown in Figure 13, the gate insulating films 41 and 42 and the insulator 32 are removed from the upper surface of the lower electrode BE by reactive ion etching via holes HL2. After this, the oxide semiconductor 40 is formed on the gate insulating film 41 and the lower electrode BE. The oxide semiconductor 40 is in direct contact with the lower electrode BE.

[0105] The formation of pillars (PI) leads to the formation of cell transistors (CT).

[0106] As described above, in this embodiment, the recess 90 is formed on the side surface of the wiring layer 23. Depending on the shape of the recess 90, a portion of the gate insulating film 41, 42 is curved. A protrusion 99 is formed in the oxide semiconductor 40 to correspond to the recess 90.

[0107] In this embodiment, the gate insulating films 41 and 42 are formed on recesses 90 on the side surface of the wiring layer 23A. The gate insulating films 41 and 42 are positioned recessed in a direction parallel to the surface of the substrate SUB compared to the side surface of the opening of the insulator 34. The portions of the gate insulating films 41 and 42 within the recesses 90 are recessed in the X or Y direction compared to portions of the gate insulating films 41 and 42 above or below the recesses 90 in the Z direction.

[0108] In Figure 4, the position closest to the upper electrode TE in the gate insulating films 41 and 42 is defined as the third position, and the position closest to the lower electrode BE is defined as the fourth position. For example, a portion of the oxide semiconductor 40 exists between the third position and the fourth position in the Z direction.

[0109] During etching to expose the upper surface of the lower electrode BE, ions of the highly anisotropic etching gas converge within the opening of the insulator 34 and are incident in the hole HL2 along the Z direction. The positions of the gate insulating films 41 and 42 are recessed in the Y direction relative to the opening of the insulator 34, depending on the depth Db of the recess 90 in the Y direction (or X direction). The gate insulating films 41 and 42 are formed within the recess 90. Therefore, when the recess 90 is formed, the probability of reactive gas ions colliding with the gate insulating films 41 and 42 is reduced compared to when the recess 90 is not formed.

[0110] Furthermore, the insulator 32 may be removed from the upper surface of the lower electrode BE after wet etching and before the formation of the gate insulating films 41 and 42. After this, the gate insulating films 41 and 42 are formed on the side surface of the wiring layer 23 and on the upper surface of the lower electrode BE. After the gate insulating films 41 and 42 covering the lower electrode BE are removed, the oxide semiconductor 40 is formed in the hole HL2 so as to be in contact with the lower electrode BE.

[0111] <S18,S19> As shown in Figures 4 and 5, the conductors 24, 25, and 26 are sequentially formed on the insulator 34 and the pillar PI. The conductors 24, 25, and 26 are processed into predetermined shapes by photolithography and etching. This forms the upper electrode TE on the pillar PI.

[0112] An insulator 35 is formed on the upper electrode TE and on the insulator 34 so as to cover the upper electrode TE. A planarization process such as CMP (Chemical-Mechanical Polishing) is performed on the insulator 35 using the upper electrode TE as a stopper. As a result, the upper surface of the upper electrode TE is exposed from the insulator 35.

[0113] Conductors 27, 28, and 29 are sequentially formed on the upper electrode TE and the insulator 35. The insulator 36 is formed on the conductor 29. Conductors 24, 25, and 26 are processed into predetermined shapes by photolithography and etching. For example, a slit extending in the Y direction is formed within the insulator 36 and conductors 27, 28, and 29 so as to reach the upper electrode TE. The member SLT containing the insulator is embedded in the slit. This forms the bit line BL.

[0114] The semiconductor device 1 of this embodiment is completed through the manufacturing process described above.

[0115] (c) Summary The semiconductor device 1 of this embodiment includes a cell transistor CT, a gate electrode GE having a recess 90, and an oxide semiconductor 40 having a protrusion 99.

[0116] As in this embodiment, when the recess 90 is provided on the side surface facing the hole HL2 in the gate electrode GE, the gate insulating films 41 and 42 are formed on the side surface of the gate electrode GE along the recess 90 which is recessed in a direction parallel to the surface of the substrate SUB. In this case, when the member covering the upper surface of the lower electrode BE is removed through the hole HL2, the probability of etching gas ions colliding with the gate insulating films 41 and 42 can be reduced. As a result, the semiconductor device 1 of this embodiment can reduce damage to the gate insulating films 41 and 42 of the transistor CT.

[0117] This makes it possible to improve the transistor characteristics of the semiconductor device 1 in this embodiment.

[0118] Furthermore, in the semiconductor device 1 of this embodiment, the recess 90 is provided on the upper side surface of the gate electrode GE, but not on the lower side surface of the gate electrode GE. Therefore, the lower part of the gate electrode GE maintains a relatively thick film thickness. As a result, in this embodiment, the risk of disconnection of the wiring layer 23 between adjacent transistors CT is reduced compared to the case where the recess 90 is provided across the entire side surface of the gate electrode GE.

[0119] Furthermore, in the semiconductor device 1 of this embodiment, the oxide semiconductor 40 has protrusions. Therefore, in a part of the hole HL2, the dimension of the hole HL2 in the X or Y direction becomes larger, making it easier to form the oxide semiconductor 40 inside the hole HL2.

[0120] In general semiconductor device manufacturing methods, when forming holes for embedding cell transistor pillars within a wiring layer, the wiring layer is etched in a single dry etching process. Ions of the reactive gas react with the material of the wiring layer, causing it to volatilize and etch the wiring layer. When the reactive gas (reactive ions) used in dry etching penetrates the wiring layer, it collides with the insulator beneath the wiring layer. The reactive gas may bounce off the insulator with little to no reaction. If the bounced reactive gas collides with the side of the wiring layer within the hole, the side of the wiring layer may be unintentionally etched by the bounced reactive gas. This unintentional side etching of the wiring layer by the bounced reactive gas can cause the wiring layer to disappear from the area where the gate electrode and word lines are intended to be formed. In this case, a break in the word line formed from the wiring layer or a defect in the gate electrode of the cell transistor may occur. As a result, semiconductor devices manufactured using general manufacturing methods may be defective.

[0121] In the manufacturing method of the semiconductor device 1 of this embodiment, when forming holes HL2 for embedding pillars PI within the wiring layer 23, the wiring layer 23 is etched in two separate steps. Between the first and second etching steps, a chemical reaction layer 50 (50A, 50B) is partially formed within the wiring layer 23 by a chemical reaction treatment such as oxidation or nitriding.

[0122] The first etching step to form the hole HL2 is a highly anisotropic dry etching. This forms the groove 85 within the wiring layer 23.

[0123] Depending on the shape of the groove 85, chemical reaction layers (compounds) 50A and 50B are formed on the exposed portion of the wiring layer 23 by a chemical reaction process.

[0124] The second etching step to form hole HL2 is wet etching. Wet etching removes the chemical reaction layers 50A and 50B. Wet etching selectively removes the chemical reaction layer 50A from above the lower electrode BE.

[0125] Removal of the chemical reaction layer 50B creates a recess 90 on the side surface of the wiring layer 23.

[0126] In this embodiment, the dimensions of the upper surface of the oxide semiconductor 40 and the dimensions of the lower surface of the oxide semiconductor 40 are shown to be equal in the X or Y direction, but this is not limited to this. The dimensions of the upper surface of the oxide semiconductor 40 may be smaller than the dimensions of the lower surface of the oxide semiconductor 40, or the dimensions of the upper surface of the oxide semiconductor 40 may be larger than the dimensions of the lower surface of the oxide semiconductor 40.

[0127] Thus, in the manufacturing method of the semiconductor device 1 of this embodiment, unintended removal of the wiring layer 23 due to recoiled reactive gas is suppressed. Therefore, in this embodiment, the occurrence of defective semiconductor devices is reduced.

[0128] As a result, the manufacturing method of the semiconductor device 1 in this embodiment can improve the manufacturing yield of the semiconductor device.

[0129] As described above, the semiconductor device of this embodiment can improve the transistor characteristics of the semiconductor device. Furthermore, the manufacturing method of the semiconductor device of this embodiment can improve the quality of the semiconductor device.

[0130] (2) Second embodiment Referring to Figures 14 to 17, a semiconductor device and a method for manufacturing a semiconductor device according to a second embodiment will be described.

[0131] (a) Structure The structure of the semiconductor device 1 of this embodiment will be described with reference to Figures 14 and 15.

[0132] Figure 14 is a cross-sectional view of the memory cell array 11 along the XZ plane, showing an example of the cross-sectional structure of the memory cell array 11 of the semiconductor device 1 of the embodiment. Figure 15 is a cross-sectional view of the memory cell array 11 along the YZ plane, showing an example of the cross-sectional structure of the memory cell array 11 of the semiconductor device 1 of the embodiment.

[0133] As shown in Figures 14 and 15, in the semiconductor device 1 of this embodiment, the gate electrode GE of the wiring layer 23 does not include a recess. The gate electrode GE has a flat side surface. The flat side surface of the gate electrode GE faces the oxide semiconductor 40 via gate insulating films 41 and 42.

[0134] Depending on the shape of the gate electrode GE without a recess, the oxide semiconductor 40 of the pillar PI does not have any protrusions. Furthermore, the gate insulating films 41 and 42 are provided flat between the side surface of the gate electrode GE and the side surface of the oxide semiconductor 40 without bending.

[0135] In this embodiment, the dimensions of the upper surface of the oxide semiconductor 40 and the dimensions of the lower surface of the oxide semiconductor 40 are shown to be equal in the X or Y direction, but this is not limited to this. The dimensions of the upper surface of the oxide semiconductor 40 may be smaller than the dimensions of the lower surface of the oxide semiconductor 40, or the dimensions of the upper surface of the oxide semiconductor 40 may be larger than the dimensions of the lower surface of the oxide semiconductor 40.

[0136] (b) Manufacturing method The manufacturing method of the semiconductor device 1 of this embodiment will be described with reference to Figures 16 and 17. Figures 16 and 17 are cross-sectional process diagrams illustrating the manufacturing method of the semiconductor device 1 of this embodiment.

[0137] As shown in Figure 16, the groove 85 is formed in the wiring layer 23A by dry etching through the process described in Figures 7 to 9 above.

[0138] After this, oxidation treatment with oxygen ions 82 (or nitriding treatment with nitrogen ions) is performed on the wiring layer 23A exposed in the groove 85.

[0139] During oxidation treatment with ions 82, if the substrate temperature SUB (temperature inside the etching chamber) is low, the generation of oxidizing species such as radical oxygen is suppressed. In addition, the penetration of oxygen into the sides of the wiring layer 23A is suppressed. Therefore, the oxidation reaction on the sides of the wiring layer 23A is suppressed. As a result, the wiring layer 23A at the bottom of the groove 85 is oxidized by the implantation of oxygen ions, but the wiring layer 23A on the sides of the groove 85 is not oxidized. Consequently, an oxide layer is not formed on the sides of the wiring layer 23A.

[0140] As shown in Figure 17, the oxide layer 50A is selectively removed by wet etching. As a result, in this embodiment, holes HL2 are formed within the wiring layer 23.

[0141] In this embodiment, the oxide layer is not formed on the side surface of the wiring layer 23A. Therefore, etching does not occur on the side surface of the wiring layer 23A. Consequently, recesses are not formed on the side surface of the wiring layer 23A.

[0142] After this, the pillar PI is formed in the hole HL2 of the wiring layer 23 by the process described above, and then the upper electrode TE and bit wire BL are formed sequentially.

[0143] Through the above steps, the semiconductor device 1 of this embodiment is completed.

[0144] The semiconductor device 1 of this embodiment, like the embodiment described above, can suppress unintended side etching of the wiring layer 23 when forming holes in the wiring layer 23.

[0145] Therefore, the transistor characteristics of the semiconductor device 1 in this embodiment can be improved. Furthermore, the manufacturing method of the semiconductor device 1 in this embodiment can improve the quality of the semiconductor device.

[0146] (3) Third Embodiment A semiconductor device and a method for manufacturing a semiconductor device according to a third embodiment will be described with reference to Figures 18 to 23.

[0147] (a) Structure The structure of the semiconductor device 1 of this embodiment will be described with reference to Figures 18 and 19.

[0148] Figure 18 is a cross-sectional view of the memory cell array 11 along the XZ plane, showing an example of the cross-sectional structure of the memory cell array 11 of the semiconductor device 1 of the embodiment. Figure 19 is a cross-sectional view of the memory cell array 11 along the YZ plane, showing an example of the cross-sectional structure of the memory cell array 11 of the semiconductor device 1 of the embodiment.

[0149] As shown in Figures 18 and 19, in the semiconductor device 1 of this embodiment, the stepped portion 95 is provided on the lower side surface of the wiring layer 23 (gate electrode GE).

[0150] A recess 90 is provided on the side of the wiring layer 23.

[0151] At the lower part of the recess 90 in the Z direction, a stepped section 95 is provided within the wiring layer 23. The stepped section 95 is a stepped height.

[0152] The oxide semiconductor 40 includes a step 96. The step 96 is provided at a position corresponding to the stepped portion 95. For example, the step 96 is provided within a protrusion 99.

[0153] In this embodiment, the gate insulating films 41 and 42 are further recessed in the X and Y directions than the openings of the insulator 34. Therefore, in this embodiment, damage caused by ion collisions in the gate insulating films 41 and 42 can be further reduced.

[0154] (b) Manufacturing method The manufacturing method of the semiconductor device 1 of this embodiment will be described with reference to Figures 20 to 23. Figures 20 to 23 are cross-sectional process diagrams illustrating the manufacturing method of the semiconductor device 1 of this embodiment.

[0155] As shown in Figure 20, the groove 85 is formed in the wiring layer 23A by dry etching through the process described in Figures 7 to 9 above.

[0156] Subsequently, oxidation treatment with oxygen ions 82 (or nitriding treatment with nitrogen ions) is performed on the wiring layer 23A exposed in the groove 85. This forms oxide layers 50B and 50X within the wiring layer 23A.

[0157] At this time, within the groove 85, the surface of the wiring layer 23A is oxidized, while a portion of the bottom of the wiring layer 23A is not oxidized. Therefore, the conductor 230 remains between the oxide layer 50X and the insulator 32.

[0158] As shown in Figure 21, the first wet etching is performed on the oxide layers 50A and 50B within the wiring layer 23A. This removes the oxide layers 50A and 50B. A recess 90 is formed within the wiring layer 23A.

[0159] The conductor 230 on the insulator 32 remains because it is not removed by wet etching.

[0160] As shown in Figure 22, oxidation treatment with oxygen ions 82Z is ​​performed again on the wiring layer 23B having recesses 90. This partially oxidizes the wiring layer 23.

[0161] An oxide layer 50C is formed on the insulator 32 by oxidation of the conductor 230. In addition, an oxide layer 50D is formed within the wiring layer 23A along the recess 90. Due to the formation of the oxide layer 50D, the side surface of the wiring layer 23A recedes in a direction parallel to the surface of the substrate SUB.

[0162] As shown in Figure 23, a second wet etching is performed on the oxide layers 50C and 50D formed by the second oxidation treatment. The wet etching removes the oxide layers 50C and 50D. This forms holes HL2 within the wiring layer 23.

[0163] On the side surface of the wiring layer 23 within hole HL2, a step is created between the portion subjected to the first wet etching and the portion subjected to the second wet etching. As a result, a stepped step (staircase portion) 95 is formed on the lower part of the side surface of the wiring layer 23.

[0164] Subsequently, after the pillar PI is formed in the hole HL2 of the wiring layer 23 by the process described above, the upper electrode TE and bit line BL are formed sequentially. A step 96 is formed on the lower part of the side surface of the oxide semiconductor 40 of the pillar PI, corresponding to the stepped portion 95 of the wiring layer 23.

[0165] Through the above steps, the semiconductor device 1 of this embodiment is completed.

[0166] Furthermore, depending on the thickness of the conductive film 230 remaining on the insulator 32, the number of process cycles, including one chemical reaction treatment and one wet etching, may be three or more. Accordingly, the number of steps included in the stepped section 95 will also increase.

[0167] The semiconductor device 1 of this embodiment, like the embodiment described above, can suppress unintended side etching of the wiring layer 23 when forming holes in the wiring layer 23.

[0168] Therefore, the semiconductor device 1 of this embodiment can improve the transistor characteristics of the semiconductor device. Furthermore, the manufacturing method of the semiconductor device 1 of this embodiment can improve the quality of the semiconductor device.

[0169] (4) Others In the semiconductor device 1 of the above embodiment, an example of a memory device in which a capacitor CC is used as a memory element has been described. However, other elements besides capacitors may be used as memory elements, as long as they are elements capable of storing data. For example, the memory element may be a magnetoresistive element, a variable resistor element, a ferroelectric element, or a phase change element.

[0170] Furthermore, in the above-described embodiment, an example was given in which the semiconductor device 1 is a memory device. However, the semiconductor device 1 in the embodiment may be a device other than a memory device.

[0171] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0172] 1: Semiconductor device, MC: Memory cell, CC: Cell capacitor, CT: Cell transistor, BE: Lower electrode, TE: Upper electrode, GE: Gate electrode, WL: Word line, BL: Bit line, 23: Wiring layer, 40: Oxide semiconductor, 41, 42: Gate insulating film, 90: Recess, 95: Stepped section, 99: Protrusion.

Claims

1. The first electrode and A second electrode is provided above the first electrode in a first direction perpendicular to the surface of the first electrode, An oxide semiconductor having one end in contact with the first electrode and the other end in contact with the second electrode, extending in the first direction, A gate insulating film surrounding the side surface of the oxide semiconductor, A gate electrode surrounding the side surface of the gate insulating film, It is equipped with, The gate electrode includes a recess provided on the surface facing the oxide semiconductor. Semiconductor equipment.

2. The oxide semiconductor includes a protrusion facing the recess and projecting in a second direction perpendicular to the first direction. The semiconductor device according to claim 1.

3. The gate electrode includes a stepped portion provided on the first electrode side. The semiconductor device according to claim 1.

4. The gate electrode has a bottom surface on the first electrode side and an upper surface on the second electrode side. One end of the recess on the first electrode side is located above the bottom surface. The semiconductor device according to claim 1.

5. The first dimension from the bottom surface to the first electrode side of the recess is greater than the second dimension from the opening surface of the recess to the side surface of the gate electrode in a second direction perpendicular to the first direction. The semiconductor device according to claim 4.

6. The position of the gate insulating film within the recess is set back in a second direction perpendicular to the first direction from the position of the gate insulating film above the recess in the first direction. The semiconductor device according to claim 1.

7. The oxide semiconductor comprises at least one element selected from the group consisting of indium, gallium, silicon, aluminum, and tin, zinc, and oxygen. The semiconductor device according to claim 1.

8. A memory element provided below the first electrode in the first direction and electrically connected to the oxide semiconductor via the first electrode, A word wire electrically connected to the gate electrode, A bit wire provided above the second electrode in the first direction and electrically connected to the second electrode, It further possesses, The semiconductor device according to claim 1.

9. Forming a wiring layer on the first insulator on the first electrode, A portion of the wiring layer is etched by a first etching using a reactive gas to form a groove, A first chemical reaction treatment is performed on the wiring layer through the groove, and a first chemical reaction layer is formed in the first portion located at the bottom of the groove in the wiring layer. The first chemical reaction layer is removed by a second etching using a solution, and holes are formed within the wiring layer. A pillar including a gate insulating film and a channel is formed within the aforementioned hole. A second electrode is formed above the aforementioned pillar, A method for manufacturing a semiconductor device comprising the above.

10. The first chemical reaction treatment described above forms a second chemical reaction layer within the second portion located on the side of the groove in the wiring layer, The second etching removes the second chemical reaction layer, and a recess is formed on the side surface of the wiring layer. A gate insulating film is formed on the side surface of the wiring layer, An oxide semiconductor having a protrusion opposite to the recess is formed on the gate insulating film, A method for manufacturing a semiconductor device according to claim 9, further comprising the above.

11. The wiring layer has a bottom surface on the first electrode side and an upper surface on the second electrode side. One end of the recess on the first electrode side is located above the bottom surface of the wiring layer. A method for manufacturing a semiconductor device according to claim 10.

12. The first dimension from the bottom surface to the first end of the recess on the first electrode side is greater than the second dimension from the opening surface of the recess to the side surface of the wiring layer in a second direction parallel to the surface of the first electrode of the recess. A method for manufacturing a semiconductor device according to claim 11.

13. After removing the first chemical reaction layer, a second chemical reaction treatment is performed to form a third chemical reaction layer within the third portion of the wiring layer remaining on the first insulator. The third chemical reaction layer is removed by a third etching using the aforementioned solution, A method for manufacturing a semiconductor device according to claim 9, further comprising:

14. The first chemical reaction treatment described above forms a second chemical reaction layer within the second portion located on the side of the groove in the wiring layer, The second etching removes the second chemical reaction layer, and a recess is formed on the side surface of the wiring layer. The second chemical reaction treatment described above forms a fourth chemical reaction layer within the fourth portion corresponding to the recess in the wiring layer, The third etching removes the fourth chemical reaction layer, A method for manufacturing a semiconductor device according to claim 13, further comprising the above.

15. A stepped portion is formed on the first electrode side of the wiring layer. The method for manufacturing a semiconductor device according to claim 14.

16. The aforementioned wiring layer contains tungsten or titanium. The method for manufacturing a semiconductor device according to claim 9.

17. The aforementioned reactive gas is a fluorine-based gas. The method for manufacturing a semiconductor device according to claim 16.

18. The first chemical reaction treatment described above is a treatment using oxygen ions or nitride ions. The method for manufacturing a semiconductor device according to claim 9.

19. If the first chemical reaction layer contains a tungsten compound or a titanium compound, the solution is hydrochloric acid or trimethyl-2-hydroxyethylammonium hydroxide solution. The method for manufacturing a semiconductor device according to claim 9.

20. Before forming the first electrode, a memory element electrically connected to the first electrode is formed. The first and second etching processes form the holes within the wiring layer, and the gate electrode and the word line connected to the gate electrode are formed within the wiring layer. A bit line electrically connected to the second electrode is formed above the second electrode, A method for manufacturing a semiconductor device according to claim 9, further comprising the above.

21. The channel comprises an oxide semiconductor, The oxide semiconductor comprises at least one element selected from the group consisting of indium, gallium, silicon, aluminum, and tin, zinc, and oxygen. The method for manufacturing a semiconductor device according to claim 9.

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