Semiconductor equipment

Abstract

To provide a semiconductor device that can prevent a decrease in breakdown resistance during turn-off. [Solution] According to the embodiment, the semiconductor device includes a semiconductor member, a gate metal layer, a first gate electrode, and an emitter electrode. The gate metal layer includes a first portion and a second portion. The first gate electrode is connected to the gate metal layer in the first portion. The emitter electrode includes a third portion and a fourth portion. The emitter electrode is electrically connected to the semiconductor member in the third and fourth portions. The second portion is located between the third and fourth portions in a first direction.

Description

[Technical Field]

[0001] The embodiments relate to semiconductor devices. [Background technology]

[0002] In semiconductor devices, it is desirable to prevent a decrease in breakdown resistance during turn-off. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-46187 [Patent Document 2] Japanese Patent Publication No. 2009-111081 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device capable of preventing a decrease in breakdown resistance during turn-off. [Means for solving the problem]

[0005] According to embodiments of the present invention, a semiconductor device includes a semiconductor member, a gate metal layer, a first gate electrode, and an emitter electrode. The gate metal layer includes a first portion and a second portion. The first gate electrode extends along a first direction from the first portion toward the second portion. The first gate electrode is connected to the gate metal layer in the first portion. The emitter electrode is provided on the semiconductor member. The emitter electrode includes a third portion and a fourth portion. The emitter electrode is electrically connected to the semiconductor member in the third and fourth portions. The second portion is located between the third and fourth portions in the first direction. [Brief explanation of the drawing]

[0006] [Figure 1]FIG. 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view illustrating a semiconductor device according to an embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line A-A of FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along line B-B of FIG. 2. [Figure 5] FIG. 5 is a cross-sectional view taken along line C-C of FIG. 2. [Figure 6] FIG. 6 is an enlarged view of the periphery of the second portion. [Figure 7] FIG. 7 is a schematic plan view illustrating a semiconductor device according to a first modification of the embodiment. [Figure 8] FIG. 8 is a schematic plan view illustrating a semiconductor device according to a first modification of the embodiment. [Figure 9] FIG. 9 is a schematic plan view illustrating a semiconductor device according to a second modification of the embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line H-H of FIG. 9.

BEST MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each figure, elements similar to those described above with respect to the previously presented figures are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0008] FIGS. 1 and 2 are schematic plan views illustrating a semiconductor device according to an embodiment. The semiconductor device 100 shown in FIG. 1 has a semiconductor member 10M, a gate metal layer 53L including a first pad 71, a second pad 72, and an emitter electrode 52. The gate metal layer 53L includes a portion surrounding the emitter electrode 52 and a portion located between the emitter electrodes 52 in the XY plane. The first pad 71 is, for example, a gate pad.

[0009] A third direction D3 from the collector electrode 51 to the emitter electrode 52, not shown in FIG. 1, intersects a first plane including the first direction D1 and the second direction D2. The semiconductor member 10M is between the collector electrode 51 and the emitter electrode 52.

[0010] The second pad 72 is electrically insulated from the gate metal layer 53L. The second pad 72 is, for example, a pad such as a temperature sense diode, a gate pad of a multi-gate, a current sense pad, etc.

[0011] The emitter electrode 52 is provided spaced apart from the gate metal layer 53L. The emitter electrode 52 is provided divided into a plurality. The gate metal layer 53L has an outer periphery 53LA formed annularly surrounding the plurality of emitter electrodes 52 in the XY plane. The gate metal layer 53L has a wiring 53LB connecting two sides of the outer periphery 53LA. For example, as shown in FIG. 1, the wiring 53LB extends in the Y direction and connects the sides extending in the X direction of the outer periphery 53LA. The wiring 53LB connects the opposing sides of the outer periphery 53LA.

[0012] The fact that the gate metal layer 53L has the wiring 53LB is desirable for reducing the difference in the timing of voltage application between the plurality of gate electrodes 53 when controlling the gate potential of the gate electrodes 53 (the first gate electrode 53a, the second gate electrode 53b, and the third gate electrode 53c) shown in FIG. 2. Since not only the outer periphery 53LA but also the wiring 53LB is connected to the gate electrode 53 and a voltage can be applied to the gate electrode 53, the distance between the gate electrode 53 and the gate metal layer 53L is reduced.

[0013] FIG. 2 shows the region S1 shown in FIG. 1. As shown in Figure 2, the semiconductor device 100 according to this embodiment includes a semiconductor member 10M (semiconductor substrate), a gate metal layer 53L, a first gate electrode 53a, and an emitter electrode 52.

[0014] The X-axis direction is defined along the upper surface of the semiconductor member 10M. The Y-axis direction is defined along the upper surface of the semiconductor member 10M and perpendicular to the X-axis direction. The Z-axis direction is defined perpendicular to both the X-axis and Y-axis directions. The X-axis direction is, for example, the first direction D1. The Y-axis direction is, for example, the second direction D2. The Z-axis direction is, for example, the third direction D3. The XY plane is, for example, the first plane.

[0015] The gate metal layer 53L includes a first portion P1 and a second portion P2. An insulating member 85 is provided between the gate metal layer 53L and the semiconductor member 10M, as will be described later in Figure 3. The insulating member 85 includes an insulating layer 85a and a first insulating film 85b. The gate metal layer 53L is provided on the semiconductor member 10M via the insulating layer 85a.

[0016] The first gate electrode 53a extends along a first direction D1 from the first portion P1 to the second portion P2. The gate metal layer 53L is electrically connected to the first gate electrode 53a in the first portion P1. The first gate electrode 53a is, for example, a gate electrode 53 embedded in a semiconductor member 10M. The first gate electrode 53a faces the semiconductor member 10M via a first insulating film 85b. For example, a transistor is formed in the semiconductor member 10M, and the conduction state of the transistor is controlled by applying a voltage to the first gate electrode 53a. The first gate electrode 53a is, for example, a trench gate electrode. Multiple gate electrodes 53 extend in the first direction D1.

[0017] The emitter electrode 52 is provided on the semiconductor member 10M. The emitter electrode 52 includes a third portion P3 and a fourth portion P4. The emitter electrode 52 is electrically connected to the semiconductor member 10M in the third portion P3 and the fourth portion P4. The second portion P2 is located between the third portion P3 and the fourth portion P4 in the first direction D1.

[0018] The semiconductor device 100 according to this embodiment includes a collector electrode 51 (see Figure 3) and an insulating member 85. As will be described later in Figure 4, the emitter electrode 52 includes an emitter contact portion 52C that contacts the semiconductor member 10M. The emitter contact portion 52C includes a first emitter contact region 52a continuous with the third portion P3 and a second emitter contact region 52b continuous with the fourth portion P4.

[0019] The first insulating film 85b functions as a gate insulating film. Depending on the potential of the gate electrode 53, the current flowing between the collector electrode 51 and the emitter electrode 52 can be controlled. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0020] During conduction, carriers accumulate in the region outside the outermost first gate electrode 53a in the negative direction of the second direction D2. In a reference example where the emitter electrode 52 does not have a third portion P3, current may concentrate at the contacts in the active region during turn-off and load short circuits, potentially leading to current concentration or failure due to latch-up. In the semiconductor device 100 according to this embodiment, the emitter contact portion 52C (first emitter contact region 52a) outside the active region makes it possible to discharge carriers. This prevents a decrease in breakdown withstand capability during turn-off and load short circuits. Note that the emitter contact portion 52C, which electrically connects the emitter electrode 52 and the semiconductor member 10M, does not necessarily extend into the semiconductor member 10M. On the other hand, as shown later in Figure 5, making the emitter contact portion 52C extend into the semiconductor member 10M is desirable in order to increase the contact area between the emitter electrode 52 and the semiconductor member 10M.

[0021] As shown in Figure 2, the length of the third portion P3 along the first direction D1 is longer than the length of the second portion P2 along the first direction D1. Also, the length of the third portion P3 along the first direction D1 is longer than the length of the first portion P1 along the first direction D1. As shown in Figure 2, the length of the first gate electrode 53a in the third portion P3 along the first direction D1 is longer than the length of the first gate electrode 53a in the second portion P2 along the first direction D1.

[0022] Figures 3 to 5 are cross-sectional views of a semiconductor device according to an embodiment. Figure 3 is a cross-sectional view of AA in Figure 2. Figure 4 is a cross-sectional view of BB in Figure 2. Figure 5 is a cross-sectional view of CC in Figure 2.

[0023] This will be explained with reference to Figure 3. Figure 3 shows an example of a trench gate type semiconductor device. This does not preclude the application of this embodiment to a planar gate type semiconductor device. An insulating layer 85a is provided on the semiconductor member 10M, the first gate electrode 53a, and the first insulating film 85b. The insulating layer 85a is interposed between the first gate electrode 53a and the emitter electrode 52. The connecting member 60 (for example, a plug) electrically connects the first part P1 and the first gate electrode 53a. The connecting member 60 electrically connects the gate metal layer 53L and the first gate electrode 53a.

[0024] In the example shown in Figure 3, there is no electrical connection between the second portion P2 and the first gate electrode 53a. On the other hand, a plug may be formed between the second portion P2 and the first gate electrode 53a in the same AA cross-section as in Figure 3.

[0025] In the first insulating film 85b, the edge in the first direction D1 may be covered by a semiconductor region having a conductivity opposite to that of the first semiconductor region 11. The gate metal layer 53L, which is provided on the insulating layer 85a, and the emitter electrode 52 are spaced apart.

[0026] Please refer to Figure 4 for further explanation. As shown in Figure 4, the emitter contact portion 52C is in contact with the semiconductor member 10M. At least a portion of the emitter contact portion 52C extends along the first direction D1. The emitter contact portion 52C includes a first emitter contact region 52a provided in the third portion P3 and a second emitter contact region 52b provided in the fourth portion P4.

[0027] The emitter contact portion 52C is connected to the third semiconductor region 13. Figure 4 shows a cross-section where the emitter contact portion 52C is located on the third semiconductor region 13, but depending on the position of the cross-section, the third semiconductor region 13 and the emitter contact portion 52C may not be in contact. For example, as shown in Figure 5, the emitter contact portion 52C extending within the semiconductor member 10M extends through the third semiconductor region 13 along the third direction D3, resulting in a cross-section where the emitter contact portion 52C and the second semiconductor region 12 are in contact.

[0028] The gate metal layer 53L faces the semiconductor member 10M via the insulating layer 85a.

[0029] According to the semiconductor device 100 of this embodiment, since it includes a first emitter contact region 52a, carriers can move through the first emitter contact region 52a, thus preventing a decrease in the breakdown resistance during turn-off.

[0030] Please refer to Figure 5 for further explanation. The first gate electrode 53a faces the second semiconductor region 12 of the semiconductor member 10M via the first insulating film 85b. The first gate electrode 53a extends from the upper surface of the semiconductor member 10M to the first semiconductor region 11.

[0031] Multiple first gate electrodes 53a are arranged in a row in the Y direction. The first gate electrodes 53a are connected to the gate metal layer 53L via a connecting member 60, for example, as shown in Figure 3, in a cross-section not shown in Figure 5.

[0032] In addition to the examples shown in Figures 2 and 5, the gate electrode may also have a dummy gate electrode embedded in a trench, in addition to the first gate electrode 53a connected to the gate metal layer 53L. The dummy gate electrode is electrically connected to the emitter electrode 52. The first gate electrode 53a and the dummy gate electrode are arranged periodically, for example, in the Y direction. For example, the first gate electrode 53a and the dummy gate electrode are arranged alternately in the Y direction.

[0033] The operation of the semiconductor device 100 will be explained with reference to Figure 5. An IGBT is a type of power semiconductor capable of high-power, high-speed switching. An IGBT has three electrodes: a gate, a collector, and an emitter. The current flowing between the collector and emitter is controlled by the voltage applied to the gate. By controlling the voltages applied between the gate and emitter and between the collector and emitter, a channel of electrons is formed in the layer facing the gate electrode, and the IGBT turns on.

[0034] As shown in Figure 3, the semiconductor device 100 according to the embodiment further includes a connecting member 60 including a first connecting portion 61. The first connecting portion 61 is located between the first gate electrode 53a and the first portion P1. The first connecting portion 61 electrically connects the first portion P1 to the first gate electrode 53a. The connecting member 60 including the first connecting portion 61 is, for example, a plug. The first connecting portion 61 is, for example, a metal including W or Al.

[0035] Let's refer to Figure 2 again for further explanation. The position 61P of the first connection portion 61 in the second direction D2 intersecting the first direction D1 is different from the position 52aP of the first contact region of the first emitter contact region 52a in the second direction D2.

[0036] The gate electrode 53 of the semiconductor device 100 according to this embodiment further includes a second gate electrode 53b along a first direction D1. The direction from the second gate electrode 53b to the first gate electrode 53a is along the second direction D2. The second gate electrode 53b is positioned alongside the first gate electrode 53a, which is located at the negative end of the second direction D2, in the second direction D2. The connecting member 60 further includes a second connecting portion 62. The second connecting portion 62 is located between the second gate electrode 53b and the second portion P2. The second connecting portion 62 electrically connects the second portion P2 to the second gate electrode 53b at the second connecting portion position 62P.

[0037] The length of the first gate electrode 53a along the first direction D1 is longer than the length of the second gate electrode 53b along the first direction D1. In the third direction D3 (Z direction), at least a portion of the second gate electrode 53b and the second portion P2 overlap.

[0038] The first contact area position 52aP is located in the second direction D2 between the second connection portion position 62P and the first connection portion position 61P of the second connection portion 62.

[0039] The direction from the first emitter contact region 52a to the second emitter contact region 52b is along the first direction D1. The second emitter contact region 52b extends, for example, in the first direction D1.

[0040] The third part P3 is located between the first part P1 and the second part P2 in the first direction D1.

[0041] The gate metal layer 53L further includes a fifth portion P5. The fifth portion P5 is continuous with the first portion P1 and the second portion P2. The direction from the fifth portion P5 to the third portion P3 intersects the first direction D1. The direction from the fifth portion P5 to the third portion P3 is along the second direction D2. The first portion P1 extends along the second direction D2, and the fifth portion P5 extends along the first direction D1. When we say that the first portion P1 extends along the second direction D2, it means that the first portion P1 is defined in the portion of the gate metal layer 53L that extends along the second direction D2.

[0042] The semiconductor device 100 according to the embodiment further includes a third gate electrode 53c along a first direction D1. The direction from the third gate electrode 53c to the second gate electrode 53b is along the second direction D2. In other words, the second gate electrode 53b and the third gate electrode 53c are arranged side by side in the second direction D2. The second gate electrode 53b is located between the first gate electrode 53a and the third gate electrode 53c in the second direction D2. The third gate electrode 53c extends along the first direction D1, and the length of the third gate electrode 53c in the first direction D1 is shorter than the length of the first gate electrode 53a in the first direction D1.

[0043] The gate metal layer 53L further includes a sixth portion P6. The sixth portion P6 is continuous with the fifth portion P5. The direction from the sixth portion P6 to the fifth portion P5 intersects the first direction D1 (for example, along the second direction D2). The sixth portion P6 extends, for example, along the second direction D2. In the example shown in Figure 2, the length of the fifth portion P5 in the first direction D1 is longer than the length of the second direction D2. The length of the sixth portion P6 in the second direction D2 is longer than the length of the first direction D1. The first portion P1 and the fifth portion P5 form, for example, an L-shaped portion of the gate metal layer 53L. The fifth portion P5, the second portion P2, and the sixth portion P6 form, for example, a T-shaped portion of the gate metal layer 53L. The second portion P2, part of the fifth portion P5, and the sixth portion P6 extend, for example, along the second direction D2 and are connected to the second gate electrode 53b and the third gate electrode 53c. The lengths of the first direction D1 of the second gate electrode 53b and the third gate electrode 53c are, for example, equal, but are not limited to this.

[0044] The connecting member 60 further includes a third connecting portion 63. The third connecting portion 63 is located between the third gate electrode 53c and the sixth portion P6. The third connecting portion 63 is also located, for example, between the third gate electrode 53c and the fifth portion P5. The third connecting portion 63 electrically connects the fifth portion P5 to the third gate electrode 53c. The third connecting portion 63 electrically connects the fifth portion P5 and the sixth portion P6 to the third gate electrode 53c.

[0045] The emitter electrode 52 further includes a seventh portion P7. The seventh portion P7 is continuous with the third portion P3 and the fourth portion P4. The length of the seventh portion P7 in the first direction D1 is greater than the sum of the length of the third portion P3 in the first direction D1 and the length of the fourth portion P4 in the first direction D1. The length of the seventh portion P7 in the first direction D1 is equal to or greater than the sum of the length of the third portion P3 in the first direction D1, the length of the fourth portion P4 in the first direction D1, and the length of the second portion P2 in the first direction D1. The emitter electrode 52 is electrically connected to the semiconductor member 10M in the seventh portion P7. The second portion P2 is located between the sixth portion P6 and the seventh portion P7 in the second direction D2.

[0046] The fifth part P5, the second part P2, and the seventh part P7 are arranged in this order in the second direction D2. Furthermore, the sixth part P6, the fifth part P5, the second part P2, and the seventh part P7 are arranged in this order in the second direction D2.

[0047] Referring again to Figure 5, the semiconductor member 10M includes a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, and a fourth semiconductor region 14. The first semiconductor region 11 and the third semiconductor region 13 are, for example, a first conductivity type. The second semiconductor region 12 and the fourth semiconductor region 14 are, for example, a second conductivity type. The first conductivity type is either n-type or p-type. The second conductivity type is the other of n-type and p-type. In this embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0048] The second semiconductor region 12 is located between the first semiconductor region 11 and the emitter electrode 52. The third semiconductor region 13 is located between the second semiconductor region 12 and the emitter electrode 52. The third semiconductor region 13 is electrically connected to the emitter electrode 52. The fourth semiconductor region 14 is located between the first semiconductor region 11 and the collector electrode 51. The emitter contact portion 52C extends, for example, within the semiconductor member 10M, and the second semiconductor region 12 is electrically connected to the emitter electrode 52.

[0049] In the semiconductor device 100, the concentration of the third impurity of the first conductivity type in the third semiconductor region 13 is higher than the concentration of the first impurity of the first conductivity type in the first semiconductor region 11. The first semiconductor region 11 is, for example, an n - layer or an n layer. The third semiconductor region 13 is, for example, an n + layer.

[0050] In the semiconductor device 100, the concentration of the impurity of the first conductivity type in the first semiconductor region 11 is, for example, 1×10 13 cm -3 or more and 1×10 15 cm -3 or less. The concentration of the impurity of the first conductivity type in the third semiconductor region 13 is, for example, 1×10 18 cm -3 [[ID=2)).or more and 1×10 21 cm -3 or less. The concentration of the impurity of the second conductivity type in the second semiconductor region 12 is, for example, 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The concentration of the impurity of the second conductivity type in the fourth semiconductor region 14 is, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less.

[0051] In the semiconductor device 100, when conducting, conductivity modulation occurs and the carrier density in the first semiconductor region 11 becomes higher than the impurity concentration of the first conductivity type, for example, 1×10 16 cm -3 or more and 1×10 18 cm -3 or less.

[0052] Figure 6 is an enlarged view of the periphery of the second part P2. The first length L1 along the second direction D2 of the second portion P2 is at least 1 and no more than 15 times the second length L2 in the second direction D2 between the first center E1 of the first gate electrode 53a in the second direction D2 and the second center E2 of the second gate electrode 53b in the second direction D2. The first length L1 may be at least 1 and no more than 12 times the second length L2. The first length L1 may be at least 1 and no more than 10 times the second length L2. If the first length L1 is less than 1 times the second length L2, the length of the second portion P2 in the second direction D2 may not be sufficient, resulting in a second gate electrode 53b that cannot be connected to the second portion P2 of the gate metal layer 53L, or it may not be possible to obtain a first emitter contact region 52a in the third portion P3.

[0053] The margin length Lm is defined as the length of the second direction D2 between the second portion P2 and the seventh portion P7. The margin length Lm is appropriately selected so that the second portion P2 and the seventh portion P7 are spaced apart. By having a first length L1 that is greater than or equal to the second length L2, the first emitter contact region 52a and the second connection portion 62 (gate contact) can be more reliably formed within the range of length L1+Lm in the second direction D2. Therefore, it is desirable that the first length L1 be greater than or equal to the second length L2. If the first length L1 is 1 times or more the second length L2, it becomes easier to achieve both the formation of the first emitter contact region 52a and the formation of the second connection portion 62 (gate contact).

[0054] If the first length L1 exceeds 15 times the second length L2, the area of ​​the seventh portion P7 in Figure 2 decreases, and the region where the emitter contact portion 52C cannot be obtained becomes too large, which is undesirable.

[0055] The second length L2 is the sum of the width of the first gate electrode 53a (or second gate electrode 53b) in the second direction D2 and the width L4 of the mesa M between the first gate electrode 53a and the second gate electrode 53b in the second direction D2. The second portion P2 and the mesa M overlap in the third direction D3. A first emitter contact region 52a is provided between the semiconductor member 10M and the third portion P3 at a position where the mesa M extending in the first direction D1 is extended in the negative direction of the first direction D1. If the first length L1 is shorter than the second length L2, it may be difficult to form one second gate electrode 53b and one mesa M in a region below the second portion P2 that has the width of the first length L1 in the second direction D2. On the other hand, if the first length L1 is longer than or equal to the second length L2, it becomes possible to form at least one second gate electrode 53b and at least one mesa M in a region below the second portion P2 that has a width of the first length L1 in the second direction D2. This makes it easier to achieve both the formation of the first emitter contact region 52a and the formation of the second connection portion 62 (gate contact).

[0056] The distance F (spacing) between the first emitter contact region 52a and the second emitter contact region 52b in the first direction D1 may be 40 μm or less. In the semiconductor device 100 according to this embodiment, an emitter contact portion 52C cannot be provided near the second portion P2, but because the area is small, current concentration to nearby emitter contacts is small. Therefore, damage due to current concentration and latch-up is reduced.

[0057] The first length L1 may be between 1 μm and 30 μm.

[0058] The third length L3 of the second portion P2 along the first direction D1 may be 5 μm or more and 30 μm or less.

[0059] The distance F between the first emitter contact region 52a and the second emitter contact region 52b may be 20 μm to 60 μm or less.

[0060] Figures 7 and 8 are schematic plan views illustrating a semiconductor device according to a first modified embodiment. Figure 8 shows region S2 as shown in Figure 7. As shown in Figure 7, the semiconductor device 101 has a gate metal layer 53L and an emitter electrode 52. The gate metal layer 53L has an outer periphery 53LA surrounding the emitter electrode 52. Although not shown in Figure 7, the gate electrode 53 extends along the first direction D1, and the portion of the outer periphery 53LA that extends along the second direction D2 is connected to the gate electrode 53.

[0061] The gate metal layer 53L has a first portion P1, a second portion P2, a fifth portion P5, a sixth portion P6, and an eighth portion P8, as will be described later with reference to Figure 8. The gate metal layer 53L includes a first pad 71. The first pad 71 includes at least a portion of the fifth portion P5, at least a portion of the sixth portion P6, and the eighth portion P8, and is, for example, a gate pad.

[0062] As shown in Figure 8, the gate metal layer 53L further includes an eighth portion P8. The eighth portion P8 is continuous with the fifth portion P5 and the sixth portion P6. The direction from the eighth portion P8 to the fifth portion P5 intersects with the first direction D1. The eighth portion P8 is provided in the negative Y direction relative to the fifth portion P5 and in the negative X direction relative to the sixth portion P6. The combined portion of the fifth portion P5, the sixth portion P6, and the eighth portion P8 is the first pad 71.

[0063] The gate metal layer 53L has a first portion P1, a second portion P2, and a first pad 71. The first pad 71 is provided in continuity with the first portion P1. The first pad 71 is provided in continuity with the second portion P2. The first portion P1 and the second portion P2 are continuous via the first pad 71. The first portion P1 is part of the outer circumference 53LA surrounding the emitter electrode 52. The first portion P1 and the second portion P2 are located in the positive direction of the second direction D2 with respect to the first pad 71. The first portion P1 extends from the first pad 71 in the positive direction of the second direction D2. The third portion P3 of the emitter electrode 52 is located in the positive direction of the second direction D2 with respect to the first pad 71. The third portion P3 is located on the same side as the first portion P1 and the second portion P2 are located with respect to the first pad 71. In the first direction D1, the third portion P3 is located between the first portion P1 and the second portion P2.

[0064] Figure 9 is a schematic plan view illustrating a semiconductor device according to a second modified example of the embodiment. Figure 10 is a cross-sectional view of HH in Figure 9. As shown in Figures 9 and 10, the semiconductor device 102 includes a gate metal layer 53L and an emitter electrode 52. The gate metal layer 53L includes a first pad 71. The emitter electrode 52 is provided overlapping at least a portion of the gate metal layer 53L in a third direction D3.

[0065] The first pad 71 is provided on the semiconductor member 10M. The first pad 71 is electrically connected to the first portion P1 and the second portion P2. The first pad 71 is connected via the outer circumference 53LA to the wiring 53LB which includes the first portion P1 and the second portion P2. The first pad 71 is, for example, a gate pad.

[0066] The gate metal layer 53L includes a first portion P1 and a second portion P2. The first portion P1 extends along the second direction D2.

[0067] The semiconductor device 102 may include a second pad 72. The second pad 72 is provided on a semiconductor member 10M. The second pad 72 is insulated from the gate metal layer 53L. The second pad 72 is, for example, a temperature sense pad, a multi-gate gate pad, a current sense pad, and the like.

[0068] The gate metal layer 53L includes a fifth portion P5 connected to the first portion P1 and extending in a first direction D1. The gate metal layer 53L includes a sixth portion P6 connected to the fifth portion P5 and the outer circumference 53LA and extending in a second direction D2. The second portion P2 is connected to the fifth portion P5 and is located opposite the sixth portion P6 to the fifth portion P5. The second pad 72 is adjacent to the fifth portion P5 and the sixth portion P6 and is insulated from the fifth portion P5 and the sixth portion P6.

[0069] Figure 10 shows a cross-section along the HH line shown in Figure 9. The insulating member 85 includes a second insulating film 85c and a third insulating film 85d. The second insulating film 85c is provided on the semiconductor member 10M. A gate metal layer 53L is provided on the second insulating film 85c. The third insulating film 85d is provided on the gate metal layer 53L so as to cover the gate metal layer 53L. The emitter electrode 52 is provided on the semiconductor member 10M and the second insulating film 85c. The gate metal layer 53L is insulated from the semiconductor member 10M and the emitter electrode 52 by the second insulating film 85c and the third insulating film 85d. Along the third direction D3, the semiconductor member 10M, the second insulating film 85c, the gate metal layer 53L, the third insulating film 85d, and a portion of the emitter electrode 52 are provided in this order.

[0070] In Figure 10, the portion of the emitter electrode 52 located between the second insulating film 85c and the third insulating film 85d surrounding the first portion P1 and the second insulating film 85c and the third insulating film 85d surrounding the second portion P2 in the first direction D1 is called the third portion P3. The third portion P3 is located between the first portion P1 and the second portion P2 in the first direction D1.

[0071] Furthermore, the configuration shown as the second modified example can also be applied to the layout shown in Figure 7. That is, in Figure 7, the wiring 53LB of the gate metal layer 53L can be provided below the emitter electrode 52 in the same manner as in Figure 9.

[0072] The semiconductor devices 100, 101, and 102 can be applied to semiconductor devices having pads such as temperature-sensing diodes, multi-gate gate pads, and current-sensing pads.

[0073] According to this embodiment, it is possible to provide a semiconductor device 100 that can prevent a decrease in breakdown resistance during turn-off.

[0074] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configuration of each element included in the semiconductor device, such as the semiconductor member 10M, electrodes, conductive part, and insulating part, is included within the scope of the present invention as long as it can be implemented in the same manner and similar effects can be obtained by appropriately selecting from the range known to those skilled in the art.

[0075] Furthermore, combinations of two or more elements from any of the specific examples, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0076] Furthermore, all semiconductor devices that a person skilled in the art can implement by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0077] Furthermore, within the scope of the concept of the present invention, a person skilled in the art could conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of the present invention.

[0078] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0079] 10M semiconductor material, 11 first semiconductor region, 12 second semiconductor region, 13 third semiconductor region, 14 fourth semiconductor region, 51 Collector electrode, 52 Emitter electrode, 52C Emitter contact area, 52a First emitter contact region, 52aP First contact region position, 52b Second emitter contact region, 53 gate electrode, 53a first gate electrode, 53b second gate electrode, 53c third gate electrode, 53L gate metal layer, 53LA outer perimeter, 53LB wiring, 60 Connecting member, 61 First connecting part, 61P Position of the first connecting part, 62 Second connecting part, 62P Position of the second connecting part, 63 Third connecting part, 71 First pad, 72 Second pad, 85 insulating material, 85a insulating layer, 85b first insulating film, 85c second insulating film, 85d third insulating film, 100, 101, 102 Semiconductor equipment, E1: First center, E2: Second center, F: Distance between the first and second emitter contact regions, L1-L3: First to third length, L4: Width, Lm: Margin length, M: Mesa, P1-P8: First to eighth part

Claims

1. Semiconductor components and A gate metal layer including the first and second parts, A first gate electrode extending along a first direction from the first portion toward the second portion, wherein the first gate electrode is connected to the gate metal layer in the first portion, An emitter electrode provided on the semiconductor member, including a third portion and a fourth portion, wherein the emitter electrode is electrically connected to the semiconductor member in the third portion and the fourth portion, and the second portion is located between the third portion and the fourth portion in the first direction, and is connected to the emitter electrode. A semiconductor device equipped with [the necessary components].

2. The semiconductor device according to claim 1, wherein the third portion is located between the first portion and the second portion in the first direction.

3. The gate metal layer further comprises a first pad provided on the semiconductor member, The semiconductor device according to claim 1, wherein the first pad is connected to the first portion and the second portion.

4. The gate metal layer comprises an outer circumference surrounding the emitter electrode, Wiring connecting the opposing sides of the outer circumference, It has, The semiconductor device according to claim 3, wherein the first and second parts are included in the wiring.

5. The semiconductor device according to claim 3, wherein the first portion and the second portion are continuous via the first pad, and the third portion is located on the same side as the direction in which the first portion and the second portion are located relative to the first pad.

6. The semiconductor device according to claim 3, wherein the gate metal layer faces the semiconductor member and the emitter electrode via an insulating film, and includes a portion in which the semiconductor member, the insulating film, the gate metal layer, the insulating film, and the emitter electrode are stacked in that order.

7. The emitter electrode includes an emitter contact portion that contacts the semiconductor material. At least a portion of the emitter contact portion extends along the first direction, The semiconductor device according to claim 1, wherein the emitter contact portion includes a first emitter contact region provided in the third portion and a second emitter contact region provided in the fourth portion.

8. The device further comprises a second gate electrode along the first direction, The semiconductor device according to claim 1 or 2, wherein the first length is greater than or equal to the second length, with respect to the first length of the second portion along the second direction intersecting the first direction, and the second length in the second direction between the first center of the first gate electrode in the second direction and the second center of the second gate electrode in the second direction.

9. The device further comprises a second gate electrode along the first direction, The direction from the second gate electrode to the first gate electrode is along the second direction intersecting the first direction, The semiconductor device according to claim 1 or 2, wherein the length of the first gate electrode along the first direction is longer than the length of the second gate electrode along the first direction.

10. The gate metal layer further includes a fifth portion, The fifth part is continuous with the first and second parts, The semiconductor device according to claim 1, wherein the direction from the fifth portion to the third portion intersects with the first direction.

11. The connecting member further comprises a second gate electrode oriented in the first direction and a third gate electrode oriented in the first direction, Along the second direction intersecting the first direction, the first gate electrode, the second gate electrode, and the third gate electrode are arranged in this order. The gate metal layer further includes a sixth portion, The sixth part is continuous with the fifth part, The direction from the sixth part to the fifth part intersects with the first direction, The semiconductor device according to claim 10, wherein the connecting member electrically connects the sixth portion and the third gate electrode.

12. The semiconductor member further comprises a second pad provided on the semiconductor member, The semiconductor device according to claim 3, wherein the second pad is insulated from the gate metal layer.

13. The gate metal layer further includes a fifth portion, The fifth part is continuous with the first and second parts, The semiconductor device according to claim 12, wherein the fifth portion is located between the second pad and the third portion in a second direction intersecting the first direction.

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