Semiconductor equipment

Abstract

Even if the power supply voltage is cut off, the connections between logic circuit sections, or within each logic circuit section To provide a semiconductor device that can maintain its circuit configuration. Also, to change the connection relationships between logic circuit sections, This invention provides a semiconductor device that allows for high-speed modification of the circuit configuration within each logic circuit section. [Solution] In a reconfigurable circuit, a semiconductor that stores data such as circuit configuration and connection relationships. Oxide semiconductors are used for the body elements. In particular, oxide semiconductors are used in the channel formation region of the semiconductor element. It is being used.

Description

[Technical Field]

[0001] The technical fields are semiconductor devices, methods for driving semiconductor devices, and methods for manufacturing semiconductor devices. As semiconductor devices, in particular, semiconductor integrated circuits having semiconductor elements such as transistors. do. [Background technology]

[0002] As one type of semiconductor integrated circuit, a programmable logic device (Programma) There is a PLD (Pyrolithography Logic Device). PLDs have internal circuits that are modified after manufacturing. It is an integrated circuit whose configuration and other aspects can be determined and changed (reconfigurable) (see Patent Document 1). ).

[0003] PLDs are different from conventional ASICs (Application Specific Integers). Compared to rated circuits, etc., it is possible to shorten the development period and the design specifications It has advantages such as being able to flexibly adapt to changes, and its use is progressing in various devices.

[0004] A PLD has, for example, multiple logic circuit sections and wiring between the logic circuit sections. By changing the circuit configuration within the path section, or by changing the connection relationships between logic circuit sections, the function of the PLD can be changed. The ability can be changed.

[0005] Furthermore, the PLD may have a memory circuit, and the circuit structure within the logic circuit section may be determined by the memory circuit. It can store information about the configuration and the connection relationships between logic circuit sections.

[0006] The above logic circuit section may include, for example, an arithmetic logic unit (Arithmetic L An ALU (Adder Unit) is used. An ALU is generally used in adders, subtractors, etc. It consists of an arithmetic unit that combines AND gates, OR gates, etc., and a logic unit that combines AND gates, OR gates, etc. A shift calculation unit with a shift circuit and a selection circuit such as a multiplexer that selects and outputs them. It is composed of roads and, [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 11-317659 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] When using SRAM or DRAM as the above memory circuit, changes to the connection relationship between ALUs, Alternatively, it is possible to quickly change the circuit configuration within each ALU. However, SRAM and D Because RAM is volatile, the stored information is lost when the power supply voltage is cut off. It ends up happening.

[0009] Furthermore, when flash memory is used as the above-mentioned memory circuit, it is non-volatile, therefore, power supply The information can be retained even if the voltage supply is cut off. However, because the drive voltage is high, Achieving high-speed operation and reduced power consumption is difficult.

[0010] In view of the above, in one embodiment of the present invention, even if the power supply voltage is stopped, the connections between logic circuit sections remain connected. The objective is to provide a semiconductor device that can maintain relationships or the circuit configuration within each logic circuit section for a long period of time. This will be the first topic.

[0011] Furthermore, in one embodiment of the present invention, the connection relationship between logic circuit sections is changed, or within each logic circuit section One of the objectives is to provide a semiconductor device that allows for high-speed modification of the circuit configuration. [Means for solving the problem]

[0012] One aspect of the present invention has a memory circuit that stores information such as circuit configuration, and an acid is contained within the memory circuit. This is a semiconductor device having a semiconductor element made of a crystalline semiconductor. Specifically, the semiconductor device is P It is an LD (Programmable Logic Device), and consists of a logic circuit section, It has a memory circuit and, according to the data stored in the memory circuit, within the logic circuit section Maintain the same circuit configuration.

[0013] Furthermore, it is preferable that the semiconductor device has multiple logic circuit sections, in which case the above The memory circuit maintains the circuit configuration of each logic circuit section, or the connection relationships between logic circuit sections. The circuit section can use an ALU (Arithmetic Logic Unit). It may also have arithmetic circuits, selection circuits, etc.

[0014] In this specification, PLDs are also referred to as reconfigurable circuits.

[0015] Furthermore, in this specification, a semiconductor device is defined as an object (element) that functions by utilizing a semiconductor. It refers to all things (devices, etc.). Semiconductor devices include semiconductor elements (transistors, diodes, etc.). Electrical devices (electronic circuits, display devices, light-emitting devices, etc.) equipped with such semiconductor elements, and the electrical devices thereof. This category includes electronic devices equipped with air-powered devices.

[0016] Another aspect of the present invention includes a plurality of arithmetic circuits, a selection circuit, and a memory circuit, and the memory The circuit has a transistor and a capacitive element, and the memory circuit has a capacitive element via the transistor. Data is input to the child and selection circuits, and the selection circuit performs calculations on multiple arithmetic circuits according to the data. Select one or more of the results, and in the channel formation region of the transistor, use an oxide semiconductor. This is a semiconductor device that uses [a specific technology / technology].

[0017] Another aspect of the present invention includes a plurality of logic circuit sections and a connection section, wherein the connection section is a memory circuit The device has a first transistor and a first transistor, and one of the sources or drains of the first transistor is , electrically connected to one of the multiple logic circuit sections, and the source or The other end of the drain is electrically connected to one of the other logic circuit sections, and the memory circuit is The memory circuit has a second transistor and a capacitive element, and the memory circuit is connected via the second transistor. Data is input to the capacitive element and the gate of the first transistor, and the first transistor, Depending on the data, it controls the electrical connection between one of several logic circuit sections and another. In the channel formation region of the second transistor, an oxide semiconductor is used in the semiconductor device. That is the case.

[0018] Another aspect of the present invention includes a plurality of logic circuit sections, a first memory circuit, and a connection section, Multiple logic circuit sections have multiple arithmetic circuits and selection circuits, and the first memory circuit is the first The first memory circuit has a transistor and a first capacitive element, and the first transistor The first data is input to the first capacitive element and the selection circuit via the first data, and the selection circuit receives the first data Depending on the result, one or more of the calculation results of multiple calculation circuits are selected, and the connection part is second It has a memory circuit and a second transistor, and the source or drain of the second transistor. One end is electrically connected to one of several logic circuit sections, and the second transistor is connected to The other end of the drain or the other end is electrically connected to one of the other logic circuit sections, The second memory circuit has a third transistor and a second capacitive element, and the second memory circuit is Data is transmitted to the second capacitive element and the gate of the second transistor via the third transistor. Upon input, the second transistor, depending on the data, interacts with one of several logic circuit sections and others. Controlling the electrical connection with one of them, the first transistor and the third transistor control the chat This is a semiconductor device in which an oxide semiconductor is used in the flannel formation region. [Effects of the Invention]

[0019] According to one aspect of the present invention, even if the power supply voltage is stopped, the information regarding the connection relationships between logic circuit sections can be maintained. or to provide a semiconductor device that can retain information about the circuit configuration within each logic circuit section for a long period of time. It is possible.

[0020] Furthermore, according to one aspect of the present invention, the connection relationships between logic circuit sections can be changed, or the rotation of each logic circuit section can be changed. It is possible to provide a semiconductor device that can change the circuit configuration at high speed or with low power consumption. Cut. [Brief explanation of the drawing]

[0021] [Figure 1] A diagram illustrating an example of a semiconductor device. [Figure 2] A diagram illustrating an example of a semiconductor device. [Figure 3] A diagram illustrating an example of a semiconductor device. [Figure 4] A diagram illustrating an example of a semiconductor device. [Figure 5] A diagram illustrating an example of a semiconductor device. [Figure 6] A diagram illustrating an example of a semiconductor device. [Figure 7] A diagram illustrating an example of a semiconductor device. [Figure 8] A diagram illustrating an example of CAAC. [Figure 9] A diagram illustrating an example of CAAC. [Figure 10] A diagram illustrating an example of CAAC. [Figure 11] A diagram illustrating an example of a semiconductor device fabrication method. [Figure 12] A diagram illustrating the relationship between the gate voltage and field-effect mobility of a transistor. [Figure 13] A diagram illustrating an example of a cross-sectional structure of a semiconductor device. [Figure 14] A diagram illustrating the calculation results of the electrical characteristics of a semiconductor device. [Figure 15] A diagram illustrating the calculation results of the electrical characteristics of a semiconductor device. [Figure 16] A diagram illustrating the calculation results of the electrical characteristics of a semiconductor device. [Figure 17] A diagram illustrating the measurement results of electrical characteristics in a semiconductor device. [Figure 18] A diagram illustrating the measurement results of electrical characteristics in a semiconductor device. [Figure 19] A diagram illustrating the measurement results of electrical characteristics in a semiconductor device. [Figure 20] A diagram illustrating the XRD measurement results of oxide semiconductor films in semiconductor devices. [Figure 21] A diagram illustrating the characteristics of a semiconductor device. [Figure 22] A diagram illustrating the characteristics of a semiconductor device. [Figure 23] A diagram illustrating the characteristics of a semiconductor device. [Figure 24] A diagram illustrating an example of a processing unit. [Figure 25] A diagram illustrating an example of an electronic device. [Figure 26] A diagram illustrating an example of CAAC. [Figure 27] A diagram illustrating an example of a semiconductor device. [Modes for carrying out the invention]

[0022] The embodiments will be described in detail below with reference to the drawings. However, the present invention is as follows Not limited to the description, the form and details thereof may be described without departing from the spirit and scope of the present invention. Those skilled in the art will readily understand that it can be modified in various ways. Therefore, the present invention is The description of the embodiments shown below is not to be interpreted as being limited to the following.

[0023] Note that the "source" and "drain" functions are used when transistors with different polarities are employed. For example, when the direction of current changes during circuit operation, the positions may be reversed. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably. It is assumed that this is possible.

[0024] "Electrically connected" means connected via "something that has some kind of electrical effect". This includes connections. Here, "something that has some kind of electrical effect" refers to electrical signals between connected objects. There are no particular restrictions as long as it enables the exchange of numbers. For example, "some kind of electrical action "Things that possess" include electrodes and wiring, as well as switching elements such as transistors and resistive elements. This includes components such as sub-units, inductors, capacitors, and other elements with various functions.

[0025] In the circuit diagram, independent components are shown as being electrically connected to each other. Even in such cases, in reality, for example, when part of the wiring also functions as an electrode, one conductor In some cases, the film may possess the functions of multiple components. In this specification, electrically A connection is also a case where a single conductive film combines the functions of multiple components. Include it in that category.

[0026] The terms "up" and "down" do not limit the positional relationship of the constituent elements to "directly above" or "directly below". It is not fixed. For example, if the expression is "gate electrode on gate insulating layer", then it is not fixed. This excludes cases that include other components between the insulating layer and the gate electrode.

[0027] The position, size, and extent of each component shown in the drawings, etc., are for ease of understanding. The location, size, range, etc., may not be described. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, scope, etc., disclosed in drawings, etc.

[0028] Ordinal numbers such as "1st," "2nd," and "3rd" are added to avoid confusion of constituent elements. That is the case.

[0029] (Embodiment 1) This embodiment describes an example of a semiconductor device.

[0030] Figure 1(A) shows an example of a block diagram of a semiconductor device.

[0031] The semiconductor device shown in Figure 1(A) has a logic circuit section 101 and a memory circuit 103. The circuit section 101 has multiple logic circuits 105. And in the semiconductor device, the memory circuit 1 Depending on the data (also called a signal) stored in 03, one of the multiple logic circuits 105 Alternatively, multiple options are selected, and the circuit configuration within the logic circuit section 101 is determined.

[0032] An example of a logic circuit section 101 is an ALU. Multiple logic circuits 105 are used. For example, adders, subtractors, multipliers, AND gates, OR gates, NOT gates, XOR gates, or Examples include arithmetic circuits such as shift circuits and selection circuits such as multiplexers. Also, logic circuits The path 105 may consist of a single element, such as a single transistor. Logic circuit 10 5 has one or more elements (such as transistors) that function as switches. It could also be called a circuit.

[0033] Then, the logic circuit unit 101 performs, for example, an additional operation according to the data stored in the memory circuit 103. The circuit configuration can be changed as appropriate, such as using it as an arithmetic unit or as an AND gate. can.

[0034] Furthermore, by holding data in the memory circuit 103, the circuit configuration of the logic circuit section 101 It can maintain this. Furthermore, the logic circuit section 101 has a memory circuit 103 inside. This is also acceptable. The specific circuit configuration and driving method of the semiconductor device are described below.

[0035] (Circuit configuration of memory circuit 103 and logic circuit 105) Figure 1(B) shows an example of a specific circuit configuration for the memory circuit 103 and the logic circuit 105. This indicates.

[0036] The memory circuit 103 includes a transistor 107 and a capacitive element 109. Multiple circuits 103 may be provided, and the number of circuits depends on the configuration of the logic circuit section 101. You just need to decide. If there are multiple, the set of them is simply called a memory circuit, or memory It is sometimes called a circuit section. It may also contain elements such as resistors and diodes.

[0037] Transistor 107 uses an oxide semiconductor. In particular, transistor 107 In Figure 1(B), the transient The designation "OS" is added to indicate that an oxide semiconductor is used in STA107. ru.

[0038] The gate of transistor 107 is electrically connected to terminal W, and the saw of transistor 107 Either the source or drain of transistor 107 is electrically connected to terminal D, and the source or drain of transistor 107 is connected to terminal D. The other end of Rain is electrically connected to terminal F and one of the pair of electrodes of the capacitive element 109. The other electrode of the pair of electrodes of the capacitive element 109 is electrically connected to terminal C. Each terminal can be configured to be electrically connected to wiring or electrodes. This configuration allows for a constant potential, such as a low power supply potential, to be input.

[0039] On the other hand, logic circuit 105 has transistor 111. Here, for simplicity, This explanation will describe the case with one ZISTA, but other configurations may also be used.

[0040] The gate of transistor 111 is electrically connected to terminal F of memory circuit 103. The gate is the other of the source or drain of transistor 107 and the capacitive element 109. It is electrically connected to one of the pair of electrodes. Source or Dray of transistor 111 One end of the transistor is electrically connected to terminal I, and the other end is either the source or drain of transistor 111. This side is electrically connected to terminal O.

[0041] Transistor 111 contains semiconductors from Group 14 of the periodic table (such as silicon). Using various semiconductors such as semiconductors, organic semiconductors, compound semiconductors, or oxide semiconductors. It is possible to use amorphous semiconductors, microcrystalline semiconductors, polycrystalline semiconductors, or single-crystal semiconductors, etc. These semiconductors can be used, especially in the channel formation region of transistor 111. It is being used.

[0042] Furthermore, as transistors using single-crystal semiconductors, bulk transistors using single-crystal semiconductor substrates are available. Examples include transistors and thin-film transistors using SOI substrates. Examples of substrates include glass substrates and semiconductor substrates. Amorphous semiconductors, microcrystalline semiconductors. Alternatively, transistors using polycrystalline semiconductors may be made on a glass substrate or a semiconductor substrate. Examples include thin-film transistors provided therein.

[0043] (Method for driving memory circuit 103 and logic circuit 105) The driving method for the memory circuit 103 and logic circuit 105 shown in Figure 1(B) will be explained below.

[0044] The storage (also called retention) of data in the memory circuit 103 is performed in the following manner. First, The transistor 107 receives a control signal input to the gate, Write (the control signal input to terminal W). It is selected to be ON by the signal. And, via the ON state transistor 107 The signal potential corresponding to the data (the signal potential input to terminal D) is at capacitive element 109 It is input to one of the pair of electrodes. That is, the memory circuit 103 is transistor 1 It has the function of inputting data to the capacitive element 109 via 07.

[0045] Subsequently, transistor 107 receives the control signal Write (input to terminal W) which is input to the gate. The pair of electrodes of the capacitive element 109 are selected to be in the off state by the applied control signal. The signal potential is held in one of the terminals. At that time, the signal potential is also held in terminal F. In this way, the data can be stored in the memory circuit 103.

[0046] Here, an oxide semiconductor is used in transistor 107, for example, silicon-based Compared to other transistors, the off-current (also called leakage current) is significantly smaller. Therefore, The memory circuit 103 controls the pair of capacitive elements 109 when transistor 107 is in the off state. The above signal potential can be maintained for a long period of time at one of the electrodes and at terminal F. Therefore, the memory circuit 103 continues to operate even after, for example, the supply of power voltage to the semiconductor device is stopped. It can retain data for extended periods.

[0047] Furthermore, the memory circuit 103 having a transistor 107 made of an oxide semiconductor is, for example, Compared to flash memory using recon transistors, etc., the drive voltage is lower. Compared to the aforementioned flash memory, it enables faster operation and reduced power consumption.

[0048] On the other hand, in the logic circuit 105 of Figure 1(B), the above signal potential is the gate of transistor 111. The input is used to control the on / off state of transistor 111. That is, terminals I and O The conductivity is controlled. And the memory circuit 103 can hold the data for a long time. Therefore, the circuit configuration of logic circuit 105 is maintained even after the power supply voltage to the semiconductor device is stopped. This is possible. Maintaining the circuit configuration of logic circuit 105 in Figure 1(B) means that the transition Maintaining the ON or OFF state of terminal 111 (conduction or non-conduction between terminal I and terminal O) It means that.

[0049] Here, since it is desirable for transistor 111 to operate at high speed, it has high mobility. Crystalline semiconductors are preferable. In particular, single-crystal semiconductors are preferred, and crystalline semiconductors are also preferable. It is preferable to use a semiconductor containing silicon, which is easy to improve. It is preferable to use single-crystal silicon for the inverter 111.

[0050] Furthermore, by stacking transistors 107 and 111, the circuit area can be reduced. This is possible. For example, as shown in Figure 7(C), transistor 111 is placed on transistor 1 07 should be provided. In that case, on the transistor 111 made of single crystal silicon, A structure in which a transistor 107 made of a material semiconductor is provided is preferred. As shown in Figure 7(D), stacked A specific example of the cross-sectional structure in that case is shown.

[0051] The cross-sectional structure in Figure 7(D) corresponds to the circuit configuration in Figure 1(B), and is made of single crystal silicon. On top of transistor 111 which uses a semiconductor, transistor 107 which uses an oxide semiconductor and a capacitor This shows the structure in which element 109 is provided.

[0052] The transistor 111 consists of a single-crystal silicon layer 131, a gate insulating layer 133, and a gate electric It has pole 135 and, the transistor 107 has an oxide semiconductor layer 137 and a gate insulating It has a marginal layer 139 and a gate electrode 141. The capacitive element 109 is a pair of electrodes It has one electrode 143 and the other electrode 145, and an insulating layer 147 which serves as a dielectric layer. And the gate electrode 135 of transistor 111 is one electrode of capacitive element 109. 143, and one of the electrodes 149 of the source electrode or drain electrode of transistor 107 They are electrically connected.

[0053] In the example shown in Figure 7(D), one electrode 143 of the capacitive element 109 is connected to the transistor 107 One of the source or drain electrodes 149 is extended. The insulating layer 147 that forms the dielectric layer of element 109 is the gate insulating layer 139 of transistor 107. This is an extended version of the above. Also, the other electrode 145 of the capacitive element 109 is connected to transistor 1 It is located on the same layer as the gate electrode 141 of 07. By using part or all of the structure, the films, electrodes, etc. of each element can be made using the same material. It can be formed in a single process, reducing costs and the number of steps involved.

[0054] A semiconductor device having the structure shown in Figure 7(D) offers high-speed operation, data retention, and a compact circuit area. This enables the reduction of both size and the reduction of costs and the number of manufacturing steps. The cross-sectional structure is not limited to Figures 7(C) and (D), and a transistor is placed on transistor 107. 111 may be provided. Also, in Figure 7(D), part of transistor 107 is a transistor Although it overlaps with transistor 111, the entirety of transistor 107 overlaps with transistor 111. It is also acceptable to leave them as they are. Furthermore, it is not necessary to stack transistors 111 and 107. ..., a structure in which transistor 107 and capacitive element 109 are stacked, and transistor 111 and A structure in which the capacitive element 109 is stacked may also be used.

[0055] As described above, the logic circuit 105 is configured according to the data stored in the memory circuit 103. It can be controlled.

[0056] Note that in Figure 1(B), the logic circuit 105 is shown as having one transistor, Other circuit configurations are also possible. For example, as shown in Figure 1(C), the logic circuit 105 is an inverter It may have CMOS circuits such as a . The operation in Figure 1(C) is the same as the operation in Figure 1(B). In accordance with the data stored in the memory circuit 103, the transistor 121 and the transistor Controls the on / off state of the inverter 123. That is, the continuity between terminal I1 and terminal O, or Select the continuity between terminal I2 and terminal O. Note that a high power supply potential is input to terminal I1, and terminal I2 can be configured to receive a low power supply potential.

[0057] (Circuit configuration and driving method of memory circuit 103 and logic circuit section 101) Figure 2(A) shows an example of the circuit configuration of the memory circuit 103 and the logic circuit section 101.

[0058] The logic circuit section 101 corresponds to the logic circuit 105 in Figure 1(A), and includes an adder 20 It has 1, an AND circuit 203, and a selection circuit 205. That is, logic circuit section 101 It includes arithmetic circuits such as an adder 201 and an AND gate 203, and a selection circuit 205. Other logic circuits as described above may also be used. Furthermore, they may have elements such as resistors and diodes. That's good too.

[0059] For the adder 201 and AND gate 203, any known circuits may be used. Adder 20 The AND circuit 203 performs calculations based on the inputs from terminals A and B, and the calculation result It has the function of inputting to the selection circuit 205.

[0060] An example of the selection circuit 205 is a multiplexer, etc. The selection circuit 205 is described The data D of the memory circuit 103 is electrically connected to terminal F of the memory circuit 103 and is used as the selection signal S. The input "ata" is received. Then, the selection circuit 205, according to the data, uses an adder. Select one of the inputs from either 201 or AND gate 203 and output it to terminal O. In other words, the selection circuit 205 selects an adder 201 or an AND circuit 20 depending on the data. It has a function to select one of the calculation results of the 3rd arithmetic circuit. Also, logic circuit section 10 Depending on the configuration of (1), it is also possible to select multiple arithmetic circuits.

[0061] Figure 2(B) shows the specific circuit configuration of the memory circuit 103 and the selection circuit 205.

[0062] The selection circuit 205 has two inputs (an input from the AND gate and an input from the adder). This is an example of a multiplexer, and it has transistor 207, transistor 209, and inverter It has transistor 211 and, here, transistor 207 and transistor 209 are polar They use components of the same gender. Furthermore, the circuit configuration of the selection circuit 205 is by transistor It is sufficient to control the electrical connection between the arithmetic circuit and terminal O, and the design is not limited to Figure 2(B).

[0063] The gate of transistor 207 is electrically connected to terminal F via inverter 211. Either the source or drain of transistor 207 is electrically connected to AND circuit 203. The gate of transistor 209 is electrically connected to terminal F, and the saw of transistor 209 Either the drain or the source of transistor 207 is electrically connected to adder 201. Alternatively, the other side of the drain and the other side of the source or drain of transistor 209 are electrically connected to terminal O. They are connected accordingly. The inputs of the multiplexer are configured as follows, depending on the configuration of the logic circuit section 101. You can change it to any number of m (where m is a positive integer) as needed. Also, the number of selection signals S is equal to the number of inputs. The decision should be made accordingly. Furthermore, the number of memory circuits 103 should be determined according to the number of selection signals S. For example, if there are four inputs (m=4: I0, I1, I2, I3), terminal O Since there are four possible outputs, there are two selection signals S0 and S1 ("S0S1" = "00", "0 Using the four options (1, 10, 11), the two selection signals S0 and S1 are used in relation to each of them. It is sufficient to provide two corresponding memory circuits 103 (see Figures 27(A) and (B)).

[0064] The circuit in Figure 2(B) can be driven in the same way as the circuits in Figures 1(B) and (C). First, note The memory circuit 103 selects the data Data which becomes the selection signal S via the transistor 107. The input is sent to path 205. Next, the selection circuit 205 performs a transient according to the data. The on / off state of TA209 is controlled, and the transistor responds according to the inverted data of the corresponding data. It controls the on / off state of transistor 207. And when transistor 207 is on, When 209 is in the OFF state, the input from AND gate 203 is selected and output to terminal O. Also, when transistor 209 is ON and transistor 207 is OFF, the adder The input from 201 is selected and output to terminal O.

[0065] In this way, the selection circuit 205 is controlled according to the data in the memory circuit 103. One of the results of the adder 201 or the AND gate 203 is selected. For simplicity, the logic circuits 105 of the logic circuit section 101 are defined as an adder 201 and an AND circuit. Although only circuit 203 and selection circuit 205 are shown, other configurations are also possible. A more practical example can be seen in Figure 3. This shows the configuration.

[0066] Figure 3 is a block diagram when a typical ALU is used as the logic circuit section 101. The logic circuit section 101 consists of an arithmetic operation section 301 which combines adders and subtractors, and AND circuits and A logic operation unit 303 that combines OR circuits and the like, and a shift operation unit 305 that has a shift circuit. It also includes a selection circuit 205 such as a multiplexer that selects and outputs them. Each of the calculation units 301, 303, and 305 is connected to selection circuits 307, 309, and 31 such as multiplexers. It has 1, and the combination of circuit configurations of logic circuits within each arithmetic unit can be changed. .

[0067] The selection circuits 307, 309, and 311 within each arithmetic unit, similar to the selection circuit 205, select the signal It is controlled according to the data Data in the memory circuit 103, which is S. In the case of Figure 3, memory circuit 1 03 is provided with multiple sets of transistor 107 and capacitive element 109 as shown in Figure 1(B). This should be configured as a memory circuit, and data should be output from terminals F1 to F4. The number of such sets is determined by the number of inputs to selection circuits 205, 307, 309, and 311. That's all. Also, if the same data is output from terminals F1 to F4, see Figure 1( The memory circuit 103 as in B) can be shared by the selection circuits 205, 307, 309, and 311. Furthermore, it is possible to miniaturize semiconductor devices.

[0068] Furthermore, since the memory circuit 103 can retain data for a long time, the semiconductor Even after the power supply voltage to the device is stopped, the circuit configuration of the logic circuit section 101 is maintained. Yes, it is possible. Also, as the circuit configuration becomes more complex as shown in Figure 3, the high-speed operation of the memory circuit 103 is also possible. The effect of reducing power consumption becomes even more pronounced.

[0069] Furthermore, by providing multiple circuits as shown in Figures 2 and 3, inputs from terminals A and B are received. The number of bits in a signal can be increased. That is, any n (where n is a positive integer) bits The control circuit section 101 can be configured.

[0070] This embodiment can be implemented in appropriate combination with other embodiments.

[0071] (Embodiment 2) This embodiment describes an example of a semiconductor device different from that of Embodiment 1.

[0072] Figures 4(A) and 4(B) show modified versions of Figure 1(B).

[0073] First, let's explain the example in Figure 4(A). The memory circuit 103 is the same as in Figure 1(B), etc. ru.

[0074] The logic circuit 105 in Figure 4(A) consists of transistor 111, transistor 401, and Transistor 111 and transistor 401 have terminal I and terminal I. It is electrically connected in parallel with child O. That is, the source or dot of transistor 111. One side of the rain and one side of the source or drain of transistor 401 are electrically connected to terminal I. The other side of the source or drain of transistor 111 and the source of transistor 401 are connected. The other end of the pipe or drain is electrically connected to terminal O.

[0075] Transistor 111 and transistor 401 are N-channel type and P-channel type, respectively. It is a Nell type, and one with different polarity is used. And the gate of transistor 111 is marked Data is input to the memory circuit 103, and the gate of transistor 401 receives the corresponding data. The inverted data of the Data is input. Transistor 11 has different polarity as shown in Figure 4(A). By using transistors 111 and 401, voltage fluctuations equal to the threshold voltage of transistors 111 and 401 are suppressed. It is possible.

[0076] Next, we will explain the example in Figure 4(B).

[0077] The memory circuit 103 in Figure 4(B) consists of a transistor 107, a capacitive element 109, and a transistor It has a st 405, a capacitive element 407, and an inverter 409. Transistor 107 And the capacitive element 109 is the same as in Figure 1(B), etc. And transistor 40 The gate of 5 is electrically connected to terminal W, and one of the source or drains of transistor 405 The inverter 409 is electrically connected to terminal D, and the source of transistor 405 Alternatively, the other drain is electrically connected to one of the pair of electrodes of the capacitive element 407 and terminal F2. Connected.

[0078] The logic circuit 105 in Figure 4(B) is similar to Figure 4(A) in that it uses transistors 11 with different polarities. 1 and transistor 401 are electrically connected in parallel between terminals I and O. Then, the data from the memory circuit 103 is input to the gate of transistor 111, The gate of the transistor 401 receives the inverted data of the relevant data. Figure 4(A Similarly, by using transistors 111 and 401 with different polarities, transistor 11 1. Voltage fluctuations equivalent to a threshold voltage of 401 can be suppressed.

[0079] This embodiment can be implemented in appropriate combination with other embodiments.

[0080] (Embodiment 3) This embodiment describes an example of a semiconductor device different from the embodiment described above.

[0081] The semiconductor device shown in Figure 5(A) has a plurality of logic circuit sections 101 and a connection section 501. The logic circuit section 101 is the same as in Figures 1 to 3, and an ALU or the like can be used. .

[0082] The connection section 501 controls the continuity of the wiring 503 that electrically connects multiple logic circuit sections 101. It has a control function. Figure 5(B) shows the details.

[0083] The circuit configuration and driving method of the connection part 501 in Figure 5(B) are the same as in Figure 1(B), and memory The on / off state of transistor 111 is controlled according to the data from circuit 103. In other words, the conductivity between terminal I and terminal O is controlled. Terminals I and O are different It is electrically connected to the logic circuit section 101, and the continuity between terminal I and terminal O is controlled, The electrical connections between the logic circuit sections 101 are controlled. Note that the logic circuit 105 is a transistor. Not limited to circuits with a single 111, but also elements that function as switches (transistors) The circuit may have one or more (e.g., a 'T').

[0084] Thus, the transistor 111 of the connection part 501 reacts to the data Data in multiple ways. It has the function of controlling the electrical connection between one of the number logic circuit sections 101 and another. Furthermore, terminals I and O are terminals A and O of one logic circuit unit 101, respectively (Figure 3) (See etc.) It may be electrically connected to a single logic circuit unit 101 The output may be configured to feed back to the input. Furthermore, a memory circuit 103 may be located outside the connection section 501. It may have.

[0085] Figure 5(C) shows an example of electrical connections between multiple logic circuit units 101. Figure 5 The semiconductor device (C) has a memory 505 and a selection circuit 507. This contains information a to n, such as control signals (Write) and data (Data). Circuit 507 is a multiplexer, etc., and selects the information and stores it in the memory circuit 1 of the connection unit 501. Output to 03.

[0086] In Figure 5(C), information a is selected, and the wiring 503 between the logic circuit units 101 is as shown by the arrow. This shows how the connections are made. Also, when information b to n are selected, the connection relationship changes. It should be modified accordingly. Note that in Figure 5(C), only the connected wiring 503 is shown. ru.

[0087] Furthermore, in the semiconductor device shown in Figure 5(C), the memory circuit 103 of the connection part 501 is Because the data can be retained for a long time, the power supply voltage to the semiconductor device is stopped. Even after this, the connection relationship between multiple logic circuit sections 101 can be maintained. The oxide semiconductor transistor 107 in 501 has a low drive voltage. Therefore, When changing connection relationships, for example, compared to flash memory, it offers faster operation and lower power consumption. It is possible to reduce it.

[0088] Alternatively, the memory 505 may use the memory circuit 103. In that case, the memory 505 may also be high-speed. Furthermore, it can be operated with low power consumption. Also, the circuit configuration of the connection part 501 is shown in Figure 4. (A) and (B) may also be used.

[0089] This embodiment can be implemented in appropriate combination with other embodiments.

[0090] (Embodiment 4) This embodiment describes an example of a semiconductor device combining Embodiments 1 and 3. I will reveal it.

[0091] The semiconductor device in Figure 6(A) has multiple logic circuit sections 101 (with "+" and "AND" etc.) (The part) and connection part 501, memory circuit 103, memory 505, selection circuit 507, It has a memory 505 and a selection circuit 507 outside the semiconductor device.

[0092] The memory circuit 103 is a circuit of a plurality of logic circuit units 101, as described in Embodiment 1 and the like. It has the function of maintaining the configuration.

[0093] The connection section 501 is used for connecting multiple logic circuit sections 101, as described in Embodiment 3 and other embodiments. It has the function of maintaining relationships.

[0094] Furthermore, each of the pieces of information a to n stored in memory 505 is related to the circuit configuration and It has information on both the connection and the relationship between the devices. This information is stored in the memory circuit 103 and the connection unit 501. By providing this functionality, the semiconductor device will maintain its circuit configuration and connections even after the power supply voltage has been cut off. It is possible to maintain both relationships. In addition, the oxide semiconductor of the memory circuit 103 is used Transistors have a low drive voltage. Therefore, it is not possible to change the circuit configuration or connection relationships quickly. It can be done with low power consumption.

[0095] This embodiment can be implemented in appropriate combination with other embodiments.

[0096] (Embodiment 5) This embodiment shows an example of a configuration that reduces the power consumption of a semiconductor device.

[0097] Figure 6(B) shows a configuration in which the supply of power voltage to circuits not used in a semiconductor device is stopped. This shows the logic circuit section 101 (logic circuit section 101a and logic circuit section 101b), and the connections. The configuration of section 501, memory circuit 103, etc., is the same as in other embodiments.

[0098] Of the logic circuit section 101a and memory circuit 103 used, data Da is stored in the logic circuit section 101a. The part that supplies ta, and the connection relationship of the logic circuit section 101a among the connection section 501. The memory circuit is supplied with power voltage.

[0099] On the other hand, among the logic circuit section 101b and memory circuit 103 that are not used, the logic circuit section 101b is used The part that supplies data, and the connection relationship of the logic circuit part 101b in the connection part 501. The power supply voltage to the memory circuit that controls it will be cut off. Also, the power to any of them will be cut off. The voltage supply may be stopped. That is, only the unused logic circuit section 101b. You may also choose to stop supplying power voltage.

[0100] As an example of stopping the supply of power voltage, the logic circuit 105 shown in Figure 1(C) is shown. In a converter, the electrical connection between terminals I1 and I2 and the power line is interrupted by a switch or the like. This allows for the cessation of both the supply of high and low power potentials. Figure 2(A) Similarly, the adder 201, AND gate 203, and selection gate 205, etc., use switches, etc. This allows for the cessation of supplying high or low power potentials.

[0101] In this way, by stopping the supply of power voltage to unused circuits, the consumption of semiconductor devices is reduced. It can reduce power consumption.

[0102] This embodiment can be implemented in appropriate combination with other embodiments.

[0103] (Embodiment 6) In this embodiment, an oxide applicable to the transistor of the memory circuit shown in the above embodiment is used. An example of a field-effect transistor including a semiconductor layer will be described.

[0104] An example of a transistor in this embodiment will be explained using Figures 7(A) and 7(B). do.

[0105] The transistor shown in Figure 7(A) consists of a conductive layer 601_a, an insulating layer 602_a, and a semiconductor. It includes layer 603_a, conductive layer 605a_a, and conductive layer 605b_a.

[0106] Semiconductor layer 603_a includes region 604a_a and region 604b_a. Region 604a Regions _a and 604b_a are separated from each other and are regions to which dopants have been added. Furthermore, the region between region 604a_a and region 604b_a becomes the channel-forming region. The semiconductor layer 603_a is provided on top of the element formation layer 600_a. It is not necessary to provide regions 604a_a and 604b_a.

[0107] The conductive layer 605a_a and the conductive layer 605b_a are provided on the semiconductor layer 603_a. It is electrically connected to the semiconductor layer 603_a. Also, conductive layer 605a_a and conductive layer 605 The side surface of b_a is tapered.

[0108] Furthermore, the conductive layer 605a_a is superimposed on a portion of region 604a_a, but not necessarily on this portion. Not limited to. By superimposing the conductive layer 605a_a onto a part of region 604a_a, The resistance between the conductive layer 605a_a and region 604a_a can be reduced. The entire region of the semiconductor layer 603_a superimposed on the conductive layer 605a_a is region 604a_a It can be structured in a certain way.

[0109] Furthermore, the conductive layer 605b_a is superimposed on a portion of region 604b_a, but not necessarily on this portion. Not limited. By superimposing the conductive layer 605b_a onto a part of region 604b_a, The resistance between the conductive layer 605b_a and region 604b_a can be reduced. Also, The entire region of the semiconductor layer 603_a superimposed on the conductive layer 605b_a is region 604b_a. It may also be structured in this way.

[0110] The insulating layer 602_a consists of the semiconductor layer 603_a, the conductive layer 605a_a, and the conductive layer 605b It is placed above _a.

[0111] The conductive layer 601_a is provided on a portion of the insulating layer 602_a, and via the insulating layer 602_a It is then superimposed on the semiconductor layer 603_a. It is superimposed on the conductive layer 601_a via the insulating layer 602_a. The region of semiconductor layer 603_a becomes the channel formation region.

[0112] Furthermore, the transistor shown in Figure 7(B) has a conductive layer 601_b and an insulating layer 602_b, Semiconductor layer 603_b, conductive layer 605a_b, conductive layer 605b_b, insulating layer 606a This includes insulating layer 606b and insulating layer 607.

[0113] Semiconductor layer 603_b includes regions 604a_b and 604b_b. Region 604a Regions _b and 604b_b are separated from each other and are regions to which dopants have been added. The semiconductor layer 603_b is, for example, a conductive layer 605a_b, a conductive layer 605b_b, and a substrate. A layer is provided on the substrate-forming layer 600_b, and electrical currents are supplied to the conductive layer 605a_b and the conductive layer 605b_b. They are connected in a specific manner. Note that it is not always necessary to provide regions 604a_b and 604b_b. good.

[0114] The insulating layer 602_b is provided on a portion of the semiconductor layer 603_b.

[0115] The conductive layer 601_b is provided on a portion of the insulating layer 602_b, and via the insulating layer 602_b It is then superimposed onto the semiconductor layer 603_b. Note that the conductive layer 601_b is connected via the insulating layer 602_b. The region of semiconductor layer 603_b that overlaps with this becomes the channel formation region of the transistor. An insulating layer may be provided on top of the conductive layer 601_b.

[0116] The insulating layer 606a is provided on top of the insulating layer 602_b, and one pair in the conductive layer 601_b It is in contact with one of its sides.

[0117] The insulating layer 606b is provided on top of the insulating layer 602_b, and one pair in the conductive layer 601_b It is in contact with the other side of the other side.

[0118] Furthermore, region 6 superimposed on insulating layer 606a and insulating layer 606b via insulating layer 602_b The dopant concentration in areas 04a_b and 604b_b is determined by the insulating layer 606a and the insulating layer. Dopant concentration in regions 604a_b and 604b_b that do not overlap with layer 606b It can be lower than a degree.

[0119] The conductive layers 605a_b and 605b_b are provided on the semiconductor layer 603_b. .

[0120] The conductive layer 605a_b is electrically connected to region 604a_b. a_b is in contact with the insulating layer 606a.

[0121] The conductive layer 605b_b is electrically connected to the region 604b_b. Also, the conductive layer 605 b_b is in contact with the insulating layer 606b.

[0122] The insulating layer 607 is provided over the conductive layer 601_b, the conductive layer 605a_b, the conductive layer 605b_b, the insulating layer 606a, and the insulating layer 606b.

[0123] Furthermore, each component shown in FIGS. 7(A) and 7(B) will be described.

[0124] As the device-forming layers 600_a and 600_b, for example, an insulating layer or a substrate having an insulating surface can be used. Also, a layer on which elements are previously formed can be used as the device-forming layers 600_a and 600_b.

[0125] Each of the conductive layers 601_a and 601_b has a function as a gate of a transistor. Note that a layer having a function as a gate of a transistor is also referred to as a gate electrode or a gate wiring.

[0126] As the conductive layers 601_a and 601_b, for example, a layer of a metal material such as molybdenum, magnesium, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material having these as main components can be used. [[ID=4V]] 601_a and the conductive layer 601_b can also be formed by laminating materials applicable to the conductive layers 601_a and 601_b.

[0127] Insulating layer 602_a and insulating layer 602_b are each connected to the gate insulating layer of the transistor. It has the function of being a .

[0128] Examples of insulating layers 602_a and 602_b include silicon oxide layer, silicon nitride layer, etc. Silicon oxide layer, silicon oxide nitride layer, silicon oxide nitride layer, aluminum oxide layer, aluminum nitride Aluminum layer, aluminum oxide nitride layer, aluminum oxide nitride layer, hafnium oxide layer, or oxide A lanthanum layer can be used. This is also applicable to insulating layer 602_a and insulating layer 602_b. Insulating layers 602_a and 602_b can also be constructed by laminating possible materials. .

[0129] Furthermore, the insulating layers 602_a and 602_b may be, for example, elements in the periodic table of elements. An insulating layer made of a material containing Group 13 elements and oxygen can also be used. For example, semiconductor layer 6 When 03_a and semiconductor layer 603_b contain Group 13 elements, semiconductor layer 603_a and By using an insulating layer containing a Group 13 element as the insulating layer in contact with the semiconductor layer 603_b, This allows for a good condition of the interface between the insulating layer and the oxide semiconductor layer.

[0130] Examples of materials containing Group 13 elements and oxygen include gallium oxide and aluminum oxide. Examples include aluminum oxide, gallium oxide, and aluminum gallium oxide. Aluminum gallium is defined as having a higher aluminum content (percentage of gallium atoms) than gallium content (percentage of atomic gallium atoms) This refers to a substance with a high atomic %) content, and gallium aluminum oxide is a substance with a high gallium content ( This refers to a substance in which the atomic percentage is greater than or equal to the aluminum content (atomic percentage). For example, Al2O x (x=3+α, where α is greater than 0 and less than 1), Ga2Ox (x = 3 + α, where α is a value greater than 0 and less than 1), or Ga Also, materials expressed as (x is a value greater than 0 and less than 2, and α is a value greater than 0 and less than 1) can be used. x Al 2-x O 3+α (x is a value greater than 0 and less than 2, and α is a value greater than 0 and less than 1) can also be used. Small value, and α is a value greater than 0 and less than 1) can also be used.

[0131] In addition, the insulating layers 602_a and 602_b can also be formed by laminating layers of materials applicable to them. For example, the insulating layers 602_a and 602_b can be formed by laminating multiple layers containing gallium oxide expressed as Ga2O Also, the insulating layers 602_a and 602_b can be formed by laminating an insulating layer containing gallium oxide expressed as Ga2O and an insulating layer containing aluminum oxide expressed as Al2 x Each of the semiconductor layers 603_a and 603_b functions as a layer in which the channel of the transistor is formed. Examples of oxide semiconductors applicable to the semiconductor layers 603_a and 603_b include In-based oxides (such as indium oxide), Sn Also, the insulating layers 602_a and 602_b can be formed. Further, the insulating layers 602_a and 602_b can be formed by laminating an insulating layer containing gallium oxide expressed as Ga2O and an insulating layer containing aluminum oxide expressed as Al2 x O O x O. The insulating layers 602_a and 602_b can also be formed.

[0132] Each of the semiconductor layers 603_a and 603_b functions as a layer in which the channel of the transistor is formed. Examples of oxide semiconductors applicable to the semiconductor layers 603_a and 603_b include In-based oxides (such as indium oxide), Sn Formed layer. Examples of oxide semiconductors applicable to the semiconductor layers 603_a and 603_b include In-based oxides (such as indium oxide), Sn Based oxides (such as tin oxide), or Zn-based oxides (such as zinc oxide) can be used. Based oxides (such as tin oxide), or Zn-based oxides (such as zinc oxide) can be used. For example, In-based oxides (such as indium oxide), Sn-based oxides (such as tin oxide), or Zn-based oxides (such as zinc oxide) can be used.

[0133] In addition, as the above metal oxides, for example, metal oxides such as quaternary metal oxides, ternary metal oxides, and binary Metal oxides such as binary metal oxides can also be used. Note that the metal oxides applicable as the above oxide semiconductors are gallium as a stabilizer to reduce variations in characteristics, And It may also contain one or more of tin, hafnium, and aluminum. Metal oxides applicable as oxide semiconductors include lanthanides, which can be used as stabilizers. These are lanthanum, cerium, praseodymium, neodymium, samarium, europium, and Dolinium, Terbium, Dysprosium, Holmium, Erbium, Thulium, Itte The oxide semiconductor may contain one or more rubium and lutetium. The metal oxides applicable as such may include silicon oxide.

[0134] For example, as a quaternary metal oxide, there are, for example, In-Sn-Ga-Zn oxides, In- Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides, etc. are used. It is possible to be there.

[0135] Furthermore, as ternary metal oxides, for example, In-Ga-Zn oxides (also known as IGZO) (u) In-Sn-Zn oxides, In-Al-Zn oxides, Sn-Ga-Zn oxides Materials, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, I n-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In -Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In- Yb-Zn oxides or In-Lu-Zn ​​oxides can be used.

[0136] As the binary metal oxide, for example, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Sn oxide, or In-Ga oxide can be used.

[0137] Note that, for example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, metal elements other than In, Ga, and Zn may be included.

[0138] As the oxide semiconductor, a material represented by InLO3(ZnO) m (m is a number greater than 0) can also be used. In the InLO3(ZnO) , L represents one or more metal elements selected from Ga, Al, Mn, m and Co.

[0139] For example, as the oxide semiconductor, In-Ga-Zn oxides with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3: 1 / 3) or In:Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) and oxides in the vicinity of their compositions can be used. Also, as the oxide semiconductor, In-Sn-Zn oxides with an atomic ratio of In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In: Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1: 5 (= 1 / 4:1 / 8:5 / 8) and oxides in the vicinity of their compositions can be used.

[0140] However, it is not limited to these, and those with an appropriate composition can be used according to the required semiconductor characteristics (mobility, threshold voltage, variation, etc.). Also, to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond distance, density It is preferable to set the degree and other parameters appropriately.

[0141] Oxide semiconductors can be single crystals or non-single crystals. In the latter case, they can be amorphous or multicrystalline. It can be crystalline. Also, a structure that includes crystalline parts within an amorphous material is also acceptable. "S" is also acceptable.

[0142] Furthermore, the semiconductor layers 603_a and 603_b are oriented along the c-axis and ab It has a triangular or hexagonal atomic arrangement when viewed from the direction of a face, surface, or interface, and along the c-axis Metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers, and in the ab plane, the a axis or This is an oxide semiconductor (CAAC-O) containing crystals with different b-axis orientations (rotated around the c-axis). S:C Axis Aligned Crystalline Oxide Semiconductor A layer of (also called an induction layer) can be used.

[0143] CAAC, in a broad sense, refers to a non-single crystal that, when viewed from a direction perpendicular to its ab-plane, has a triangular shape. , having an atomic arrangement of hexagons, equilateral triangles, or regular hexagons, and viewed from a direction perpendicular to the c-axis direction This refers to materials containing layers of metal atoms, or phases in which metal atoms and oxygen atoms are arranged in layers.

[0144] CAAC is not a single crystal, but it is also not a material formed solely from amorphous material. CAAC contains crystalline parts (crystalline portions), but the boundary between one crystalline portion and another crystalline portion is not clear. It can sometimes be difficult to clearly distinguish between them.

[0145] If CAAC contains oxygen, some of the oxygen may be replaced with nitrogen. The c-axes of the individual crystal parts constituting C may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab-planes of the individual crystal parts constituting CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab-planes of the individual crystal parts constituting CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab-planes of the individual crystal parts constituting CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). AAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, it may be transparent or opaque to visible light depending on its composition and the like.

[0146] AAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, it may be transparent or opaque to visible light depending on its composition and the like. AAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, it may be transparent or opaque to visible light depending on its composition and the like. AAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, it may be transparent or opaque to visible light depending on its composition and the like.

[0147] Examples of such CAAC include, for example, a crystal that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the substrate surface, a triangular or hexagonal atomic arrangement is recognized, and when observing its film cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is recognized. Examples of such CAAC include, for example, a crystal that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the substrate surface, a triangular or hexagonal atomic arrangement is recognized, and when observing its film cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is recognized. Examples of such CAAC include, for example, a crystal that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the substrate surface, a triangular or hexagonal atomic arrangement is recognized, and when observing its film cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is recognized. Examples of such CAAC include, for example, a crystal that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the substrate surface, a triangular or hexagonal atomic arrangement is recognized, and when observing its film cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is recognized.

[0148] Also, as the oxide semiconductor, the composition of the crystal region oriented in the c-axis direction is In 1+σ Ga1 -σ O3(ZnO) M (where 0 < σ < 1, M is a number of 1 or more and 3 or less), and the composition of the entire semiconductor layer including the crystal region oriented in the c-axis direction is In Ga P Ga Q O R (ZnO) M (where 0 < P < 2, 0 < Q < 2, M is a number of 1 or more and 3 or less) can also be used. 0 < P < 2, 0 < Q < 2, M is a number of 1 or more and 3 or less) can also be used.

[0149] Also, for example, semiconductor layer 603_a and semiconductor layer 603_b are CAAC oxide semiconductors In the case of a layer, when the channel length of the transistor is 30 nm, the semiconductor layer 603_ Even if the thickness of a and semiconductor layer 603_b is reduced to, for example, about 5nm, the short-circuit of the transistor The channel effect can be suppressed.

[0150] Here, we will further explain an example of the crystal structure contained in CAAC using Figures 8 to 10. To clarify. Unless otherwise specified, in Figures 8 to 10, the upward direction is the c-axis direction. Let the plane perpendicular to it be called plane ab. Note that when we simply refer to the upper half and the lower half, we mean the plane with plane ab as the boundary. This refers to the upper and lower halves of a case. Also, in Figure 8, the circled O represents a 4-coordinate O. The O enclosed in a double circle indicates a 3-coordinate O.

[0151] Figure 8(A) shows one 6-coordinate indium atom (also called 6-coordinate In) and a 6-coordinate It exhibits a structure having six 4-coordinate oxygen atoms (also called 4-coordinate O) adjacent to In. Furthermore, a part composed of one metal atom such as In and an oxygen atom adjacent to the metal atom. Each of these is called a small group. Also, in Figure 8(A), for convenience, the octahedral structure is shown as a planar structure. Furthermore, the upper and lower halves of Figure 8(A) each contain three 4-coordinate oxygen atoms. Furthermore, the charge of the small group shown in Figure 8(A) is 0.

[0152] Figure 8(B) shows one 5-coordinate Ga atom and three 3-coordinate oxygen atoms adjacent to the 5-coordinate Ga atom. It has an atom (also called 3-coordinate O) and two 4-coordinate O atoms adjacent to a 5-coordinate Ga. The structure is shown. Each of the three three-coordinate oxygen atoms is located on the ab plane. Also, Figure 8( In the upper and lower halves of B), there is one 4-coordinate oxygen atom each. Also, indium In addition to 6-coordinate atoms, there are also 5-coordinate indium atoms (5-coordinate In). Therefore, with 5-coordinate In, 3 3-coordinate O, and 2 4-coordinate O, as shown in Figure 8(B) It is also possible to form a structure. Furthermore, the charge of the small group shown in Figure 8(B) is 0.

[0153] Figure 8(C) shows one 4-coordinate zinc atom (also called 4-coordinate Zn) and 4-coordinate Zn It shows a structure having four 4-coordinate oxygen atoms adjacent to it. The upper half of Figure 8(C) shows one 4 There is a coordinated oxygen atom, and the lower half has three four-coordinated oxygen atoms. Note that the small group shown in Figure 8(C) The charge of P is 0.

[0154] Figure 8(D) shows one 6-coordinate tin atom (also called 6-coordinate Sn) and 6-coordinate Sn It shows a structure having six 4-coordinate oxygen atoms in close proximity to it. The upper half of Figure 8(D) shows three 4 There is a coordinated oxygen atom, and in the lower half there are three four-coordinate oxygen atoms. Note that the small group shown in Figure 8(D) The charge of P becomes +1.

[0155] Figure 8(E) shows a small group containing two zinc atoms. The upper half of Figure 8(E) shows 1 There are four-coordinate oxygen atoms, and one four-coordinate oxygen atom in the lower half. Small group shown in Figure 8(E) The charge of P becomes -1.

[0156] Furthermore, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a large group. This is called a group (also called a unit cell).

[0157] Here, we will explain the rules by which the above subgroups combine. For example, the 6-coordinate In The three 4-coordinate oxygen atoms in the upper half are bonded to the three 6-coordinate inductive atoms located nearby below. The three 4-coordinate oxygen atoms in the lower half bond to the three 6-coordinate inductors located in close proximity above. Furthermore, one 3-coordinate O in the upper half of the 5-coordinate Ga is adjacent to one 5-coordinate Bonded to Ga at position 1, one 3-coordinate O in the lower half is adjacent to one 5-coordinate O in the upper direction It bonds to the Ga. Also, one 4-coordinate O in the upper half of the 4-coordinate Zn is directed downwards. Bonded to one adjacent 4-coordinate Zn, the three 4-coordinate O atoms in the lower half are positioned upwards. It bonds to the three four-coordinate Zn atoms that are in contact with it. In this way, the four-coordinate atoms in the upward direction of the metal atom The number of oxygen atoms is equal to the number of metal atoms adjacent to that oxygen atom in the direction below it, and similarly, in the direction below the metal atom The number of four-coordinate oxygen atoms is equal to the number of metal atoms adjacent to those oxygen atoms in the direction above them. Since O is 4-coordinate, the number of metal atoms adjacent to it in the downward direction and the number of metal atoms adjacent to it in the upward direction are... The sum is 4. Therefore, the number of 4-coordinate oxygen atoms above a metal atom and the number of oxygen atoms below another metal atom When the sum of the number of O atoms in 4-coordinate groups in a given direction is 4, the two types of small groups containing metal atoms are the same. Metals can bond together. For example, a 6-coordinate metal atom (In or Sn) can bond with the lower half of 4 When bonded via coordinating oxygen, there are three 4-coordinate oxygen atoms, so a 5-coordinate metal atom or 4 It will bond with the coordinating metal atom.

[0158] Metal atoms with these coordination numbers are bonded in the c-axis direction via 4-coordinate oxygen atoms. In addition, multiple small groups combine in such a way that the total charge of the layered structure becomes 0. They form a middle group.

[0159] Furthermore, Figure 9(A) shows a model of the intermediate group that constitutes the layered structure of the In-Sn-Zn system. The diagram is shown. Figure 9(B) also shows a large group composed of three smaller groups. Furthermore, in Figure 9(C), the atomic arrangement when the layer structure shown in Figure 9(B) is observed from the c-axis direction is shown. show.

[0160] Note that in Figure 9(A), for convenience, three-coordinate oxygen atoms are omitted, and only the number of four-coordinate oxygen atoms is shown. For example, if there are 3 four-coordinate oxygen atoms in the upper half and 3 in the lower half of Sn, then circle the It is shown as 3. Similarly, in Figure 9(A), the upper half and lower half of In The presence of four-coordinate oxygen atoms in each of these is indicated by the circled "1". Similarly, In Figure 9(A), there is one 4-coordinate oxygen atom in the lower half and three 4-coordinate oxygen atoms in the upper half. n and Zn, which has one 4-coordinate oxygen atom in the upper half and three 4-coordinate oxygen atoms in the lower half, are shown. They are doing it.

[0161] In Figure 9(A), in the middle group that constitutes the In-Sn-Zn layer structure, from the top It has the following structure in order: Sn has three 4-coordinate oxygen atoms in the upper half and three in the lower half, One oxygen atom is bonded to the in atoms in the upper half and one to the lower half of the molecule. There are four-coordinate oxygen atoms bonded to a Zn molecule. The Zn molecule has one four-coordinate oxygen atom in the lower half of the Zn molecule. Three oxygen atoms in a 4-coordinate structure are bonded to the in atoms in the upper and lower halves of the molecule via oxygen. It is bonded to a small group consisting of two Zn atoms, with one 4-coordinate O atom in the upper half. The group has three four-coordinate oxygen atoms in the lower half of the subgroup via one four-coordinate oxygen atom. It is joined to the Sn in the upper half and lower half, respectively. Multiple of the above middle groups are joined together. This leads to the formation of large groups.

[0162] Here, in the case of 3-coordinate oxygen and 4-coordinate oxygen, the charge per bond is -0, in each case. It can be considered as 667, -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of (coordinate) and Sn (5-coordinate or 6-coordinate) are +3, +2, and +4, respectively. Therefore, the charge of the small group containing Sn becomes +1. To achieve this, a charge of -1 is needed to cancel out a charge of +1. As shown in Figure 8(E), a small group containing two Zn atoms can be cited. For example, Sn If there is one small group containing Zn and another small group containing two Zn, the charge will be Because they cancel each other out, the total charge of the layered structure can be set to 0.

[0163] Furthermore, by creating a structure in which the large groups shown in Figure 9(B) are repeated, In-S n-Zn-based crystals (In2SnZn3O8) can be obtained. The layered structure of the Sn-Zn system is In2SnZn2O7(ZnO) m (m is 0 or a natural number) It can be represented by the following chemical formula.

[0164] Furthermore, other quaternary metal oxides, ternary metal oxides, and binary metal oxides shown in this embodiment The same applies when using materials, other metal oxides, etc.

[0165] For example, Figure 10(A) shows a model diagram of the intermediate group that constitutes the layered structure of the In-Ga-Zn system. This will be shown.

[0166] In Figure 10(A), the middle group constituting the In-Ga-Zn layer structure is, from top to bottom: It has the following structure in order: In which there are 3 oxygen atoms in the upper half and 3 oxygen atoms in the lower half, 4 One coordination oxygen atom is bonded to the Zn atom in the upper half. This Zn atom is then bonded to three 4 atoms in the lower half of the Zn atom. Through coordinating oxygen atoms, one oxygen atom in the 4-coordinate system is bonded to the Ga in the upper and lower halves, respectively. The Ga has three 4-coordinate oxygen atoms in the upper half, connected by one 4-coordinate oxygen atom in the lower half of the Ga. It is bonded to the In in the lower half. Multiple of the above middle groups are bonded together to form a large group A loop is formed.

[0167] Figure 10(B) shows the large group, which is composed of three subgroups. Figure 10(C) shows the atomic arrangement when the layer structure shown in B) is observed from the c-axis direction.

[0168] Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are as follows: Since they are +3, +2, and +3 respectively, the small group of electrons containing any of In, Zn, and Ga The load will be 0. Therefore, for combinations of these small groups, the sum of the medium groups is The charge is always 0.

[0169] The intermediate groups that constitute the layered structure of the In-Ga-Zn system are shown in Figure 10(A). Not limited to a single group, a large group can be formed by combining intermediate groups with different arrangements of In, Ga, and Zn. You can also construct loops.

[0170] Specifically, the large groups shown in Figure 10(B) are repeated, resulting in In-Ga-Z n-based crystals can be obtained. The resulting In-Ga-Zn layer structure is InG aO3(ZnO) n It can be expressed by a compositional formula where n is a natural number.

[0171] For n=1 (InGaZnO4), for example, it takes the crystal structure shown in Figure 26(A). Furthermore, in the crystal structure shown in Figure 26(A), as explained in Figure 8(B), Ga and Since in takes a 5-coordinate state, it can also take a structure in which Ga is replaced by in.

[0172] Furthermore, in the case of n=2(InGaZn2O5), for example, the crystal structure shown in Figure 26(B) is obtained. It is possible to have the crystal structure shown in Figure 26(B), as explained in Figure 8(B). Since Ga and In can form a 5-coordinate structure, a structure in which Ga is replaced by In is also possible.

[0173] The above is an example of the structure of CAAC. CAAC is a crystalline oxide semiconductor. The conductor has a low defect rate within the bulk.

[0174] Furthermore, regions 604a_a, 604b_a, and region shown in Figures 7(A) and 7(B) Regions 604a_b and 604b_b are dopant-added and are the source of the transistor. Alternatively, it functions as a drain. As a dopant, for example, element 1 in the periodic table. Elements of Group 3 (e.g., boron), elements of Group 15 in the periodic table (e.g., nitrogen, phosphorus, (and one or more arsenic elements), and noble gas elements (e.g., helium, argon, and xenon) One or more of the following can be used. Note that the source of the transistor and The region that functions as the drain of a transistor is also called the source region, and it functions as the drain of a transistor. The region containing these regions is also called the drain region. Region 604a_a, Region 604b_a, Region 604 By adding dopants to a_b and region 604b_b, the resistance between them and the conductive layer is reduced. Because it can be made smaller, transistors can be miniaturized.

[0175] conductive layer 605a_a, conductive layer 605b_a, conductive layer 605a_b, and conductive layer 605b Each of _b functions as either the source or drain of a transistor. The layer that functions as the source of a transistor is also called the source electrode or source wiring. The layer that functions as a drain in an inverter is also called a drain electrode or drain wiring.

[0176] conductive layer 605a_a, conductive layer 605b_a, conductive layer 605a_b, and conductive layer 605b Examples of _b include aluminum, magnesium, chromium, copper, tantalum, titanium, and Metallic materials such as ribdenum or tungsten, or materials that are mainly composed of these metallic materials A layer of alloy material can be used. For example, one containing copper, magnesium, and aluminum. Due to the layers of alloy material, conductive layer 605a_a, conductive layer 605b_a, conductive layer 605a_b , and conductive layer 605b_b can be formed. Also, conductive layer 605a_a, conductive layer Lamination of materials applicable to 605b_a, conductive layer 605a_b, and conductive layer 605b_b Therefore, conductive layer 605a_a, conductive layer 605b_a, conductive layer 605a_b, and conductive layer 60 5b_b can also be composed of, for example, copper, magnesium, and aluminum. By laminating layers of alloy material and copper-containing layers, conductive layer 605a_a, conductive layer 605b_a, A dielectric layer 605a_b and a conductive layer 605b_b can be formed.

[0177] Also, conductive layer 605a_a, conductive layer 605b_a, conductive layer 605a_b, and conductive layer 6 For 05b_b, a layer containing a conductive metal oxide can also be used. Conductive metal Examples of oxides include indium oxide, tin oxide, zinc oxide, and indium tin oxide. Alternatively, indium zinc oxide can be used. Note that conductive layer 605a_a, conductive conductive gold applicable to layer 605b_a, conductive layer 605a_b, and conductive layer 605b_b The group oxide may contain silicon oxide.

[0178] Examples of insulating layers 606a and 606b include insulating layer 602_a and insulating layer 60 A layer of material applicable to 2_b can be used. Also, insulating layer 606a and insulating layer 6 Even if insulating layers 606a and 606b are formed by laminating materials applicable to 06b, good.

[0179] The insulating layer 607 functions as a protective insulating layer that suppresses the intrusion of impurities into the transistor. To possess.

[0180] For example, the insulating layer 607 may be a material applicable to insulating layer 602_a and insulating layer 602_b. A layer of material can be used. In addition, by laminating a material applicable to the insulating layer 607, insulation Layer 607 may be formed by, for example, a silicon oxide layer, an aluminum oxide layer, An insulating layer 607 may be formed. For example, by using an aluminum oxide layer, a semiconductor The effect of suppressing the penetration of impurities into the body layer 603_b can be further enhanced, and the semiconductor layer 60 This can enhance the effect of suppressing oxygen detachment in 3_b.

[0181] Furthermore, the transistor of this embodiment is made of an oxide semiconductor having the function of a channel forming layer. A conductive layer is included on a portion of the conductive layer, and the oxide semiconductor layer is superimposed on the conductive layer via the insulating layer. The structure may include a conductive layer that functions as a source or drain. In this case, the insulating layer is a layer that protects the channel formation layer of the transistor (also called the channel protection layer). It has the function of (u). As an insulating layer that has the function of a channel protection layer, for example Alternatively, layers of material applicable to insulating layer 602_a and insulating layer 602_b can be used. Furthermore, channel retention is achieved by laminating materials applicable to insulating layer 602_a and insulating layer 602_b. An insulating layer that functions as a protective layer may be constructed.

[0182] Furthermore, a base layer is formed on the element-forming layer 600_a and the element-forming layer 600_b, A transistor may be formed on top of a base layer. In this case, the base layer may be, for example, an insulating layer. Layers of material applicable to 602_a and insulating layer 602_b can be used. Even if the underlayer is constructed by laminating materials applicable to the edge layer 602_a and the insulating layer 602_b Good. For example, the base layer can be formed by laminating an aluminum oxide layer and a silicon oxide layer. As a result, oxygen contained in the underlying layer enters via semiconductor layer 603_a and semiconductor layer 603_b. This can prevent detachment.

[0183] Furthermore, an example of the method for fabricating the transistor in this embodiment is shown in Figure 7(A). An example of a transistor fabrication method will be explained using Figure 11. Figure 11 is a reference to Figure 7 ( This is a schematic cross-sectional diagram illustrating the method for fabricating the transistor shown in A).

[0184] First, as shown in Figure 11(A), prepare the element formation layer 600_a, and then prepare the element formation layer 6 A semiconductor layer 603_a is formed on top of 00_a.

[0185] For example, an oxide semiconductor material applicable to the semiconductor layer 603_a using the sputtering method By forming a film (also called an oxide semiconductor film), a semiconductor layer 603_a is formed. This can be done. Furthermore, after forming the oxide semiconductor film, a portion of the oxide semiconductor film can be used. It may be done in a noble gas atmosphere, an oxygen atmosphere, or a mixed atmosphere of noble gas and oxygen. The oxide semiconductor film may be deposited under ambient air conditions.

[0186] Also, as a sputtering target, In2O3:Ga2O3:ZnO=1:1: By using an oxide target with a composition ratio of 1 [molar ratio], an oxide semiconductor film is formed. This can be done. Also, for example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] ], 4:2:3[mol ratio], 3:1:2[mol ratio], 2:1:3[mol ratio] Using an oxide target with a composition ratio of 3:1:4 [molar ratio], an oxide semiconductor film is produced. A thin film may be formed.

[0187] Furthermore, as a sputtering target, In:Sn:Zn=1:2:2 [atomic ratio] , 2:1:3 [atomic ratio], 1:1:1 [atomic ratio], or 20:45:35 [atomic ratio] An oxide semiconductor film may be formed using an oxide target with the composition ratio of ]. By using an oxide target with a specific composition ratio, a highly crystalline oxide semiconductor film can be formed. It can be made into a film. In particular, an oxide target with a composition ratio of In:Sn:Zn=2:1:3 By using this method, it is possible to form oxide semiconductor films with higher crystallinity.

[0188] Furthermore, as a sputtering target, In:Zn=50:1 or In:Zn=1: 2 (When converted to a molar ratio, In2O3:ZnO=25:1 or In2O3:ZnO=1: 4) Preferably In:Zn=20:1 or In:Zn=1:1 (when converted to mole ratio) In2O3:ZnO = 10:1 to In2O3:ZnO = 1:2), more preferably I n:Zn=15:1 or In:Zn=1.5:1 (converted to a mole ratio of In2O3:Z) Using an oxide target with a composition ratio of nO=15:2 or In2O3:ZnO=3:4 An In-Zn-based oxide film may be formed. For example, an In-Zn-based oxide semiconductor film The target used for film deposition has an atomic ratio of In:Zn:O=S:U:R, where R > 1.5. Let S + U. By increasing the amount of In, the field-effect mobility of the transistor (simply move It can improve (also called dynamism).

[0189] Furthermore, when using the sputtering method, for example, a noble gas atmosphere (typically argon) is used. Below, a semiconductor layer 603_a is formed in an oxygen atmosphere, or in a mixed atmosphere of a noble gas and oxygen. In this case, when forming the semiconductor layer 603_a under a mixed atmosphere of noble gas and oxygen, A higher amount of oxygen relative to the amount of sucrose is preferable.

[0190] Furthermore, when performing film deposition using the sputtering method, hydrogen, water, and hydroxyl groups may be present in the deposited film. To prevent the inclusion of impurities such as hydrides (also called hydrogen compounds), from the outside of the deposition chamber It is preferable to sufficiently suppress leaks and degassing from the inner wall of the film deposition chamber.

[0191] For example, before depositing a film using the sputtering method, preheat the sputtering apparatus. Preheating treatment may be performed in the room. By performing the above preheating treatment, the above impurities will be eliminated. It is possible to detach objects.

[0192] Furthermore, before depositing the film using the sputtering method, for example, argon, nitrogen, helium, In an oxygen atmosphere, voltage is applied to the substrate side using an RF power supply without applying voltage to the target side. Even when applying a plasma and performing a process to modify the surface to be formed (also called reverse sputtering), Good. By performing reverse sputtering, powdery material (particles) adhering to the surface to be formed can be removed. It can remove (also called waste).

[0193] Furthermore, when depositing a film using the sputtering method, an adsorption-type vacuum pump is used to deposit the film. It can remove residual moisture in the deposition chamber where the film is deposited. As an adsorption-type vacuum pump, For example, cryopumps, ion pumps, or titanium sublimation pumps can be used. This can be done. In addition, a turbomolecular pump equipped with a cold trap can be used to remove residual particles from the deposition chamber. It is also possible to remove the water content. By using the above vacuum pump, the above impurities can be removed. This can reduce exhaust backflow.

[0194] Furthermore, as the sputtering gas, for example, a high-purity gas from which the above-mentioned impurities have been removed can be used. This makes it possible to reduce the concentration of the above-mentioned impurities in the formed film. For example, spa It is preferable to use a gas with a dew point of -70°C or lower as the tarring gas.

[0195] Furthermore, in an example of the transistor fabrication method in this embodiment, a part of the film is etched When forming layers by chipping, for example, a photolithography process is used to apply a layer to a portion of the film. By forming a dystomask and etching the film using a resist mask, layers are formed. This can be achieved. In this case, the resist mask is removed after the layer is formed.

[0196] Furthermore, when forming an oxide semiconductor layer which is CAAC as the semiconductor layer 603_a, spa Using the tarring method, the temperature of the layer to be formed where the oxide semiconductor film is created is set to 100°C or higher. The oxide semiconductor film is formed at a temperature of 0°C or lower, preferably between 200°C and 350°C. Furthermore, by increasing the temperature of the layer to be formed and depositing an oxide semiconductor film, the device is manufactured. Improved field-effect mobility of the transistor and increased stability against gate bias stress. It is possible to do so.

[0197] Furthermore, it is preferable that the element-forming layer 600_a is flat. For example, The average surface roughness of the spawning layer 600_a is less than 1 nm, and moreover, less than 0.3 nm. Preferred. By improving the flatness of the element-forming layer 600_a, an amorphous state is achieved. It can improve mobility beyond that of oxide semiconductors. For example, chemical mechanical polishing (CM The element-forming layer 600_a is planarized by one or more of the P) treatment and plasma treatment. This can be done. In this case, the plasma treatment involves sputtering the surface with rare gas ions. This also includes processes that involve etching the surface using treatments or etching gases.

[0198] Next, as shown in Figure 11(B), a conductive layer 605a_a and A conductive layer 605b_a is formed.

[0199] For example, using a sputtering method, the conductive layers 605a_a and 605b_a are formed A film of an applicable material is formed as a first conductive film, and a portion of the first conductive film is etched. By doing so, conductive layers 605a_a and 605b_a can be formed.

[0200] Next, as shown in Figure 11(C), the insulating layer 602_ is placed in contact with the semiconductor layer 603_a. Form a

[0201] For example, under a noble gas (typically argon) atmosphere, under an oxygen atmosphere, or a mixture of noble gas and oxygen A film applicable to the insulating layer 602_a is deposited using the sputtering method under a mixed atmosphere. This allows for the formation of an insulating layer 602_a. By forming layer 602_a, it functions as the back channel of the transistor. This makes it possible to suppress the decrease in resistance in the semiconductor layer 603_a. The temperature of the element formation layer 600_a when forming 602_a is between room temperature and 300°C. It is preferable to do so.

[0202] Furthermore, before forming the insulating layer 602_a, a gas such as N2O, N2, or Ar is used. A lazma treatment is performed to remove adsorbed water and other substances adhering to the surface of the exposed semiconductor layer 603_a. This may be done. If plasma treatment is performed, the insulating layer 602 may be treated afterward without being exposed to the atmosphere. It is preferable to form _a.

[0203] Next, a conductive layer 601_a is formed on the insulating layer 602_a.

[0204] For example, a film of a material applicable to the conductive layer 601_a is formed using a sputtering method or the like. A conductive film is formed, and a part of the second conductive film is etched to form a conductive layer 601 _a can be formed.

[0205] Furthermore, in the example of the transistor fabrication method shown in Figure 7(A), for example, 600°C or more and 75°C Heat treatment is performed at a temperature below 0°C, or above 600°C but below the strain point of the substrate. For example, oxide After depositing the semiconductor film, a portion of the oxide semiconductor film is etched, and then the first conductive film is deposited. After that, a portion of the first conductive film is etched, then an insulating layer 602_a is formed, and then the second The above heat treatment is performed after forming the conductive film, or after etching a portion of the second conductive film. The above heat treatment removes impurities such as hydrogen, water, hydroxyl groups, or hydrides. It is excluded from the conductor layer 603_a.

[0206] The heat treatment apparatus used for the above heat treatment may include an electric furnace or a heat-generating device such as a resistance heating element. A device can be used that heats the object to be processed by heat conduction or thermal radiation from the body, for example G RTA (Gas Rapid Thermal Anneal) or LRTA (La Rapid Thermal Annealing (RTA) devices and other RTA (Rapid T A hermal annealing (LRTA) device can be used. For example, a halo Gen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high Radiation of light (electromagnetic waves) emitted from lamps such as sodium lamps or high-pressure mercury lamps It is a device that heats the object to be processed. Furthermore, the GRTA device uses high-temperature gas for heating. This is a device that performs processing. The high-temperature gas can be, for example, a noble gas, or the material to be treated by heat treatment. An inert gas that does not react with the substance (e.g., nitrogen) can be used.

[0207] Furthermore, after the above heat treatment, while maintaining the heating temperature or lowering it from the heating temperature During the heating process, high-purity oxygen gas and high-purity N2O gas are introduced into the same furnace in which the heat treatment was performed. Alternatively, an extremely dry air (an atmosphere with a dew point of -40°C or lower, preferably -60°C or lower) may be introduced. Good. In this case, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Furthermore, the purity of the oxygen gas or N2O gas introduced into the heating apparatus should be 6N or higher, preferably. Preferably, the impurity concentration in oxygen gas or N2O gas should be 7N or higher, i.e., 1 ppm or less. It is preferable that the concentration be 0.1 ppm or less. Due to the action of oxygen gas or N2O gas, the semiconductor Oxygen is supplied to the body layer 603_a, reducing defects caused by oxygen deficiency in the semiconductor layer 603_a. It can be reduced. Note that the above high-purity oxygen gas, high-purity N2O gas, or ultra-dry ethanol can be used. The introduction of A may be performed during the heat treatment described above.

[0208] Furthermore, in the example of the transistor fabrication method shown in Figure 7(A), the semiconductor layer 603_a is formed. After the conductive layer 605a_a and conductive layer 605b_a are formed, and after the insulating layer 602_a is formed, After layer 601_a is formed, or after the above heat treatment, oxygen doping treatment using oxygen plasma, etc. Alternatively, oxygen may be implanted into the oxide semiconductor film using a method that accelerates oxygen ions with an electric field. For example, oxygen doping treatment may be performed using a high-density plasma at 2.45 GHz. Alternatively, oxygen doping may be performed using ion implantation. This reduces variations in the electrical characteristics of the manufactured transistors. For example, by performing oxygen doping treatment, the insulating layer 602_a has more oxygen than the stoichiometric composition ratio. To make it into a good state.

[0209] By creating an excess of oxygen in the insulating layer in contact with the semiconductor layer 603_a, the semiconductor layer 603 Oxygen is more easily supplied to _a. Therefore, in the semiconductor layer 603_a, or the insulating layer 602_ Because oxygen vacancies at the interface between a and the semiconductor layer 603_a can be reduced, The carrier concentration in body layer 603_a can be further reduced. Furthermore, this is not limited to the above. Even if the manufacturing process results in an excess of oxygen in the semiconductor layer 603_a, The insulating layer in contact with layer 603_a suppresses the desorption of oxygen from the semiconductor layer 603_a. It is possible.

[0210] For example, when forming an insulating layer containing gallium oxide as the insulating layer 602_a, By supplying oxygen to the layer, the composition of gallium oxide is changed to Ga2O x It can be done.

[0211] Furthermore, when forming an insulating layer containing aluminum oxide as the insulating layer 602_a, By supplying oxygen to the margin, the composition of aluminum oxide is changed to Al2O x It can be done.

[0212] Furthermore, the insulating layer 602_a may be gallium aluminum oxide or aluminum gallium oxide. When forming an insulating layer containing aluminum, oxygen is supplied to the insulating layer, and gallium aluminum oxide is used. Alternatively, the composition of aluminum gallium oxide is Ga x Al 2-x O 3+α It can be done this way.

[0213] Through the above process, hydrogen, water, hydroxyl groups, or hydrides (water) are extracted from the semiconductor layer 603_a. This eliminates impurities such as elementary compounds and supplies oxygen to the semiconductor layer 603_a. This allows for high-purity processing of the oxide semiconductor layer.

[0214] Furthermore, separate from the above heat treatment, after forming the insulating layer 602_a, an inert gas atmosphere Heat treatment under or in an oxygen gas atmosphere (preferably 200°C to 600°C, for example 2 You may perform the procedure at temperatures between 50°C and 350°C.

[0215] The intentional heating temperature of the element formation layer 600_a shown above, or the time after deposition of the oxide semiconductor film. The heat treatment temperature is 150°C or higher, preferably 200°C or higher, more preferably 400°C or higher. The above is true. In the heat treatment after deposition of oxide semiconductor films, if the temperature is above 300°C, the film is contained within it. It is possible to release impurities such as hydrogen and remove these impurities (dehydration, dehydrogenation).

[0216] The above heat treatment can be carried out in an oxygen atmosphere, but as described above, dehydration and dehydrogenation occur. The process is done in two stages: first under a nitrogen atmosphere or reduced pressure, and then heat-treated in an oxygen atmosphere. It may also be done by heat treatment in an oxygen-containing atmosphere after dehydration and dehydrogenation, which can remove acid. It also becomes possible to add oxygen to the semiconductor, further enhancing the effect of the above heat treatment. Yes, it is possible. Furthermore, the above oxidation treatment can be performed with an insulating layer in contact with the oxide semiconductor layer. Heat treatment may be performed. For example, within the oxide semiconductor layer and at the boundary between layers stacked on the oxide semiconductor layer. Defects due to oxygen vacancies are easily generated on the surface, but the above heat treatment allows the oxide semiconductor to... By adding an excess of oxygen, the oxygen deficiency that is constantly generated can be compensated for by the excess oxygen. It can be compensated for. The excess oxygen mentioned above is mainly oxygen present between the lattice, and its oxygen concentration Degrees 1 x 10 16 / cm 3 The above 2 x 10 20 / cm 3 By doing the following, for example, crystal Even if this occurs, it does not cause distortion to the crystal, and oxygen is incorporated into the oxide semiconductor layer. It is possible.

[0217] Furthermore, transistors are fabricated by performing a heat treatment after the deposition of an oxide semiconductor film. This can improve the stability of the transistor against gate bias stress. It can also improve the field effect mobility.

[0218] Furthermore, as shown in Figure 11(E), the semiconductor layer 6 is formed on the side where the conductive layer 601_a is formed. By adding a dopant to 03_a, the region is self-aligned through the insulating layer 602_a. This forms region 604a_a and region 604b_a.

[0219] For example, adding a dopant using an ion doping device or ion implantation device. It is possible.

[0220] Although Figure 7(A) shows an example of a transistor fabrication method, it is not limited to this method. For example, in each component shown in Figure 7(B), the name is the same as the name of each component shown in Figure 7(A). If the same and at least part of the function is the same as each component shown in Figure 7(A), then Figure 7 The explanation of the example of transistor fabrication method shown in (A) can be appropriately adapted.

[0221] As explained using Figures 7 to 11, an example of a transistor in this embodiment is It consists of a conductive layer that functions as a gate and an insulating layer that functions as a gate insulating layer. , via an insulating layer that functions as a gate insulating layer, a conductive layer that functions as a gate An oxide semiconductor layer superimposed on it, forming a channel, and electrically connected to the oxide semiconductor layer A conductive layer having the function of either a source or a drain, and an oxide semiconductor layer electrically The configuration includes a conductive layer that is connected and functions as either a source or a drain. This allows us to construct a transistor.

[0222] Furthermore, in an example of a transistor in this embodiment, the carrier concentration of the oxide semiconductor layer to 1 × 10 14 / cm 3 Less than 1 × 10 12 / cm 3Less than, more preferably 1 x 10 11 / cm 3 It can be reduced to less than [amount].

[0223] To apply oxide semiconductors to transistors, the carrier density needs to be 1 × 10⁻⁶. 18 / cm 3 below It is preferable to do so. Oxide semiconductors containing In or Zn are made by adding Ga or Sn to oxide semiconductors. In addition to being included as one of the elements constituting the conductor, as mentioned above, the high performance of oxide semiconductor films Purification (removal of hydrogen, etc.) and heat treatment after film formation can increase carrier density to 1 × 10 18 / cm 3 The following can be done:

[0224] Furthermore, one or more of the heat treatments during film formation of oxide semiconductor films and the heat treatments after film formation are performed. By doing so, the threshold voltage of the transistor is shifted positively, resulting in a normally-off state. It is possible to set the off-current per 1 μm of channel width to 10 aA (1 × 10⁻¹⁰). -17 A ) and furthermore, 1aA(1×10 -18 A) Below, and furthermore, 10zA(1×10 -20 A) Below, and furthermore, 1zA(1×10 -21 A) Below, and furthermore, 100yA (1 × 10 - 22 A) It can be reduced to less than or equal to the following. The lower the transistor's off-current, the better. In this embodiment, the lower limit of the transistor's off-current is approximately 10 -30 A / μm It is estimated that...

[0225] A transistor including the oxide semiconductor layer of this embodiment, for example, in the above embodiment By using it in the transistors of memory circuits, the data retention time in memory circuits can be extended. It is possible.

[0226] Furthermore, an example of a transistor in this embodiment is another transistor (for example, element Transitions containing semiconductor layers that include semiconductors (such as silicon) of Group 14 in the periodic table It can be stacked with (T). Therefore, a transistor containing the above oxide semiconductor layer can be placed on the same substrate. The circuit area can be reduced while forming the zista and the other transistors mentioned above.

[0227] As explained in Embodiment 1, a transistor using single-crystal silicon (Figure 1(B) A transistor using an oxide semiconductor (Figure 1(B)) is placed on top of a transistor such as transistor 111. A structure that includes transistors (corresponding to transistor 107, etc.) is preferred. This structure allows for high-speed operation and data This allows for both data retention and reduction of circuit area.

[0228] Furthermore, the transistor using the above oxide semiconductor is either amorphous or crystalline. Even so, a relatively high field effect mobility can be obtained. This not only removes impurities through dehydration and dehydrogenation, but also shortens the interatomic distance through increased density. It is also presumed that this is to achieve a higher purity by removing impurities from oxide semiconductor films. Crystallization can also be achieved through this method. For example, in In-Sn-Zn oxide semiconductors, 31 cm 2 / Vsec greater than, preferably 39cm 2 / Vsec or more, more preferably 60cm 2 / It is also possible to obtain field-effect mobility exceeding Vsec. Furthermore, highly purified non-monocrystalline acids Ideally, a semiconductor can be 100 cm². 2Achieving field effect mobility exceeding / Vsec It is suggested that this will also be possible. Furthermore, in an example of a transistor in this embodiment, acid The lower the defect density of the semiconductor layer, the higher the field-effect mobility of the transistor. The reason for this is explained below.

[0229] This applies not only to field-effect transistors containing oxide semiconductor layers, but also to field-effect transistors that are actually measured. The field-effect mobility of a converter is lower than its actual field-effect mobility for various reasons. Factors that reduce field-effect mobility include defects within the semiconductor layer and the relationship between the semiconductor layer and the insulating layer. There are defects at the interface. For example, using the Levinson model, there are defects in the oxide semiconductor layer. We can theoretically derive the field-effect mobility of a transistor assuming no defects. ru.

[0230] Let μ0 be the intrinsic field-effect mobility of the semiconductor layer, and let μ be the measured field-effect mobility. Assuming that some kind of potential barrier (grain boundary, etc.) exists within the body layer, the measured electric field The effective mobility μ is expressed by the following equation (1).

[0231]

number

[0232] In equation (1) above, E is the height of the potential barrier, k is the Boltzmann constant, and T is the same as T. This is absolute temperature. Also, assuming that the potential barrier originates from a defect, Levin In the SON model, the height of the potential barrier, E, is expressed by the following equation (2). .

[0233]

number

[0234] In equation (2) above, e is the elementary charge and N is the average defect density per unit area in the channel. Degrees, ε is the dielectric constant of the semiconductor, n is the carrier surface density of the channel, C ox volume per unit area quantity, V g θ is the gate voltage, and t is the channel thickness. Note that this is a semiconductor layer with a thickness of 30 nm or less. In that case, the channel thickness can be considered the same as the semiconductor layer thickness. Furthermore, the linear region Drain current I in the region d This is expressed by the following equation (3).

[0235]

number

[0236] In equation (3) above, L is the channel length and W is the channel width, and here L = W = It is 10 μm. Also, V d This is the drain voltage. Furthermore, if we add V to both sides of the above equation... g Divide by, Furthermore, by taking the logarithm of both sides, equation (3) can be transformed into equation (4) below.

[0237]

number

[0238] In equation (4) above, the right-hand side is V g This is a function of . As can be seen from equation (4), the vertical axis is ln(I d / V g ), horizontal axis is 1 / V g The straight line on the graph obtained by plotting the measured values ​​as follows The defect density N can be determined from the slope of the curve. That is, the defect density N of a transistor. d ―V g Based on its characteristics, The density of depressions can be evaluated. For example, indium (In), gallium (Ga), and zinc. The ratio of (Zn) in an oxide semiconductor film is In:Ga:Zn = 1:1:1 [atomic ratio] The defect density N is 1 × 10⁻⁶ 12 / cm 2 It is to that extent.

[0239] Based on the defect density obtained by the above method, use equations (1) and (2) above. The field-effect mobility μ0 of the original semiconductor layer is found to be μ0 = 120 cm. 2 / Vs to na Typically, the field-effect mobility measured in defective In-Ga-Zn oxides is 40°C. m 2 The value is approximately / Vs, but there are no defects inside the semiconductor or at the interface between the semiconductor and the insulating film. The mobility μ0 of an oxide semiconductor is 120 cm⁻¹. 2 It can be expected that / Vs will be the result. The fewer defects there are, the higher the mobility of the oxide semiconductor, and furthermore, the higher the field-effect mobility of the transistor. This can be seen. For example, oxide semiconductor layers such as CAAC have a low defect density.

[0240] However, even if there are no defects inside the semiconductor layer, scattering occurs at the interface between the channel and the gate insulating layer. Therefore, the transport characteristics of the transistor are affected. That is, by x from the gate insulator interface. The mobility μ1 at a distance is expressed by the following equation (5).

[0241]

number

[0242] In equation (5) above, D is the electric field in the gate direction, and B and l are constants. B and l are real This can be determined from the measurement results, and in the above measurement results, B = 2.38 × 10 7 cm / s and l = 10 nm (depth of interfacial scattering). In equation (5), D increases (that is, As the gate voltage increases, the second term of equation (5) increases, so as D increases, the mobility increases. It can be seen that μ1 decreases.

[0243] Transistor movement using an ideal oxide semiconductor channel with no defects inside the semiconductor layer. The calculation results for the mobility μ2 are shown in Figure 12. Note that the above calculation was performed using a Synopsys device smear. We will use the simulation software, Sentaurus Device. In the body layer, the band gap is 2.8 electron volts and the electron affinity is 4.7 electron volts. The dielectric constant is set to 15 and the thickness to 15 nm. Furthermore, in the transistor, The work functions of the source, drain, and source are 5.5 electron volts and 4.6 electron volts, respectively. The voltage shall be 4.6 electron volts. In addition, the gate insulating layer shall have a thickness of 100 nm, and the dielectric constant shall be 100 nm. The ratio is set to 4.1. Furthermore, in the transistor, both the channel length and channel width are set. The mesh diameter is set to 10 μm, and the drain voltage is V d Let's assume it's 0.1V.

[0244] As shown in Figure 12, the gate voltage V G The field effect mobility when the voltage is around 1V is 100c m 2 Although it is high, above / Vs, the gate voltage V G As the value increases further, interfacial scattering becomes larger. Mobility decreases. Furthermore, in order to reduce interfacial scattering, the semiconductor layer surface must be leveled at the atomic level. It is desirable to make the layer flat (also known as Atomic Layer Flatness).

[0245] Furthermore, using oxide semiconductors with high field-effect mobility as described above, fine transistors The calculation results for the electrical characteristics of the device are shown below.

[0246] First, Figure 13 shows the cross-sectional structure of the transistor used in the calculation. The oxide semiconductor layer has N-type semiconductor regions 653a and 653b, and semiconductor region 653 It has c. The resistivity of semiconductor region 653a and semiconductor region 653b is 2 × 10 -3 Ωcm Let's assume that.

[0247] The transistor shown in Figure 13(A) is located on the base insulator 651 and the embedded insulator 652. It is provided there. The embedded insulator 652 is made of aluminum oxide and is attached to the base insulator 651. It is installed so as to be embedded.

[0248] Furthermore, the transistor shown in Figure 13(A) has a semiconductor region 653a and a semiconductor region 653 b, semiconductor region 653c, gate insulating layer 654, gate electrode 655, and side wall insulator 656a, side wall insulator 656b, insulating layer 657, source electrode 658a, drain Includes electrode 658b.

[0249] The semiconductor region 653c is sandwiched between the semiconductor region 653a and the semiconductor region 653b. It can be removed. Semiconductor region 653c is an intrinsic semiconductor region that forms a channel formation region.

[0250] The gate electrode 655 is provided on the gate insulating layer 654. The width is set to 33 nm.

[0251] The side wall insulators 656a and 656b are in contact with the side surface of the gate electrode 655. It is provided there. In the transistor shown in Figure 13(A), the semiconductor is located below the side wall insulator 656a. The region is included in the N-type semiconductor region 653a, and the semiconductor region below the side wall insulator 656b is, It is included in the N-type semiconductor region 653b. Note that the side wall insulators 656a and 656 Let each of the elements b have a width of 5 nm.

[0252] The insulating layer 657 is provided on top of the gate electrode 655. The insulating layer 657 is provided on top of the gate electrode 6 It has a function to prevent short circuits between 55 and other wiring.

[0253] The source electrode 658a is in contact with the semiconductor region 653a.

[0254] The drain electrode 658b is in contact with the semiconductor region 653b.

[0255] The channel width in the transistor shown in Figure 13(A) is set to 40 nm.

[0256] Furthermore, the transistor shown in Figure 13(B) is compared to the transistor shown in Figure 13(A). Therefore, the conductivity types of the semiconductor regions below the side wall insulators 656a and 656b are different. (Figure) In the transistor shown in 13(B), below the side wall insulators 656a and 656b The semiconductor region is included in the intrinsic semiconductor region 653c. That is, as shown in Figure 13(B) The transistor consists of the region where the semiconductor region 653a and the gate electrode 655 do not overlap, and the semiconductor region This includes the region where 653c and gate electrode 655 do not overlap. Each of these regions is offset. This is called a region, and its width is called the offset length (also called Loff). In Figure 13(B) The offset length is the same as the width of the side wall insulator 656a and the side wall insulator 656b, respectively. be.

[0257] The other parameters used in the calculation are as described above. Furthermore, the calculation involves... We used Sentaurus Device, a device calculation software from Nopsis.

[0258] Figure 14 shows the drain current (Id, solid line) of a transistor with the structure shown in Figure 13(A). And a figure showing the dependence of mobility (μ, dotted line) on gate voltage (Vg, potential difference between gate and source). The drain current Id is calculated assuming a drain voltage (potential difference between drain and source) of +1V. The field-effect mobility μ was calculated assuming a drain voltage of +0.1V.

[0259] Figure 14(A) shows the case of a transistor where the gate insulating layer 654 has a thickness of 15 nm. Figure 14(B) shows the field of a transistor where the thickness of the gate insulating layer 654 is 10 nm. Figure 14(C) shows a transistor with a gate insulating layer 654 thickness of 5 nm. This is a diagram of the case. As shown in Figures 14(A) to 14(C), the gate insulating layer 654 The thinner it becomes, the more significantly the drain current Id (off current), especially in the off state, decreases. The peak value of the field-effect mobility μ and the drain current Id (on-current) in the ON state are not particularly noticeable. There is no change. Also, at a gate voltage of around 1V, the drain current value is needed in memory circuits, etc. It exceeds the 10 μA threshold.

[0260] Figure 15 shows the structure shown in Figure 13(B), with an offset length (Loff) of 5 nm. This graph shows the dependence of the drain current Id (solid line) and mobility μ (dotted line) of the inverter on the gate voltage Vg. This is a diagram. Here, the drain voltage is set to +1V and the drain current Id is calculated, and the drain The field effect mobility μ is calculated with a voltage of +0.1V. Furthermore, Figure 15(A) shows the gauge This figure shows the case where the thickness of the gate insulating layer 654 is 15 nm, and Figure 15(B) shows the gate insulating layer This diagram shows the case where the thickness of 654 is 10 nm, and Figure 15(C) shows the gate insulating layer 654. This diagram shows the case when the thickness is 5 nm.

[0261] Furthermore, Figure 16 shows a transistor with the structure shown in Figure 13(B), with an offset length of Lof The gate voltage of the drain current Id (solid line) and mobility μ (dotted line) with f set to 15 nm. This shows the dependency. Here, the drain current Id is calculated assuming a drain voltage of +1V, and the dependency is Mobility μ is calculated assuming a drain voltage of +0.1V. Figure 16(A) shows the gate insulating layer 65 This diagram shows the case where the thickness of 4 is 15 nm, and Figure 16(B) shows the thickness of the gate insulating layer 654. This figure shows the case where the thickness is 10 nm, and Figure 16(C) shows the gate insulating layer 654 with a thickness of 5 nm. This is a diagram illustrating the case.

[0262] As can be seen from Figures 14 to 16, in all cases, the thinner the gate insulating layer 654 becomes, The transistor's off-current decreases significantly, while the peak value of mobility μ and the transistor's on-current decrease. There is no noticeable change in the current.

[0263] Note that the peak of the field-effect mobility μ is 80 cm in Figure 14. 2 It is approximately / Vs, as shown in Figure 1. 5 is 60cm 2 It is approximately / Vs, and in Figure 16, it is 40cm 2 Since it is approximately / Vs, The value decreases as the offset length (Loff) increases. Similarly, the transistor's off-current also decreases. There is a tendency for this to happen. On the other hand, the on-current of the transistor increases as the offset length (Loff) increases. It decreases as the transistor's off-current increases, but this decrease is much more gradual than the decrease in the transistor's off-current. Furthermore, all transistors have a gate voltage of around 1V, and the drain current is, for example, in a memory circuit. This exceeds the 10 μA required for applications such as [mention specific applications].

[0264] As shown above, in transistors containing oxide semiconductors, the field-effect mobility is increased. Therefore, the memory circuit in the above embodiment can be operated without any problems. .

[0265] Furthermore, as an example of the above transistor, the channel forming layer includes In, Sn, and Zn. An example of a transistor containing an oxide semiconductor layer will be described.

[0266] For example, an oxide semiconductor layer mainly composed of In, Sn, and Zn, and a 100 nm thick ge A transistor containing an insulating layer, with a channel length L of 3 μm and a channel width W of 10 μm. The characteristics are shown in Figures 17(A) to 17(C). Note that V d Let's assume it's 10V.

[0267] Figure 17(A) shows an example where the layer to be formed is not intentionally heated, and In is produced using the sputtering method. When an oxide semiconductor layer is formed by depositing an oxide semiconductor film mainly composed of Sn and Zn, This figure shows the characteristics of a transistor. In Figure 17(A), the field-effect mobility is 18 0.8cm 2 / Vsec. On the other hand, Figure 17(B) shows the substrate heated to 200°C and In, When an oxide semiconductor layer is formed by depositing an oxide semiconductor film mainly composed of Sn and Zn, This figure shows the characteristics of a transistor. In Figure 17(B), the field-effect mobility is 32.2c. m 2 / Vsec. Therefore, by intentionally heating, the field effect of the transistor It can be seen that mobility will improve.

[0268] Furthermore, Figure 17(C) shows an oxide semiconductor film mainly composed of In, Sn, and Zn, at 200°C. After forming an oxide semiconductor layer by sputtering at °C, the material is then heated at 650°C. This figure shows the characteristics of a transistor when the field effect is applied. In Figure 17(C), the field effect transfer... The range of motion was 34.5 cm. 2 / Vsec. Therefore, after forming the oxide semiconductor film, heating treatment It can be seen that the above-mentioned field effect mobility increases by performing this procedure.

[0269] Furthermore, oxygen ions are implanted into an oxide semiconductor layer mainly composed of In, Sn, and Zn, and then... The heat treatment removes impurities such as hydrogen, water, hydroxyl groups, or hydrides contained in the oxide semiconductor. The material is released, and the oxide semiconductor layer is crystallized simultaneously with or after the heat treatment. This may be done. A non-single-crystal oxide semiconductor layer with good crystallinity obtained by the above crystallization or recrystallization treatment. You can obtain this.

[0270] Furthermore, the element formation layer is formed without intentionally heating, and the main components are In, Sn, and Zn. A transistor including such an oxide semiconductor layer, for example as shown in Figure 17(A), has a threshold voltage There is a tendency for the pressure to shift to the negative. However, if the layer to be formed is intentionally heated and shaped... When the formed oxide semiconductor layer is used, for example, as shown in Figure 17(B), the threshold voltage is The transistor shifts towards the normally-off state. Therefore, the oxide semiconductor film is deposited. During heating and / or post-film deposition, one or more of these processes can cause the transistor to normally turn off. It becomes easier to develop this condition.

[0271] Furthermore, the threshold voltage of the transistor can also be controlled by changing the ratio of In, Sn, and Zn. It can be controlled. For example, the composition ratio of an oxide semiconductor film can be changed to In:Sn:Zn=2:1:3 This makes it easier to make the transistor a normally-off type.

[0272] Furthermore, for example, under conditions of 2 MV / cm, 150°C, and 1 hour of application, the gate via When a stress test (also called a BT test) is performed, the drift is preferably less than ±1.5V. The voltage will be less than ±1.0V. Therefore, heating during and after deposition of oxide semiconductor films. By performing one or more of these processes, the stability against gate bias and stress is increased. It can be seen that this is the case. Here, sample 1, which has not undergone heat treatment after oxide semiconductor film deposition, Figure 18 shows the results of the BT test on the transistor of sample 2 that underwent heat treatment at 650°C. This is shown in Figure 19. Note that both a positive BT test and a negative BT test were conducted.

[0273] For the PlusBT test, first the temperature of the element formation layer (substrate) is set to 25°C, V ds to 1 Let the voltage be 0V, and the voltage of the transistor be V gs -I ds The characteristics were measured. Next, the element formation layer (base The temperature of the plate is set to 150°C, V ds The voltage was set to 0.1V. Next, the voltage applied to the gate insulating layer was V gs 20V was applied and held for 1 hour. Next, V gs Next, the temperature of the element-forming layer (substrate) was set to 25°C, and V ds Let the voltage be 10V, and the voltage of the transistor gs -I ds Measurements were taken.

[0274] Furthermore, for the negative BT test, first the temperature of the element formation layer (substrate) is set to 25°C, V ds Let the voltage be 10V, and the voltage of the transistor gs -Ids The characteristics were measured. Next, the device formation layer (substrate) temperature was set to 150 °C, and V ds was set to 0.1 V. Next, a voltage of -20 V was applied to V so that the electric field strength applied to the gate insulating layer became -2 MV / cm, and it was held for 1 gs hour. Next, V was set to 0 V. Next, the temperature of the device formation layer (substrate) was set to 25 °C gs and V was set to 10 V, and the V ds -I gs of the transistor was measured. ds The results of the plus BT test for Sample 1 are shown in Fig. 18(A), and the results of the minus BT test for Sample 1 are shown in Fig. 18(B). Also, the results of the plus BT test for Sample 2 are shown in Fig. 19(A),

[0275] and the results of the minus BT test for Sample 2 are shown in Fig. 19(B). As shown in Fig. 18(A) and Fig. 18(B), the variations in the threshold voltage of the transistor due to the plus BT test and minus BT test for Sample 1 were 1.80 V and -0.42 V, respectively. Also, as shown in Fig. 19(A) and Fig. 19(B), the variations in the threshold voltage of the transistor due to the plus BT test and minus BT test for Sample 2 were 0.79 V and 0 .76 V, respectively. Therefore, it can be seen that for both Sample 1 and Sample 2, the variations in the threshold voltage of the transistor before and after the BT test were small and the reliability was high.

[0276] As shown in Fig. 18(A) and Fig. 18(B), the variations in the threshold voltage of the transistor due to the plus BT test and minus BT test for Sample 1 were 1.80 V and -0.42 V, respectively. Also, as shown in Fig. 19(A) and Fig. 19(B), the variations in the threshold voltage of the transistor due to the plus BT test and minus BT test for Sample 2 were 0.79 V and 0 .76 V, respectively. Therefore, it can be seen that for both Sample 1 and Sample 2, the variations in the threshold voltage of the transistor before and after the BT test were small and the reliability was high. Furthermore, using a target of metal oxide with a composition ratio of In:Sn:Zn = 1:1:1, an oxide semiconductor film formed by sputtering without intentionally heating the device formation layer showed a halo pattern in X-ray diffraction (XRD: X-Ray Diffraction). As shown in Fig. 18(A) and Fig. 18(B), the variations in the threshold voltage of the transistor due to the plus BT test and minus BT test for Sample 1 were 1.80 V and -0.42 V, respectively. Also, as shown in Fig. 19(A) and Fig. 19(B), the variations in the threshold voltage of the transistor due to the plus BT test and minus BT test for Sample 2 were 0.79 V and 0 .76 V, respectively. Therefore, it can be seen that for both Sample 1 and Sample 2, the variations in the threshold voltage of the transistor before and after the BT test were small and the reliability was high.

[0277] Furthermore, using a target of metal oxide with a composition ratio of In:Sn:Zn = 1:1:1, an oxide semiconductor film formed by sputtering without intentionally heating the device formation layer showed a halo pattern in X-ray diffraction (XRD: X-Ray Diffraction). film showed a halo pattern in X-ray diffraction (XRD: X-Ray Diffraction). It is measured. However, the above oxide semiconductor film can be crystallized by heat treatment. The heat treatment temperature at this time is arbitrary, but for example, by performing a heat treatment at 650°C... Clear diffraction peaks can be observed using X-ray diffraction.

[0278] The results of the XRD analysis of the In-Sn-Zn-O film are shown below. So, using the Bruker AXS D8 ADVANCE X-ray diffractometer, we performed an Out-o Measurements were taken using the f-plane method.

[0279] Sample A and Sample B were prepared as samples for XRD analysis. Sample A and Sample B are described below. The method for making B will be explained.

[0280] An In-Sn-Zn-O film with a thickness of 100 nm is deposited on a dehydrogenated quartz substrate. Ta.

[0281] The In-Sn-Zn-O film was produced using a sputtering apparatus in an oxygen atmosphere with a power of 10 The film was deposited at 0W (DC). The target material at this time was In:Sn:Zn=1:1 An In-Sn-Zn-O target with an atomic ratio of :1 was used. Note that the heating temperature during film deposition was The temperature was set to 200°C. The sample prepared by the above process is designated as Sample A.

[0282] Next, a sample prepared using the same method as sample A was subjected to heat treatment at a temperature of 650°C. Here, the treatment is performed in a nitrogen atmosphere for 1 hour, and then further in an oxygen atmosphere without lowering the temperature. A heat treatment was performed for one hour. The sample prepared by the above process is designated as Sample B.

[0283] The XRD spectra of sample A and sample B are shown in Figure 20. In sample A, there is a peak originating from the crystal. was not observed, but in Sample B, peaks derived from crystals were observed at around 2θ = 35° and 37° - 38°. Therefore, by performing one or more of heating during the formation of the oxide semiconductor film mainly composed of In, Sn, and Zn, and heat treatment after film formation, it can be seen that the crystallinity of the oxide semiconductor layer is improved.

[0284] By performing one or more of heating during the formation of the oxide semiconductor film and heat treatment after film formation, the off - current per 1 μm channel width of the fabricated transistor is, for example, as shown in Fig. 21, 1 aA (1×10 A) or less when the temperature of the device - forming layer (substrate) is 125 °C, 100 zA (1×10 -1 8 A) or less when the temperature is 85 °C, and 1 zA (1×10 -19 A) or less at room temperature (27 °C). In addition, the off - current per 1 μm channel width of the above transistor can preferably be 0.1 aA (1×10 -21 A) or less at 125 °C, 10 zA (1×10 A) or less at 85 °C, and 0.1 zA -19 (1×10 -20 A) or less at room temperature. (1×10 -22 A) or less.

[0285] Note that although the oxide semiconductor film mainly composed of In, Sn, and Zn can remove water in the film by heat treatment, since the water - release temperature is higher than that of the oxide semiconductor film mainly composed of In, Ga, and Zn, it is preferable to form a film that is initially free of impurities.

[0286] Furthermore, for the transistor of Sample B that was heat - treated at 650 °C after the formation of the oxide semiconductor film In this study, the relationship between the temperature of the element-forming layer (substrate) and its electrical characteristics was evaluated.

[0287] The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lo This is a transistor with v being 3 μm on each side (6 μm total) and dW being 0 μm. ds is 1 The voltage was set to 0V. Also, the temperature of the element-forming layer (substrate) was -40°C, -25°C, 25°C, and 75°C. The above evaluation was performed under six conditions: °C, 125°C, and 150°C. Note that Lov stands for Game. dW refers to the overlapping width between the electrode and the pair of electrodes, and dW is the width of the overlap between the oxide semiconductor film. This refers to the protrusion of a pair of electrodes.

[0288] Figure 22 shows I ds (Solid line) and field effect mobility (dotted line) V gs It exhibits dependency. Also, Figure 23(A) shows the relationship between the temperature of the element formation layer (substrate) and the threshold voltage, and Figure 23(B) shows the relationship between the element formation layer (substrate) This shows the relationship between the temperature of the element formation layer (substrate) and the field-effect mobility.

[0289] From Figures 22 and 23(A), the higher the temperature of the element-forming layer (substrate), the lower the threshold voltage. It can be seen that this will happen. The range is -40℃ to 150℃ and 1.09V to -0.23V. there were.

[0290] Furthermore, as can be seen from Figures 22 and 23(B), the higher the temperature of the element-forming layer (substrate), the greater the field effect. It can be seen that the mobility decreases. The range for this is 36 cm between -40°C and 150°C. 2 / V S ~ 32cm 2 The value was / Vs. Therefore, the variation in electrical characteristics was small within the above temperature range. It is clear that...

[0291] The above is a description of a transistor containing an oxide semiconductor layer containing In, Sn, and Zn.

[0292] In a transistor containing the above oxide semiconductor layer mainly composed of In, Sn, and Zn, While maintaining the current below 1 aA / μm, the field effect mobility is 30 cm 2 / Vsec or higher, good Mashiku is 40cm 2 / Vsec or more, more preferably 60cm 2 / Vsec or greater, L It can meet the on-current value required by SI. For example, L / W = 33nm / 40 In an nm transistor, when the gate voltage is 2.7V and the drain voltage is 1.0V... It can supply an on-current of 12 μA or more. Furthermore, it meets the requirements for transistor operation. Sufficient electrical characteristics can be ensured even within the temperature range. For example, a transistor containing a semiconductor layer containing Group 14 semiconductors (such as silicon) is used. Even if transistors containing the above oxide semiconductor layer are integrated into the circuit, the operating speed will be sacrificed. This allows us to provide circuits with new functions without any additional effort.

[0293] This embodiment can be implemented in appropriate combination with other embodiments.

[0294] (Embodiment 7) In this embodiment, an arithmetic processing unit such as a CPU will be described as an example of a semiconductor device. do.

[0295] Figure 24 shows an example of a processing unit.

[0296] The arithmetic processing unit in Figure 24 consists of a bus interface (also called IF) 801 and a control unit. 802 (also called CTL), cache memory (also called CACHE) 803, and instructions It has a decoder (also called an IDecoder) 805 and a processing circuit 806.

[0297] The bus interface 801 facilitates the exchange of signals with the outside world and the processing of each step within the arithmetic unit. It has functions such as exchanging signals with the road.

[0298] The control device 802 has the function of controlling the operation of each circuit in the arithmetic processing unit.

[0299] The cache memory 803 is controlled by the control unit 802 and is used in the arithmetic processing unit. It has a function to temporarily store the data at the time of creation. For example, primary cache and secondary cache. Multiple cache memories 803 may be provided in the arithmetic processing unit as a cache.

[0300] The instruction decoder 805 has the function of translating the received instruction signal. The signal is input to the control device 802, and the control device 802 processes a control signal corresponding to the command signal. Output to circuit 806.

[0301] The processing circuit 806 is controlled by the control device 802 and performs calculations according to the input command signal. It has the function of performing processing. The processing circuit 806 is the part that has an ALU, etc., as shown in Figures 1 to 6. A logic circuit section 101 and a memory circuit 103 can be provided.

[0302] Furthermore, registers or the like may be provided as memory in the arithmetic processing unit. In this case, the memory is controlled It is controlled by device 802. For example, multiple memories are provided in the arithmetic processing unit, and a certain memory One memory unit is used as memory for the processing circuit 806, and another memory unit is used as a register for the instruction decoder 805. That's fine.

[0303] Furthermore, the memory circuit 103 shown in Figures 1 to 6 is provided within the control device 802 and the instruction decoder 805. This is also acceptable. By doing so, the control device 802 and the instruction decoder 805 will have to perform the integrated circuit The data input to the transistor can be stored in the memory circuit, and the data can be retained. It enables high-speed operation and reduced power consumption.

[0304] This embodiment can be implemented in appropriate combination with other embodiments.

[0305] (Embodiment 8) In this embodiment, an example of an electronic device equipped with a processing unit in the above embodiment 7 is provided. I will explain.

[0306] An example of the electronic device in this embodiment is shown using Figures 25(A) to 25(D). explain.

[0307] The electronic device shown in Figure 25(A) is an example of a portable information terminal. The information terminal comprises a housing 1001a and a display unit 1002a provided on the housing 1001a. do.

[0308] Furthermore, the side 1003a of the housing 1001a has connection terminals for connecting to external devices, and One or more buttons may be provided for operating the portable information terminal shown in Figure 25(A). stomach.

[0309] The portable information terminal shown in Figure 25(A) has a CPU, memory, and inside the casing 1001a. An interface for sending and receiving signals between external devices and the CPU and memory, and the connection with external devices It includes an antenna for transmitting and receiving signals.

[0310] The portable information terminals shown in Figure 25(A) include, for example, telephones, e-readers, and personal computers. It has the function of a data and one or more gaming machines.

[0311] The electronic device shown in Figure 25(B) is an example of a foldable portable information terminal. The portable information terminal shown in the image comprises a housing 1001b and a display unit 10 provided on the housing 1001b. 02b, housing 1004, display unit 1005 provided in housing 1004, and housing 1001 It comprises a shaft portion 1006 that connects b and the housing 1004.

[0312] Furthermore, in the portable information terminal shown in Figure 25(B), the shaft portion 1006 connects to the housing 1001b or By moving the enclosure 1004, the enclosure 1001b can be superimposed onto the enclosure 1004. can.

[0313] Furthermore, external devices can be connected to the side 1003b of the enclosure 1001b or the side 1007 of the enclosure 1004. Connection terminals for connecting, and a button for operating the portable information terminal shown in Figure 25(B). One or more tongues may be provided.

[0314] Furthermore, the display unit 1002b and the display unit 1005 display different images or a continuous image. It may be displayed. Note that the display unit 1005 does not necessarily have to be provided. Alternatively, a keyboard, which is an input device, may be provided.

[0315] The portable information terminal shown in Figure 25(B) has a CP inside the housing 1001b or housing 1004. U, memory, and an interface for sending and receiving signals between the CPU and memory and external devices. It is equipped with the following. Furthermore, the portable information terminal shown in Figure 25(B) is capable of transmitting and receiving signals with the outside world. An antenna may be installed.

[0316] The portable information terminals shown in Figure 25(B) include, for example, telephones, e-readers, and personal computers. It has the function of a data and one or more gaming machines.

[0317] The electronic device shown in Figure 25(C) is an example of a stationary information terminal. The type of information terminal comprises a housing 1001c and a display unit 1002c provided on the housing 1001c, To be equipped with.

[0318] The display unit 1002c may also be provided on the deck portion 1008 of the housing 1001c. Cut.

[0319] Furthermore, the stationary information terminal shown in Figure 25(C) contains a CPU and memory inside the enclosure 1001c. It includes an interface for transmitting and receiving signals between external devices, the CPU, and memory. Furthermore, the stationary information terminal shown in Figure 25(C) has an antenna for transmitting and receiving signals to and from the outside. You may provide one.

[0320] Furthermore, the side 1003c of the housing 1001c in the stationary information terminal shown in Figure 25(C) The device may be equipped with one or more ticket output units for printing tickets, coin slots, and banknote slots. stomach.

[0321] The stationary information terminal shown in Figure 25(C) is used, for example, by an ATM or ticket machine for ordering tickets, etc. Information and communication terminals (also called multimedia stations) for the purpose of providing information and communication, or as gaming machines. To have the ability.

[0322] Figure 25(D) shows an example of a stationary information terminal. The stationary information terminal shown in Figure 25(D) is The device comprises a housing 1001d and a display unit 1002d provided on the housing 1001d. A support base may be provided to support the housing 1001d.

[0323] Furthermore, the side 1003d of the housing 1001d has connection terminals for connecting to external devices, and One or more buttons may be provided for operating the stationary information terminal shown in Figure 25(D). stomach.

[0324] Furthermore, the stationary information terminal shown in Figure 25(D) contains a CPU and memory inside the enclosure 1001d. It includes an interface for transmitting and receiving signals between external devices, the CPU, and memory. It is also acceptable to use the A type of stationary information terminal shown in Figure 25(D) to send and receive signals with the outside. A container may be provided.

[0325] The stationary information terminal shown in Figure 25(D) is, for example, a digital photo frame, a monitor, or It functions as a television device.

[0326] The arithmetic processing unit of the above embodiment is C of the electronic equipment shown in Figures 25(A) to 25(D). It is used as a pickup.

[0327] As explained with reference to Figure 25, an example of an electronic device in this embodiment is a CPU. The configuration includes the arithmetic processing unit described in the above embodiment.

[0328] Furthermore, in an example of the electronic device in this embodiment, the memory circuit and By using logic circuits, the power consumption of the arithmetic processing unit is suppressed while long-term data processing is performed. It is possible to retain data. Furthermore, the memory circuit and logic circuit in the above embodiment can be used. This allows for a reduction in the area required for the processing unit.

[0329] This embodiment can be implemented in appropriate combination with other embodiments. [Explanation of Symbols]

[0330] 101 Logic Circuit Section 101a Logic Circuit Section 101b Logic Circuit Section 103 Memory circuit 105 Logic Circuits 107 transistors 109 Capacitive elements 111 transistors 121 transistors 123 Transistors 131 Single-crystal silicon layer 133 Gate Insulation Layer 135 Grid gate 137 Oxide semiconductor layer 139 Gate Insulation Layer 141 Guard gate 143 Electrode 145 Electrode 147 Insulating layer 149 Electrode 201 Adder 203 AND circuit 205 Selection Circuit 207 transistors 209 transistors 211 Inverter 301 Arithmetic operation section 303 Logical Operations Unit 305 Shift Calculation Unit 307 Selection Circuit 309 Selection Circuit 311 Selection Circuit 401 Transistors 403 Inverter 405 transistors 407 Capacitive element 409 Inverter 501 Connection part 503 Wiring 505 memory 507 Selection Circuit 600 Device forming layer 601 Conductive layer 602 Insulating layer 603 Semiconductor layer 604a area 604b area 605a conductive layer 605b conductive layer 606a Insulating layer 606b Insulating layer 607 Insulating layer 651 Substrate insulation 652 Embedded Insulation 653a Semiconductor area 653b Semiconductor area 653c Semiconductor Domain 654 Gate Insulation Layer 655 Gate Shuttle 656a Sidewall insulation 656b Sidewall insulation 657 Insulating layer 658a Source electrode 658b Drain electrode 801 Bus Interface 802 Control Unit 803 Cache memory 805 Instruction Decoder 806 Processing Circuit 1001a Enclosure 1001b enclosure 1001c enclosure 1001d enclosure 1002a Display section 1002b Display section 1002c Display section 1002d Display section 1003a side 1003b Side 1003c side 1003d side 1004 cabinet 1005 Display section 1006 Shaft 1007 Side view 1008 Deck section

Claims

1. It comprises a first transistor, a second transistor above the first transistor, and a capacitive element above the first transistor, A semiconductor device in which one of the source and drain of the second transistor is electrically connected to the gate of the first transistor and the first electrode of the capacitive element, A first semiconductor layer having a channel formation region of the first transistor, A first conductive layer having a portion located above the first semiconductor layer and functioning as the gate electrode of the first transistor, A second semiconductor layer having a portion located above the first semiconductor layer and having a channel formation region for the second transistor, A second conductive layer having a portion located above the second semiconductor layer and functioning as the gate electrode of the second transistor, A third conductive layer having a portion in contact with the upper surface of the second semiconductor layer and a portion in contact with the upper surface of the first conductive layer, and having the function of one of the source electrode and drain electrode of the second transistor and the function of the first electrode of the capacitive element, A fourth conductive layer having a portion located above the third conductive layer and functioning as the second electrode of the capacitive element, The first semiconductor layer comprises silicon, The second semiconductor layer comprises an oxide semiconductor, The second conductive layer has the same material as the fourth conductive layer. The first transistor and the second transistor are arranged such that the channel length direction of the first transistor and the channel length direction of the second transistor are aligned along the first direction. Each of the first semiconductor layer and the second semiconductor layer has a portion extending in the first direction, The length of the first semiconductor layer in the first direction is greater than the length of the second semiconductor layer in the first direction, the length of the third conductive layer in the first direction, and the length of the fourth conductive layer in the first direction. The length of the first conductive layer in the first direction is greater than the length of the second conductive layer in the first direction. The length of the third conductive layer in the first direction is greater than the length of the first conductive layer in the first direction and the length of the fourth conductive layer in the first direction. A semiconductor device wherein the length of the fourth conductive layer in the first direction is greater than the length of the first conductive layer in the first direction.

2. It comprises a first transistor, a second transistor above the first transistor, and a capacitive element above the first transistor, A semiconductor device in which one of the source and drain of the second transistor is electrically connected to the gate of the first transistor and the first electrode of the capacitive element, A first semiconductor layer having a channel formation region of the first transistor, A first conductive layer having a portion located above the first semiconductor layer and functioning as the gate electrode of the first transistor, A second semiconductor layer having a portion located above the first semiconductor layer and having a channel formation region for the second transistor, A second conductive layer having a portion located above the second semiconductor layer and functioning as the gate electrode of the second transistor, A third conductive layer having a portion in contact with the upper surface of the second semiconductor layer and a portion in contact with the upper surface of the first conductive layer, and having the function of one of the source electrode and drain electrode of the second transistor and the function of the first electrode of the capacitive element, A fourth conductive layer having a portion located above the third conductive layer and functioning as the second electrode of the capacitive element, The first semiconductor layer comprises silicon, The second semiconductor layer comprises an oxide semiconductor, The second conductive layer has the same material as the fourth conductive layer. The first transistor and the second transistor are arranged such that the channel length direction of the first transistor and the channel length direction of the second transistor are aligned along the first direction. Each of the first semiconductor layer and the second semiconductor layer has a portion extending in the first direction, The length of the first semiconductor layer in the first direction is greater than the length of the second semiconductor layer in the first direction, the length of the third conductive layer in the first direction, and the length of the fourth conductive layer in the first direction. The length of the first conductive layer in the first direction is greater than the length of the second conductive layer in the first direction. The length of the third conductive layer in the first direction is greater than the length of the first conductive layer in the first direction and the length of the fourth conductive layer in the first direction. The length of the fourth conductive layer in the first direction is greater than the length of the first conductive layer in the first direction. A semiconductor device wherein each of the second conductive layer and the second semiconductor layer has a portion that overlaps with the first semiconductor layer.

3. In claim 1 or 2, The semiconductor device has an oxide semiconductor in which the second semiconductor layer contains In, Ga, and Zn.

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