Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device that enables improved voltage resistance. [Solution] The semiconductor device of the embodiment comprises an element region and a termination region surrounding the element region. The termination region includes a semiconductor layer having a first surface and a second surface facing the first surface, the semiconductor layer including a first semiconductor region of a first conductivity type and a plurality of fourth semiconductor regions of a second conductivity type provided between the first semiconductor region and the first surface and provided in a direction toward the termination region from the element region; a first insulating layer including a first portion and a second portion between which the fourth semiconductor region is provided in the above direction and the first portion; and a first conductive layer between which the first portion, the fourth semiconductor region, and the second portion are provided and the first semiconductor region. The first portion includes the first region and the second region, the first region is provided between the second region and the fourth semiconductor region in the above direction, and the depth of the first region is greater than the depth of the second region.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] A power semiconductor device is provided with an element region and a termination region surrounding the element region. The element region includes semiconductor elements such as Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The termination region has the function of mitigating the strength of the electric field applied to the pn junction at the end of the element region, thereby improving the breakdown voltage of the power semiconductor device. To improve the breakdown voltage of the power semiconductor device, it is desirable to improve the breakdown voltage of the termination region. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2008-78282 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device that enables improved voltage resistance. [Means for solving the problem]

[0005] The semiconductor device of the embodiment comprises an element region and a termination region surrounding the element region, the element region being a semiconductor layer having a first surface and a second surface facing the first surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of a first conductivity type provided between the second semiconductor region and the first surface, a gate electrode facing the second semiconductor region, a gate insulating film provided between the second semiconductor region and the gate electrode, a first electrode provided on the side of the first surface of the semiconductor layer and electrically connected to the third semiconductor region, and a second electrode provided on the side of the second surface of the semiconductor layer, the termination region being provided between the first semiconductor region and the first surface The semiconductor layer includes a plurality of fourth semiconductor regions of a second conductivity type provided in the direction from the element region toward the termination region; a first insulating layer including a first portion and a second portion between which the fourth semiconductor region is provided in the direction toward the first portion; a first conductive layer between which the first portion, the fourth semiconductor region, and the second portion are provided; and a second electrode, wherein the first portion includes a first region and a second region, and in the direction toward which the first region is provided between the second region and the fourth semiconductor region, and the depth of the first region is greater than the depth of the second region; the second portion includes a third region and a fourth region, and in the direction toward which the third region is provided between the fourth region and the fourth semiconductor region, and the depth of the third region is greater than the depth of the fourth region. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic top view of the semiconductor device according to the embodiment. [Figure 2] A schematic cross-sectional view of a part of the semiconductor device of the embodiment. [Figure 3] A schematic cross-sectional view of a part of the semiconductor device of the embodiment. [Figure 4] A schematic cross-sectional view of a part of the semiconductor device of the embodiment. [Figure 5] Schematic top view of the semiconductor device of the embodiment. [Figure 6] Schematic top view of the semiconductor device of the embodiment. [Figure 7] Schematic enlarged cross-sectional view of a part of the semiconductor device of the embodiment. [Figure 8] Schematic enlarged cross-sectional view of a part of the semiconductor device of the embodiment. [Figure 9] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 10] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 11] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 12] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 13] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 14] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 15] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 16] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 17] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 18] Schematic cross-sectional view showing the manufacturing method of the semiconductor device of the embodiment. [Figure 19] Schematic enlarged cross-sectional view of a part of the semiconductor device of the comparative example. [Figure 20] Schematic enlarged cross-sectional view of a part of the semiconductor device of the first modification of the embodiment. [Figure 21] Schematic enlarged cross-sectional view of a part of the semiconductor device of the second modification of the embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0008] In this specification, n + shape, n shape, n - When the notation "shape" is used, n + shape, n shape, n - This means that the concentration of n-type impurities decreases in the order of their shapes. Also, p + shape, p shape, p - If there is a notation for the shape, p + shape, p shape, p - This means that the concentration of p-type impurities decreases in the order of their shapes.

[0009] In this specification, the n-type impurity concentration refers to the effective n-type impurity concentration after compensation, not the actual n-type impurity concentration. Similarly, the p-type impurity concentration refers to the effective p-type impurity concentration after compensation, not the actual p-type impurity concentration. For example, if the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the n-type impurity concentration is calculated by subtracting the p-type impurity concentration from the actual n-type impurity concentration. The same applies to the p-type impurity concentration.

[0010] In this specification, the distribution and absolute value of impurity concentrations in semiconductor regions can be measured, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitudes of impurity concentrations in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentrations can be measured, for example, using spreading resistance analysis (SRA). SCM and SRA provide the relative magnitudes and absolute values ​​of carrier concentrations in the semiconductor regions. By assuming an activation rate for impurities, the relative magnitudes, distribution, and absolute values ​​of impurity concentrations between two semiconductor regions can be determined from the measurement results of SCM and SRA.

[0011] Unless otherwise specified in the specification, the impurity concentration in the semiconductor region shall be represented by the concentration in the central part of that semiconductor region.

[0012] For measuring the shape, thickness, and distance between components of the semiconductor device components described herein, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM) can be used. Furthermore, for qualitative and quantitative analysis of the chemical composition of the components of the semiconductor device components described herein, for example, Rutherford backscattering spectroscopy (RBS), secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or electron energy loss spectroscopy (EELS) can be used.

[0013] (Embodiment) The semiconductor device of the embodiment comprises an element region and a termination region surrounding the element region. The element region is a semiconductor layer having a first surface and a second surface facing the first surface, and includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of a first conductivity type provided between the second semiconductor region and the first surface; a gate electrode facing the second semiconductor region, a gate insulating film provided between the second semiconductor region and the gate electrode, a first electrode provided on the side of the first surface of the semiconductor layer and electrically connected to the third semiconductor region, and a second electrode provided on the side of the second surface of the semiconductor layer. The termination region includes a semiconductor layer comprising a first semiconductor region and a plurality of fourth semiconductor regions of a second conductivity type provided between the first semiconductor region and a first surface and arranged in a direction toward the termination region from the element region; a first insulating layer comprising a first portion and a second portion between which the fourth semiconductor region is provided in the above direction and the first portion; a first conductive layer between which the first portion, the fourth semiconductor region, and the second portion are provided and the first semiconductor region; and a second electrode. The first portion comprises a first region and a second region, and in the above direction, the first region is provided between the second region and the fourth semiconductor region, and the depth of the first region is greater than the depth of the second region; the second portion comprises a third region and a fourth region, and in the above direction, the third region is provided between the fourth region and the fourth semiconductor region, and the depth of the third region is greater than the depth of the fourth region.

[0014] The semiconductor device of this embodiment is an IGBT100. The IGBT100 has a trench-gate type IGBT, which has a gate electrode in a trench formed in a semiconductor layer. The following explanation will be given using the case where the first conductivity type is n-type and the second conductivity type is p-type as an example.

[0015] In this specification, "trench" means a groove provided in a semiconductor layer. A "trench" is part of a semiconductor layer. A "trench" is filled with, for example, a conductor or an insulator.

[0016] Figure 1 is a schematic top view of a semiconductor device according to an embodiment.

[0017] As shown in FIG. 1, the IGBT 100 has an element region 101 and a termination region 102. The termination region 102 surrounds the element region 101.

[0018] The element region 101 operates as an IGBT. The termination region 102 relaxes the intensity of the electric field applied to the pn junction at the end portion of the element region 101 when the IGBT 100 is in the off state. The termination region 102 has a function of improving the breakdown voltage of the IGBT 100.

[0019] FIG. 2 is a schematic cross-sectional view of a part of the semiconductor device of the embodiment. FIG. 2 is a schematic cross-sectional view of the element region 101. FIG. 2 is a cross-section taken along the line AA' of FIG. 1.

[0020] As shown in FIGS. 1 and 2, the element region 101 includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a gate electrode 16, a gate insulating film 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring layer 24.

[0021] In the semiconductor layer 10 of the element region 101, as shown in FIG. 2, a gate trench 41 (trench), a p + -shaped collector region 51 (fifth semiconductor region), an n - -shaped drift region 52 (first semiconductor region), a p-shaped base region 53 (second semiconductor region), and an n + -shaped emitter region 54 (third semiconductor region) are provided.

[0022] The semiconductor layer 10 has a first surface F1 and a second surface F2 facing the first surface F1. The "surfaces" of the first surface F1 and the second surface F2 are, for example, interfaces between a semiconductor layer and an insulating layer, or between a semiconductor layer and a conductive layer.

[0023] The semiconductor layer 10 is, for example, single-crystalline silicon. The film thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0024] In this specification, a direction parallel to the first surface F1 is referred to as the first direction. A direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. In this specification, "depth" is defined as the distance in the direction toward the second surface F2 with respect to the first surface F1.

[0025] The emitter electrode 12 is provided on the side of the first surface F1 of the semiconductor layer 10. At least a portion of the emitter electrode 12 is in contact with the first surface F1 of the semiconductor layer 10.

[0026] The emitter electrode 12 is, for example, a metal. The emitter electrode 12 includes, for example, aluminum.

[0027] The emitter electrode 12 is in contact with the emitter region 54. The emitter electrode 12 is electrically connected to the emitter region 54. The emitter electrode 12 is electrically connected to the base region 53.

[0028] The collector electrode 14 is provided on the side of the second surface F2 of the semiconductor layer 10. At least a portion of the collector electrode 14 is in contact with the second surface F2 of the semiconductor layer 10.

[0029] The collector electrode 14 is, for example, made of metal.

[0030] The collector electrode 14 is in contact with the collector region 51. The collector electrode 14 is electrically connected to the collector region 51.

[0031] The collector area 51 is p + This is a semiconductor region of a certain shape. The collector region 51 is in contact with the second surface F2. The collector region 51 is electrically connected to the collector electrode 14. The collector region 51 is in contact with the collector electrode 14. The collector region 51 is a source of holes when the IGBT is ON.

[0032] The drift region 52 is n - This is a semiconductor region of a certain shape. The drift region 52 is provided between the collector region 51 and the first surface F1.

[0033] The drift region 52 serves as the path for the on-current when the IGBT is on. The drift region 52 depletes when the IGBT is off, maintaining the IGBT's breakdown voltage.

[0034] The base region 53 is a p-type semiconductor region. The base region 53 is located between the drift region 52 and the first surface F1. The base region 53 sandwiches the drift region 52 between itself and the collector region 51.

[0035] In the base region 53, an n-type inversion layer is formed in the region opposite the gate electrode 16 to which the gate voltage Vg is applied when the IGBT is in the ON state. The base region 53 functions as the channel region of the transistor.

[0036] The emitter region 54 is n + This is a semiconductor region of a certain shape. The emitter region 54 is provided between the base region 53 and the first surface F1. The emitter region 54 is in contact with the gate insulating film 18.

[0037] The n-type impurity concentration in the emitter region 54 is higher than the n-type impurity concentration in the drift region 52.

[0038] The emitter region 54 is in contact with the emitter electrode 12. The emitter region 54 is electrically connected to the emitter electrode 12. The emitter region 54 is an electron source when the transistor is in the ON state.

[0039] The gate trenches 41 are provided on the side of the first surface F1 of the semiconductor layer 10. The gate trenches 41 are repeatedly provided in a first direction. The gate trenches 41 extend in a second direction that is parallel to the first surface F1 and perpendicular to the first direction.

[0040] The gate trench 41 is in contact with the drift region 52, the base region 53, and the emitter region 54. The gate trench 41 penetrates the base region 53 and reaches the drift region 52.

[0041] The depth of the gate trench 41 is, for example, between 3 μm and 7 μm.

[0042] The gate electrode 16 is located within the gate trench 41. The gate electrode 16 is electrically connected to the gate electrode pad 22 via the gate wiring layer 24.

[0043] The gate electrode 16 is a conductor. The gate electrode 16 is, for example, a semiconductor or a metal. The gate electrode 16 is, for example, amorphous silicon containing n-type or p-type impurities, or polycrystalline silicon containing n-type or p-type impurities.

[0044] The gate insulating film 18 is provided between the gate electrode 16 and the semiconductor layer 10. For example, the gate insulating film 18 is provided between the gate electrode 16 and the base region 53.

[0045] The gate insulating film 18 is an insulator. For example, the gate insulating film 18 is silicon oxide.

[0046] The interlayer insulating layer 20 is provided between the gate electrode 16 and the emitter electrode 12. The interlayer insulating layer 20 electrically isolates the gate electrode 16 and the emitter electrode 12.

[0047] The interlayer insulating layer 20 is an insulator. For example, the interlayer insulating layer 20 is silicon oxide.

[0048] The gate electrode pad 22 and the gate wiring layer 24 are provided on the interlayer insulating layer 20. As shown in Figure 1, the gate wiring layer 24 is connected to the gate electrode pad 22.

[0049] The gate electrode pad 22 and gate wiring layer 24 are made of, for example, metal. The gate electrode pad 22 and gate wiring layer 24 include, for example, aluminum.

[0050] The gate electrode pad 22 and gate wiring layer 24 are formed, for example, from the same material as the emitter electrode 12. The gate electrode pad 22 and gate wiring layer 24 are formed, for example, using the same process steps as the emitter electrode 12.

[0051] Figures 3 and 4 are schematic cross-sectional views of a part of the semiconductor device of the embodiment. Figure 3 is a schematic cross-sectional view of the terminal region 102. Figure 3 is the BB' section of Figure 1. Figure 4 is a schematic cross-sectional view of the terminal region 102. Figure 4 is the CC' section of Figure 1.

[0052] As shown in Figures 1, 3, and 4, the termination region 102 comprises a semiconductor layer 10, a collector electrode 14 (second electrode), an interlayer insulating layer 20, a field insulating layer 30 (first insulating layer), a field plate layer 32 (first conductive layer), a field plate insulating film 34 (first insulating film), and a guard ring metal layer 36 (second conductive layer).

[0053] Within the semiconductor layer 10 of the termination region 102, there are field trenches 42, p + The collector region 51 (fifth semiconductor region) of the shape, n - Shape drift region 52 (first semiconductor region), p + A guard ring region 55 (fourth semiconductor region) is provided.

[0054] Guard ring area 55 is p + This is a semiconductor region of a certain shape. The guard ring region 55 is provided between the drift region 52 and the first surface F1.

[0055] Figure 5 is a schematic top view of the semiconductor device of the embodiment. Figure 5 is a diagram showing the layout pattern of the guard ring region 55.

[0056] As shown in Figure 5, the guard ring region 55 surrounds the element region 101. The guard ring region 55 is annular.

[0057] Multiple guard ring regions 55 are repeatedly provided in the direction from the element region 101 toward the termination region 102. In Figure 3, the first direction is an example of the direction from the element region 101 toward the termination region 102. In Figure 4, the second direction is an example of the direction from the element region 101 toward the termination region 102. Note that the direction from the element region 101 toward the termination region 102 also includes the direction from the termination region 102 toward the element region 101.

[0058] Figures 1, 3, 4, and 5 illustrate the case where there are three guard ring regions 55, but there may be two or four or more guard ring regions 55.

[0059] The multiple guard ring regions 55 have the function of mitigating the intensity of the electric field applied to the pn junction at the end of the element region 101, thereby improving the breakdown voltage of the IGBT 100.

[0060] The p-type impurity concentration in the guard ring region 55 is, for example, higher than the p-type impurity concentration in the base region 53.

[0061] The depth of the guard ring area 55 is greater than the depth of the field trench 42. The depth of the guard ring area 55 is greater than, for example, the depth of the gate trench 41. The depth of the guard ring area 55 is greater than, for example, the depth of the base area 53.

[0062] The guard ring region 55 is electrically floating. Being electrically floating means that it is not electrically connected to any voltage source or ground.

[0063] The field trenches 42 are provided on the side of the first surface F1 of the semiconductor layer 10. The field trenches 42 are repeatedly provided in the direction from the device region 101 toward the termination region 102.

[0064] The depth of the field trench 42 is, for example, between 0.5 μm and 3 μm.

[0065] The field insulating layer 30 is provided inside the field trench 42. The field insulating layer 30 fills the field trench 42.

[0066] The field insulating layer 30 is provided between two adjacent guard ring regions 55 in the direction from the element region 101 to the termination region 102. The guard ring regions 55 are provided between the field insulating layers 30 in the direction from the element region 101 to the termination region 102.

[0067] The field insulating layer 30 has the function of electrically isolating the field plate layer 32 from the drift region 52, for example.

[0068] The field insulating layer 30 is an insulator. The field insulating layer 30 is, for example, an oxide. The field insulating layer 30 is, for example, silicon oxide.

[0069] The field plate layer 32 is provided on top of the field insulating layer 30 and the guard ring region 55. The field insulating layer 30 and the guard ring region 55 are provided between the field plate layer 32 and the drift region 52.

[0070] Figure 6 is a schematic top view of the semiconductor device according to the embodiment. Figure 6 shows the layout pattern of the field plate layer 32.

[0071] As shown in Figure 6, the field plate layer 32 surrounds the element region 101. The field plate layer 32 is annular in shape.

[0072] Multiple field plate layers 32 are repeatedly provided in the direction from the element region 101 toward the termination region 102. Adjacent field plate layers 32 in the direction from the element region 101 toward the termination region 102 are separated.

[0073] Figures 1, 3, 4, and 6 illustrate the case where there are three field plate layers 32, but there may be two, four or more, or other cases.

[0074] The multiple field plate layers 32 have the function of mitigating the intensity of the electric field applied to the pn junction at the end of the element region 101 and improving the breakdown voltage of the IGBT 100.

[0075] The field plate layer 32 is, for example, a semiconductor or a metal. The gate electrode 16 is, for example, amorphous silicon containing n-type or p-type impurities, or polycrystalline silicon containing n-type or p-type impurities.

[0076] The field plate layer 32 is formed, for example, from the same material as the gate electrode 16. The field plate layer 32 is formed, for example, using the same process steps as the gate electrode 16.

[0077] The field plate layer 32 is electrically connected to the guard ring region 55. The field plate layer 32 is electrically floating.

[0078] The field plate insulating film 34 is provided between the field plate layer 32 and the guard ring region 55. The field plate insulating film 34 is an insulator. For example, the field plate insulating film 34 is silicon oxide.

[0079] The field plate insulating film 34 is formed, for example, from the same material as the gate insulating film 18. The field plate insulating film 34 is formed, for example, using the same process steps as the gate insulating film 18.

[0080] It is also possible to omit the field plate insulating film 34 and have a structure in which the field plate layer 32 is in contact with the guard ring region 55.

[0081] The guard ring metal layer 36 is provided on the guard ring region 55 and the field plate layer 32. The field plate layer 32 is provided between the guard ring metal layer 36 and the guard ring region 55.

[0082] As shown in Figure 1, the guard ring metal layer 36 surrounds the element region 101. The guard ring metal layer 36 is annular in shape.

[0083] Multiple guard ring metal layers 36 are repeatedly provided in the direction from the element region 101 toward the termination region 102. Adjacent guard ring metal layers 36 in the direction from the element region 101 toward the termination region 102 are separated.

[0084] Figures 1, 3, and 4 illustrate the case where there are three guard ring metal layers 36, but there may be two, four or more guard ring metal layers 36, or any other combination of layers.

[0085] The multiple guard ring metal layers 36 have the function of shielding from external electric fields, stabilizing the strength of the electric field applied to the pn junction at the end of the element region 101, and suppressing fluctuations in the breakdown voltage of the IGBT 100.

[0086] The guard ring metal layer 36 is a conductor. The guard ring metal layer 36 is, for example, a metal. The guard ring metal layer 36 includes, for example, aluminum.

[0087] The guard ring metal layer 36 is formed, for example, from the same material as the emitter electrode 12. The guard ring metal layer 36 is formed, for example, using the same process steps as the emitter electrode 12.

[0088] The guard ring metal layer 36 is electrically connected to the field plate layer 32 and the guard ring region 55. The guard ring metal layer 36 is electrically floating.

[0089] The interlayer insulating layer 20 is provided between the field plate layer 32 and the guard ring metal layer 36.

[0090] Figure 7 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the embodiment. Figure 7 is an enlarged schematic cross-sectional view of the terminal region 102. Figure 7 is an enlarged schematic cross-sectional view of the portion enclosed by the dotted line in Figure 3.

[0091] The field insulating layer 30 includes a first portion 30a and a second portion 30b. In the direction from the element region 101 toward the termination region 102, the guard ring region 55 is provided between the first portion 30a and the second portion 30b. In Figure 7, the direction from the element region 101 toward the termination region 102 is the first direction.

[0092] The first portion 30a includes a first deep region 30ax (the first region) and a first shallow region 30ay (the second region). The second portion 30b includes a second deep region 30bx (the third region) and a second shallow region 30by (the fourth region).

[0093] In the direction from element region 101 toward termination region 102, the first deep region 30ax is provided between the first shallow region 30ay and the guard ring region 55. In the direction from element region 101 toward termination region 102, the second deep region 30bx is provided between the second shallow region 30by and the guard ring region 55.

[0094] The depth of the first deep region 30ax (d1 in Figure 7) is greater than the depth of the first shallow region 30ay (d2 in Figure 7). The depth d1 of the first deep region 30ax is, for example, between 1.1 and 1.5 times the depth d2 of the first shallow region 30ay.

[0095] The depth of the field trench 42 in contact with the first deep region 30ax is greater than the depth of the field trench 42 in contact with the first shallow region 30ay.

[0096] The depth of the second deep region 30bx (d3 in Figure 7) is greater than the depth of the second shallow region 30by (d4 in Figure 7). The depth d3 of the second deep region 30bx is, for example, between 1.1 and 1.5 times the depth d4 of the second shallow region 30by.

[0097] The depth of the field trench 42 in contact with the second deep region 30bx is greater than the depth of the field trench 42 in contact with the second shallow region 30by.

[0098] The guard ring region 55 is in contact with the first portion 30a and the second portion 30b in the direction from the element region 101 toward the termination region 102. The guard ring region 55 is in contact with the first deep region 30ax and the second deep region 30bx in the direction from the element region 101 toward the termination region 102.

[0099] The thickness of the field insulating layer 30 in the direction perpendicular to the first surface F1 in the first shallow region 30ay (t1 in Figure 7) is, for example, less than or equal to the depth d2 of the first shallow region 30ay. The thickness of the field insulating layer 30 in the direction perpendicular to the first surface F1 in the second shallow region 30by (t2 in Figure 7) is, for example, less than or equal to the depth d4 of the second shallow region 30by.

[0100] In a direction perpendicular to the first surface F1, a first portion 30a, a guard ring region 55, and a second portion 30b are provided between the field plate layer 32 and the drift region 52.

[0101] In a direction perpendicular to the first surface F1, a first portion 30a and a second portion 30b are provided between the field plate layer 32 and the guard ring region 55. In a direction perpendicular to the first surface F1, a first deep region 30ax and a second deep region 30bx are provided between the field plate layer 32 and the guard ring region 55.

[0102] The width of the guard ring region 55 in the direction from the element region 101 to the termination region 102 (w1 in Figure 7) is, for example, greater than the distance between the first portion 30a and the second portion 30b of the field insulating layer 30 in the direction from the element region 101 to the termination region 102 (L1 in Figure 7). The width w1 of the guard ring region 55 is, for example, 1.1 times or more and 2 times or less the distance L1 between the first portion 30a and the second portion 30b.

[0103] The guard ring region 55 wraps around the bottom of the first portion 30a and the bottom of the second portion 30b.

[0104] The width of the field plate layer 32 in the direction from the element region 101 to the termination region 102 (w2 in Figure 7) is, for example, greater than the width of the guard ring region 55 in the direction from the element region 101 to the termination region 102 (w1 in Figure 7). The width w2 of the field plate layer 32 is, for example, 1.1 times or more and 20 times or less the width w1 of the guard ring region 55.

[0105] The field plate layer 32 includes a first wedge portion 32a (part of the first conductive layer) and a second wedge portion 32b (another part of the first conductive layer). The first wedge portion 32a and the second wedge portion 32b are portions of the field plate layer 32 that protrude toward the semiconductor layer 10. The first wedge portion 32a is in contact with, for example, the first deep region 30ax of the field insulating layer 30. The second wedge portion 32b is in contact with, for example, the second deep region 30bx of the field insulating layer 30.

[0106] In the direction from the element region 101 toward the termination region 102, the guard ring region 55 is provided between the first wedge portion 32a and the second wedge portion 32b.

[0107] The width of the guard ring metal layer 36 in the direction from the element region 101 to the termination region 102 (w3 in Figure 7) is, for example, greater than the width of the guard ring region 55 in the direction from the element region 101 to the termination region 102 (w1 in Figure 7). The width w3 of the guard ring metal layer 36 is, for example, 1.1 times or more and 20 times or less the width w1 of the guard ring region 55.

[0108] Figure 8 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the embodiment. Figure 8 is an enlarged schematic cross-sectional view of the terminal region 102. Figure 8 is a cross-sectional view of Figure 7 in the depth direction of the plane of paper. That is, Figure 8 is a cross-sectional view of the portion located in the second direction of Figure 7.

[0109] As shown in Figure 8, the guard ring metal layer 36 is in contact with the guard ring region 55. The guard ring metal layer 36 penetrates the interlayer insulating layer 20, the field plate layer 32, and the field plate insulating film 34. By contacting the guard ring region 55, the guard ring metal layer 36 is electrically connected to the guard ring region 55. The field plate layer 32 is electrically connected to the guard ring region 55, for example, via the guard ring metal layer 36.

[0110] Next, an example of a method for manufacturing the semiconductor device of the embodiment will be described.

[0111] The semiconductor device manufacturing method of the embodiment involves ion implanting a second conductivity type impurity into a first conductivity type semiconductor layer to form an annular semiconductor region of the second conductivity type on the surface of the semiconductor layer, forming a first trench on the inside of the semiconductor region on the surface of the semiconductor layer, with the depth on the semiconductor region side being deeper than the other parts, and forming a second trench on the outside of the semiconductor region on the surface of the semiconductor layer, with the depth on the semiconductor region side being deeper than the depth of the other parts, filling the first and second trenches with an insulating film, performing a heat treatment to activate the impurities in the semiconductor region, and forming a conductive film on the insulating film and the semiconductor region. The first and second trenches are in contact with the semiconductor region, and the distance between the first trench and the second trench in the direction from the inside to the outside of the semiconductor region is smaller than the width of the semiconductor region in the above direction.

[0112] Figures 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are schematic cross-sectional views showing the manufacturing method of the semiconductor device of the embodiment. Figures 9 to 18 correspond to Figure 7.

[0113] First, n- A first mask material 61 is formed on the surface of a silicon layer 60 (semiconductor layer). The first mask material 61 is, for example, a photoresist formed using a photolithography method. The first mask material 61 has an annular opening on the surface of the silicon layer 60. A portion of the silicon layer 60 eventually becomes a drift region 52.

[0114] Next, the first mask material 61 is used as a mask, and boron (B) is ion-implanted into the silicon layer 60, p + A silicon region 62 (semiconductor region) is formed (Figure 9). The silicon region 62 is ring-shaped on the surface of the silicon layer 60. The silicon region 62 eventually becomes a guard ring region 55.

[0115] Next, after removing the first mask material 61, a second mask material 63 is formed on the surface of the silicon layer 60 (Figure 10). The second mask material 63 is, for example, a photoresist formed using photolithography. The second mask material 63 has openings on the inside and outside of the silicon region 62. That is, the second mask material 63 has openings on the left and right sides of the silicon region 62 in Figure 10.

[0116] Next, using the second mask material 63 as a mask, an inner trench 64a (first trench) and an outer trench 64b (second trench) are formed in the silicon layer 60 (Figure 11). The inner trench 64a is formed inside the silicon region 62. The outer trench 64b is formed outside the silicon region 62. The inner trench 64a and the outer trench 64b ultimately become the field trench 42.

[0117] In the inner trench 64a, the portion on the side of the silicon region 62 (E1 in Figure 11) is deeper than the other portions. Similarly, in the outer trench 64b, the portion on the side of the silicon region 62 (E2 in Figure 11) is deeper than the other portions.

[0118] The inner trench 64a and the outer trench 64b are formed, for example, using an isotropic dry etching method. The inner trench 64a and the outer trench 64b are formed, for example, using a chemical dry etching (CDE) method.

[0119] The silicon region 62 contains crystal defects generated during boron (B) ion implantation. For example, when etching using an isotropic dry etching method, the etching rate in the areas containing crystal defects will be faster than in other areas.

[0120] In this case, as shown in Figure 11, the depth of the portion of the inner trench 64a on the silicon region 62 side (E1 in Figure 11) becomes deeper than the depth of the other portions of the inner trench 64a. The depth of the inner trench 64a formed in the silicon region 62 becomes deeper than the depth of the inner trench 64a formed in the other silicon layers 60.

[0121] Furthermore, as shown in Figure 11, the depth of the portion of the outer trench 64b on the silicon region 62 side (E2 in Figure 11) is greater than the depth of the other portions of the outer trench 64b. The depth of the outer trench 64b formed in the silicon region 62 is greater than the depth of the outer trench 64b formed in the other silicon layers 60.

[0122] The inner trench 64a and the outer trench 64b are in contact with the silicon region 62. The distance between the inner trench 64a and the outer trench 64b in the direction from the inside to the outside of the silicon region 62 (L in Figure 11) is smaller than the width of the silicon region 62 in the direction from the inside to the outside of the silicon region 62 (W in Figure 11).

[0123] Next, the second mask material 63 is removed (Figure 12).

[0124] Next, the inner trench 64a and the outer trench 64b are filled with a first silicon oxide film 65 (insulating film) (Figure 13). The first silicon oxide film 65 is formed, for example, using the Plasma-Enhanced Chemical Vapor Deposition (PECVD) method. A portion of the first silicon oxide film 65 ultimately becomes the field insulating layer 30.

[0125] Next, a heat treatment is performed to activate the boron (B) in the silicon region 62. The heat treatment is carried out, for example, in an inert gas atmosphere at a temperature between 1000°C and 1100°C. By activating the boron (B) in the silicon region 62, crystal defects in the silicon region 62 are restored.

[0126] Next, a third mask material 66 is formed on the first silicon oxide film 65 (Figure 14). The third mask material 66 is, for example, a photoresist formed using photolithography. The third mask material 66 has an annular opening on the surface of the first silicon oxide film 65.

[0127] Next, using the third mask material 66 as a mask, a portion of the first silicon oxide film 65 is removed to expose the silicon region 62 (Figure 15). The first silicon oxide film 65 is removed, for example, using a wet etching method. When the first silicon oxide film 65 is removed, a portion of the side surface of the silicon region 62 is exposed.

[0128] Subsequently, the third mask material 66 is removed, and the element region 101 is formed in a region of the silicon layer 60 not shown. That is, in the region of the silicon layer 60 not shown, finally, a p-shaped base region 53, n + A structure is formed consisting of a shape emitter region 54, a gate trench 41, a gate insulating film 18, and a gate electrode 16.

[0129] Next, a second silicon oxide film 67 is formed on the surface of the silicon region 62. The second silicon oxide film 67 is formed, for example, by thermal oxidation. The second silicon oxide film 67 may be formed, for example, at the same time as the formation of the gate insulating film 18 of the device region 101.

[0130] Next, a polycrystalline silicon film 68 (conductive film) containing phosphorus (P) as an impurity is formed on the second silicon oxide film 67 (Figure 16). The polycrystalline silicon film 68 is formed, for example, by film deposition using the Chemical Vapor Deposition (CVD) method and patterning using the dry etching method. The polycrystalline silicon film 68 ultimately becomes the field plate layer 32. The polycrystalline silicon film 68 may be formed, for example, at the same time as the formation of the gate electrode 16 of the device region 101.

[0131] Next, a third silicon oxide film 69 having openings 69a is formed on the surface of the polycrystalline silicon film 68 (Figure 17). The third silicon oxide film 69 is formed, for example, by film deposition by CVD and opening of the openings 69a by dry etching. A portion of the third silicon oxide film 69 ultimately becomes the interlayer insulating layer 20.

[0132] Next, an aluminum film 70 is formed on the third silicon oxide film 69 (Figure 18). The aluminum film 70 is formed, for example, by film deposition using a sputtering method and patterning using a dry etching method. A portion of the aluminum film 70 ultimately becomes the guard ring metal layer 36. Another portion of the aluminum film 70 becomes, for example, the emitter electrode 12, the gate electrode pad 22, and the gate wiring layer 24.

[0133] Subsequently, using known process steps, a silicon region that will ultimately become the collector region 51 and a metal film that will ultimately become the collector electrode 14 are formed on the back side of the silicon layer 60.

[0134] The IGBT100 of the embodiment is formed by the manufacturing method described above.

[0135] Next, the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the embodiment will be described.

[0136] Figure 19 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the comparative example. Figure 19 corresponds to Figure 7 of the embodiment.

[0137] The comparative semiconductor device differs from the embodiment in that the depth of the field insulating layer 30 is constant. Furthermore, the comparative semiconductor device differs from the embodiment in that, in the direction perpendicular to the first surface, there are no first and second portions between the first conductive layer and the fourth semiconductor region. Additionally, the comparative semiconductor device differs from the embodiment in that the width of the fourth semiconductor region in the direction from the element region to the termination region is equal to the distance between the first and second portions in that direction.

[0138] The comparative IGBT, like the IGBT 100 of the embodiment, has a field insulating layer 30 that includes a first portion 30a and a second portion 30b. In the comparative IGBT, the depth of the first portion 30a (d5 in Figure 19) and the depth of the second portion 30b (d6 in Figure 19) are constant. In the comparative IGBT, the depth of the field trench 42 in contact with the first portion 30a and the depth of the field trench 42 in contact with the second portion 30b are constant.

[0139] In the comparative example IGBT, the thickness of the field insulating layer 30 in the portion of the first part 30a that contacts the guard ring region 55 (ty1 in Figure 19) is thinner than the thickness of the field insulating layer 30 in the other portion of the first part 30a (t1 in Figure 19). Also, the thickness of the field insulating layer 30 in the portion of the second part 30b that contacts the guard ring region 55 (ty2 in Figure 19) is thinner than the thickness of the field insulating layer 30 in the other portion of the second part 30b (t2 in Figure 19).

[0140] In the comparative example IGBT, the first portion 30a and the second portion 30b are not provided between the field plate layer 32 and the guard ring region 55 in a direction perpendicular to the first surface F1. Also, in the comparative example IGBT, the width of the guard ring region 55 in the direction from the element region 101 to the termination region 102 (w4 in Figure 19) is equal to the distance between the first portion 30a and the second portion 30b of the field insulating layer 30 in the direction from the element region 101 to the termination region 102 (L2 in Figure 19).

[0141] In the comparative example IGBT, unlike the IGBT 100 of the embodiment, the guard ring region 55 does not wrap around to the bottom of the first portion 30a and the bottom of the second portion 30b.

[0142] In the comparative example IGBT, the thickness of the field insulating layer 30 in the portion in contact with the guard ring region 55 is reduced, resulting in a higher electric field strength near the edge of the field insulating layer 30. Consequently, the breakdown voltage of the comparative example IGBT decreases.

[0143] The IGBT 100 of the embodiment has a first portion 30a which includes a first deep region 30ax (first region) and a first shallow region 30ay (second region). The second portion 30b which includes a second deep region 30bx (third region) and a second shallow region 30by (fourth region).

[0144] In the embodiment of the IGBT 100, the depth of the first deep region 30ax (d1 in Figure 7) is greater than the depth of the first shallow region 30ay (d2 in Figure 7). Therefore, the thickness of the field insulating layer 30 in the portion of the first part 30a that contacts the guard ring region 55 (tx1 in Figure 7) is greater than the thickness of the field insulating layer 30 in the portion of the first part 30a that contacts the guard ring region 55 in the comparative example IGBT (ty1 in Figure 19).

[0145] Similarly, the depth of the second deep region 30bx (d3 in Figure 7) is greater than the depth of the second shallow region 30by (d4 in Figure 7). Therefore, the thickness of the field insulating layer 30 in the portion of the second part 30b that contacts the guard ring region 55 (tx2 in Figure 7) is greater than the thickness of the field insulating layer 30 in the portion of the second part 30b of the comparative example IGBT that contacts the guard ring region 55 (ty2 in Figure 19).

[0146] In this embodiment, the IGBT 100 has a thicker field insulating layer 30 in the portion that contacts the guard ring region 55, thereby mitigating the electric field strength near the edges of the field insulating layer 30. Consequently, the breakdown voltage of the IGBT 100 in this embodiment is improved.

[0147] From the viewpoint of improving the pressure resistance of the IGBT100, it is preferable that the depth d1 of the first deep region 30ax is 1.1 times or more the depth d2 of the first shallow region 30ay. From a similar viewpoint, it is preferable that the depth d3 of the second deep region 30bx is 1.1 times or more the depth d4 of the second shallow region 30by.

[0148] Furthermore, in the IGBT 100 of this embodiment, the guard ring region 55 wraps around the bottom of the first portion 30a and the bottom of the second portion 30b of the field insulating layer 30. Because the guard ring region 55 wraps around the bottom of the first portion 30a and the bottom of the second portion 30b, the intensity of the electric field near the edge of the field insulating layer 30 is further reduced. Therefore, the withstand voltage of the IGBT 100 of this embodiment is further improved.

[0149] From the viewpoint of increasing the wrap-around of the field insulating layer 30 in the guard ring region 55 to the bottom and improving the withstand voltage of the IGBT 100, the width w1 of the guard ring region 55 is preferably 1.1 times or more the distance L1 between the first portion 30a and the second portion 30b, more preferably 1.2 times or more, and even more preferably 1.5 times or more.

[0150] The manufacturing method for the IGBT 100 of this embodiment involves forming the inner trench 64a and the outer trench 64b, which ultimately become the field trench 42, so that the ends on the silicon region 62 side are deepened. Thus, it becomes possible to manufacture the IGBT 100 of this embodiment.

[0151] In particular, the inner trench 64a and outer trench 64b are formed using the CDE method before the heat treatment to activate the boron (B) in the silicon region 62. That is, the silicon layer 60 is etched using the CDE method before the crystal defects in the silicon region 62 that were generated during the ion implantation of boron (B) are restored. By making the etching rate faster in the areas where crystal defects exist than in other areas, the ends of the inner trench 64a and outer trench 64b on the silicon region 62 side can be formed to be deeper.

[0152] As described above, according to the embodiment, an IGBT that enables improved pressure resistance can be realized.

[0153] (First variation) The semiconductor device of the first modification of the embodiment differs from the semiconductor device of the embodiment in that, in a direction perpendicular to the first surface, the first and second portions are not provided between the first conductive layer and the fourth semiconductor region. Furthermore, it differs from the semiconductor device of the embodiment in that the width of the fourth semiconductor region in the direction from the element region to the termination region is equal to the distance between the first portion and the second portion in the above direction.

[0154] Figure 20 is an enlarged schematic cross-sectional view of a part of a semiconductor device of the first modified embodiment. Figure 20 corresponds to Figure 7 of the embodiment.

[0155] In the first modified IGBT, the first portion 30a and the second portion 30b are not provided between the field plate layer 32 and the guard ring region 55 in a direction perpendicular to the first surface F1. Also, in the first modified IGBT, the width of the guard ring region 55 in the direction from the element region 101 to the termination region 102 (w5 in Figure 20) is equal to the distance between the first portion 30a and the second portion 30b of the field insulating layer 30 in the direction from the element region 101 to the termination region 102 (L3 in Figure 20).

[0156] Unlike the IGBT 100 of the embodiment, the guard ring region 55 does not wrap around to the bottom of the first portion 30a and the bottom of the second portion 30b.

[0157] In the first modified IGBT of the embodiment, similar to the IGBT 100 of the embodiment, the thickness of the field insulating layer 30 in the portion in contact with the guard ring region 55 is increased, thereby mitigating the electric field strength near the edge of the field insulating layer 30. Therefore, the withstand voltage of the first modified IGBT of the embodiment is improved.

[0158] In the first modified IGBT, the inner trench 64a and outer trench 64b are formed, for example, using reactive ion etching (RIE). The first modified IGBT can be manufactured by selecting RIE conditions such that the ends of the silicon regions 62 in the inner trench 64a and outer trench 64b become deeper.

[0159] (Second variation) The semiconductor device of the second modification of the embodiment differs from the semiconductor device of the embodiment in that a portion of the first conductive layer and another portion of the first conductive layer that sandwich the fourth semiconductor region are not provided.

[0160] Figure 21 is an enlarged schematic cross-sectional view of a part of a semiconductor device of a second modified embodiment. Figure 21 corresponds to Figure 7 of the embodiment.

[0161] In the second modified IGBT, the field plate layer 32 does not include the first wedge portion 32a and the second wedge portion 32b.

[0162] In the second modified IGBT of the embodiment, similar to the IGBT 100 of the embodiment, the thickness of the field insulating layer 30 in the portion in contact with the guard ring region 55 is increased, and the guard ring region 55 wraps around to the bottom of the first portion 30a and the bottom of the second portion 30b, thereby mitigating the electric field strength near the edges of the field insulating layer 30. Therefore, the breakdown voltage of the second modified IGBT of the embodiment is improved.

[0163] In the second modified IGBT of the embodiment, the thickness of the field insulating layer 30 in contact with the guard ring region 55 (tx1, tx2 in Figure 21) is further increased compared to the IGBT 100 of the embodiment. Therefore, the withstand voltage of the IGBT of the second modified IGBT of the embodiment is further improved compared to the IGBT 100 of the embodiment.

[0164] Furthermore, the IGBT of the second modified embodiment can be formed, for example, by using chemical mechanical polishing (CMP) instead of wet etching when removing a portion of the first silicon oxide film 65 to expose the silicon region 62.

[0165] As described above, according to the embodiments and modifications, a semiconductor device and a method for manufacturing a semiconductor device that enable improved pressure resistance can be realized.

[0166] In the embodiments described, the semiconductor layer was described as being single-crystal silicon, but the semiconductor layer is not limited to single-crystal silicon. For example, it may be other single-crystal semiconductors such as single-crystal silicon carbide.

[0167] In this embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0168] In the embodiments, the example of an IGBT was used to describe the semiconductor device, but the semiconductor device is not limited to IGBTs. For example, it may be a Reverse-Conducting IGBT (RC-IGBT) in which an IGBT and a free-wheeling diode are formed on the same semiconductor chip. Alternatively, the semiconductor device may be a MOSFET, for example.

[0169] In the embodiments, the example described was that the semiconductor device is a trench gate type IGBT, but for example, the semiconductor device may be a planar gate type IGBT.

[0170] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0171] 10 Semiconductor layer 12. Emitter electrode (first electrode) 14. Collector electrode (second electrode) 16 Shuttle gates 18 Gate Insulator 30. Field insulating layer (first insulating layer) 30a Part 1 30ax First Deep Region (First Region) 30ay First shallow area (second area) 30b Second part 30bx Second deep region (third region) 30by Second shallow region (fourth region) 32. Field plate layer (first conductive layer) 32a First wedge portion (part of the first conductive layer) 32b Second wedge portion (another part of the first conductive layer) 34. Field plate insulating film (first insulating film) 36 Guard ring metal layer (second conductive layer) 41 Gate trench (trench) 51. Collector region (5th semiconductor region) 52. Drift region (first semiconductor region) 53 Base region (second semiconductor region) 54. Emitter region (third semiconductor region) 55 Guard Ring Region (Fourth Semiconductor Region) 60. Silicon layer (semiconductor layer) 62. Silicon Domain (Semiconductor Domain) 64a Inner trench (first trench) 64b Outer trench (second trench) 65. First silicon oxide film (insulating film) 68. Polycrystalline silicon film (conductive film) 100 IGBTs (Integrated Head Turn Signals) 101 Element Region 102 Termination area d1 Depth of the first region d2 Depth of the second region d3 Depth of the third domain d4 Depth of the fourth domain F1 First Side F2 Second side

Claims

1. Element region and, The system comprises a termination region surrounding the aforementioned element region, The aforementioned element region is A semiconductor layer having a first surface and a second surface facing the first surface, A first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type is provided between the first semiconductor region and the first surface, A semiconductor layer including a third semiconductor region of a first conductivity type provided between the second semiconductor region and the first surface, A gate electrode facing the second semiconductor region, A gate insulating film is provided between the second semiconductor region and the gate electrode, A first electrode is provided on the side of the first surface of the semiconductor layer and electrically connected to the third semiconductor region, A second electrode provided on the side of the second surface of the semiconductor layer, Includes, The aforementioned termination region is The semiconductor layer includes the first semiconductor region and a plurality of fourth semiconductor regions of a second conductivity type provided between the first semiconductor region and the first surface and arranged in a direction toward the terminal region from the element region, A first insulating layer including a first portion and a second portion in which the fourth semiconductor region is provided between the first portion in the aforementioned direction, A first conductive layer having the first portion, the fourth semiconductor region, and the second portion between it and the first semiconductor region, The first electrode 2, Includes, The first part includes a first region and a second region, In the aforementioned direction, the first region is provided between the second region and the fourth semiconductor region. The depth of the first region is greater than the depth of the second region. The aforementioned second part includes the third and fourth regions, In the aforementioned direction, the third region is provided between the fourth region and the fourth semiconductor region. A semiconductor device in which the depth of the third region is greater than the depth of the fourth region.

2. The semiconductor device according to claim 1, wherein the depth of the first region is 1.1 times or more and 1.5 times or less the depth of the second region.

3. The semiconductor device according to claim 1, wherein the first portion and the second portion are provided between the first conductive layer and the fourth semiconductor region in a direction perpendicular to the first surface.

4. The semiconductor device according to claim 1, wherein the width of the fourth semiconductor region in the direction is greater than the distance between the first portion and the second portion in the direction.

5. The semiconductor device according to claim 1, wherein the fourth semiconductor region is provided between a part of the first conductive layer and another part of the first conductive layer in the aforementioned direction.

6. The semiconductor device according to claim 1, wherein the thickness of the first insulating layer in the second region in a direction perpendicular to the first surface is less than or equal to the depth of the second region.

7. The semiconductor device according to claim 1, wherein the first conductive layer and the fourth semiconductor region are electrically connected.

8. The semiconductor device according to claim 1, wherein the first conductive layer and the fourth semiconductor region are electrically floating.

9. The semiconductor device according to claim 1, wherein the termination region further includes a second conductive layer, and the first conductive layer is provided between the second conductive layer and the fourth semiconductor region.

10. The semiconductor device according to claim 9, wherein the second conductive layer is electrically connected to the first conductive layer and the fourth semiconductor region.

11. The semiconductor device according to claim 1, wherein the fourth semiconductor region surrounds the element region.

12. The semiconductor device according to claim 1, wherein the first conductive layer surrounds the element region.

13. The semiconductor device according to claim 9, wherein the second conductive layer surrounds the element region.

14. The semiconductor device according to claim 1, wherein the first conductive layer is polycrystalline silicon.

15. The semiconductor device according to claim 1, wherein the termination region further includes a first insulating film provided between the first conductive layer and the fourth semiconductor region.

16. The semiconductor device according to claim 1, wherein the semiconductor layer of the element region further includes a fifth semiconductor region of a second conductivity type provided between the first semiconductor region and the second surface and in contact with the second electrode.

17. The semiconductor device according to claim 1, wherein the semiconductor layer of the element region further includes a trench provided on the side of the first surface, and the gate electrode is provided in the trench.

18. The semiconductor device according to claim 1, wherein the semiconductor layer is silicon.

19. A semiconductor layer of a first conductivity type is ion-implanted with an impurity of a second conductivity type to form an annular semiconductor region of the second conductivity type on the surface of the semiconductor layer. A first trench is formed on the inside of the semiconductor region on the surface of the semiconductor layer, with the depth on the semiconductor region side being deeper than the depth on the other side, and a second trench is formed on the outside of the semiconductor region on the surface of the semiconductor layer, with the depth on the semiconductor region side being deeper than the depth on the other side. The first trench and the second trench are filled with an insulating film. A heat treatment is performed to activate the impurities in the semiconductor region. A method for manufacturing a semiconductor device, comprising forming a conductive film on the insulating film and the semiconductor region.

20. The method for manufacturing a semiconductor device according to claim 19, wherein the first trench and the second trench are in contact with the semiconductor region, and the distance between the first trench and the second trench in the direction from the inside to the outside of the semiconductor region is smaller than the width of the semiconductor region in that direction.

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