Semiconductor equipment

Abstract

This disclosure aims to provide a technology that can improve the voltage withstand capability of semiconductor devices using a simple method. [Solution] The semiconductor device 100 of the present disclosure comprises a first frame portion 1 having a pad portion 11 on which a first chip C1 that performs predetermined processing in response to an applied input voltage is mounted, and lead portions 12 and 13 extending in a predetermined direction from the pad portion 11, and being in a floating state by the lead portions 12 and 13; a second frame portion 2 having a pad portion 21 on which a second chip C2 electrically connected to the first chip C1 is mounted, lead terminals L3 and L14 that fix the silicon substrate potential of the second chip C2, and lead portions 22 and 23 extending from the pad portion 21 toward the lead terminals L3 and L14.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device to which a high voltage is applied to a lead terminal.

Background Art

[0002] Conventionally, a semiconductor device in which a circuit element is mounted on a die pad of a lead frame and then encapsulated with an encapsulating resin is known. For example, Patent Document 1 discloses a semiconductor device having a multi-chip structure in which a first chip that reduces (steps down) a high-voltage signal and a second chip that processes a signal reduced (stepped down) via the first chip are separately mounted on a lead frame.

[0003] In Patent Document 1, a dielectric member is disposed between the first chip and a die pad or a lead terminal connected to a voltage lower than the input voltage, and the capacitance of the first chip and the capacitance of the dielectric member are connected in series to reduce the voltage applied to the first chip, thereby improving the withstand voltage.

[0004] However, in the technique of Patent Document 1, it is necessary to dispose a dielectric member to improve the withstand voltage, which increases the manufacturing process and the cost. Therefore, it is desired to improve the withstand voltage of a semiconductor device by a simpler method.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In order to solve the above problems, an object of the present disclosure is to provide a technique capable of improving the withstand voltage of a semiconductor device by a simple method.

Means for Solving the Problems

[0007] To achieve the above objective, the semiconductor device of this disclosure comprises a first frame and a second frame, each of which a chip is mounted, and employs a method of electrically floating the first frame portion on the input voltage side.

[0008] Specifically, the semiconductor device of this disclosure is A first pad portion is mounted on a first chip that performs predetermined processing in response to an applied input voltage, and a first lead portion extends from the first pad portion in a predetermined direction, and a first frame portion is made floating by the first lead portion, A second frame portion having a second pad portion on which a second chip electrically connected to the first chip is mounted, a lead terminal for fixing the silicon substrate potential of the second chip, and a second lead portion extending from the second pad portion toward the lead terminal, It is equipped with.

[0009] Furthermore, the first frame section and the second frame section are arranged separately. The first chip and the second chip may be electrically connected by a wire.

[0010] Furthermore, the predetermined direction may be different from the direction in which the lead terminals that fix the silicon substrate potential of the second chip extend.

[0011] Furthermore, multiple first lead portions may be provided.

[0012] Furthermore, on one side, there are multiple terminals arranged at predetermined intervals from the lead terminals of the second frame portion, The distance between the first lead portion and the lead terminal may be longer than the predetermined interval.

[0013] Furthermore, the above disclosures can be combined as much as possible. [Effects of the Invention]

[0014] According to the present disclosure, the breakdown voltage of a semiconductor device can be improved by a simple method.

Brief Description of the Drawings

[0015] [Figure 1] It is a diagram for explaining the configuration of a semiconductor device according to the first embodiment of the present disclosure. [Figure 2] It is a cross-sectional view of a semiconductor device according to the first embodiment of the present disclosure. [Figure 3] It is a diagram for explaining the manufacturing process of a semiconductor device. [Figure 4] It is a diagram for explaining the configuration of a semiconductor device according to the first modification example. [Figure 5] It is a diagram for explaining the configuration of a semiconductor device according to the second modification example. [Figure 6] It is a diagram for explaining the configuration of a semiconductor device according to the third modification example. [Figure 7] It is a diagram for explaining the configuration of a semiconductor device according to the fourth modification example. [Figure 8] It is a diagram for explaining the configuration of a semiconductor device according to the fifth modification example. [Figure 9] It is a diagram for explaining the configuration of a semiconductor device according to the sixth modification example. [Figure 10] It is a diagram for explaining the configuration of a semiconductor device according to the seventh modification example. [Figure 11] It is a diagram for explaining the configuration of a semiconductor device according to the eighth modification example. [Figure 12] It is a diagram for explaining the configuration of a semiconductor device according to the second embodiment. [Figure 13] It is a diagram for explaining the configuration of a semiconductor device according to the first modification example of the second embodiment. [Figure 14] It is a diagram for explaining the configuration of a semiconductor device according to the second modification example of the second embodiment. [Figure 15] It is a diagram for explaining the configuration of a related semiconductor device. [Figure 16] It is a cross-sectional view of a related semiconductor device. [Modes for carrying out the invention]

[0016] Embodiments of this disclosure will be described in detail below with reference to the drawings. However, this disclosure is not limited to the embodiments shown below. These examples are illustrative only, and this disclosure can be implemented in various modified and improved forms based on the knowledge of those skilled in the art. In this specification and in the drawings, components with the same reference numerals refer to the same components. Furthermore, in the following description, the top, bottom, left, and right of the drawings will be used as reference points.

[0017] (First Embodiment) A semiconductor device 100 according to the first embodiment will be described with reference to Figures 1 to 3. As shown in Figure 1, the semiconductor device 100 mainly comprises a first frame portion 1 and a second frame portion 2. Lead portions 31 and 32 are provided to the left of the first frame portion 1, symmetrically arranged vertically in the figure.

[0018] The first frame portion 1 is formed symmetrically from top to bottom and has a pad portion 11 and lead portions 12 and 13. A high voltage of, for example, about 1200V can be applied to the first frame portion 1 via the lead terminal L2 of the lead portion 31 and the lead terminal L1 of the lead portion 32.

[0019] The pad portion 11 is equipped with a first chip C1 that performs predetermined processing on the applied input voltage. The first chip C1 and the lead portions 31 and 32 are electrically connected via predetermined wires. The first chip C1 has the function of reducing (stepping down) the high-voltage signal applied to the lead terminal L1 or lead terminal L2. The first chip C1 is a semiconductor element (e.g., a thin-film resistive element) that can be formed by a normal semiconductor device manufacturing method. The first chip C1 is manufactured, for example, by forming a thick insulating film (e.g., an oxide film about 6 to 8 μm thick formed by CVD) on a P-type silicon substrate about 200 μm thick, and forming a resistive element on the insulating film. The pad portion 11 is an example of the "first pad portion" in this disclosure.

[0020] Figure 2 shows the formation of an oxide film C10 on the first chip C1. The capacitance of the first chip C1 corresponds to the capacitance formed by the electrode pads, resistance patterns, etc., of the resistive element formed on the semiconductor substrate via the oxide film C10. In this embodiment, the pattern is formed so that two capacitances C11 and C12 are connected in series. As a result, the voltage applied to the first chip C1 is reduced by voltage division, enabling high voltage resistance of the semiconductor device 100.

[0021] Returning to Figure 1, the lead portions 12 and 13 extend from the pad portion 11 in an upward and downward symmetrical manner. In other words, the lead portions 12 and 13 extend from the pad portion 11 in a predetermined direction. Specifically, the lead portion 12 extends upward from the upper end of the pad portion 11 in a meandering manner, and the lead portion 13 extends downward from the lower end of the pad portion 11 in a meandering manner. The lead portions 12 and 13 are examples of the "first lead portion" in this disclosure.

[0022] Generally, the lead sections 12 and 13 are called suspension leads. They are leads that fix the area (die pad) for mounting the chip, which is provided in the IC pattern of the semiconductor package, to the outer frame, and are also called die pad supports.

[0023] The second frame portion 2 is formed symmetrically from top to bottom and has a pad portion 21 and lead portions 22 and 23. The pad portion 21 is mounted on a second chip C2 which is electrically connected to the first chip C1. The second chip C2 is electrically connected to the first chip C1 via predetermined wires. The second chip C2 is provided according to various applications of the semiconductor device and processes signals that have been reduced in voltage (stepped down) via the first chip C1 (see Patent Document 1). The second chip C2 is manufactured, for example, by forming an operational amplifier on a P-type silicon substrate with a thickness of about 200 μm using a normal semiconductor device manufacturing method. The pad portion 21 is an example of the "second pad portion" in this disclosure.

[0024] Figure 2 shows the formation of an oxide film C20 on the second chip C2. The capacitance of the second chip C2 corresponds to the capacitance formed by the electrode pads of the operational amplifier, impurity regions, etc., formed on the semiconductor substrate.

[0025] Returning to Figure 1, the lead portions 22 and 23 extend from the pad portion 21 in an upward and downward symmetrical manner. Specifically, the lead portion 22 extends upward from the upper end of the pad portion 21 and then extends to the right. The lead portion 23 extends downward from the lower end of the pad portion 21 and then extends to the right. The lead portion 22 is provided with a lead terminal L3, and the lead portion 23 is provided with a lead terminal L14. The lead portions 22 and 23 extend from the pad portion 21 toward the lead terminals L3 and L14. The lead terminals L3 and L14 are connected to the low-potential side and fix the silicon substrate potential of the second chip C2. Furthermore, the direction in which the lead terminals L3 and L14 that fix the silicon substrate potential of the second chip C2 extend is different from the direction in which the lead portions 12 and 13 extend. The lead terminals L3 and L14 are examples of "lead terminals" in this disclosure. Lead portions 22 and 23 are examples of the "second lead portion" in this disclosure.

[0026] Multiple lead terminals L4 to L13, which function as pins, are provided between lead terminals L3 and L14. These multiple lead terminals L4 to L13 and the second chip C2 are electrically connected via predetermined wires. In the cross-sectional view of Figure 2, lead terminals L4 to L13 are shown so as not to overlap with lead terminals L3 and L14 in order to represent that they are connected by wires as functional pins of the second chip C2.

[0027] The first frame section 1, the second frame section 2, and each lead terminal are sealed with sealing resin. Specifically, the semiconductor device 100 may be manufactured by any conventional method. For example, as shown in Figure 3(1), first the lead frame is processed into a predetermined shape (first frame section 1, second frame section 2, etc.). Next, as shown in Figure 3(2), chips are mounted on the pad sections (die pads) of each frame. Next, as shown in Figure 3(3), each electrode is electrically connected using a predetermined wire. Next, each frame and each lead terminal is sealed with sealing resin. Finally, the lead frame is cut.

[0028] (Surface distance) Returning to Figure 1, we will now explain the creepage distance of the semiconductor device 100. Generally, it is recommended that a distance (creepage distance) be provided between outer lead terminals to which high voltage is applied and outer lead terminals to which low potential is applied, according to standards (IEC (International Electrotechnical Commission) and JIS (Japanese Industrial Standards), etc.). This is mainly to prevent discharge between terminals.

[0029] Specifically, the semiconductor device 100 has a plurality of terminals L4 to L13 arranged at predetermined intervals from the lead terminals L3 and L14 of the second frame portion 2 on the output side, The distance between the lead portions 12 and 13 of the first frame portion 1 and the lead terminals L3 and L14 is set to be longer than the predetermined interval described above.

[0030] First, in this embodiment, the lead portions 31 and 32 are arranged symmetrically in the vertical direction, and the lead terminals L1 and L2 are also spaced apart by a sufficient creepage distance (=A) to suppress discharge in the vertical direction.

[0031] Furthermore, in this embodiment, the lead portion 12 of the first frame portion 1 extends to approximately the center of the upper end of the semiconductor device 100. This ensures a sufficient creepage distance (=B) between the lead terminal L2 extending to the left from the left end of the semiconductor device 100 and the lead portion 12. Similarly, the lead portion 13 of the first frame portion 1 extends to approximately the center of the lower end of the semiconductor device 100. This ensures a sufficient creepage distance (=B) between the lead terminal L1 extending to the left from the left end of the semiconductor device 100 and the lead portion 13.

[0032] Furthermore, because the lead portion 12 extends to approximately the center of the upper end of the semiconductor device 100, sufficient creepage distance (=C) can be secured between the lead terminal L3 extending to the right from the lead portion 22 of the second frame portion 2 and the lead portion 12. Similarly, because the lead portion 13 extends to approximately the center of the lower end of the semiconductor device 100, sufficient creepage distance (=C) can be secured between the lead terminal L14 extending to the right from the lead portion 23 of the second frame portion 2 and the lead portion 13.

[0033] (floating) Next, the floating structure of the semiconductor device 100 will be described with reference to the cross-sectional view in Figure 2. The first frame portion 1 is in a floating state as an independent portion that is not electrically connected to other parts (especially the second frame portion 2) by the lead portions 12 and 13. In other words, the first frame portion 1 and the second frame portion 2 are arranged separately. In this embodiment, by making the first frame portion 1 an independent portion that is not connected to other parts (especially the second frame portion 2), the withstand voltage performance is improved and discharge is suppressed.

[0034] Specifically, as shown in Figure 2, the first frame section 1 is independent of the other parts. Therefore, for example, even when a short-circuit fault occurs in the insulating film of the first chip C1, the flow of a large current to the second frame section 2 via the first frame section 1 is suppressed. Furthermore, the voltage at the first chip C1 on the pad section 11 of the first frame section 1 is divided by capacitors C11 and C12. This makes it possible to improve the withstand voltage performance without providing a separate dielectric material. In other words, in this embodiment, it is possible to improve the withstand voltage performance while suppressing the flow of a large current to the lead frame.

[0035] As shown in Figure 1, this embodiment is a structure used when the potential difference on the high-voltage side is generated as a "positive voltage - negative voltage" and that potential difference is used for signal processing. In this case, the device is in a floating state when viewed from either the high-voltage side or the low-voltage side. The same applies to other embodiments of this disclosure unless otherwise specified.

[0036] (effect) Next, the effects of this embodiment will be described in comparison with the configuration of the related semiconductor device 100A shown in Figures 15 and 16. The semiconductor device 100A mainly comprises a first frame portion 1A, a second frame portion 2A, and a pair of lead portions 31A and 32A.

[0037] Lead portions 12A and 13A extend from the pad portion 11A of the first frame portion 1A. Specifically, lead portion 12A extends upward from the upper end of the pad portion 11A and then extends to the right. Lead portion 13A extends downward from the lower end of the pad portion 11A and then extends to the right. Lead terminal L3 is provided on lead portion 12A, and lead terminal L14 is provided on lead portion 13A.

[0038] Lead portions 22A and 23A extend from the pad portion 21A of the second frame portion 2A. Specifically, lead portion 22A extends upward from the upper end of the pad portion 21A and then extends to the right. Lead portion 23A extends downward from the lower end of the pad portion 21A and then extends to the right. Lead terminal L4 is provided on lead portion 22A, and lead terminal L13 is provided on lead portion 23A.

[0039] As described above, both the lead portion provided on the first frame portion 1A and the lead portion provided on the second frame portion 2A extend to the right. Also, as shown in Figure 15, at the right end of the semiconductor device 100A, lead terminals L3 and L4 are adjacent, and lead terminals L13 and L14 are adjacent. Therefore, it is not possible to secure sufficient creepage distance (=C') between lead terminals L3 and L4, and between lead terminals L13 and L4. As a result, as shown by the root R of the arrow in Figure 16, a large current from the first frame portion 1A flows directly to the low-voltage side, i.e., to the second frame portion 2A without going through a wire (discharges), causing the components to be destroyed.

[0040] For example, when a short circuit occurs in the insulating film of the first chip C1, even if lead terminals L3 and L14 are floating on the PCB board, discharge occurs between lead terminals L3 and L4, and between lead terminals L14 and L13. A large current flows from the first frame section 1A to the low-voltage side, i.e., the second frame section 2A, destroying the component. The creepage distance C' in the related semiconductor device 100A corresponds to the creepage distance C in the semiconductor device 100.

[0041] In contrast, in this embodiment, as described above, the lead portions 12 and 13 extend to approximately the center of the upper and lower ends of the semiconductor device 100, thereby making the first frame portion 1 floating. In other words, in this embodiment, a predetermined creepage distance is secured while making it floating. As a result, as shown by the arrow route R in Figure 2, the current from the first frame portion 1 flows to the second frame portion 2 only through the wires, and it is possible to suppress the direct flow of a large current to the second frame portion 2. In particular, according to this embodiment, it is possible to suppress a large current from the high-voltage side to the low-voltage side in the event of a short-circuit failure of the mounted chip.

[0042] Furthermore, in the related semiconductor device 100A, even if lead terminals L3 and L14 are in a floating state on the PCB board, the voltage division effect is low because lead terminals L3 and L4, and lead terminals L14 and L13 are adjacent, so no improvement in withstand voltage performance can be expected. Moreover, in the semiconductor device 100A, if lead terminals L3 and L14 are in a floating state on the PCB board, a floating voltage will be generated between lead terminals L3 and L14, which may cause discharge between lead terminals L3 and L4, and between lead terminals L14 and L13.

[0043] In contrast, in this embodiment, while ensuring sufficient creepage distance, the first frame portion 1 is in a floating state at the lead portions 12 and 13. As shown by the root R of the arrow in Figure 2, current flows only through the wires, and the desired voltage division effect can be obtained. Thus, in this embodiment, the withstand voltage performance can be improved without providing a separate dielectric member.

[0044] Furthermore, input voltages containing noise components may be applied to lead terminals L1 and L2. In this case, the capacitive component of chip C1 mounted on pad portion 11 of first frame portion 1 allows high-frequency noise components to pass through. However, in this embodiment, since the first frame portion 1 is in a floating state, noise interference to the second frame portion 2 can be mitigated.

[0045] (modified version) Next, a modified semiconductor device will be described with reference to Figures 4 to 11. The scope of this disclosure is not limited to what has been described above. Various structures are included in the lead frame (first frame portion, second frame portion) of this disclosure.

[0046] Figure 4 shows a semiconductor device 101 according to the first modification. In the semiconductor device 101, the lead portion 32 is connected to the pad portion 11 of the first frame portion 1. The structure of this modification is used when the potential difference on the high-voltage side is generated as "positive voltage - GND" and that potential difference is used for signal processing. In this case, it is in a floating state only when viewed from the low-voltage side.

[0047] Figure 5 shows a semiconductor device 102 according to a second modified example. The semiconductor device 102 is provided with an additional lead terminal L15 adjacent to the lead terminal L1. The lead terminal L15 is a functional pin that functions, for example, as a terminal to which a reference voltage is applied when reducing resistance.

[0048] Figure 6 shows a semiconductor device 103 according to a third modified example. In semiconductor device 103, lead terminal L16 is provided in addition to lead terminal L15. Lead terminal L16 is provided as a functional pin other than a functional pin that functions, for example, as a terminal to apply a reference voltage when reducing resistance, and is an input or output functional pin that can be used when expanding the functionality of the semiconductor device.

[0049] Figure 7 shows a semiconductor device 104 according to the fourth modification, and Figure 8 shows a semiconductor device 105 according to the fifth modification. In the fourth modification, the first frame portion 5 is floating using only the lead portion 12. In the fifth modification, the first frame portion 51 is floating using only the lead portion 13. Thus, the first frame portion may be made floating using only either the lead portion 12 or the lead portion 13.

[0050] Figure 9 shows a semiconductor device 106 according to a sixth modified example. In the semiconductor device 106, the first frame portion 6 is separated into a first portion 61 located at the top and a second portion 62 located at the bottom. This configuration is effective when separating the silicon substrate potential of the mounted chip.

[0051] Figure 10 shows a semiconductor device 107 according to a seventh modified example. The first frame portion 7 of the semiconductor device 107 has lead portions 71 and 72. Lead portion 71 extends upward from the upper end of the pad portion 11 and then extends to the right. Lead portion 72 extends downward from the lower end of the pad portion 11 and then extends to the right. Lead terminal L3 is provided on lead portion 71, and lead terminal L8 is provided on lead portion 72. In this configuration, the first frame portion 7 becomes floating by connecting lead terminals L3 and L8 to the floating pattern on the PCB substrate.

[0052] The second frame portion 8 of the semiconductor device 107 has lead portions 81 and 82. Lead portion 81 extends to the right from the upper end of the pad portion 21. Lead portion 82 extends to the right from the lower end of the pad portion 21. Lead terminal L4 is provided on lead portion 81, and lead terminal L7 is provided on lead portion 82.

[0053] As shown in Figure 10, lead terminals L3 and L4 (lead terminals L8 and L7) are spaced apart and configured to ensure a sufficient creepage distance (=C).

[0054] In this modified example, since the first frame section 7 for the resistor chip is connected to lead terminals L3 and L8, it is possible to have a floating state when viewed from either the high-voltage or low-voltage side, and it is also possible to have a floating state when viewed only from the low-voltage side. In other words, by switching the lead terminal L1 between "connected / unconnected" to the pad section 11, it is possible to select between a floating state for "both high-voltage and low-voltage sides" and a floating state for "low-voltage side only".

[0055] Figure 11 shows a semiconductor device 108 according to the eighth modification. The semiconductor device 108 is provided with either the first frame portion 5 of the semiconductor device 104 according to the fourth modification, or the first frame portion 51 of the semiconductor device 105 according to the fifth modification. A pair of lead portions 33 and 34 are provided in positions that allow connection to the first frame portion 51. A first chip C1 is mounted on the first frame portion 5, and a third chip C3 is mounted on the first frame portion 51. This configuration is suitable when employing a multi-chip configuration of three or more chips. The semiconductor device 108 can also be configured, for example, with a chip having a voltage reduction function as the first chip, a chip having a galvanic transmission function as the second chip, and a signal processing chip as the third chip.

[0056] In any of the above semiconductor device configurations, it is possible to improve voltage withstand performance without providing additional dielectric materials while ensuring sufficient creepage distance. Furthermore, even in the event of a short-circuit failure of the mounted chip, it is possible to suppress large currents from the high-voltage side to the low-voltage side.

[0057] (Second Embodiment) Next, a semiconductor device 200 according to a second embodiment of the present disclosure will be described with reference to Figure 12. In the embodiments described above, each component (first frame section, second frame section, etc.) was configured symmetrically vertically, assuming that the voltage is input from the left end. However, the scope of the present disclosure is not limited thereto, and each component (first frame section, second frame section, etc.) may be configured symmetrically horizontally, assuming that the voltage is input from the left end.

[0058] The semiconductor device 200 mainly comprises a first frame portion 91 and a second frame portion 92. Above the first frame portion 91, lead portions 35 and 36 are provided symmetrically on the left and right sides of the figure. Lead portion 35 is provided with a lead terminal L6, and lead portion 36 is provided with a lead terminal L7.

[0059] The first frame portion 91 is formed symmetrically and has a pad portion 93 and lead portions 94 and 95. The first chip C1 is mounted on the pad portion 93. The lead portions 94 and 95 extend symmetrically from the pad portion 93. Specifically, the lead portion 94 extends from the left end of the pad portion 93 in a meandering manner to the left, and the lead portion 95 extends from the right end of the pad portion 93 in a meandering manner to the right. The lead portion 94 is provided with a lead terminal L5, and the lead portion 95 is provided with a lead terminal L8.

[0060] The second frame portion 92 is formed symmetrically and has a pad portion 96 and a lead portion 97. The second chip C2 is mounted on the pad portion 96. The lead portion 97 extends downward from the lower end of the pad portion 96. The second frame portion 92 is in a floating state due to the lead portion 97. Lead terminals L1 to L4 are provided on the left side of the pad portion 96, and lead terminals L9 to L12 are provided on the right side of the pad portion 96.

[0061] As shown in Figure 12, the components are arranged so that sufficient creepage distances D, E, and F are ensured between each terminal.

[0062] Even with the configuration of the semiconductor device 200, it is possible to improve the withstand voltage performance without providing a separate dielectric material while ensuring sufficient creepage distance. Furthermore, even in the event of a short-circuit failure of the mounted chip, it is possible to suppress large currents from the high-voltage side to the low-voltage side.

[0063] In this embodiment, since the first frame portion 91 for the resistor chip is connected to lead terminals L5 and L8, it is possible to have a floating state when viewed from either the high-voltage side or the low-voltage side, and it is also possible to have a floating state when viewed from the low-voltage side only. In other words, by switching the lead terminal L6 between "connected / unconnected" with the pad portion 93, it is possible to select between a floating state for "both high-voltage and low-voltage sides" and a floating state for "low-voltage side only".

[0064] (Modified version of the second embodiment) Next, a semiconductor device according to a modification of the second embodiment will be described with reference to Figures 13 and 14. This disclosure is not limited to the second embodiment described above, assuming that the voltage is input from the left end and that each component (first frame section, second frame section, etc.) is configured symmetrically. Various structures are included for the lead frame (first frame section, second frame section) of this disclosure.

[0065] Figure 13 shows a semiconductor device 201 according to a first modification of the second embodiment. The first frame portion 91A of the semiconductor device 201 has a pad portion 93A and a lead portion 94A. A first chip C1 is mounted on the pad portion 93A. The lead portion 94A extends upward from the upper end of the pad portion 93A. The first frame portion 91A is in a floating state due to the lead portion 94A.

[0066] Figure 14 shows a semiconductor device 202 according to a second modification of the second embodiment. The second frame portion 92A of the semiconductor device 202 has lead portions 98A and 99A. Lead portion 98A extends to the left from the lower part of the left end of the pad portion 96. Lead portion 99A extends to the right from the lower part of the right end of the pad portion 96. Lead terminal L1 is provided on lead portion 98A, and lead terminal L8 is provided on lead portion 99A.

[0067] In any of the above semiconductor device configurations, it is possible to improve voltage withstand performance without providing additional dielectric materials while ensuring sufficient creepage distance. Furthermore, even in the event of a short-circuit failure of the mounted chip, it is possible to suppress large currents from the high-voltage side to the low-voltage side.

[0068] (Other examples) Up to this point, the explanation has been based on the assumption that the semiconductor device is of the gull-wing type. However, the scope of this disclosure is not limited to this, and the semiconductor device may be of the flat-lead type or leadless type. In this case as well, it is possible to improve the withstand voltage performance without providing a separate dielectric material while ensuring sufficient creepage distance. Furthermore, even in the event of a short-circuit failure of the mounted chip, it is possible to suppress the large current flowing from the high-voltage side to the low-voltage side.

[0069] In the above-described semiconductor device configuration, the first frame section was described as being in a floating state. However, if an active element is provided on the first chip, the pad section of the first frame section may not operate stably during transient responses such as power-on if it is in a floating state. In such cases, stable operation can be achieved by connecting the first frame section and the second frame section with a wire. Alternatively, the first frame section may be connected to a lead terminal at the same potential as the second frame section with a wire. Even with this configuration, if a short-circuit failure occurs in the insulating film of the first chip, the wire will burn out and a large current will not flow to the second frame section, thus suppressing a large current from the high-voltage side to the low-voltage side. [Explanation of Symbols]

[0070] 100, 101, 102, 103, 104, 105, 106, 107, 108, 200, 201, 202: Semiconductor devices 1, 5, 51, 6, 7, 91, 91A: First frame section 11, 93, 93A: Pad section C1: First chip 12, 13, 71, 72, 94, 95, 94A: Lead section 61: Part 1 62:Second part 2, 8, 92, 92A: Second frame section 21, 96: Pad section C2: Second chip 22, 23, 81, 82, 97, 98A, 99A: Lead section 31, 32, 33, 34, 35, 36: Lead section 4: Sealing resin

Claims

1. A first pad portion is mounted on a first chip that performs predetermined processing on an applied input voltage, and a first lead portion extends from the first pad portion in a predetermined direction, and a first frame portion is made floating by the first lead portion, A second frame portion having a second pad portion on which a second chip electrically connected to the first chip is mounted, a lead terminal for fixing the silicon substrate potential of the second chip, and a second lead portion extending from the second pad portion toward the lead terminal, Equipped with, Semiconductor equipment.

2. The first frame section and the second frame section are arranged separately. The first chip and the second chip are electrically connected by a wire. The semiconductor device according to claim 1.

3. The predetermined direction is different from the direction in which the lead terminals that fix the silicon substrate potential of the second chip extend. The semiconductor device according to claim 1.

4. Multiple first lead sections are provided. The semiconductor device according to claim 1.

5. On one side, there are multiple terminals arranged at predetermined intervals from the lead terminals of the second frame portion, The distance between the first lead portion and the lead terminal is longer than the predetermined interval. The semiconductor device according to claim 1.

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