Multilayer electronic components

Abstract

To provide a multilayer electronic component that offers excellent reliability and can suppress hydrogen diffusion. [Solution] A stacked electronic component according to one embodiment of the present invention includes a body containing a dielectric layer and internal electrodes, and external electrodes disposed on the body, wherein the external electrodes include a Ni plating layer, and the Ni plating layer can have a Texture Coefficient (TC) value of TC(111), TC(200), and TC(220) with TC(200) being the largest.

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and plays the role of charging or discharging electricity.

[0003] Multilayer ceramic capacitors can be used as components in various electronic devices due to their advantages of being small, yet guaranteeing high capacitance, and being easy to implement.

[0004] Recently, with the miniaturization and increased performance of electronic devices, multilayer ceramic capacitors have also tended to become smaller and have higher capacitance. This trend has increased the importance of ensuring high reliability in multilayer ceramic capacitors.

[0005] Generally, to improve the mountability of MLCCs, external electrodes can include a plating layer. However, if hydrogen generated during the plating process to form the plating layer, or hydrogen present externally, diffuses into the body, the reliability of the MLCC may be reduced. [Overview of the project] [Problems that the invention aims to solve]

[0006] One of the various objectives of the present invention is to provide a highly reliable stacked electronic component.

[0007] One of the various objectives of the present invention is to provide a stacked electronic component that can suppress hydrogen diffusion.

[0008] However, the objectives of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0009] A stacked electronic component according to one embodiment of the present invention includes a body containing a dielectric layer and internal electrodes, and external electrodes disposed on the body, wherein the external electrodes include a Ni plating layer, and the Ni plating layer can have a Texture Coefficient (TC) value of TC(111), TC(200), and TC(220) with TC(200) being the largest.

[0010] A stacked electronic component according to one embodiment of the present invention includes a body containing a dielectric layer and internal electrodes arranged alternately with the dielectric layer, and an external electrode containing a base electrode layer disposed on the body and connected to the internal electrodes, wherein the base electrode layer may be made of Al, Cu, or glass. [Effects of the Invention]

[0011] One of the various effects of the present invention is that it can improve the reliability of stacked electronic components.

[0012] One of the various effects of the present invention is that it can suppress the deterioration of the insulation resistance of multilayer electronic components.

[0013] One of the various effects of the present invention is the provision of a stacked electronic component that can suppress hydrogen diffusion into the main body.

[0014] However, the diverse yet significant advantages and effects of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Brief explanation of the drawing]

[0015] [Figure 1] This is a schematic perspective view of a laminated electronic component according to an embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view taken along line I-I' of FIG. 1. [Figure 3] This is a schematic cross-sectional view taken along line II-II' of FIG. 1. [Figure 4] This is a schematic view showing the disassembled body. [Figure 5] These are X-ray diffraction (XRD) analysis graphs for test numbers 1 to 3. [Figure 6] This is a graph showing the TC values for test numbers 1 to 4. [Figure 7] This is a graph showing the TC values for test numbers 5 to 9. [Figure 8] This is a graph showing the measured insulation resistance (IR) for test numbers 1 to 3. [Figure 9] This is a drawing corresponding to FIG. 2 according to another embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0016] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into several other forms, and the scope of the present invention is not limited to the embodiments described below. Also, the embodiments of the present invention are provided to more fully explain the present invention to an ordinary technician. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or emphasized or simplified) for clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0017] In order to clearly describe the present invention in the drawings, parts not related to the description are omitted. The sizes and thicknesses of the illustrated components are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited by the illustrations. Also, components having the same functions within the scope of the same concept are described using the same reference numerals. Further, throughout the specification, when a certain part "includes" a certain component, it means that other components can be further included, rather than excluding other components, unless otherwise stated to the contrary.

[0018] In the drawings, the X direction can be defined as the first direction, the stacking direction or the thickness (T) direction, the Y direction as the second direction or the length (L) direction, and the Z direction as the third direction or the width (W) direction.

[0019] Multilayer electronic component FIG. 1 schematically shows a perspective view of a multilayer electronic component 100 according to an embodiment of the present invention. FIG. 2 schematically shows a cross-sectional view taken along the line I-I' of FIG. 1. FIG. 3 schematically shows a cross-sectional view taken along the line II-II' of FIG. 1. FIG. 4 schematically shows the disassembled body. FIG. 5 is an X-ray diffraction (XRD) analysis graph for test numbers 1 to 3.

[0020] Hereinafter, referring to FIGS. 1 to 5, a multilayer electronic component 100 according to an embodiment of the present invention will be described in detail. Also, as an example of the multilayer electronic component, a multilayer ceramic capacitor (hereinafter referred to as "MLCC") will be described, but the present invention is not limited thereto and can also be applied to various multilayer electronic components using ceramic materials, such as inductors, piezoelectric elements, varistors, or thermistors.

[0021] A stacked electronic component 100 according to one embodiment of the present invention includes a body 110 including a dielectric layer 111 and internal electrodes 121 and 122, and external electrodes 131 and 132 disposed on the body, wherein the external electrodes include Ni plating layers 131b and 132b, and the Ni plating layer can have the largest Texture Coefficient (TC) value among TC(111), TC(200), and TC(220).

[0022] Generally, to improve the mountability of MLCCs, external electrodes can include a plating layer. However, if hydrogen generated during the plating process to form the plating layer, or hydrogen present externally, diffuses into the body, the reliability of the MLCC may decrease.

[0023] Hydrogen generated during the formation of the Ni plating layer is a common by-product in the electroplating process. If it diffuses into the interior of the device, it can cause deterioration of insulation resistance and potentially lead to malfunction.

[0024] In the case of a Ni plating layer, the hydrogen diffusion anisotropy may be large depending on the crystallographic properties. Therefore, in one embodiment of the present invention, by controlling the Texture Coefficient (TC) value of the Ni plating layers 131b and 132b so that TC(200) is the largest among TC(111), TC(200), and TC(220), it is possible to suppress the penetration of hydrogen generated during the plating process and hydrogen from the external environment.

[0025] The following describes the various components included in the stacked electronic component 100 according to one embodiment of the present invention.

[0026] The main body 110 may have dielectric layers 111 and internal electrodes 121 and 122 stacked alternately.

[0027] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 is not a perfectly straight hexahedron, but can be substantially hexahedral.

[0028] The main body 110 may have a first surface 1 and a second surface 2 facing each other in the thickness direction (X direction), a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in the length direction (Y direction), and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in the width direction (Z direction).

[0029] As margin regions where internal electrodes 121 and 122 are not placed overlap the dielectric layer 111, steps are created due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface with the third, fourth, and fifth surfaces and / or the corners connecting the second surface with the third, fourth, and fifth surfaces may have a form that is contracted toward the center in the thickness direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 and / or the corners connecting the second surface 2 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 may have a form that is contracted toward the center in the thickness direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the main body 110 can be rounded by performing a separate process to round the corners connecting the first face with the third, fourth, fifth, and sixth faces, and / or the corners connecting the second face with the third, fourth, fifth, and sixth faces.

[0030] On one hand, in order to suppress the step formed by the internal electrodes 121 and 122, after cutting such that the internal electrodes after lamination are exposed on the fifth surface 5 and the sixth surface 6 of the main body, when laminating a single dielectric layer or two or more dielectric layers in the width direction on both side surfaces of the capacitance forming portion Ac to form the margin portions 114 and 115, the portions connecting the first surface to the fifth and sixth surfaces, and the portions connecting the second surface to the fifth and sixth surfaces do not necessarily have a shrunk form.

[0031] The plurality of dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM). The number of laminated dielectric layers is not particularly limited and can be determined in consideration of the size of the multilayer electronic component. For example, 400 or more dielectric layers can be laminated to form the main body.

[0032] The dielectric layer 111 can be formed by manufacturing a ceramic slurry containing ceramic powder, an organic solvent, and a binder, applying and drying the slurry on a carrier film to provide a ceramic green sheet, and then firing the ceramic green sheet. The ceramic powder is not particularly limited as long as sufficient capacitance can be obtained. For example, barium titanate-based (BaTiO3) powder can be used as the ceramic powder. More specifically, the ceramic powder can be one or more of BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba[[ID=)) 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) and Ba(Ti 1-y Zr y )O3 (0 < y < 1). [[ID=))

[0033] The average thickness td of the dielectric layer 111 does not need to be particularly limited, but can be, for example, 0.01 μm to 10 μm. Furthermore, the average thickness td of the dielectric layer 111 can be arbitrarily set according to the desired characteristics and application. For example, in the case of small IT electronic components, the average thickness td of at least one of the multiple dielectric layers 111 may be 1.5 μm or less in order to achieve miniaturization and high capacitance.

[0034] Here, the average thickness td of the dielectric layer 111 can refer to the size of the dielectric layer 111 in the X direction (thickness direction) that is placed between the internal electrodes 121 and 122. The average thickness of the dielectric layer 111 can be measured by scanning the cross-section (LT cross-section) of the main body 110 in the length direction and thickness direction with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the thickness of a single dielectric layer 111 can be measured at multiple points, for example, at 30 points equally spaced in the length direction, and the average value can be measured. The 30 equally spaced points can be specified in the capacitance forming section Ac described later. Furthermore, by extending such average value measurement to 10 dielectric layers 111 and measuring the average value, the average thickness of the dielectric layer 111 can be further generalized.

[0035] The main body 110 may include a capacitance forming section Ac which is disposed inside the main body 110 and includes a first internal electrode 121 and a second internal electrode 122 which are arranged to face each other with a dielectric layer 111 in between, and cover sections 112 and 113 which are formed on the upper and lower parts of the capacitance forming section Ac in the first direction.

[0036] Furthermore, the capacitance-forming portion Ac can be formed by repeatedly stacking multiple first internal electrodes 121 and second internal electrodes 122 with a dielectric layer 111 in between, as a portion that contributes to the capacitance formation of the capacitor.

[0037] The cover portions 112 and 113 may include an upper cover portion 112 positioned above the volume-forming portion Ac in the X direction and a lower cover portion 113 positioned below the volume-forming portion Ac in the X direction.

[0038] The upper cover portion 112 and the lower cover portion 113 described above can be formed by stacking a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, respectively, and can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0039] The upper cover portion 112 and the lower cover portion 113 described above do not include internal electrodes and may contain the same material as the dielectric layer 111.

[0040] In other words, the upper cover portion 112 and the lower cover portion 113 may include a ceramic material, for example, a barium titanate (BaTiO3) based ceramic material.

[0041] On the other hand, the thickness of the cover portions 112 and 113 is not particularly limited. However, in order to more easily achieve miniaturization and high capacitance of the stacked electronic component, the thickness tc of the cover portions 112 and 113 may be 60 μm or less.

[0042] The average thickness tc of the cover portions 112 and 113 can represent the size in the X direction, and may be the average value of the X-direction size of the cover portions 112 and 113 measured at five equally spaced points on the upper or lower part of the volume forming portion Ac.

[0043] Furthermore, margin portions 114 and 115 can be arranged on the side surface of the volume-forming portion Ac.

[0044] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface 5 of the main body 110 and a second margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 can be located on both end surfaces in the width direction of the ceramic main body 110.

[0045] As shown in Figure 3, the margin portions 114 and 115 can refer to the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the main body 110 in the width-thickness (WT) direction.

[0046] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0047] The margin portions 114 and 115 may be formed by applying conductive paste to the ceramic green sheet, except where the margin portions are formed, to form internal electrodes.

[0048] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, after cutting the laminated internal electrodes so that they are exposed on the fifth surface 5 and sixth surface 6 of the main body, a single dielectric layer or two or more dielectric layers can be laminated on both sides of the capacitance forming portion Ac in the Z direction (width direction) to form margin portions 114 and 115.

[0049] On the other hand, the width of the margin portions 114 and 115 does not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the average width of the margin portions 114 and 115 may be 45 μm or less.

[0050] The average width of margin portions 114 and 115 can represent the average size in the Z direction of the region where the internal electrode is separated from the fifth surface and the average size in the Z direction of the region where the internal electrode is separated from the sixth surface, and can be the average value of the Z-direction size of margin portions 114 and 115 measured at five equally spaced points on the side surface of the capacitance forming portion Ac.

[0051] Therefore, in one embodiment, the average size MW1 and MW2 in the third direction of the region where the internal electrodes 121 and 122 are separated from the fifth and sixth surfaces may be 45 μm or less, respectively.

[0052] On the other hand, if a magnetic material is applied to the main body 110 instead of a dielectric material, the multilayer electronic component can function as an inductor. The magnetic material may be, for example, ferrite and / or metallic magnetic particles. When the multilayer electronic component functions as an inductor, the internal electrodes may be coiled conductors.

[0053] Furthermore, if a piezoelectric material is applied to the main body 110 instead of a dielectric material, the multilayer electronic component can function as a piezoelectric element. The piezoelectric material may be, for example, PZT (lead zirconate titanate).

[0054] Furthermore, if a ZnO-based or SiC-based material is applied to the main body 110 instead of a dielectric material, the multilayer electronic component can function as a varistor, and if a spinel-based material is applied to the main body 110 instead of a dielectric material, the multilayer electronic component can function as a thermistor.

[0055] In other words, the multilayer electronic component 100 according to one embodiment of the present invention can function not only as a multilayer ceramic capacitor, but also as an inductor, piezoelectric element, varistor, or thermistor by appropriately changing the material and structure of the main body 110.

[0056] The internal electrodes 121 and 122 can be arranged alternately with respect to the dielectric layer 111. For example, a pair of electrodes, the first internal electrode 121 and the second internal electrode 122, having opposite polarities, can be arranged facing each other with the dielectric layer 111 in between. The first internal electrode 121 and the second internal electrode 122 can be electrically isolated from each other by the dielectric layer 111 placed between them. In this case, the internal electrodes 121 and 122 can be arranged alternately with respect to the dielectric layer 111 in the X direction.

[0057] The first internal electrode 121 may be separated from the fourth surface 4 and extend toward the third surface 3. The second internal electrode 122 may be separated from the third surface 3 and extend toward the fourth surface 4. The first internal electrode 121 can be electrically connected to the first external electrode 131 on the third surface 3 side, and the second internal electrode 122 can be electrically connected to the second external electrode 132 on the fourth surface 4 side.

[0058] The conductive metals contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, Sn, W, Ti, and alloys thereof. For example, the internal electrodes 121 and 122 may contain Ni as the main component, and containing Ni as the main component means that when analyzing the cross-section of the internal electrode with SEM-EDS, the area ratio of Ni to the total area of ​​the internal electrode is 90% or more.

[0059] The method for forming the internal electrodes 121 and 122 is not particularly limited. For example, the internal electrodes 121 and 122 can be formed by applying a conductive paste for internal electrodes containing a conductive metal onto a ceramic green sheet and firing it. The method for applying the conductive paste for internal electrodes can be screen printing or gravure printing, but the present invention is not limited thereto.

[0060] The average thickness te of the internal electrodes 121 and 122 does not need to be particularly limited, but may be, for example, 0.01 μm to 3 μm. Furthermore, the average thickness te of the internal electrodes 121 and 122 can be arbitrarily set according to the desired characteristics and application. For example, in the case of small IT electronic components, in order to achieve miniaturization and high capacitance, the average thickness te of at least one of the multiple internal electrodes 121 and 122 may be 0.8 μm or less.

[0061] Here, the average thickness te of the internal electrodes can be measured by scanning the longitudinal and thickness-direction cross-sections (LT cross-sections) of the main body 110 with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the thickness of one internal electrode 121, 122 can be measured at multiple points, for example, 30 points equally spaced in the Y direction, and the average value can be measured. The 30 equally spaced points can be specified in the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 internal electrodes 121, 122 and measuring the average value, the average thickness of the internal electrodes 121, 122 can be further generalized.

[0062] External electrodes 131 and 132 can be placed on the main body 110.

[0063] As shown in Figure 2, the external electrodes 131 and 132 may include a first external electrode 131 positioned on the third surface of the main body 110 and connected to the first internal electrode 121, and a second external electrode 132 positioned on the fourth surface 4 of the main body 110 and connected to the second internal electrode 122.

[0064] In this embodiment, a structure in which the stacked electronic component 100 has two external electrodes 131 and 132 is described, but the number and shape of the external electrodes 131 and 132 can be changed depending on the form of the internal electrodes 121 and 122 and other purposes.

[0065] The external electrodes 131 and 132 include Ni plating layers 131b and 132b, respectively, and the Ni plating layer can have the largest Texture Coefficient (TC) value among TC(111), TC(200), and TC(220), with TC(200) being the largest.

[0066] In the case of a nickel plating layer, due to its crystallographic properties, the hydrogen diffusion anisotropy is large. When TC(200) is the largest among TC(111), TC(200), and TC(220), the nickel plating layer can act as a hydrogen barrier and suppress hydrogen diffusion.

[0067] The Texture Coefficient (TC) value of a nickel-plated layer is one of the important indicators used in materials science and surface engineering to evaluate the crystal structure and orientation of the plated layer. Texture Coefficient (TC) can mean the microstructure coefficient or texture coefficient. TC can be measured via X-ray diffraction (XRD) analysis and can numerically represent how predominantly a particular crystal plane (hk1) is oriented in the plated layer, allowing for an understanding of the microstructure and physical properties of the plated layer.

[0068] In the case of a Ni plating layer, it generally has an FCC (face-centered cubic) structure, and the main diffraction planes of an FCC structure are the (111), (200), and (220) planes. Therefore, the fact that TC(200) is the largest among TC(111), TC(200), and TC(220) means that the (220) plane is the most predominantly oriented of the main diffraction planes.

[0069] On the other hand, the Texture Coefficient can be calculated using the following formula 1.

number

[0070] In Equation 1 above, TC(hkl) represents the Texture Coefficient of the crystal plane (hkl), I(hkl) represents the diffraction peak intensity of the crystal plane (hkl) in the measured XRD data, and I0(hkl) represents the diffraction peak intensity of the crystal plane (hkl) in the standard JCPDS data.

[0071] Furthermore, in Equation 1 above, N represents the total number of diffraction planes to be considered, and Σ(I(hkl) / I0(hkl)) can represent the sum of the relative intensities across all (hkl) planes.

[0072] First, the diffraction pattern of the Ni plating layer is obtained by XRD analysis. From the XRD data, the intensity (I(hkl)) at multiple diffraction planes (Miller indices, e.g., (111), (200), (220)) is obtained. This indicates the degree to which the crystal structure within the plating layer is aligned in a specific direction.

[0073] After this, the intensity value (I0(hkl)) for the same diffraction plane can be confirmed using standard data for Ni standard powder provided by ICDD (International Centre for Diffraction Data).

[0074] Next, the sum of the relative intensities calculated for all diffraction surfaces is obtained, and then this is divided by the total number of diffraction surfaces (N) to calculate the average value. The above average value represents the average crystal intensity of the entire sample.

[0075] Finally, the Texture Coefficient for each diffraction surface can be calculated using Equation 1 above.

[0076] If the calculated value of TC(hkl) is greater than 1, it can be said that texture was formed (dominant crystal growth occurred) in the direction in question (hkl). If the calculated value of TC(hkl) is 1, it can be said that there is an ideal random distribution. If the calculated value of TC(hkl) is less than 1, it can be said that little crystal growth occurred in the direction in question.

[0077] On the other hand, the Texture Coefficient (TC) values ​​of the Ni plating layers 131b and 132b may be values ​​for the (111), (200), and (220) planes, which are the main diffraction planes of the Ni plating layers 131b and 132b.

[0078] That is, the above TC(111), TC(200), and TC(220) are defined as follows: TC(111)={I(111) / I0(111)} / [1 / 3*{I(111) / I0(111)+I(200) / I0(200)+I(220) / I0(220)}], TC(200)={I(200) / I0(200)} / [1 / 3*{I(111) / I0(111)+I(200) / I0(200)+I(220) / I0(220)}], and TC(220)={I(22 The formula satisfies {I(111) / I0(111)+I(200) / I0(200)+I(220) / I0(220)}, where I(111), I(200), and I(220) are the diffraction peak intensities of the (111), (200), and (220) planes obtained from the XRD analysis data of the Ni plating layer, respectively, and I0(111), I0(200), and I0(220) are the diffraction peak intensities of the (111), (200), and (220) planes of Ni standard powder provided by ICDD (International Centre for Diffraction Data), respectively.

[0079] On the other hand, the values ​​for TC(111), TC(200), and TC(220) of the Ni plating layers 131b and 132b can vary depending on the number of diffracted surfaces analyzed. When TC(200) is the largest value among the values ​​for TC(111), TC(200), and TC(220) of the Ni plating layers 131b and 132b, the Ni plating layer acts as a hydrogen barrier, suppressing hydrogen diffusion. Therefore, there is no need to specifically limit the values ​​for TC(111), TC(200), and TC(220).

[0080] For example, when the Texture Coefficient (TC) values ​​of the Ni plating layers 131b and 132b are values ​​for the (111), (200), and (220) planes, which are the main diffraction planes of the Ni plating layers 131b and 132b, the above TC(200) can be 1.2 or higher. This makes it possible to further improve the hydrogen diffusion suppression effect according to the present invention.

[0081] In this case, the above TC(220) may be 1.0 or less.

[0082] Furthermore, TC(111) may be 0.5 or greater relative to TC(220).

[0083] On the other hand, when (200)Factor = TC(200) / [{TC(111)+TC(220)} / 2], the above Ni plating layer may have a (200)Factor greater than 1. The (200)Factor is the value corresponding to TC(200) relative to the average value of TC(111) and TC(220), and when the (200)Factor is greater than 1.0, the hydrogen diffusion suppression effect of the Ni plating layer can be further improved.

[0084] Furthermore, the hydrogen diffusion suppression effect can be improved as the (200)Factor increases. In one embodiment, the Ni plating layers 131b and 132b may have a (200)Factor of 1.3 or higher. This further improves the hydrogen diffusion suppression effect of the Ni plating layers 131b and 132b. Therefore, it is more preferable that the Ni plating layers 131b and 132b have a (200)Factor of 1.3 or higher, and even more preferably that the Ni plating layers 131b and 132b have a (200)Factor of 1.5 or higher.

[0085] On the other hand, the method for forming the Ni plating layers 131b and 132b is not particularly limited. For example, they can be formed using the electroplating method. Furthermore, the method for controlling the Texture Coefficient (TC) value of the Ni plating layers 131b and 132b is not particularly limited. For example, by adjusting the current density among the various process conditions of electroplating, it is possible to control TC(200) to be the largest among TC(111), TC(200), and TC(220).

[0086] In one embodiment, the Ni plating layer can have an FCC (Face-Centered Cubic) structure. By having an FCC (Face-Centered Cubic) structure, the Ni plating layer can be clearly distinguished from NiO, which has a cubic crystal structure.

[0087] The crystal structure of the Ni plating layer can be confirmed by XRD analysis. When peaks are detected at diffraction angles (2θ) of 44.441°, 51.784°, and 76.276° relative to the Cu Kα line, it can be confirmed that it has an FCC (Face-Centered Cubic) structure. On the other hand, NiO has a cubic crystal structure, and peaks can be detected at diffraction angles (2θ) of 37°, 43°, and 62°.

[0088] In one embodiment, the Ni plating layer may have an atomic percentage of Ni of 95 at% or more. This can be interpreted as meaning that the Ni plating layer is substantially composed of Ni as it is formed by the plating process. It can also be clearly distinguished from NiO, which has an atomic percentage of O of 50 at%. The atomic percentage of Ni can be confirmed by analyzing the Ni plating layer using SEM-EDS.

[0089] In one embodiment, the external electrodes 131 and 132 are connected to the internal electrodes 121 and 122 and may further include electrode layers 131a and 132a located beneath the Ni plating layers 131b and 132b, and additional plating layers 131c and 132c located on top of the Ni plating layers. That is, the external electrodes 131 and 132 may be configured such that the electrode layers 131a and 132a, the Ni plating layers 131b and 132b, and the additional plating layers 131c and 132c are arranged sequentially.

[0090] To give a more specific example for the electrode layers 131a and 132a, the electrode layers 131a and 132a may be firing electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0091] Furthermore, the electrode layers 131a and 132a may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Also, the electrode layers 131a and 132a may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto the fired electrode.

[0092] The conductive metal contained in the electrode layers 131a and 132a can be any material with excellent electrical conductivity, and is not particularly limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and their alloys.

[0093] The additional plating layers 131c and 132c can serve to improve mountability. The type of additional plating layers 131c and 132c is not particularly limited and can be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and can be formed in multiple layers.

[0094] To give a more specific example of the additional plating layers 131c and 132c, the additional plating layers 131c and 132c may be Sn plating layers or Pd plating layers, and may be in a form in which Sn plating layers, Ni plating layers and Sn plating layers are formed sequentially.

[0095] There is no particular limit to the size of the stacked electronic component 100.

[0096] However, the smaller the size of the multilayer electronic component 100, the easier hydrogen penetration can be. In particular, when the size of the multilayer electronic component 100 is 1005 (length × width, 1.0 mm × 0.5 mm) or less, it is necessary to further improve the hydrogen penetration suppression effect. Considering manufacturing tolerances, external electrode size, etc., when the maximum length of the multilayer electronic component 100 is 1.1 mm or less and the maximum width is 0.55 mm or less, it is necessary to further improve the hydrogen diffusion suppression effect according to the present invention.

[0097] Therefore, in one embodiment, the multilayer electronic component 100 has a maximum length of 1.1 mm or less, a maximum width of 0.55 mm or less, and the above TC(200) may be 1.3 or more. Also, in one embodiment, the multilayer electronic component 100 has a maximum length of 1.1 mm or less, a maximum width of 0.55 mm or less, and when (200)Factor = TC(200) / [{TC(111) + TC(220)} / 2], the above Ni plating layer may have a (200)Factor of 1.5 or more.

[0098] However, the hydrogen suppression effect according to the present invention is also effective for large-sized chips, and the hydrogen diffusion suppression effect according to the present invention can be confirmed even in stacked electronic components having a size of 1608 (length × width, 1.6 mm × 0.8 mm) or larger. Therefore, in one embodiment, the stacked electronic component may have a maximum length of 1.44 mm or more and a maximum width of 0.72 mm or more.

[0099] On the other hand, the Ni plating layers 131b and 132b do not need to be spaced apart on the exposed surfaces of the internal electrodes, as shown in Figure 2.

[0100] Referring to Figure 9, which corresponds to Figure 2 according to another embodiment of the present invention, the Ni plating layers 131b-1 and 132b-1 are arranged in contact with the main body 110 and can directly contact the internal electrodes 121 and 122. By arranging the Ni plating layers 131b-1 and 132b-1 in contact with the main body 110, the hydrogen diffusion suppression effect according to the present invention can be further improved.

[0101] Furthermore, the external electrodes 131-1 and 132-1 may further include electrode layers 131a-1 and 132a-1 disposed on the Ni plating layers 131b-1 and 132b-1.

[0102] In this case, the external electrodes 131-1 and 132-1 may further include additional Ni plating layers 131b-2 and 132b-2 disposed on the electrode layers 131a-1 and 132a-1. This further improves the hydrogen diffusion suppression effect according to the present invention. In this case, the additional Ni plating layers 131b-2 and 132b-2 may have a Texture Coefficient (TC) value of TC(111), TC(200), and TC(220) with TC(200) being the largest.

[0103] Furthermore, additional plating layers 131c-1, 132c-1 disposed on the additional Ni plating layers 131b-2, 132b-2 may be further included. The additional plating layers 131c-1, 132c-1 may be Sn plating layers.

[0104] Manufacturing method for multilayer electronic components The following describes an example of a method for manufacturing a stacked electronic component 100 according to one embodiment of the present invention. However, the method for manufacturing the stacked electronic component 100 of the present invention is not limited thereto.

[0105] First, a ceramic slurry containing ceramic powder, an organic solvent, and a binder is applied to a carrier film to prepare a ceramic green sheet.

[0106] Subsequently, a conductive paste for internal electrodes containing metal powder, binder, organic solvent, etc., is printed onto the ceramic green sheet to a predetermined thickness using screen printing or gravure printing to form an internal electrode pattern, thereby manufacturing a ceramic green sheet for capacitance formation.

[0107] A laminate can be obtained by stacking ceramic green sheets for the volume-forming section in the X direction. At this time, ceramic green sheets without internal electrode patterns can be stacked on the upper and lower parts of the laminate in order to form cover sections 112 and 113 after sintering.

[0108] After this, the laminate can be cut to obtain a unit laminate having a predetermined chip size.

[0109] After this, the unit laminate can be sintered to obtain the main body. The sintering temperature can be, for example, 1000°C to 1400°C, but the present invention is not limited thereto.

[0110] Next, external electrodes 131 and 132 are formed. For example, if the external electrodes 131 and 132 include electrode layers 131a and 132a, and the electrode layers 131a and 132a are fired electrodes, the main body 110 can be dipped in a conductive paste for external electrodes containing metal powder, glass frit, binder, and organic solvent, and then the conductive paste for external electrodes can be fired at a temperature of 500°C to 900°C to form a fired electrode layer.

[0111] Furthermore, if the electrode layers 131a and 132a are resin electrode layers, the main body can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then cured at a temperature of 250°C to 550°C to form the resin electrode layer.

[0112] Subsequently, Ni plating layers 131b and 132b can be formed using the electroplating method. At this time, by adjusting the current density among the various process conditions of electroplating, it is possible to control the current so that TC(200) is the largest among TC(111), TC(200), and TC(220).

[0113] Subsequently, Sn plating layers 131c and 132c can be formed on the Ni plating layers 131b and 132b using an electrolytic plating method.

[0114] (Example of experiment) Using the manufacturing method described above, sample chips of size 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm, thickness: approximately 0.5 mm) were prepared. At this time, when forming the Ni plating layers 131b and 132b, the current density was varied so that the TC values ​​differed as shown in Table 1 below.

[0115] XRD analysis was performed on test specimens with a Ni plating layer obtained from each sample chip. The measurement conditions were [Target: Cu Kα, 2θ interval: 0.01°, 2θ scan speed: 3° / min], and an XRD graph like the one in Figure 5 was obtained. In Figure 5, the Y axis represents intensity in arbitrary units, and the X axis represents diffraction angle (2θ) in degrees.

[0116] I(111), I(200), and I(220) were obtained from the XRD graph, and TC(111), TC(200), and TC(220) were calculated using Equation 1 above, with I0(111), I0(200), and I0(220) of the Ni standard powder provided by ICDD (International Centre for Diffraction Data). These results are listed in Table 1 below, and Figures 6 and 7 show the TC values ​​for each test number graphically.

[0117] Furthermore, the (200)Factor calculated using (200)Factor=TC(200) / [{TC(111)+TC(220)} / 2] is listed in Table 1 below.

[0118] [Table 1]

[0119] First, referring to Figure 5, peaks are detected at diffraction angles (2θ) 44.441°, 51.784°, and 76.276°, confirming that all of the samples from test numbers 1 to 3 have an FCC (Face-Centered Cubic) structure. In Figure 5, the diffraction peak intensity at diffraction angle (2θ) 44.441° is for the (111) plane, the diffraction peak intensity at diffraction angle (2θ) 51.784° is for the (200) plane, and the diffraction peak intensity at diffraction angle (2θ) 76.276° is for the (220) plane.

[0120] Referring to Table 1 above, it can be confirmed that for test numbers 1 and 2, TC(200) is the largest among TC(111), TC(200), and TC(220). For test numbers 3 to 8, TC(220) is the largest among TC(111), TC(200), and TC(220). Referring to Figures 6 and 7, which show the TC values ​​in graph form, it can be confirmed that for test numbers 5 to 8, TC(220) is significantly larger than TC(111) and TC(200), and that test numbers 3 and 4 also have TC values ​​that differ from those of test numbers 1 and 2.

[0121] To confirm the hydrogen diffusion suppression effect, the insulation resistance was measured for test number 3, which had the largest TC(200) value of 1.0 among test numbers 3-8, and for test numbers 1 and 2, which had the largest TC(200) value among TC(111), TC(200), and TC(220), and is shown in Figure 8. Ten sample chips were prepared for each test number, and after hydrogen charging, the insulation resistance (IR) was measured for more than 2 hours under conditions of a temperature of 105°C and a voltage of 10V. For hydrogen charging, after mounting the chip on a substrate, the chip itself was used as the cathode and water electrolysis was performed in a 0.01M NaOH solution at 60mA for 1 hour.

[0122] Referring to Figure 8(a), which is the insulation resistance graph for test number 3, it can be confirmed that a decrease in insulation resistance occurred in four sample chips, and that the insulation resistance (IR) of two sample chips fell to less than 1 / 10 of the initial value, indicating deterioration in insulation resistance.

[0123] Referring to Figure 8(b), which is a graph for test number 1, it can be confirmed that a decrease in insulation resistance occurred in two sample chips, and the number of sample chips in which the insulation resistance (IR) dropped to less than 1 / 10 of the initial value was one. This can be interpreted as the hydrogen diffusion suppression effect increasing by more than twice compared to test number 3.

[0124] Referring to Figure 8(c), which is a graph for test number 2, it can be confirmed that there is almost no decrease in insulation resistance in all sample chips, which can be interpreted as indicating a remarkably excellent hydrogen diffusion suppression effect.

[0125] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0126] Furthermore, the expression "one embodiment" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and describe the unique and distinct features of each embodiment. However, the present embodiments are not excluded from being realized in combination with features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or is inconsistent with that matter.

[0127] The terms used in this disclosure are used solely to describe one embodiment and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0128] 100 Stacked Electronic Components 110 Main Unit 111 Dielectric layer 112, 113 Cover section 114, 115 Margin section 121, 122 Internal electrode 131, 132 External electrode 131a, 132a electrode layer 131b, 132b Ni plating layer 131c, 132c Additional plating layer

Claims

1. A main body including a dielectric layer and internal electrodes, The body includes an external electrode disposed on the main body, The external electrode includes a Ni plating layer. The Ni plating layer is a multilayer electronic component in which the Texture Coefficient (TC) value is highest at TC(200) among TC(111), TC(200), and TC(220).

2. The aforementioned TC(111), TC(200) and TC(220) are, TC(111)={I(111) / I ０ (111)} / [1 / 3*{I(111) / I ０ (111)+I(200) / I ０ (200)+I(220) / I ０ (220)}]、 TC(200) = {I(200) / I ０ (200)} / [1 / 3*{I(111) / I ０ (111)+I(200) / I ０ (200)+I(220) / I ０ (220)}], and TC(220) = {I(220) / I ０ (220)} / [1 / 3 * {I(111) / I ０ (111) + I(200) / I ０ (200) + I(220) / I ０ (220)}] is satisfied, The I(111), I(200), and I(220) mentioned above are the diffraction peak intensities of the (111), (200), and (220) planes obtained from the XRD analysis data of the Ni plating layer, respectively. The above I ０ (111), I ０ (200) and I ０ The stacked electronic component according to claim 1, wherein (220) is the diffraction peak intensity of the (111) plane, the (200) plane, and the (220) plane of a Ni standard powder provided by the International Centre for Diffraction Data (ICDD), respectively.

3. The stacked electronic component according to claim 1, wherein the TC(200) is 1.2 or more.

4. The stacked electronic component according to claim 1, wherein the TC(220) is 1.0 or less.

5. The stacked electronic component according to claim 1, wherein TC(111) is 0.5 or more relative to TC(220).

6. When (200)Factor = TC(200) / [{TC(111) + TC(220)} / 2], The stacked electronic component according to claim 1, wherein the Ni plating layer has a (200) Factor greater than 1.

0.

7. The stacked electronic component according to claim 6, wherein the Ni plating layer has a (200) Factor of 1.3 or more.

8. The stacked electronic component according to claim 6, wherein the Ni plating layer has a (200) Factor of 1.5 or more.

9. The stacked electronic component according to claim 1, wherein the Ni plating layer has an FCC (Face-Centered Cubic) structure.

10. The multilayer electronic component according to claim 1, wherein the Ni plating layer has an atomic percentage of Ni of 95 at% or more.

11. The aforementioned stacked electronic component has a maximum length of 1.1 mm or less and a maximum width of 0.55 mm or less. The stacked electronic component according to claim 1, wherein the TC(200) is 1.3 or more.

12. The aforementioned stacked electronic component has a maximum length of 1.1 mm or less and a maximum width of 0.55 mm or less. When (200)Factor = TC(200) / [{TC(111) + TC(220)} / 2], The stacked electronic component according to claim 1, wherein the Ni plating layer has a (200) Factor of 1.5 or more.

13. The stacked electronic component according to claim 1, wherein the stacked electronic component has a maximum length of 1.44 mm or more and a maximum width of 0.72 mm or more.

14. The stacked electronic component according to claim 1, wherein the external electrode is connected to the internal electrode and further includes an electrode layer disposed beneath the Ni plating layer and an additional plating layer disposed on the Ni plating layer.

15. The Ni plating layer is arranged to be in contact with the main body and in direct contact with the internal electrode, according to any one of claims 1 to 14.

16. The stacked electronic component according to claim 15, wherein the external electrode further includes an electrode layer disposed on the Ni plating layer.

17. The stacked electronic component according to claim 16, wherein the external electrode further comprises an additional Ni plating layer disposed on the electrode layer.

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