Solar cell, method for manufacturing the same, and photovoltaic power generation module

Abstract

By reducing parasitic absorption on the back of the solar cell, the current can be increased. In addition, this does not affect the contact performance between the back electrode and the back doping layer, extending the processing time and improving the efficiency and bifacial properties of the solar cell. [Solution] The solar cell comprises a silicon substrate, a tunnel passivation contact structure, and a second electrode. The silicon substrate has opposing first and second surfaces, and the second surface has alternately arranged first and second regions. The tunnel passivation contact structure is provided on the second surface, and the projection of the tunnel passivation contact structure on the second surface of the silicon substrate is located within the first region. The tunnel passivation contact structure includes a tunnel layer in direct contact with the silicon substrate, a second doping layer stacked on the tunnel layer, and a barrier layer and a third doping layer sequentially stacked on the second doping layer. The second electrode is located in the second region and is in contact with the third doping layer.

Description

[Technical Field]

[0001] This invention belongs to the field of photovoltaic cell technology, and more particularly to solar cells, methods for manufacturing the same, and photovoltaic power generation modules. [Background technology]

[0002] TOPCon (Tunnel Oxide Passivated Contact) is a solar cell structure. It involves sequentially forming an ultrathin tunnel oxide layer and a doped polycrystalline silicon layer on the back of the silicon substrate. TOPCon photocells exhibit excellent passivation effects and conductivity in both n+ and p+ polarity configurations, and are compatible with conventional industrial production methods. [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] The present invention aims to propose a solar cell, a method for manufacturing the same, and a photovoltaic power generation module in order to improve the efficiency of the photovoltaic cell by taking into account the passivation effect on the back surface and reducing parasitic absorption on the back surface. [Means for solving the problem]

[0004] To achieve the above objective, the technical means in one embodiment of the present invention are as follows:

[0005] A solar cell comprising a silicon substrate, a tunnel passivation contact structure, and a second electrode. The silicon substrate includes a first surface and a second surface facing each other. The second surface has alternating first and second regions. The tunnel passivation contact structure is provided on the second surface, and the projection of the tunnel passivation contact structure on the second surface of the silicon substrate is located within the first region. The tunnel passivation contact structure includes a tunnel layer in direct contact with the silicon substrate, a second doping layer stacked on the tunnel layer, and a barrier layer and a third doping layer sequentially stacked on the second doping layer. The doping types of the second and third doping layers are the same as those of the silicon substrate. The second electrode is located in the second region and is in contact with the third doping layer.

[0006] In one embodiment, the thickness of the third doping layer is equal to or greater than the thickness of the second doping layer.

[0007] In one embodiment, the total thickness of the second doping layer and the third doping layer is 50 nm to 150 nm or 60 nm to 100 nm.

[0008] In one embodiment, the thickness of the second doping layer is 1 nm to 100 nm, and the thickness of the third doping layer is 1 nm to 150 nm.

[0009] In one embodiment, the thickness of the second doping layer is 1 nm to 50 nm, and the thickness of the third doping layer is 50 nm to 100 nm.

[0010] In one embodiment, the solar cell further comprises a second passivation layer.

[0011] In one embodiment, the second passivation layer is in contact with the second surface of the silicon substrate in the second region, and the second passivation layer covers the third doping layer in the first region.

[0012] In one embodiment, the second passivation layer is an aluminum oxide passivation layer, and the thickness of the second passivation layer is 2 nm to 7 nm or 3 nm to 6 nm.

[0013] In one embodiment, the solar cell further includes a second antireflection layer stacked on the second passivation layer.

[0014] In one embodiment, the second antireflection layer is a laminated film formed of any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and the thickness of the laminated film is 60 nm to 130 nm.

[0015] In one embodiment, the silicon base layer is an N-type silicon base layer, and the second doping layer and the third doping layer are N-type doped polycrystalline silicon layers.

[0016] In one embodiment, the surface doping concentration of the third doping layer is not less than the surface doping concentration of the second doping layer.

[0017] In one embodiment, the surface doping concentration of the second doping layer is 3E20 cm

[0021] , , , , ,

[0020] ~3E21 cm -3 or 5E20 cm -3 ~2E21 cm -3 is.

[0018] In one embodiment, the surface doping concentration of the third doping layer is 3E20 cm -3 ~3E21 cm -3 or 5E20 cm -3 ~2E21 cm -3 is.

[0019] In one embodiment, the tunnel layer is a combination of any one or more of a silicon oxide layer and a silicon oxynitride layer.

[0020] In one embodiment, the thickness of the tunnel layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

[0021] In one embodiment, the barrier layer is any one or a combination of a silicon oxide layer and a silicon carbide layer.

[0022] In one embodiment, the thickness of the barrier layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

[0023] In one embodiment, a first doping layer and a first electrode are formed on the first surface of the silicon base layer.

[0024] In one embodiment, the doping type of the first doping layer is opposite to the doping type of the silicon base layer, and the first electrode contacts the first doping layer.

[0025] In one embodiment, the first doping layer is a P-type doping layer.

[0026] In one embodiment, the surface doping concentration of the first doping layer is 3E18 cm -3 ~3E19 cm -3 .

[0027] In one embodiment, a first passivation layer and / or a first antireflection layer are stacked on the first passivation layer.

[0028] In one embodiment, the first passivation layer is an aluminum oxide passivation layer, the thickness of the first passivation layer is 2 nm to 7 nm or 3 nm to 6 nm, the first antireflection layer is a stacked film formed of any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and the thickness of the stacked film is 60 nm to 130 nm.

[0029] In one embodiment, a plurality of first regions are parallel to each other, a plurality of second regions are parallel to each other, the plurality of first regions and the plurality of second regions are arranged alternately, the second electrode has a plurality of gate lines arranged in parallel, the plurality of gate lines of the second electrode correspond one-to-one with the plurality of first regions, and the width of each first region is not less than the width of each gate line.

[0030] In one embodiment, the width of each first region is 50 μm to 150 μm, and the width of each gate line is 15 μm to 100 μm.

[0031] In one embodiment, a pyramidal texture surface structure is formed on the first surface of the silicon substrate.

[0032] In one embodiment, the second surface of the silicon substrate is a polished surface.

[0033] The technical means in another embodiment of the present invention are as follows:

[0034] A method for manufacturing a solar cell, comprising the steps of: providing a silicon substrate, placing opposing first and second surfaces on the silicon substrate, and alternately arranging first and second regions on the second surface; forming a tunnel passivation contact structure on the second surface, and sequentially stacking a tunnel layer, a second doping layer, a barrier layer, and a third doping layer on the tunnel passivation contact structure; removing the tunnel passivation contact structure in the second region, leaving the tunnel passivation contact structure in the first region; and forming a second electrode that contacts the third doping layer on the tunnel passivation contact structure in the first region.

[0035] In one embodiment, before removing the tunnel passivation contact structure in the second region, the manufacturing method further includes the step of treating the third doping layer in the first region by laser to form an oxide layer on the surface of the third doping layer in the first region.

[0036] In one embodiment, the laser machining method is performed in an oxygen-containing atmosphere, where the volume concentration of oxygen is 20% to 80%.

[0037] In one embodiment, the laser output for the laser processing method is 1W to 100W or 30W to 60W.

[0038] In one embodiment, the laser frequency used in the laser machining method is 1kHz to 1000kHz or 300kHz to 600kHz.

[0039] In one embodiment, the scanning speed of the laser used in the laser construction method is 10,000 mm / s to 100,000 mm / s or 30,000 mm / s to 60,000 mm / s.

[0040] In one embodiment, the number of laser processing steps in the laser processing method is 1 to 100 or 1 to 10.

[0041] In one embodiment, the step of removing the tunnel passivation contact structure in the second region includes using an oxide layer as a mask film, removing the doping layer, barrier layer and third doping layer in the second region using an alkaline solution, and then removing the tunnel layer in the second region and the oxide layer in the first region using an acidic solution.

[0042] In one embodiment, the step of forming a tunnel passivation contact structure on the second surface includes sequentially depositing a tunnel layer, a first doped amorphous silicon layer, a barrier layer, and a second doped amorphous silicon layer on the second surface of a silicon substrate, and annealing the silicon substrate on which the tunnel layer, the first doped amorphous silicon layer, the barrier layer, and the second doped amorphous silicon layer are deposited at 880°C to 980°C to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer.

[0043] In one embodiment, the manufacturing method further includes the steps of forming a light trap structure on the first and second surfaces of a silicon substrate through a texture treatment, and polishing the second surface of the silicon substrate before forming a tunnel passivation contact structure.

[0044] In one embodiment, the manufacturing method further includes the steps of forming a first doping layer on a first surface, wherein the doping type of the first doping layer is the opposite of the doping type of the silicon substrate layer, and forming a first electrode on the first surface that is in contact with the first doping layer.

[0045] In one embodiment, the manufacturing method further includes the steps of forming a first passivation layer and a first anti-reflective layer on the first surface of a silicon substrate, and forming a second passivation layer and a second anti-reflective layer on the second surface of a silicon substrate.

[0046] The technical means in yet another embodiment of the present invention are as follows:

[0047] A photovoltaic power generation module characterized by comprising the aforementioned solar cell. [Effects of the Invention]

[0048] The present invention has the following beneficial effects compared to the current technology.

[0049] In the back surface of the solar cell according to the present invention, only tunnel passivation contact structures are stacked in the metal region, and there are no tunnel passivation contact structures in the non-metal region. This reduces parasitic absorption on the back surface of the solar cell, significantly increasing the current. In addition, it does not affect the contact performance between the back electrode and the back doping layer, extending the processing time and significantly improving the efficiency and bifacial properties of the solar cell.

[0050] The tunnel passivation contact structure in the back metal region comprises two doping layers and one barrier layer. The barrier layer plays a role in preventing the back electrode paste from penetrating to some extent, further reducing the total thickness of the back doping layer, which in turn increases the open-circuit voltage of the solar cell and improves its efficiency.

[0051] In the non-metallic region on the back of the solar cell, the passivation effect on the back of the solar cell is increased via the second passivation layer. In addition, the second passivation layer acts to some extent to inhibit the electrode paste on the back, which may further reduce the total thickness of the doping layer in the metallic region. This increases the short-circuit current density of the solar cell, assuming that it does not affect the metallization contact performance, and significantly improves the efficiency and bifacial properties of the solar cell. [Brief explanation of the drawing]

[0052] To better illustrate embodiments of the present invention or technical means in the existing art, we will now briefly illustrate the drawings required in the descriptions of embodiments or the existing art. It will be apparent that the drawings in the following descriptions represent only a portion of embodiments described in the present invention, and that it is possible for those skilled in the art to obtain other drawings by following these drawings, provided that they do not perform any creative work.

[0053] Figure 1 is a schematic diagram of the structure of a solar cell in Example 1 of the present invention.

[0054] Figure 2 is a schematic diagram of the structure in A of Figure 1.

[0055] Figure 3 is a schematic diagram of the second surface of the silicon substrate in Example 1 of the present invention.

[0056] Figure 4 is a schematic diagram of the second surface and second electrode in Embodiment 1 of the present invention.

[0057] Figures 5a to 5j are flowcharts of the manufacturing process of a solar cell according to Embodiment 1 of the present invention.

[0058] Figure 6 is a schematic diagram showing the laser scanning pattern of the laser machining method in Embodiment 1 of the present invention.

[0059] Figures 7a to 7c are flowcharts illustrating the process of preparing a first doping layer on the first surface of a silicon substrate in Embodiment 2 of the present invention.

[0060] Figures 8a to 8b are flowcharts showing the process of preparing a mask film in the first region in Embodiment 3 of the present invention. [Modes for carrying out the invention]

[0061] We now clearly and completely describe the technical means in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention, so that those skilled in the art may better understand the technical means of the present invention. It will be apparent that the embodiments described are only a part of the embodiments of the present invention and not all embodiments. All other embodiments obtained based on the embodiments of the present invention, on the premise that those skilled in the art do not perform any creative work, are all included within the scope of the protection of the present invention.

[0062] In this invention, unless otherwise specified, if the first feature is located "above" or "below" the second feature, the first feature may directly contact the second feature, or the first feature may indirectly contact the second feature via an intermediate medium. Furthermore, if the first feature is located "above," "above," and "above" the second feature, the first feature may be located directly above or diagonally above the second feature, or the height of the first feature may be greater than that of the second feature. If the first feature is located "above," "below," and "below" the second feature, the first feature may be located directly below or diagonally below the second feature, or the height of the first feature may be lower than that of the second feature.

[0063] The present invention discloses a solar cell. The solar cell comprises a silicon substrate, the silicon substrate having a first surface and a second surface facing each other, the second surface having alternating first and second regions, a tunnel passivation contact structure and a second electrode provided in a portion of the second surface, the projection of the tunnel passivation contact structure on the second surface of the silicon substrate located within the first region, the tunnel passivation contact structure comprising a tunnel layer in direct contact with the silicon substrate, a second doping layer stacked on the tunnel layer, and a barrier layer and a third doping layer sequentially stacked on the second doping layer, the doping type of the second and third doping layers being the same as the doping type of the silicon substrate, and the second electrode in contact with the third doping layer.

[0064] The present invention further discloses a method for manufacturing a solar cell.

[0065] The manufacturing method includes the steps of: providing a silicon substrate, placing opposing first and second surfaces on the silicon substrate, and alternately arranging first and second regions on the second surface; forming a tunnel passivation contact structure on the second surface, and sequentially stacking a tunnel layer, a second doping layer, a barrier layer, and a third doping layer on the tunnel passivation contact structure; removing the tunnel passivation contact structure in the second region and leaving the tunnel passivation contact structure in the first region; and forming a second electrode in the first region that contacts the third doping layer.

[0066] The present invention further discloses a photovoltaic module comprising the above-described solar cell.

[0067] In the back surface of the solar cell according to the present invention, only tunnel passivation contact structures are stacked in the metal region, and there are no tunnel passivation contact structures in the non-metal region. This reduces parasitic absorption on the back surface of the solar cell, significantly increasing the current. In addition, it does not affect the contact performance between the back electrode and the back doping layer, extending the processing time and significantly improving the efficiency and bifacial properties of the solar cell.

[0068] We will now further describe the present invention in combination with specific examples.

[0069] Example 1 Figure 1 is a schematic diagram of the structure of a solar cell in this embodiment. The solar cell is a TOPCon solar cell comprising a silicon substrate 10. Referring to Figure 5a, the silicon substrate 10 has a first surface S1 and a second surface S2 facing each other. The second surface S2 has a first region S21 and a second region S22. The first surface S1 is the front surface (i.e., the light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the back-light surface). The first region S21 is the back metal region, and the second region S22 is the back non-metal region.

[0070] In this embodiment, the silicon substrate 10 is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0071] Furthermore, a light-trapping structure is formed on the first surface S1 of the silicon substrate 10. For example, a pyramidal textured surface structure is formed on the first surface S1 of the silicon substrate 10 through alkaline texture treatment, with the pyramidal size being 0.5 μm to 3 μm. The second surface S2 of the silicon substrate 10 is a polished surface, which may be a surface formed after chemical polishing of the light-trapping structure, or a surface formed after chemical polishing is directly applied to the back surface of the original silicon substrate. For example, in this embodiment, a pyramidal textured surface structure with a size of 0.5 μm to 3 μm is formed on the second surface S2 of the silicon substrate 10 through alkaline texture treatment, and then the back surface is alkaline polished to obtain a polished surface. This polished surface may have multiple textured surface roots (i.e., roots remaining after polishing the pyramidal textured surface structure) compared to the back surface of a conventional silicon substrate.

[0072] In this embodiment, a first doping layer 11 (i.e., an emitter) is formed on the first surface S1 of the silicon substrate 10 by diffusion or PECVD, thereby forming a PN junction and generating electron-hole pairs after irradiation. For example, in this embodiment, the first doping layer 11 is a P-type doping layer (i.e., a P+ emitter) and is formed below the first surface S1 of the silicon substrate (i.e., inside the silicon substrate) through boron doping treatment, with a surface doping concentration of 3E18cm². -3 ~3E 19cm -3 The sheet resistance is 40Ω / sq to 300Ω / sq, preferably 150Ω / sq to 280Ω / sq.

[0073] When Figure 1 is combined with Figure 2, a tunnel passivation contact structure is formed only in the first region S21 of the second surface S2 of the silicon substrate 10, but there is no tunnel passivation contact structure in the second region S22.

[0074] Specifically, the tunnel passivation contact structure in the first region S21 has sequentially stacked tunnel layers 12, a second doping layer 13, a barrier layer 14, and a third doping layer 15. The projection of the tunnel passivation contact structure on the second surface S2 of the silicon substrate 10 is located in the first region S21. The tunnel layer 12 is in direct contact with the second surface S2 of the silicon substrate 10 in the first region S21, achieving a good surface passivation effect in the first region S21. The second doping layer 13 and the third doping layer 15 can achieve a field passivation effect, improve contact, and reduce resistance. Since there is no tunnel layer 12 or doping layer in the second region S22, the thickness of this region is significantly reduced, thereby lowering parasitic absorption of light rays on the back surface, improving the short-circuit current density of the solar cell, and significantly improving the efficiency and bifacial properties of the solar cell.

[0075] The tunnel layer 12 is made of silicon dioxide (SiO₂). X ) layer and silicon oxynitride (SiO X N YThe barrier layer 14 is a combination of one or two layers, preferably a silicon oxide layer, and the thickness of the tunnel layer is 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm. X It is a combination of one or two layers, a silicon dioxide (SiO2) layer and a silicon carbide (SiC) layer, preferably a silicon dioxide (SiO2) layer. X The barrier layer is a layer with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm.

[0076] The doping type of the second doping layer 13 and the third doping layer 15 is the same as the doping type of the silicon substrate layer. Furthermore, the surface doping concentration of the third doping layer 15 is greater than or equal to the surface doping concentration of the second doping layer 13, the thickness of the third doping layer 15 is greater than or equal to the thickness of the second doping layer 13, and the total thickness of the second doping layer 13 and the third doping layer 15 is 50 nm to 150 nm, preferably 60 nm to 100 nm. Specifically, the second doping layer 13 is a phosphorus-doped polycrystalline silicon layer with a surface doping concentration of 3E20 cm⁻¹. -3 ~3E 21cm -3 Preferably 5E20cm -3 ~2E21cm -3 The third doping layer 15 is a phosphorus-doped polycrystalline silicon layer, and the surface doping concentration is 3E20cm². The third doping layer 15 is a phosphorus-doped polycrystalline silicon layer, and the surface doping concentration is 3E20cm². -3 ~3E 21cm -3 Preferably 5E20cm -3 ~2E21cm -3 The thickness is 1 nm to 150 nm, preferably 50 nm to 100 nm.

[0077] In this invention, a tunnel passivation contact structure consisting of a tunnel layer / second doping layer / barrier layer / third doping layer is arranged only in the first region S21 (backside metal region) on the back of the silicon substrate, and a portion of the second region S22 (backside non-metal region) is removed. By stacking two doping layers in the first region S21, it is possible to avoid penetrating the doping layers and damaging the underlying tunnel layer 21 when sintering the electrode paste, thereby ensuring a field passivation effect. The thickness of the backside of the second region S22 is significantly reduced, thereby lowering parasitic absorption of light rays on the backside, improving the short-circuit current density of the solar cell, and significantly improving the efficiency and bifacial properties of the solar cell.

[0078] Furthermore, by introducing a barrier layer 14 between the second doping layer 13 and the third doping layer 15, the barrier layer 14 has the ability to prevent the electrode paste on the back from penetrating to some extent, making it possible to further reduce the total thickness of the second doping layer 13 and the third doping layer 15. For example, in this embodiment, it is possible to reduce the thickness to 60 nm to 100 nm, thereby further increasing the open-circuit voltage (Voc) of the solar cell and, consequently, further improving the efficiency of the solar cell.

[0079] The thickness of the barrier layer 14 in this embodiment significantly affects the manufacturing method of the solar cell and the performance of the solar cell. If the barrier layer 14 is too thin, it cannot reliably prevent the electrode paste on the back from penetrating through, and if the barrier layer 14 is too thick, it increases the effect of inhibiting phosphorus diffusion inward, affecting ohmic contact. Therefore, the thickness of the barrier layer 14 in this embodiment is limited to 0.5 nm to 3 nm, preferably 1.5 nm to 2 nm.

[0080] Preferably, in this embodiment, a first passivation layer 21 and a first anti-reflective layer 31 are sequentially stacked on the first surface S1 of the silicon substrate 10, and a second passivation layer 22 and a second anti-reflective layer 32 are sequentially stacked on the second surface S2 of the silicon substrate 10, with the second passivation layer 22 and the second anti-reflective layer 32 covering the second doping layer 13 and extending into the second region S22, where the second passivation layer 22 is in direct contact with the silicon substrate 10. The first passivation layer 21 can achieve excellent field passivation and chemical passivation effects, the second passivation layer 22 can achieve a chemical passivation effect, and the first anti-reflective layer 31 can reduce reflectivity and increase light utilization.

[0081] For example, both the first passivation layer 21 and the second passivation layer 22 are aluminum oxide passivation layers with a thickness of 2 nm to 7 nm, preferably 3 nm to 6 nm. The first anti-reflective layer 31 and the second anti-reflective layer 32 may be a laminated film formed on one or more of silicon nitride layers, silicon oxynitride layers, and silicon oxide layers, with a thickness of 60 nm to 130 nm, preferably both being silicon nitride layers. The silicon nitride layer is chemically inert, has strong corrosion resistance in alkali and acid resistance, and reduces the sensitivity of the solar cell to the environment.

[0082] Furthermore, in this embodiment, the first electrode 41 is located on the first surface S1 of the silicon substrate 10 and in contact with the first doping layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically in the first region S21 of the second surface S2 and in contact with the second doping layer 13.

[0083] As shown in Figure 3, in this embodiment, the first region S21 has a plurality of first dependent regions 101 arranged in parallel and spaced apart, the second region S22 has a plurality of second dependent regions 102 arranged in parallel and spaced apart, and the first dependent regions 101 and the second dependent regions 102 are arranged alternately. The width of the first dependent regions 101 is smaller than the width of the second dependent regions 102, for example, the ratio of the two is 1:(5~20), and preferably the first region S21 occupies about 10% of the total area of ​​the second surface S2.

[0084] As shown in Figure 4, the second electrode 42 is a gate line electrode and has at least a plurality of parallel-arranged thin gate lines 421, and the width of the first dependent region 101 is greater than or equal to the width of the thin gate lines 421. Preferably, the second electrode 42 may have a plurality of main gate lines (not shown) perpendicular to the thin gate lines 421.

[0085] In this embodiment, taking the 210TOPCon solar cell as an example, the size is 203.396 ± 15 mm, with 230 thin gate lines 421 arranged, each with a width of 15 μm to 100 μm, and the spacing between adjacent thin gate lines is 0.907 ± 0.015 mm. The spacing between adjacent first dependent regions 101 is equal to the spacing between adjacent thin gate lines, and one thin gate line 421 is arranged in each first dependent region 101. The width of the first dependent region 101 is greater than the width of the thin gate line 421, and the width of the first dependent region 101 is 50 μm to 150 μm. For example, the width of the thin gate line is 40 μm, and the width of the first dependent region is 80 μm.

[0086] The method for manufacturing a solar cell in this embodiment specifically includes the following steps.

[0087] 1. Texture processing on both sides As shown in Figure 5a, a silicon substrate 10 is provided, with opposing first surface S1 and second surface S2 placed on the silicon substrate 10, and a first region S21 and a second region S22 are arranged on the second surface S2. The first surface S1 is the front surface (i.e., the light-receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e., the back-light surface) of the silicon substrate 10, the first region S21 is the back metal region, and the second region S22 is the back non-metal region.

[0088] In this embodiment, the silicon substrate 10 is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0089] As shown in Figure 5b, in this embodiment, a pyramidal textured surface structure is formed on the first surface S1 and the second surface S2 of the silicon substrate 10 through alkaline texture treatment, and the size of the pyramids is 0.5 μm to 3 μm.

[0090] 2. Boron diffusion As shown in Figure 5c, a first doping layer 11 (i.e., a P+ emitter) of P-type doping is formed on the first surface S1 of the silicon substrate 10 through boron diffusion treatment. Specifically, boron diffusion is carried out by continuously depositing a boron source (e.g., BCl3 or BBr3, etc.) inside the high-temperature furnace tube, and a silicon oxide layer is formed on the outer layer. The surface doping concentration of the diffused first doping layer is 3E18cm². -3 ~3E 19cm -3 The sheet resistance is 40Ω / sq to 300Ω / sq, preferably 150Ω / sq to 280Ω / sq. During the boron diffusion treatment, BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0091] In this embodiment, the silicon layer on the outer layer of the first surface S1 of the silicon substrate 10 is converted into a boron diffusion layer, and the total thickness of the silicon substrate 10 and the first doping layer 11 after boron diffusion in Figure 5c is equal to the thickness of the silicon substrate 10 before boron diffusion in Figure 5b.

[0092] 3. Back polishing As shown in Figure 5d, first the silicon substrate after boron diffusion passes through a single-sided chain apparatus, where the silicon oxide on the back surface is removed using a hydrofluoric acid solution. Next, the back surface is polished with alkali to remove the edge junction and backside plating (BSG), and finally, it is washed.

[0093] 4. Form a tunnel passivation structure on the rear. As shown in Figure 5e, the tunnel layer 12, second doping layer 13, barrier layer 14, and third doping layer 15 are sequentially stacked and formed on the second surface.

[0094] For example, in this embodiment, deposition is carried out using the PECVD method. First, one silicon oxide tunnel layer is deposited on the back surface, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm. Next, one phosphorus-doped amorphous silicon layer (first doping layer) is deposited, with a thickness of 1 nm to 100 nm, preferably 1 nm to 50 nm. Then, one silicon oxide barrier layer is deposited, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm. Finally, one phosphorus-doped amorphous silicon layer (second doping layer) is deposited, with a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm.

[0095] For example, the thicknesses of the silicon oxide tunnel layer, the first phosphorus-doped amorphous silicon layer, the silicon oxide barrier layer, and the second phosphorus-doped amorphous silicon layer are 1.8 nm, 50 nm, 1.5 nm, and 70 nm, respectively, and the total thickness of the back doping layer is 120 nm.

[0096] 5. Laser oxidation As shown in Figure 5f, the third doping layer 15 in the first region S21 is processed by laser processing to form an oxide layer 151 on the surface of the third doping layer 15 in the first region S21.

[0097] In laser processing, the instantaneous high temperature of the laser is used to create silicon oxide (SiO₂) on the surface of the phosphorus-doped polycrystalline silicon layer in the first region S21. XA layer is formed, and this silicon oxide layer functions as a mask film for subsequent processes.

[0098] Specifically, the laser processing method is performed in an oxygen-containing atmosphere with an oxygen volume concentration of 20% to 80%, a laser output of 1W to 100W, preferably 30W to 60W, a laser frequency of 1kHz to 1000kHz, preferably 300kHz to 600kHz, a laser scanning speed of 10000mm / s to 100000mm / s, preferably 30000mm / s to 60000mm / s, and 1 to 100 laser processing cycles, preferably 1 to 10. This forms an oxide layer 151 with a thickness of 1nm to 50nm.

[0099] For example, if the oxygen volume concentration is 50%, the laser output is 30W, the laser frequency is 500kHz, the laser scanning speed is 50000mm / s, and the number of laser processing passes is 2, then an oxide layer with a thickness of 0.01nm to 10nm is formed on the surface of the phosphorus-doped amorphous silicon layer.

[0100] Figure 6 is a schematic diagram showing the laser scanning pattern of the laser machining method in this embodiment. The black lines correspond to the laser scanning area, i.e., the first region S21 (metal region), and the blank areas represent the second region S22 (non-metal region). After processing with the laser machining method, the first region S21 has the structure of a tunnel layer / phosphorus-doped polycrystalline silicon layer / barrier layer / phosphorus-doped polycrystalline silicon layer / silicon oxide layer, and the second region S22 has the structure of a tunnel layer / phosphorus-doped polycrystalline silicon layer / barrier layer / phosphorus-doped polycrystalline silicon layer.

[0101] It should be understood that the laser scanning pattern in this invention can be designed according to different electrode structures, thereby forming a stylized silicon oxide mask film on the surface of the amorphous silicon layer below the laser scanning region (i.e., the back metal region). There is no need to provide examples of laser scanning patterns related to other electrode structures here.

[0102] 6. Activation of phosphorus by annealing The annealing process is carried out in a high-temperature annealing furnace, with an annealing temperature of 880°C to 980°C, preferably 900°C to 950°C. After the annealing process is complete, the phosphorus-doped amorphous silicon layer is converted into a phosphorus-doped polycrystalline silicon layer, activating phosphorus through the annealing process and forming a tunnel passivation contact structure on the back surface. The surface doping concentration of the annealed second doping layer 13 and third doping layer 15 is 3E20cm². -3 ~3E 21cm -3 Preferably 5E20cm -3 ~2E21cm -3 That is the case.

[0103] For example, the annealing temperature is 910°C. The surface doping concentration of the annealed second doping layer 13 is 8E20cm². -3 Therefore, the surface doping concentration of the annealed third doping layer 15 is 1E21cm². -3 That is the case.

[0104] 7. Removal of backside plating (BSG) and chemical etching. As shown in Figure 5g, the tunnel passivation contact structure in the second region S22 and the oxide layer 151 in the first region S21 are removed by a chemical etching method, while the tunnel passivation contact structure in the first region S21 is retained.

[0105] The specific steps are as follows:

[0106] In the alkaline etching process, the second doping layer 13, barrier layer 14, and third doping layer 15 in the second region S22 are removed using an alkaline solution in an alkaline cleaning tank, and the back plating on the front and edges is removed simultaneously, with the mass fraction of the alkaline solution being 3% to 15%.

[0107] In the pickling process, the tunnel layer 12 in the second region S22 and the oxide layer 151 in the first region are removed using an acidic solution in the pickling tank, and the PSG on the front is also removed at the same time, with the mass fraction of the acidic solution being 5% to 20%.

[0108] Finally, the RCA cleaning process is performed. This RCA cleaning process is based on current technology and will not be repeated here.

[0109] Preferably, in this embodiment, an acidic solution is obtained by mixing an industrial hydrofluoric acid solution (mass fraction approximately 40%) with water in a fixed ratio, and an alkaline solution is obtained by mixing an industrial sodium hydroxide solution (mass fraction approximately 32%) with water in a fixed ratio.

[0110] In current technology, it is necessary to go through a frontal chain process (pickling) before the alkaline etching process, pass through a chain-type hydrofluoric acid tank, and remove the silicon oxide mask film of back-side plating at the edges on one side. However, in the present invention, since a silicon oxide mask film is not formed through the PECVD method and back-side plating does not occur at the edges, it is not necessary to go through the frontal chain process.

[0111] During the alkaline etching process, the phosphorus-doped amorphous silicon layer in the second region S22 is corroded, which reduces parasitic absorption on the back of the solar cell and significantly increases the current. Furthermore, because the barrier layer 14 is thin and has pores on its surface, it is possible to remove the barrier layer 14 simultaneously during the alkaline etching process.

[0112] Specifically, an additive to protect the silicon oxide mask film in the first region S21, such as EST-10 additive from Jiaxing Shangneng Optical Fiber Materials Technology Co., Ltd., is added to the alkaline etching solution. The additive contains a protective group and a catalytic component. The protective group can selectively adsorb to the oxide layer and block contact with the alkaline component, while the catalytic component can accelerate the reaction between the exposed polycrystalline silicon and the alkaline component. Because the barrier layer 14 is thin and has pores on its surface, and is not a complete oxide layer, wet etching using a mixture of the alkaline component and the additive allows the alkaline component to penetrate the barrier layer 14 and subsequently corrode the polycrystalline silicon beneath it. By protecting the first region S21 with a complete oxide layer 151, corrosion of the polycrystalline silicon beneath it can be prevented.

[0113] 8. Formation of the passivation layer As shown in Figure 5h, a first passivation layer 21 and a second passivation layer 22 are formed on the first surface S1 and the second surface S2 of the silicon substrate through the ALD method. Both the first passivation layer 21 and the second passivation layer 22 are aluminum oxide passivation layers with a thickness of 2 nm to 7 nm, preferably 3 nm to 6 nm.

[0114] After the processes of removing the backside plating (BSG) and chemical etching, the tunnel layer and doped amorphous silicon layer in the first region S21 still maintain a passivation effect. However, since the second region S22 is not protected by a passivation layer, it is necessary to form a second passivation layer 22 on the back surface of the second region S22 in order for it to have a good surface passivation effect.

[0115] Furthermore, under high-temperature sintering conditions that ensure good contact with the front, the second passivation layer 22 obstructs the electrode paste on the back to some extent, which may allow the second doping layer 13 and the third doping layer 15 to be made even thinner, thereby improving the short-circuit current density of the solar cell.

[0116] 9. Formation of an anti-reflective layer As shown in Figure 5i, a first anti-reflective layer 31 and a second anti-reflective layer 32 are formed on the first surface S1 and second surface S2 of the silicon substrate through the PECVD process. The first anti-reflective layer 31 and the second anti-reflective layer 32 may be a laminated film formed on one or more of the silicon nitride layer, silicon oxynitride layer, and silicon oxide layer, with a thickness of 60 nm to 130 nm.

[0117] 9. Print the metal electrodes. As shown in Figure 5j, the first electrode 41 and the second electrode 42 are printed on the front and back surfaces, respectively, through a screen printing process, followed by sintering and light injection or electrical injection to form an ohmic contact.

[0118] The first electrode 41 and the second electrode 42 are gate line electrodes in current technology, and are usually divided into a main gate line and a thin gate line. Since the thin gate line of the second electrode 42 needs to be printed in the first region S21, the width of the first dependent region 101 needs to be larger than the width of the thin gate line 421 of the second electrode 42, thereby allowing the thin gate line 421 to be positioned appropriately.

[0119] The process flow chart for this embodiment is as follows: texture treatment → boron diffusion → back polishing → PE-poly → laser oxidation → annealing → back plating removal → ALD → PECVD → screen printing. Following these steps, TOPCon solar cells can be manufactured, and finally, the solar cells are detected, sorted, and stored.

[0120] Example 2 The structure and manufacturing method of the solar cell in this embodiment are substantially the same as those of Example 1, except that the first doping layer 11 in Example 1 is formed below the first surface S1 of the silicon substrate through a boron diffusion treatment, while the first doping layer 11 in this embodiment is formed above the first surface S1 of the silicon substrate through a PECVD method.

[0121] Specifically, in this embodiment, first, a boron-doped amorphous silicon layer 11' is deposited on the first surface S1 by the PECVD method, followed by high-temperature oxidation annealing to form the first doping layer 11, i.e., a polycrystalline silicon layer with P-type doping.

[0122] As shown in Figure 7a, first, a double-sided texture treatment is performed on the silicon substrate 10. The texture treatment is exactly the same as in Example 1 and will not be repeated here.

[0123] As shown in Figure 7b, first, a boron-doped amorphous silicon layer 11' is deposited on the first surface S1 by the PECVD method. For example, in the PECVD method, N2O is first introduced to form a silicon oxide layer (not shown) on the first surface S1, then SiH4 and trimethylboron are introduced to form a boron-doped amorphous silicon layer on the silicon oxide layer, and finally N2O is introduced to form a silicon oxynitride mask film (not shown).

[0124] As shown in Figure 7c, the first doping layer 11 is finally formed through a high-temperature oxidative annealing treatment, that is, the amorphous silicon layer with P-type doping is converted to a polycrystalline silicon layer with P-type doping through a high-temperature oxidative annealing treatment.

[0125] The difference from Example 1 is that in this example, a polycrystalline silicon layer with P-type doping is formed on the surface of the silicon substrate 10 through the PECVD method and annealing treatment, and the thickness of the silicon substrate 10 remains unchanged during this process. The total thickness of the silicon substrate 10 and the first doping layer 11 after annealing in Figure 7c is equal to the total thickness of the silicon substrate 10 and the boron-doped amorphous silicon layer 11' before annealing in Figure 7b, and is greater than the thickness of the silicon substrate 10 before treatment by the PECVD method in Figure 7a.

[0126] Example 3 The structure and manufacturing method of the solar cell in this embodiment are substantially the same as those of Example 1, except that in step 5 of the preparation method of Example 1, the first region S21 is processed by a laser process, thereby forming an oxide layer mask film on the surface of the third doping layer 15, while the manufacturing process of the mask film in the first region S21 in this embodiment is as follows.

[0127] As shown in Figure 8a, first, during the process of forming a tunnel passivation structure on the back surface, one oxide layer 152 is deposited on the surface of the third doping layer by the PECVD method, preferably a silicon oxynitride layer.

[0128] As shown in Figure 8b, after annealing, the mask film is removed from the second region S22 by laser defilm removal.

[0129] The back structure of the silicon substrate after annealing is a tunnel layer / phosphorus-doped polycrystalline silicon layer / barrier layer / phosphorus-doped polycrystalline silicon layer / silicon oxide layer. Laser treatment mainly acts on the mask film (SiO2), and the laser parameters are set according to the material and thickness of the mask film using the laser defilm removal method, which is not repeated here.

[0130] The structure of the solar cell and other manufacturing methods in this embodiment are the same as in the embodiment and will not be repeated here.

[0131] According to the above technical means, the present invention has at least the following technical effects.

[0132] In the back surface of the solar cell according to the present invention, only tunnel passivation contact structures are stacked in the metal region, and there are no tunnel passivation contact structures in the non-metal region. This reduces parasitic absorption on the back surface of the solar cell, significantly increasing the current. In addition, it does not affect the contact performance between the back electrode and the back doping layer, extending the processing time and significantly improving the efficiency and bifacial properties of the solar cell.

[0133] The tunnel passivation contact structure in the back metal region comprises two doping layers and one barrier layer. The barrier layer acts to some extent to prevent the back electrode paste from adhering, further reducing the total thickness of the back doping layer, which in turn increases the open-circuit voltage of the solar cell and improves its efficiency.

[0134] In the non-metallic region on the back of the solar cell, the passivation effect on the back of the solar cell is increased via the second passivation layer. In addition, the second passivation layer acts to some extent to inhibit the electrode paste on the back, which may further reduce the total thickness of the doping layer in the metallic region. This increases the short-circuit current density of the solar cell, assuming that it does not affect the metallization contact performance, and significantly improves the efficiency and bifacial properties of the solar cell.

[0135] It will be apparent to those skilled in the art that the present invention is not limited to the details of the above embodiments and can be realized in other specific forms without departing from the spirit or essential features of the invention. Therefore, all embodiments are considered illustrative and non-restrictive, and the scope of the invention is limited by the claims rather than the above description; all modifications within the implications and scope of the equivalent elements of the claims are included in the present invention. Any drawing marking relating to a claim shall not be considered a limitation of the relevant claim.

[0136] Therefore, the specification is described according to embodiments, but each embodiment does not necessarily contain only one independent technical solution. This style of description in the specification is for clarity only, and those skilled in the art should consider the specification as a whole. The technical means in each embodiment can be appropriately combined to form other embodiments that will be understood by those skilled in the art. [Explanation of symbols]

[0137] 10 Silicon substrate 11. First Doping Layer 11' Boron-doped amorphous silicon layer 21. First Passivation Layer 31 First anti-reflection layer 12 Tunnel Layer 13. Second Doping Layer 14 Barrier Layer 15. Third Doping Layer 151 Oxide layer 152 Oxide layer 22 Second Passivation Layer 32 Second anti-reflection layer 41 First electrode 42 Second electrode 421 Gate Line S1 first surface S2 second surface S21 First area S22 Second area 101 First Dependent Domain 102 Second Dependent Domain

Claims

1. A silicon substrate having a first surface and a second surface facing each other, with first and second regions alternately arranged on the second surface, A tunnel passivation contact structure comprising: a tunnel layer provided on the second surface, the projection of the silicon substrate on the second surface located within the first region and in direct contact with the silicon substrate; a second doping layer provided on the tunnel layer; and a barrier layer and a third doping layer sequentially provided on the second doping layer, wherein the doping types of the second and third doping layers are the same as those of the silicon substrate; A second electrode located in the second region and in contact with the third doping layer, A solar cell characterized by the following features.

2. The aforementioned second doping layer and third doping layer are The thickness of the third doping layer is greater than or equal to the thickness of the second doping layer. The total thickness of the second doping layer and the third doping layer is 50 nm to 150 nm or 60 nm to 100 nm. The thickness of the second doping layer is 1 nm to 100 nm, and the thickness of the third doping layer is 1 nm to 150 nm, or The thickness of the second doping layer is 1 nm to 50 nm, and the thickness of the third doping layer is 50 nm to 100 nm, satisfying at least one of these conditions. The solar cell according to feature 1.

3. The solar cell according to claim 1, further comprising a second passivation layer, wherein the second passivation layer is in contact with the second surface of the silicon substrate layer in the second region, and the second passivation layer covers the third doping layer in the first region.

4. The second passivation layer is an aluminum oxide passivation layer, and the thickness of the second passivation layer is 2 nm to 7 nm or 3 nm to 6 nm. The solar cell according to feature 3.

5. The solar cell further comprises a second anti-reflective layer stacked on the second passivation layer, wherein the second anti-reflective layer is a laminated film formed of one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and the thickness of the laminated film is 60 nm to 130 nm. The solar cell according to feature 3.

6. The aforementioned solar cell is The silicon substrate is an N-type silicon substrate, and the second doping layer and the third doping layer are N-type doped polycrystalline silicon layers. The surface doping concentration of the third doping layer is equal to or greater than the surface doping concentration of the second doping layer. The surface doping concentration of the second doping layer is 3E20cm -3 ~3E21cm -3 Or 5E20cm -3 ~2E21cm -3 Being The surface doping concentration of the third doping layer is 3E20cm -3 ~3E21cm -3 Or 5E20cm -3 ~2E21cm -3 Being The tunnel layer is a combination of one or more silicon oxide layers and silicon oxynitride layers. The thickness of the tunnel layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm. The barrier layer is a combination of one or more silicon oxide layers and silicon carbide layers, and The barrier layer has a thickness of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm, satisfying at least one of these conditions. The solar cell according to feature 1.

7. The solar cell further comprises a first doping layer and a first electrode formed on the first surface of the silicon substrate, wherein the doping type of the first doping layer is the opposite of the doping type of the silicon substrate, and the first electrode is in contact with the first doping layer. The solar cell according to feature 1.

8. The aforementioned first doping layer is The first doping layer is a P-type doping layer, and The surface doping concentration of the first doping layer is 3E18 cm -3 ~3E19 cm -3 and satisfies at least one of the above conditions. The solar cell according to feature 7.

9. The solar cell according to claim 7, further comprising a first passivation layer and a first anti-reflective layer stacked on the first doping layer.

10. The first passivation layer is an aluminum oxide passivation layer, the thickness of the first passivation layer is 2 nm to 7 nm or 3 nm to 6 nm, and the first anti-reflective layer is a laminated film formed of one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, the thickness of the laminated film is 60 nm to 130 nm. The solar cell according to feature 9.

11. Multiple first regions are parallel to each other, multiple second regions are parallel to each other, and multiple first regions and multiple second regions are arranged alternately. The second electrode has a plurality of gate lines arranged in parallel, and the plurality of gate lines of the second electrode correspond one-to-one with a plurality of first regions, and the width of each first region is greater than or equal to the width of each gate line. The solar cell according to feature 1.

12. The solar cell according to claim 11, characterized in that the width of each first region is 50 μm to 150 μm, and the width of each gate line is 15 μm to 100 μm.

13. A silicon substrate is provided, the silicon substrate having a first surface and a second surface facing each other, and the second surface having first and second regions arranged alternately, The steps include forming a tunnel passivation contact structure on the second surface, and including a tunnel layer, a second doping layer, a barrier layer, and a third doping layer in which the tunnel passivation contact structures are sequentially stacked, The process involves removing the tunnel passivation contact structure in the second region, leaving the tunnel passivation contact structure in the first region, The step includes forming a second electrode in a tunnel passivation contact structure in the first region that contacts the third doping layer, A method for manufacturing a solar cell according to any one of claims 1 to 12.

14. Before removing the tunnel passivation contact structure in the second region, the manufacturing method is as follows: The process further includes the step of treating the third doping layer in the first region with a laser method to form an oxide layer on the surface of the third doping layer in the first region. The manufacturing method according to claim 13.

15. The aforementioned laser construction method is The laser method is performed in an oxygen-containing atmosphere, and the volume concentration of oxygen is 20% to 80%. The laser output for the aforementioned laser construction method is 1W to 100W or 30W to 60W. The laser frequency used in the aforementioned laser construction method is 1 kHz to 1000 kHz or 300 kHz to 600 kHz. The scanning speed of the laser used in the aforementioned laser construction method is 10,000 mm / s to 100,000 mm / s or 30,000 mm / s to 60,000 mm / s, and The laser processing method satisfies at least one of the following conditions: the number of laser processing steps is 1 to 100 or 1 to 10. The manufacturing method according to claim 14.

16. The step of removing the tunnel passivation contact structure in the second region is The method involves using an oxide layer as a mask film, removing the second doping layer, barrier layer, and third doping layer in the second region using an alkaline solution, and then removing the tunnel layer in the second region and the oxide layer in the first region using an acidic solution. The manufacturing method according to claim 14.

17. The step of forming a tunnel passivation contact structure on the second surface is A tunnel layer, a first doped amorphous silicon layer, a barrier layer, and a second doped amorphous silicon layer are sequentially deposited on the second surface of the silicon substrate. This includes annealing a silicon substrate on which a tunnel layer, a first doped amorphous silicon layer, a barrier layer, and a second doped amorphous silicon layer have been deposited at 880°C to 980°C to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer. The manufacturing method according to claim 13.

18. A step of forming a first doping layer on the first surface, wherein the doping type of the first doping layer is the opposite of the doping type of the silicon substrate, and The further step includes forming a first electrode on the first surface that contacts the first doping layer. The manufacturing method according to claim 13.

19. The steps include forming a first passivation layer and a first anti-reflective layer on the first surface of a silicon substrate, The process further includes the step of forming a second passivation layer and a second anti-reflective layer on the second surface of the silicon substrate. The manufacturing method according to claim 18.

20. A device comprising several solar cells according to any one of claims 1 to 12, A solar power generation module characterized by the following features.

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