Pre-etching rinse for achieving dopant-selective silicon etching

Abstract

This invention provides a method for reducing the etching rate of n-type silicon relative to the etching rate of coexisting materials before an oxidative wet etching process. [Solution] A method for reducing the etching rate of n-type silicon relative to the etching rate of a coexisting material which is a different material from n-type silicon, before an oxidative wet etching process, includes exposing a surface containing n-type silicon and the coexisting material to an aqueous rinse solution at a predetermined temperature for a predetermined time.

Description

[Technical Field]

[0001] Cross-references to related applications This application claims priority to U.S. Patent Provisional Application 63 / 740,113, filed with the U.S. Patent and Trademark Office on 30 December 2024, which is incorporated herein by reference in its entirety.

[0002] This disclosure relates generally to the technical field of semiconductor device manufacturing, and more particularly to wet etching processes for semiconductors. [Background technology]

[0003] Semiconductor photolithography is a mature and sophisticated technique used to fabricate highly advanced, small-scale integrated electronic devices. The fundamental process in most photolithography operations is mask etching of semiconductor or dielectric structures. In mask etching, a resinous photoresist is applied to a semiconductor wafer and exposed to ultraviolet (UV) light projected through a carefully aligned optical mask. Selected areas of the photoresist layer either harden within a pattern defined by the optical mask or degrade due to UV light. A solvent is then used to remove the uncured or degraded portions of the photoresist, leaving a pattern consisting of protected and unprotected regions.

[0004] Subsequent processing may vary depending on the embodiment. In plasma etching, an unprotected area of ​​the semiconductor wafer or die is exposed to high-energy reactants formed in the plasma. Such reactants convert the unprotected solid material into a gaseous residue. In wet (i.e., liquid-phase) etching, the unprotected area is exposed to a corrosive solution that dissolves unwanted materials, after which the soluble residue is washed away. In both embodiments, subsequent processing typically requires the removal of the entire hardened photoresist from the surface of the wafer or die. For this purpose, a well-formulated solvent composition can be used in the wet etching process.

[0005] For example, Patent Document 1 discloses an etching solution suitable for selective removal of polysilicon from silicon dioxide from microelectronic devices, comprising water; about 1% by mass of tetramethylammonium hydroxide (TMAH); about 15% to about 20% by mass of monoethanolamine (MEA); about 50% to about 59.5% by mass of ethylene glycol (EG); about 0.5% by mass of 8-hydroxyquinoline (8-HQ); and optionally a surfactant. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] United States Patent Publication No. 11,180,697 [Overview of the Initiative]

[0007] One aspect of this disclosure relates to a method for reducing the etching rate of n-type silicon relative to the etching rate of a coexisting material, which is a material different from n-type silicon, before an oxidative wet etching process. This method includes exposing a surface containing n-type silicon and the coexisting material to an aqueous rinse solution at a predetermined temperature for a predetermined time. The coexisting material will be described later, but unless otherwise specified, the coexisting material may be a material different from n-type silicon. The coexisting material may be present on the surface to be etched, and may be a material adjacent to the n-type silicon or a material not adjacent to the n-type silicon.

[0008] This summary is provided to introduce, in a simplified form, a selection of concepts that will be further described in embodiments for carrying out the invention. This summary is not intended to identify any important or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is not limited to embodiments that resolve any or all of the defects described in any part of this disclosure. [Brief explanation of the drawing]

[0009] [Figure 1] This diagram schematically shows an exemplary lateral resection of a p-type silicon (p-Si) layer. [Figure 2] This diagram schematically illustrates the removal of an exemplary p-type Si layer. [Figure 3] This document illustrates an exemplary method for reducing the etching rate of n-type (n-Si) silicon relative to the etching rate of coexisting materials before an oxidative wet etching process. [Figure 4] Figure 3 illustrates an application of the method to semiconductors. [Figure 5] Figure 4 shows an application of the method shown in Figure 3 to a semiconductor that differs from that shown in Figure 4 in terms of layer structure and dry etching patterning. [Figure 6] Figures 4 and 5 show different applications of the method in Figure 3 to semiconductors with respect to layer structure and dry etching patterning. [Modes for carrying out the invention]

[0010] The following describes in detail embodiments for carrying out the present invention (hereinafter simply referred to as "these embodiments"). These embodiments are illustrative for explaining the present invention and are not intended to limit the present invention to the following content. The present invention can be appropriately modified and implemented within the scope of its gist. Furthermore, the configurations and parameters disclosed herein can be any combination unless otherwise specified. Moreover, the upper and lower limits of the values ​​disclosed herein can be any combination unless otherwise specified.

[0011] Wet etching can offer certain advantages over plasma etching for several applications in semiconductor manufacturing. For example, wet etching tools and chemicals are typically less expensive than those for plasma etching, resulting in lower operating costs. In contrast to plasma etching, wet etching is performed at lower temperatures, simplifying the processing of heat-sensitive materials and structures. Wet etching can also result in cleaner surfaces with less residue compared to plasma etching, which may require additional cleaning protocols due to residues and by-products from the etching gas. Furthermore, wet etching is inherently more isotropic, which can be advantageous in applications where isotropic etching is the most efficient process route to a particular form and / or device configuration, or in applications for undercutting sacrificial layers.

[0012] Finally, wet etching can provide high etching selectivity for one material compared to another when multiple different materials are subjected to the same etching conditions simultaneously. Available etching solutions can, for example, etch silicon and silicon oxide at rates that differ by several orders of magnitude. This feature provides functional selectivity for semiconductor etching versus dielectric etching. Other etching solutions can distinguish between dissimilar semiconductors (e.g., germanium (Ge) versus silicon (Si)) with high selectivity. Yet another etching solution is available that provides a 17-fold difference in etching rate between 111 and 100 faces of silicon. Such selectivity can be utilized to reduce the number of mask alignment and curing steps required in a given manufacturing process, and / or to enable the selective removal of unprotected structures such as undercuts.

[0013] Herein, the inventors of the present invention have sought to extend the selectivity of the wet etching process to semiconductor systems where the material differences between separate unprotected regions of a wafer or die are minimal. This includes semiconductor materials that expose the same crystal plane and differ only in dopant type. An exemplary method using silicon as the semiconductor is shown herein.

[0014] Doping involves introducing impurities into a semiconductor. These impurities can generate space charges within the doped semiconductor, which alters the Fermi levels of electrons within the semiconductor relative to the valence band and conduction band.

[0015] The n-type doping process involves adding chemical elements with more than four valence electrons to a silicon lattice. Common n-type dopants include phosphorus (P) and arsenic (As), both of which have five valence electrons per atom. In effect, each n-type dopant atom adds one electron to the conduction band of silicon.

[0016] The typical dopant density of n-type Si at low to moderate dopant levels is per cubic centimeter (cm³).

[0018] )Per 10 15 ~10 17 atoms. In many semiconductor applications such as integrated circuits and transistors, n-type silicon is doped within this range. The typical dopant density of n-type Si at high dopant levels is 10 3 to 10 18 ~10 20 atoms per cm. In applications that require high electron conductivity, such as certain types of power devices or certain high-speed transistors, doping concentrations within this range can be used.

[0017] The p-type doping process adds elements with fewer than 4 valence electrons to the silicon lattice. Common p-type dopants include boron (B), gallium (Ga), and indium (In), each of which has 3 valence electrons per atom. In fact, each p-type dopant atom adds one hole to the valence band of silicon.

[0018] The typical dopant density of p-type Si at low to medium dopant levels is 10 3 to 10 15 ~10 17 atoms per cm. In many semiconductor applications such as integrated circuits and transistors, p-type silicon is doped within this range. The typical dopant density of p-type Si at high dopant levels is 10 3 to 10 18 ~10 20 atoms per cm. In applications that require high hole conductivity, such as certain types of power devices or certain high-speed transistors, doping concentrations within this range can be used.

[0019] Dopants can be added to silicon by diffusion or ion implantation. In diffusion, the wafer is exposed to a gas containing dopant atoms at a high temperature (typically between 800 and 1200°C). The dopant diffuses into the silicon wafer, gradually penetrating the surface and being incorporated into the silicon lattice. In ion implantation, dopant ions are accelerated in an electric field and directed towards the silicon wafer. The ions penetrate the surface and are embedded in the silicon lattice. This method allows for more precise control of doping concentration and depth compared to diffusion. After the doping process, the wafer is typically subjected to a thermal annealing process. Thermal annealing helps repair damage caused by ion implantation and involves a heating process that activates the dopant by allowing it to occupy its expected position within the silicon lattice.

[0020] Certain parts of semiconductor devices may include intrinsic silicon (i-Si) in which the concentration of conduction band electrons is equal to the concentration of valence band holes. In some examples, this type of silicon may be extremely pure and may not undergo any n-type or p-type doping process (i.e., undoped or "undoped"). In other examples, i-Si may be "intrinsically doped," meaning that the Fermi level of electrons in silicon may be approximately the same as that of undoped silicon, due to the presence of approximately equal (and typically low) concentrations of n-type and p-type dopants. As used herein, the term "dopant-type" includes p-type, n-type, i-type, and undoped silicon.

[0021] Polycrystalline silicon (poly-Si) contains multiple relatively small silicon crystals, in contrast to wafers cut from single-crystal booleans. In some cases, poly-Si can be used to form thin-film transistors and solar cells as gate materials for metal-oxide-semiconductor (MOS) devices or flexible microelectronics.

[0022] Amorphous silicon (a-Si) is a non-crystalline form of silicon, distinct from crystalline silicon, which is used in the vast majority of semiconductor applications. Amorphous silicon lacks long-range periodic atomic arrangements, resulting in somewhat different electrical properties compared to crystalline silicon. For example, amorphous silicon has a larger band gap than crystalline silicon. Amorphous silicon is typically deposited as thin films using techniques such as chemical vapor deposition (CVD) (e.g., plasma CVD (PECVD)). Amorphous silicon is often deposited in thin layers, making it suitable for use in flexible substrates and various electronic devices. Generally speaking, a-Si can be doped or undoped.

[0023] Those skilled in the art will understand that the dopant density in silicon for the manufacture of integrated circuits rarely exceeds 0.01 mass%. Therefore, selective etching of p-type silicon (p-Si) in the presence of n-type silicon (n-Si), for example, is more difficult than selective etching of materials in which all atoms being etched are chemically different. Referring here to the drawings, Figures 1 and 2 illustrate exemplary applications of the etching solution compositions and methods disclosed herein.

[0024] Figure 1 shows an exemplary lateral resection of an epitaxial p-Si layer 102 formed on a SiGe layer 104. An epitaxial n-Si layer 106 is formed on top of the epitaxial p-Si layer. Etching is achieved by a wet etching process in which the surfaces of the p-Si and n-Si are simultaneously exposed to the etching solution composition. As shown in the figure, the n-Si withstands etching with only very slight dimensional changes, while the width of the p-Si layer is significantly reduced.

[0025] Figure 2 shows an embodiment of the complete removal of an epitaxial p-Si layer 202 formed over an epitaxial n-Si layer 206 formed on a SiGe layer 204. Since the etching solution composition etches p-Si much faster than it etches n-Si, layer 206 is preserved in this process. While Figures 1 and 2 illustrate selective etching of epitaxial layers, this embodiment is not entirely necessary. In other examples, some, some, or all of the layers subjected to selective etching may be deposited non-epitaxially on a glassy layer, such as amorphous SiO2.

[0026] As described above, wet etching uses a specific etching solution composition to remove material from unprotected areas of a wafer or die. The etching solution composition is selected based on the etching rate of the target material against one or more coexisting materials that may also be present on the surface to be etched. In this disclosure, the target material may be any material different from n-type silicon, as described above. Examples of target materials include semiconductors of a specific dopant type or dopant level. Exemplary coexisting materials may be the same semiconductor with different dopant types, or the same semiconductor with the same dopant type but higher or lower dopant densities. Other coexisting materials include the same semiconductor exhibiting different crystal planes (e.g., (100) vs. (111)), different semiconductors (e.g., Ge vs. Si), dielectrics such as silicon oxide (SiO2) and silicon nitride (Si3N4), cured photoresists (including one or more crosslinked polymers), and various additive structures formed on the semiconductor wafer or die surface (e.g., metallic or epitaxial semiconductor structures). Such structures may include, in particular, at least one selected from the group consisting of aluminum, copper, tungsten, molybdenum, cobalt, tantalum, and gold.

[0027] [Table 1]

[0028] In the examples presented herein, the silicon surface interacting with the surfactant is intentionally exposed to controlled oxidation before interaction with the etching solution composition. Controlled oxidation is achieved by short-term immersion in an aqueous rinse solution. As used herein, the term “aqueous rinse solution” refers to a water-containing liquid applied to the surface to be treated. In some examples, the aqueous rinse solution may consist only of water (e.g., distilled water or deionized water). In some examples, the aqueous rinse solution may further contain one or more solutes and / or water-miscible cosolvents dissolved in water, as further described below. Thus, the aqueous rinse solution may consist of an aqueous rinse solution. In some examples, water may be the main component of the aqueous rinse solution, and in other examples, water may not be the primary component in the aqueous rinse solution. For example, in a preferred example where water is the main component of the aqueous rinse solution, the proportion of water is preferably 50% by mass or more, more preferably 60% by mass or more, even more preferably 70% by mass or more, even more preferably 80% by mass or more, and even more preferably 90% by mass or more. Alternatively, for example, in some examples where the proportion of water in the aqueous rinse solution is not the primary component, the proportion of water in the aqueous rinse solution may be 10% by mass or less, and the main component may be a water-miscible organic solvent. Therefore, the term "aqueous rinse solution" refers to any rinse solution to which a certain amount of water is added as a compound. In some examples, the term "rinse solution" is synonymous with "aqueous rinse solution" in this specification. Neutral, acidic, and basic aqueous rinse solutions are assumed in this disclosure, but aqueous rinse solutions do not contain hydrogen fluoride (HF) under acidic conditions.

[0029] Oxides formed on any type of silicon by immersion in an aqueous rinse solution reduce the subsequent etching rate of the silicon. However, the overall effect on the etching rate may vary depending on the silicon dopant type. It is plausible that the oxide growth rate and the final etching rate may be dopant-sensitive. The results are summarized in Table 1.

[0030] In the examples and comparative examples in Table 1, an oxide-etched surface containing n-type silicon or a co-existing material is exposed to a rinse solution at a predetermined temperature for a predetermined time. Immediately after exposure to the rinse solution, the surface is exposed to a basic etching solution composition at a predetermined temperature for a predetermined time. In the examples shown in the table, the “co-existing material” is a dopant-type silicon different from n-Si (e.g., p-Si or poly-Si). In other examples, the “co-existing material” may include a metal, such as any metal used to form ohmic contacts on a silicon patterned or unpatterned silicon structure. In yet another example, the co-existing material may include a dielectric such as SiO2 or Si3N4. Thus, in some examples, the co-existing material may include a metal or a dielectric.

[0031] The rinsing and etching processes using conditions 1 to 12 in the examples in Table 1 yield etching rates for silicon corresponding to the silicon dopant type. The susceptibility to dopant types is shown in columns 7 to 11 of Table 1. Column 7 lists the etching rates in nm / min for p-Si, column 8 lists the corresponding etching rates for poly-Si, and column 9 lists the corresponding etching rates for n-Si. Columns 10 and 11 show the ratios of these rates.

[0032] The etching rates shown in Table 1 were determined as follows: Epitaxial films of n-Si and p-Si were grown on silicon germanium (SiGe) wafers by chemical vapor deposition (CVD). Poly-Si films were grown on SiO2 substrates by CVD. Wafers coated with each film were divided into multiple test samples of approximately 1 to 10 square centimeters. The film thickness of each test sample was measured by ellipsometry or X-ray fluorescence analysis (XRF).

[0033] For each test sample, 100 ml (mL) of aqueous hydrofluoric acid solution (HF, 0.5 mass%) was poured into the first plastic cup and magnetically stirred at 300 rpm at 25°C. The same volume of etching solution composition was poured into the second plastic cup and magnetically stirred at 300 rpm at the temperature shown in the fifth column of Table 1. 100 mL of rinse solution containing deionized water and, optionally, one or more organic solvents was poured into the third and fourth plastic cups. The rinse solution was magnetically stirred at 300 rpm at the temperature shown in the third column of Table 1. Each test sample was placed in the first cup for 60 seconds, then transferred to the third cup for the time shown in the fourth column of Table 1, then transferred to the second cup for 60 seconds, and then transferred to the fourth cup for 5 seconds. The samples were then dried, and the film thickness was measured repeatedly using an ellipsometer or XRF.

[0034] Figure 3 shows an embodiment of exemplary method 300 in which the etching rate of n-type silicon is reduced relative to the etching rate of the coexisting material before the oxidative wet etching process. In some examples, the coexisting material may include one or more of p-type silicon, polysilicon, or amorphous silicon. Alternatively, in some examples, the coexisting material may include one or more of p-type silicon, undoped silicon, polysilicon, or amorphous silicon. In these and other examples, the coexisting material may include a metal or a dielectric, as described above.

[0035] In method 300, in step 301A, a photoresist is applied to the surface. In step 301B, the mask is positioned on the surface. In step 301C, the photoresist is cured by UV exposure through the mask. In step 301D, the uncured photoresist is removed from the surface.

[0036] In 301E, the surface containing n-type silicon and coexisting materials is exposed to an aqueous rinse solution at a predetermined temperature for a predetermined time. In some examples, the rinse solution may contain more than 90% water. In some modifications of Method 300, exposure to the rinse solution is dip exposure (i.e., immersion). In other modifications, exposure to the rinse solution is spray or continuous flow exposure.

[0037] In some cases, the rinse solution contains a base. Examples of bases include ammonium hydroxide or another weak base. In other cases, the rinse solution may contain an acid. Examples of acids include acetic acid or another acid. In some cases, the rinse solution may contain a pH buffer to set the pH of the rinse solution to any appropriate value. In some cases, the rinse solution does not need to contain hydrogen fluoride under acidic conditions.

[0038] In some examples, the rinse solution may further contain an organic solvent. For example, the rinse solution may contain water and an organic solvent. The rinse solution may further contain a water-miscible organic solvent. Examples of such organic solvents include 2-propanol (IPA) or dimethyl sulfoxide (DMSO). Other water-miscible organic solvents, such as polar protic and aprotic solvents, may also be used. Examples of such solvents include methanol, ethanol, acetone, acetonitrile, or tetrahydrofuran (THF). In some examples, the rinse solution may contain cationic, anionic, or nonionic surfactants.

[0039] In some examples, the predetermined temperature of the rinse solution is preferably above 10°C. In some examples, the predetermined time the surface is exposed to the rinse solution is preferably above 5 seconds. Temperatures and exposure times outside these ranges are also possible.

[0040] In 301F, the rinsed surface is exposed to a basic etching solution composition. Here again, among other exposure modes, dip exposure, spray exposure, and continuous flow exposure are assumed. In some examples, the basic etching solution composition contains quaternary ammonium hydroxides such as tetramethylammonium hydroxide (TMAH), tetraethylammonium hydroxide (TEAH), and tetra-n-butylammonium hydroxide. In some examples, the basic etching solution composition may also contain alkali metal hydroxides such as NaOH or KOH. In some examples, the basic etching solution composition may, among others, contain 4-dimethylaminopyridine, 1,2-ethylenediamine, 1,3-dimethylbutylamine, triethanolamine, n-butylamine, N,N-diethylhydroxylamine (DEHA), 2,5-dimethyl-2,5-hexanediol (DMHD), triethylenetetramine (TETA), tris(2-aminoethyl)amine (TAEA), and / or diethylenetriamine (DETA). In some examples, the basic etching solution composition may contain, among other things, alcohols or polyols such as 1-butanol and 1,2-heptanediol. In some examples, the basic etching solution composition may contain one or more organic solvents such as methanol, ethanol, IPA, n-butanol, cyclic ethers, alcohol ethers, acetone, acetonitrile, DMSO, DMF, propylene carbonate (PC), and / or propylene glycol methyl ether acetate (PGMEA). In some examples, the basic etching solution composition may contain one or more nonionic, anionic, or cationic surfactants.

[0041] In some embodiments of Method 300, the process flow returns from 301F to 301A for one or more additional mask-rinse-etching iterations. In some embodiments, the process flow returns from 301F to 301E. Thus, Method 300 also embodies a method for reducing the etching rate of n-type silicon relative to the etching rate of a coexisting material after an oxidative wet etching process. A specific example of such a method is a method for reducing the etching rate of n-type silicon relative to the etching rate of a coexisting material after an oxidative wet etching process, comprising exposing the etched surface of n-type silicon and the coexisting material to a rinse solution at a predetermined temperature for a predetermined time. In some examples of such a method, it is preferable to further include exposing the surface to a basic etching solution composition. In some examples of such a method, the coexisting material preferably includes one or more of, for example, p-type silicon, polysilicon, amorphous silicon, metals, or dielectrics. In some examples of such a method, the rinse solution preferably contains more than 99% water. In some examples of such methods, the rinse solution preferably contains a base. In some examples of such methods, the predetermined temperature is preferably greater than 10°C, the predetermined time is preferably greater than 5 seconds, and the rinse solution preferably does not contain hydrogen fluoride under acidic conditions.

[0042] In 301G, the surface undergoes a final rinse. In some examples, the rinse agent may contain water. In some examples, the rinse agent may contain an alcohol such as methanol, ethanol, or IPA. Optionally, after rinsing and properly drying the surface, one or more dry etching processes may be performed as needed. Optionally, the cured photoresist may be removed at this point.

[0043] Method 300 can be used to form various types of microstructures on semiconductor surfaces, such as layered and / or patterned semiconductor surfaces. In some situations, the results of applying Method 300 depend on the initial layer structure and whether any additional etching processes, such as dry etching, are also used. Figures 4–6 illustrate this feature as an example. In each figure, the initial structure includes a pattern of cured photoresist (shown in black), as present following step 301D of Method 300.

[0044] In the structure shown in Figure 4, an n-Si layer 406 is formed on a SiGe layer 404. A p-Si layer 402 is formed on top of the n-Si layer. A rinse performed at 301E imparts dopant-type selectivity (promoting p-Si etching over n-Si etching) to the subsequent wet etching, allowing the wet etching to penetrate the p-Si layer and effectively stop at the p-Si / n-Si boundary. As the etching progresses vertically downward, the n-Si is exposed to the etching solution composition, but the etching of n-Si occurs very limitedly.

[0045] In the structure shown in Figure 5, a p-Si layer 502 is formed on a SiGe layer 504. An n-Si layer 506 is formed on top of the p-Si layer. The rinsing performed in 301E imparts dopant-type selectivity to the subsequent wet etching (which promotes p-Si etching over n-Si etching). However, since neither of the p-Si layers is exposed to the etching solution composition, etching occurs very limitedly.

[0046] The initial structure in Figure 6 is the same as in Figure 5, with a p-Si layer 602 formed on a SiGe layer 604. An n-Si layer 606 is formed on top of the p-Si layer. However, in this example, anisotropic dry etching is performed before dopant-selective wet etching. Anisotropic dry etching etches the layer structure into the SiGe layer 604. Rinsing at 301E imparts dopant-type selectivity (promoting p-Si etching over n-Si etching) to the subsequent wet etching, so that the subsequent wet etching acts laterally on the exposed p-Si, preferentially over the exposed n-Si.

[0047] No aspect of this disclosure should be construed as restrictive, as numerous modifications, extensions, and omissions are equally likely. For example, while the method in Figure 3 demonstrates selective etching after circuit patterning, selective etching by the methods herein may also be useful before patterning or between separate patterning steps. The foregoing description specifically refers to etching compositions having selectivity based on dopant type, but the same or similar etching compositions may exhibit selectivity of etching rate based on dopant density, such as normal dopant density versus high dopant density versus degenerate doping. Furthermore, the same or similar etching compositions may exhibit sensitivity of etching rate based on dopant depth, such as deep doping versus shallow doping.

[0048] Again, while the aspects of this disclosure are not intended to be tied to any particular theory, the main chemical effect of dopant type and dopant density may be that it affects the space charge generated within the semiconductor material when the semiconductor surface reaches electrostatic equilibrium with the etching solution composition. Such equilibrium causes charge to accumulate at the interface between the semiconductor surface and the solution, depending on the dopant type, dopant density, and dopant depth. The relative etching rate reported in this disclosure as a function of dopant type is likely to be attributable to the changes in surface chemistry resulting from the accumulated surface charge and is therefore likely to be extendable to dopant depth and dopant density.

[0049] This disclosure is presented with reference, by example, to the attached drawings. Components, process stages, and other elements that may be substantially identical in one or more of the drawings are synchronously identified and described with minimal repetition. However, it should be noted that synchronously identified elements may differ to some extent. Furthermore, it should be noted that the drawings are schematic and not generally drawn to scale. Rather, the various drawing scales, aspect ratios, and number of components shown in the drawings may be intentionally distorted to make certain features or relationships easier to understand. Also, redundant explanations have been omitted in the descriptions of the drawings.

[0050] The configurations and / or methods described herein are illustrative in nature and numerous variations are possible; therefore, it will be understood that these particular embodiments or examples should not be considered limiting. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various operations illustrated and / or described may be performed in the order illustrated and / or described, in other orders, in parallel, or omitted. Similarly, the order of the processes described above may be changed. In some examples, the terms “about” and “approximately” extend x to include any value within the range of 0.9x to 1.1x when applied to a numerical value x; and in some examples, these terms extend x to include any value within the range of 0.95x to 1.05x.

[0051] Furthermore, unless otherwise specified, each composition and parameter disclosed herein may be in any combination. Furthermore, unless otherwise specified, the upper and lower limits of the values ​​disclosed herein may be in any combination. In addition, in this specification, "comprise" may be replaced with "consist essentially of" and "consist of" as needed. Furthermore, unless otherwise specified, "A and / or B" or "A and / or B" means "A, B, or both." In addition, unless otherwise specified, in this specification, amounts are in parts by mass or mass percent. In this specification, the amount used may be the content, and the content may be the amount used.

[0052] The subject matter of this disclosure includes all novel, non-obvious, and partial combinations of the various processes, systems, and configurations disclosed herein, as well as other features, functions, operations, and / or characteristics, and all of their equivalents.

[0053] In this specification, "doing or to do" such as "doing..." may be replaced with "process" or "step," and "process" may be replaced with "doing or to do" or "step," and "step" may be replaced with "doing" or "process." Furthermore, in this specification, "process" such as "process" may be "an apparatus or part configured to perform a process," "apparatus" may be "a mechanism or part," and "part" may be "a part or apparatus to be provided in a mechanism, apparatus, or system, etc."

[0054] Furthermore, this disclosure also discloses embodiments as illustrated below. <1> A method for reducing the etching rate of n-type silicon relative to the etching rate of a coexisting material that is a different material from the n-type silicon, prior to an oxidative wet etching process, Exposing the surface containing n-type silicon and the coexisting material to an aqueous rinse solution at a predetermined temperature for a predetermined time. This method includes [something]. <2> The surface is further exposed to a basic etching solution composition. <1> This is the method used. <3> The basic etching solution composition comprises a quaternary ammonium hydroxide. <3> This is the method used. <4> The aforementioned coexisting material includes one or more of p-type silicon, undoped silicon, polysilicon, or amorphous silicon. <1> This is the method used. <5> The aforementioned coexisting material includes a metal or a dielectric. <1> This is the method used. <6> The rinse solution contains more than 99% water. <1> This is the method used. <7> The rinse solution further contains an organic solvent. <6> This is the method used. <8> The rinse solution contains a base, <1> This is the method used. <9> The aforementioned base contains ammonium hydroxide, <8> This is the method used. <10> The rinse solution contains an acid. <1> This is the method used. <11> The aforementioned predetermined temperature is greater than 10°C. <1> This is the method used. <12> The aforementioned predetermined time is greater than 5 seconds. <1> This is the method used. <13> The rinse solution does not contain hydrogen fluoride under acidic conditions. <1> This is the method used. <14> A method for reducing the etching rate of n-type silicon after an oxidative wet etching process relative to the etching rate of a coexisting material that is a different material from the n-type silicon, Exposing the etched surface of n-type silicon and the coexisting material to a rinse solution at a predetermined temperature for a predetermined time. This method includes [something]. <15> The surface is further exposed to a basic etching solution composition. <14> This is the method used. <16> The aforementioned coexisting material includes one or more of the following: p-type silicon, polysilicon, amorphous silicon, metal, or dielectric. <14> This is the method used. <17> The rinse solution contains more than 99% water. <14> This is the method used. <18> The rinse solution contains a base, <14> This is the method used. <19> The predetermined temperature exceeds 10°C, the predetermined time exceeds 5 seconds, and the rinse solution does not contain hydrogen fluoride under acidic conditions. <14> This is the method used. [Explanation of Symbols]

[0055] 102 Epitaxial p-Si layer 10⁴ SiGe layer 106 Epitaxial n-Si layer 202 Epitaxial p-Si layer 204 SiGe layer 206 Epitaxial n-Si layer 402 p-Si layer 404 SiGe layer 406 n-Si layer 502 p-Si layer 504 SiGe layer 506 n-Si layer 602 p-Si layer 604 SiGe layer 606 n-Si layer

Claims

1. A method for reducing the etching rate of n-type silicon relative to the etching rate of a coexisting material that is a different material from the n-type silicon, prior to an oxidative wet etching process, Exposing the surface containing n-type silicon and the coexisting material to an aqueous rinsing solution at a predetermined temperature for a predetermined time. Methods that include...

2. The surface is further exposed to a basic etching solution composition. The method according to claim 1.

3. The basic etching solution composition comprises a quaternary ammonium hydroxide. The method according to claim 2.

4. The aforementioned coexisting material includes one or more of p-type silicon, undoped silicon, polysilicon, or amorphous silicon. The method according to claim 1.

5. The aforementioned coexisting material includes a metal or a dielectric. The method according to claim 1.

6. The rinse solution contains more than 99% water. The method according to claim 1.

7. The rinse solution further contains an organic solvent. The method according to claim 6.

8. The rinse solution contains a base, The method according to claim 1.

9. The aforementioned base contains ammonium hydroxide, The method according to claim 8.

10. The rinse solution contains an acid. The method according to claim 1.

11. The aforementioned predetermined temperature is greater than 10°C. The method according to claim 1.

12. The aforementioned predetermined time is greater than 5 seconds. The method according to claim 1.

13. The rinse solution does not contain hydrogen fluoride under acidic conditions. The method according to claim 1.

14. A method for reducing the etching rate of n-type silicon after an oxidative wet etching process relative to the etching rate of a coexisting material that is a different material from the n-type silicon, Exposing the etched surface of n-type silicon and the coexisting material to a rinse solution at a predetermined temperature for a predetermined time. Methods that include...

15. The surface is further exposed to a basic etching solution composition. The method according to claim 14.

16. The aforementioned coexisting material includes one or more of the following: p-type silicon, polysilicon, amorphous silicon, metal, or dielectric. The method according to claim 14.

17. The rinse solution contains more than 99% water. The method according to claim 14.

18. The rinse solution contains a base, The method according to claim 14.

19. The predetermined temperature exceeds 10°C, the predetermined time exceeds 5 seconds, and the rinse solution does not contain hydrogen fluoride under acidic conditions. The method according to claim 14.

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