Light-emitting drive device, light-emitting device, and light-emitting system

Abstract

The light-emitting drive circuit still needed further consideration regarding the control of the light-emitting elements when the system is stopped. [Solution] The light-emitting drive device comprises a bypass circuit and a bypass control circuit. The bypass circuit is configured to individually switch each of the multiple light-emitting elements connected in series between an inflow state and a retracted state. The bypass control circuit controls the bypass circuit so that when the enable signal is at a first logic level, it flows the drive current to each light-emitting element individually or retracts it, and when the enable signal is at a second logic level, it retracts the drive current from all light-emitting elements until the drive current falls below a predetermined current value.

Description

Technical Field

[0001] The invention disclosed in this specification relates to a light-emitting driving device, a light-emitting device, and a light-emitting system.

Background Art

[0002] Conventionally, there has been a light-emitting driving device that controls the light emission / extinguishing of a plurality of light-emitting elements.

[0003] As an example of the related prior art, Patent Document 1 can be cited.

Prior Art Document

Patent Document

[0004]

Patent Document 1

[0005] [Summary] The light-emitting driving circuit disclosed in Patent Document 1 had room for further consideration regarding the control of the light-emitting elements during operation stop.

[0006] The light-emitting driving device disclosed in this specification includes a bypass circuit and a bypass control circuit. The bypass circuit is configured to individually switch each of a plurality of serially connected light-emitting elements to an inflow state in which a drive current is injected or a retreat state in which the drive current is retreated without flowing. The bypass control circuit is configured to control the bypass circuit such that when an enable signal input from the outside is at a first logic level, the drive current is individually injected into or retreated from each light-emitting element, and when the enable signal is at a second logic level, until the drive current falls below a predetermined current value, the drive current is retreated without flowing into all the light-emitting elements.

[0007] The light-emitting device disclosed in this specification includes a plurality of light-emitting elements and the light-emitting driving device having the above configuration.

[0008] The light-emitting system disclosed herein comprises a light-emitting drive device having the above configuration, and a power supply device configured to generate and supply a drive current to the light-emitting device based on an enable signal. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows the configuration of the light-emitting system 100. [Figure 2] Figure 2 shows the internal configuration of the light-emitting device 2. [Figure 3] Figure 3 is a timing chart showing the timing of light emission control for the light-emitting element array 5. [Figure 4] Figure 4 is a timing chart showing the difference between the enable signal E input to power supply unit 1 and the enable signal E input to light-emitting device 2. [Figure 5] Figure 5 is a timing chart showing the enable signal E input to power supply unit 1 and the enable signal E input to light-emitting device 2. [Figure 6] Figure 6 shows the configuration of the light-emitting device 2 according to the first embodiment. [Figure 7] Figure 7 is a timing chart showing the delays of the charge enable CE and power enable RE. [Figure 8] Figure 8 shows an example of the internal configuration of the delay control circuit 16. [Figure 9] Figure 9 shows the internal configuration of a delay control circuit 16 in another example. [Figure 10] Figure 10 is a timing chart showing the internal control of this configuration example. [Figure 11] Figure 11 shows the configuration of the gate driver 9. [Figure 12] Figure 12 shows a light-emitting device 2 according to the second embodiment. [Figure 13] Figure 13 shows a light-emitting device 2 according to the third embodiment. [Figure 14] Figure 14 shows a light-emitting system 100 that includes multiple light-emitting devices 2.

[0010] [Detailed explanation] <Basic configuration of the light-emitting system 100> First, the basic configuration of the light-emitting system 100 will be explained. Figure 1 shows the configuration of the light-emitting system 100. As shown in Figure 1, the light-emitting system 100 receives an enable signal E from the ECU [Electronic Control Unit] 200. The ECU 200 is a central processing circuit, such as a microcontroller, that comprehensively controls the light-emitting system 100. The enable signal E is a digital signal that changes between two logic levels: high level and low level.

[0011] The light-emitting system 100 performs or stops the drive control of its own light-emitting elements (light-emitting elements D1 to D4, as described later in this figure) in response to the enable signal E. For example, when the enable signal E is at a high level, the light-emitting system 100 drives each light-emitting element. Conversely, when the enable signal E is at a low level, the light-emitting system 100 turns off each light-emitting element and enters a system stop state.

[0012] The light-emitting system 100 comprises a power supply unit 1 and a light-emitting device 2. Power supply unit 1 receives an enable signal E as input. Power supply unit 1 also operates on a battery voltage Vb supply. Power supply unit 1 generates a drive current I1 and supplies it to the light-emitting device 2. Specifically, it is as follows:

[0013] Power supply unit 1 comprises a boost circuit 3 and a drive current generation circuit 4. The boost circuit 3 receives an enable signal E as input. The boost circuit 3 also operates on the supply of battery voltage Vb. In response to the enable signal E, the boost circuit 3 generates a boosted voltage Vo by boosting the battery voltage Vb. The boost circuit 3 supplies the boosted voltage Vo to the drive current generation circuit 4.

[0014] The drive current generation circuit 4 receives the input of the enable signal E and the boosted voltage Vo. The drive current generation circuit 4 also operates by receiving the supply of the battery voltage Vb. The drive current generation circuit 4 generates a drive current I1 based on the enable signal E, the battery voltage Vb, and the boosted voltage Vo. The drive current generation circuit 4 supplies the drive current I1 to the light emitting device 2 (more specifically, the light emitting element array 5 described later).

[0015] FIG. 2 is a diagram showing the internal configuration of the light emitting device 2. As shown in FIGS. 1 and 2, the light emitting device 2 receives the input of the enable signal E. The light emitting device 2 also operates by receiving the supply of the battery voltage Vb. The light emitting device 2 causes the light emitting elements D1 to D4 to emit light based on the enable signal E and the drive current I1. Specifically, it is as follows.

[0016] The light emitting device 2 includes a light emitting element array 5 and a light emitting drive device 6. The light emitting element array 5 includes a plurality of light emitting elements (in the context of this figure, light emitting elements D1 to D4). The light emitting elements D1 to D4 are connected in series. Specifically, the anode of the light emitting element D4 is connected to the drive current generation circuit 4. The cathode of the light emitting element D4 is connected to the anode of the light emitting element D3. The cathode of the light emitting element D3 is connected to the anode of the light emitting element D2. The cathode of the light emitting element D2 is connected to the anode of the light emitting element D1. The cathode of the light emitting element D1 is connected to the node n1.

[0017] Here, the node n1 is connected to the ground terminal GND. However, the node n1 may be a connection node to another predetermined circuit instead of the ground terminal GND.

[0018] The light emitting drive device 6 includes a battery terminal Tb and an enable terminal Te. The light emitting drive device 6 receives the input of the enable signal E via the enable terminal Te. The light emitting drive device 6 also operates by receiving the supply of the battery voltage Vb via the battery terminal Tb. The light emitting drive device 6 controls the light emission of the light emitting element array 5 according to the enable signal E. The specific configuration of the light emitting drive device 6 is as follows.

[0019] The light-emitting drive device 6 includes a bypass circuit 7 and a bypass control circuit 8. The light-emitting drive device 6 is a semiconductor integrated circuit (=IC [integrated circuit]) in which the bypass circuit 7 and the bypass control circuit 8 are integrated.

[0020] The bypass circuit 7 is configured to switch each of the light-emitting elements D1 to D4 to a current inflow state in which the drive current I1 is made to flow in, or a current retreat state in which the drive current I1 is not made to flow and is retreated.

[0021] The bypass circuit 7 includes a plurality of switch elements (in the context of this figure, switch elements SW1 to SW4). The switch elements SW1 to SW4 are N-channel MOSFETs [metal-oxide-semiconductor field-effect transistors]. Each of the switch elements SW1 to SW4 is connected in parallel to each of the light-emitting elements D1 to D4. Specifically, it is as follows.

[0022] The source of the switch element SW1 is connected to the cathode of the light-emitting element D1 via the terminal T1. The drain of the switch element SW1, together with the source of the switch element SW2, is connected to the anode of the light-emitting element D1 and the cathode of the light-emitting element D2 via the terminal T2.

[0023] The drain of the switch element SW2, together with the source of the switch element SW3, is connected to the anode of the light-emitting element D2 and the cathode of the light-emitting element D3 via the terminal T3. The drain of the switch element SW3, together with the source of the switch element SW4, is connected to the anode of the light-emitting element D3 and the cathode of the light-emitting element D4 via the terminal T4. The drain of the switch element SW4 is connected to the anode of the light-emitting element D4 via the terminal T5.

[0024] Each gate of switch elements SW1 to SW4 receives drive signals G1 to G4 from the bypass control circuit 8 (more specifically, the gate drivers 9 to 12 described later). Each of the switch elements SW1 to SW4 turns on or off according to the drive signals G1 to G4 input to its gate.

[0025] For example, when the switch element SW4 is in the ON state, the drive current I1 does not flow into the light-emitting element D4, but flows into the switch element SW4. At this time, the light-emitting element D4 is in a current-reserved state and turns off. Conversely, when the switch element SW4 is in the OFF state, the drive current I1 flows into the light-emitting element D4. At this time, the light-emitting element D4 is in a current-inflow state and emits light.

[0026] Similarly, the light-emitting element D3 switches between a current-reduced state and a current-inflow state depending on the on / off state of the switch element SW3. The light-emitting element D2 also switches between a current-reduced state and a current-inflow state depending on the on / off state of the switch element SW2. The light-emitting element D1 also switches between a current-reduced state and a current-inflow state depending on the on / off state of the switch element SW1.

[0027] The bypass control circuit 8 generates drive signals G1 to G4 in response to the enable signal E. Specifically, it is as follows: The bypass control circuit 8 comprises an internal power supply circuit 15, gate drivers 9 to 12, a main control circuit 13, and a charge pump 14.

[0028] The internal power supply circuit 15 receives the battery voltage Vb and generates the internal power supply voltage Vreg. The internal power supply circuit 15 supplies the internal power supply voltage Vreg to the gate drivers 9-12, the main control circuit 13, and the charge pump 14.

[0029] The main control circuit 13 operates by receiving the internal power supply voltage Vreg. The main control circuit 13 also receives the enable signal E as input. Based on the enable signal E, the main control circuit 13 generates control signals S1 to S4. The main control circuit 13 inputs the control signals S1 to S4 to the gate drivers 9 to 12.

[0030] The charge pump 14 receives an enable signal E as input. The charge pump 14 also receives an internal power supply voltage Vreg. In response to the enable signal E, the charge pump 14 boosts the internal power supply voltage Vreg to generate a charge voltage Vcp. The charge pump 14 supplies the charge voltage Vcp to gate drivers 9-12.

[0031] The gate drivers 9 to 12 generate drive signals G1 to G4 based on the charge voltage Vcp in response to the control signals S1 to S4 input to them.

[0032] Let the voltage at terminal T1 be voltage V1, the voltage at terminal T2 be voltage V2, the voltage at terminal T3 be voltage V3, the voltage at terminal T4 be voltage V4, and the voltage at terminal T5 be voltage V5.

[0033] The voltage value of the high-level drive signal G1 is set to exceed the sum of the voltage V1 and the ON threshold voltage of the switch element SW1. Therefore, when the drive signal G1 is at a high level, the switch element SW1 is reliably turned on. Conversely, when the drive signal G1 is at a low level, the switch element SW1 is turned off.

[0034] The voltage value of the high-level drive signal G2 is set to exceed the sum of the voltage V2 and the ON threshold voltage of the switch element SW2. Therefore, when the drive signal G2 is high level, the switch element SW2 is reliably turned on. Conversely, when the drive signal G2 is low level, the switch element SW2 is turned off.

[0035] The voltage value of the high-level drive signal G3 is set to exceed the sum of the voltage V3 and the ON threshold voltage of the switch element SW3. Therefore, when the drive signal G3 is high level, the switch element SW3 is reliably turned on. Conversely, when the drive signal G3 is low level, the switch element SW3 is turned off.

[0036] The voltage value of the high-level drive signal G4 is set to exceed the sum of the voltage V4 and the ON threshold voltage of the switch element SW4. Therefore, when the drive signal G4 is high level, the switch element SW4 is reliably turned on. Conversely, when the drive signal G4 is low level, the switch element SW4 is turned off.

[0037] The relationship G4 > G3 > G2 > G1 holds true. That is, the drains of the adjacent switch elements SW1 to SW3 are connected to the sources of each of the switch elements SW2 to SW4. Therefore, the gate-source voltage of switch elements SW2 to SW4 is increased by the drain voltage of the adjacent switch elements SW1 to SW3. This is why the above relationship holds true.

[0038] The charge pump 14 generates a charge voltage Vcp that can turn all of the switch elements SW1 to SW4 on and off. Specifically, the charge pump 14 sets the voltage value of the charge voltage Vcp higher than the highest voltage high-level drive signal G4.

[0039] When the enable signal E rises to a high level, light emission control is performed on the light-emitting element array 5. Specifically, this is as follows:

[0040] <Example of control of the light-emitting system 100> Figure 3 is a timing chart showing the timing of light emission control for the light-emitting element array 5. In Figure 3, the drive current I1, boost voltage Vo, and enable signal E are shown from top to bottom.

[0041] As shown in Figure 3, when time t1 arrives, the enable signal E rises to a high level. The boost circuit 3 receives the high-level enable signal E and starts boosting the voltage based on the battery voltage Vb. Then, when time t2 arrives, the boosted voltage Vo begins to rise. After the boosted voltage Vo has risen to a predetermined value, when time t3 arrives, the drive current generation circuit 4 generates a drive current I1 based on the boosted voltage Vo. The drive current I1 flows into the light-emitting device 2.

[0042] When time t4 arrives, the enable signal E falls to a low level. The boost circuit 3, upon receiving the low-level enable signal E, terminates its boost operation. As a result, the boosted voltage Vo decreases after time t4. The drive current generation circuit 4, upon receiving the low-level enable signal E, also terminates the generation of the drive current I1. Consequently, the drive current I1 no longer flows to the light-emitting device 2.

[0043] Therefore, the light-emitting drive device 6 controls the emission of light-emitting elements D1 to D4 between time t3 and time t4. When time t4 arrives, the light-emitting drive device 6 stops driving while turning off the light-emitting elements D1 to D4.

[0044] <Considerations on the instantaneous illumination of light-emitting elements> As described above, the light-emitting system 100 drives and controls its own light-emitting elements (light-emitting elements D1 to D4) in accordance with the enable signal E. Here, the enable signal E is input to both the power supply unit 1 and the light-emitting device 2 of the light-emitting system 100. Therefore, each of the power supply unit 1 and the light-emitting device 2 switches its operation start / stop according to the logic level of the enable signal E input to it.

[0045] By the way, if the light-emitting device 2 stops operating while the drive current I1 is flowing to it, there is a risk that the light-emitting elements D1 to D4 will momentarily light up. Momentarily lighting up means emitting light instantaneously. If the light-emitting elements D1 to D4, which are in an off state, momentarily light up at the timing when the light-emitting system 100 stops, the light-emitting elements D1 to D4 will light up at the timing when they should be off. In such a case, the operation of the light-emitting system 100 will deviate significantly from its intended operation, which is undesirable.

[0046] One possible cause of the momentary light flash is the following: There may be a slight time delay in the input enable signal E between the power supply unit 1 and the light-emitting device 2. This delay can be caused by differences in the wiring length of the enable signal E (more specifically, the difference between the wiring length from ECU200 to power supply unit 1 and the wiring length from ECU200 to light-emitting device 2), differences in wiring resistance, noise, etc.

[0047] When such a discrepancy occurs, the timing of the start / stop operation of power supply unit 1 and the timing of the start / stop operation of light-emitting device 2 may not coincide.

[0048] Figure 4 is a timing chart showing the difference between the enable signal E input to power supply unit 1 (referred to here as enable signal E1) and the enable signal E input to light-emitting device 2 (referred to here as enable signal E2).

[0049] As shown in Figure 4, let's assume that the enable signal E1 is delayed compared to the enable signal E2. Suppose the ECU200 drops the enable signal E to a low level. Immediately afterward, at time t4', the enable signal E2 drops to a low level. Meanwhile, the enable signal E1 remains at a high level at time t4'. A short time after time t4', at time t5, the enable signal E1 drops to a low level. Then, a short time after time t5, at time t6, the drive current I1 stops flowing.

[0050] In this case, at time t4', the light-emitting device 2 stops operating before the power supply device 1. Specifically, the charge pump 14 stops operating while the drive current I1 is flowing. As a result, the supply of charge voltage Vcp to gate drivers 9~12 stops. Consequently, even though the drive current I1 is flowing, the gates of switch elements SW1~SW4 become high impedance. Consequently, switch elements SW1~SW4, which were on just before time t4', can no longer maintain the on state after time t4'. However, between time t4' and time t6, the drive current I1 flows into the light-emitting device 2. As a result, the light-emitting elements D1~D4, which were in a current-reserved state, switch to a current-inflow state, and there is a risk that the drive current I1 will flow in and cause them to emit light. When time t6 arrives, the drive current I1 will stop flowing, and the light-emitting elements D1~D4 will turn off, but there is a risk that they will emit light between time t4' and time t6.

[0051] Other causes of momentary illumination include the following. For example, as shown in Figure 5, suppose there is almost no difference between the enable signal E1 and the enable signal E2. In this case, when the ECU 200 drops the enable signal E to a low level, the power supply unit 1 and the light-emitting device 2 stop operating almost simultaneously at time t7. However, if there is a delay in each operation within the light-emitting device 2, or if a drive current I1 flows to the light-emitting elements D1 to D4 due to residual charge, the operation of the charge pump 14 may stop while the drive current I1 is being supplied to the light-emitting device 2. In this case, there is a risk that the light-emitting elements D1 to D4 will emit light between time t7, which is the falling edge timing of the enable signal E2, and time t8, when the supply of the drive current I1 to the light-emitting device 2 ends.

[0052] To address these issues, the light-emitting device 2 of this disclosure is capable of suppressing momentary illumination of each light-emitting element (light-emitting elements D1 to D4) when the light-emitting system 100 is stopped. The light-emitting systems 100 according to each embodiment of this disclosure will be described in detail below.

[0053] <Regarding the light-emitting device 2 according to the first embodiment of this disclosure> Figure 6 shows the configuration of the light-emitting device 2 according to the first embodiment. As shown in Figure 6, the bypass control circuit 8 of this disclosure includes an OR gate OG in addition to the configuration described above. Furthermore, the main control circuit 13 according to this disclosure is designed to suppress the problems described above in its internal configuration. A detailed explanation follows below.

[0054] The main control circuit 13 includes a delay control circuit 16 and a driver control circuit 17. The delay control circuit 16 generates a power supply enable RE, a charge enable CE, and a switch drive enable SE in response to the enable signal E1.

[0055] The delay control circuit 16 generates the charge enable CE with a delay relative to the power enable RE. The delay control circuit 16 also generates the switch drive enable SE with a delay relative to the charge enable CE. Details of the delay control circuit 16 will be described later.

[0056] The first input terminal of OR gate OG is connected to the enable terminal Te. The second input terminal of OR gate OG is connected to the main control circuit 13. The output terminal of OR gate OG is input to the internal power supply circuit 15.

[0057] The OR gate OG receives an enable signal E1 at its first input terminal. The OR gate OG receives a power enable RE at its second input terminal. The OR gate OG sets the battery enable BE to a high level when at least one of the enable signal E1 and the power enable RE is at a high level. The OR gate OG also sets the battery enable BE to a low level when both the enable signal E1 and the power enable RE are at a low level.

[0058] The internal power supply circuit 15 receives a high-level battery enable BE input and generates the internal power supply voltage Vreg. The internal power supply circuit 15 also stops generating the internal power supply voltage Vreg when it receives a low-level battery enable BE input.

[0059] The charge pump 14 receives a high-level input from the charge enable CE and generates a charge voltage Vcp. The charge pump 14 also stops generating the charge voltage Vcp when it receives a low-level input from the charge enable CE.

[0060] The driver control circuit 17 receives a high-level input of the switch drive enable SE and sets the control signals S1 to S4 to any logic level to arbitrarily control the gate drivers 9 to 12. In other words, at this time, the light emission state of the light-emitting elements D1 to D4 is controlled to any state by the driver control circuit 17. On the other hand, the driver control circuit 17 receives a low-level input of the switch drive enable SE and sets the control signals S1 to S4 to a high level to control the gate drivers 9 to 12 so that the light-emitting elements D1 to D4 are turned off.

[0061] <Example of control of the main control circuit 13> Figure 7 is a timing chart showing the delays of the charge enable CE and power enable RE. As shown in Figure 7, at time t10, the enable signal E1 falls to a low level. In response to the falling edge of the enable signal E1, the main control circuit 13 sets the switch drive enable SE to a low level without any intentional delay. In response, the gate drivers 9 to 12 turn on the switch elements SW1 to SW4. As a result, at time t10, the light-emitting elements D1 to D4 are in a current-saving state (= off state).

[0062] At time t11, after a delay time d1 has elapsed from time t10, the delay control circuit 16 lowers the charge enable CE to a low level. In response to the falling edge of the charge enable CE, the charge pump 14 stops generating the charge voltage Vcp. As a result, the gate drivers 9-12 stop generating the drive signals G1-G4. Therefore, at time t11, the gates of the switch elements SW1-SW4 are in a high-impedance state.

[0063] Then, at time t12, after a delay time d2 has elapsed from time t12, the delay control circuit 16 drops the power enable RE to a low level. The OR gate OG then receives the low-level enable signal E1 and the low-level power enable RE input and drops the battery enable BE to a low level. The internal power supply circuit 15 stops generating the internal power supply voltage Vreg in response to the falling edge of the power enable RE. As a result, at time t13, a relatively short time after time t12, the internal power supply voltage Vreg becomes 0V. Therefore, at time t13, the gate drivers 9~12, the main control circuit 13, and the charge pump 14 are all in a stopped state. This suppresses the power consumption of the light-emitting device 2 while the light-emitting system 100 is stopped.

[0064] Therefore, it is preferable to set the delay time d1 so that the supply of the drive current I1 to the light-emitting device 2 ends between the time when the ECU200 drops the enable signal E to a low level and time t11. In this way, when the supply of the drive current I1 to the light-emitting device 2 ends, the charge enable CE is maintained at a high level, and the charge pump 14 continues to generate the charge voltage Vcp. As a result, it is possible to suppress the gates of the switch elements SW1~SW4 from becoming high impedance when the drive current I1 is supplied to the light-emitting device 2, as described above. Consequently, momentary illumination of the light-emitting elements D1~D4 can be suppressed.

[0065] <Example 1 of configuration of delay control circuit 16> Next, an example of the internal configuration of the delay control circuit 16 will be described. Figure 8 shows an example of the internal configuration of the delay control circuit 16. As shown in Figure 8, the delay control circuit 16 in this configuration example includes a signal generation unit 18 and a counter 19.

[0066] The signal generation unit 18 receives the enable signal E1 and generates the charge enable CE, power supply enable RE, and switch drive enable SE. The counter 19 receives the input of the charge enable CE and outputs the charge enable CE with a delay time of d1. The counter 19 also receives the input of the power supply enable RE and outputs the power supply enable RE with a delay time equal to the sum of the delay times d1 and d2.

[0067] <Example 2 of the configuration of the delay control circuit 16> The delay control circuit 16 can also adopt the following internal configuration instead of the internal configuration example described above. Figure 9 shows the internal configuration of another example of the delay control circuit 16. As shown in Figure 9, the delay control circuit 16 in this configuration example includes a constant current source 20, a comparator 21, a threshold voltage generation circuit 22, a switch SWn, and a capacitor C1.

[0068] The constant current source 20 is connected to the internal power supply circuit 15 and to node n2. The non-inverting input terminal (+) of the comparator 21 is connected to node n2. The inverting input terminal (-) of the comparator 21 is connected to the threshold voltage generation circuit 22. The first terminal of switch SWn is connected to node n2. The second terminal of switch SWn is connected to the ground terminal GND. Capacitor C1 is externally connected to the light-emitting drive device 6 via terminal Tn to the ground terminal GND. Terminal Tn is connected to node n2 and capacitor C1.

[0069] The constant current source 20 receives the battery voltage Vb and generates a constant current I2. Switch SWn turns on when it receives a high-level enable signal E1. Switch SWn also turns off when it receives a low-level enable signal E1. The threshold voltage generation circuit 22 generates a threshold voltage Vth1, which is a predetermined constant voltage. Comparator 21 outputs a charge enable CE according to the comparison result between the voltage at node n2 and the threshold voltage Vth1.

[0070] Figure 10 is a timing chart showing the internal control of this configuration example. As shown in Figure 10, when the enable signal E1 is high (before time t20 in Figure 10), the switch SWn is ON as described above. Therefore, the constant current I2 flows to the ground terminal GND, and the capacitor C1 is not charged. As a result, the voltage at node n2 is below the threshold voltage Vth1. Therefore, at this time, the comparator 21 maintains the charge enable CE at a high level.

[0071] When the enable signal E1 falls to a low level, the switch SWn turns off as described above. Then a constant current I2 flows into capacitor C1, and capacitor C1 is charged. As a result, the voltage at node n2 rises. Then, at time t21, after a delay time d1 has elapsed from time t20, the voltage at node n2 exceeds the threshold voltage Vth1. Therefore, when time t20 arrives, comparator 21 drops the charge enable CE to a low level.

[0072] The delay time d1 is determined based on the capacitance of capacitor C1. Capacitor C1 is externally connected to the light-emitting drive device 6. Therefore, a capacitor C1 with an arbitrary capacitance is selected and connected to terminal Tn to achieve the desired delay time d1.

[0073] <Example configurations for gate drivers 9-12> This section describes the configuration examples for gate drivers 9 to 12. Figure 11 shows the configuration of gate driver 9. Since gate drivers 9 to 12 have basically the same configuration, only gate driver 9 will be explained, and the explanations for gate drivers 10 to 12 will be omitted.

[0074] As shown in Figure 11, the gate driver 9 comprises a regulator 30 and a drive circuit 31. The regulator 30 receives a charge voltage Vcp and steps down the charge voltage Vcp to generate an upper voltage Vh and a lower voltage Vl.

[0075] The input terminal of the drive circuit 31 receives the input of the control signal S1. The upper power supply terminal of the drive circuit 31 receives the input of the upper voltage Vh. The lower power supply terminal of the drive circuit 31 receives the input of the lower voltage Vl. The drive circuit 31 receives the supply of the upper voltage Vh and the lower voltage Vl and outputs the drive signal G1. Specifically, when the drive circuit 31 sets the drive signal G1 to a high level, the drive signal G1 corresponds to the upper voltage Vh. Conversely, when the drive circuit 31 sets the drive signal G1 to a low level, the drive signal G1 corresponds to the lower voltage Vl.

[0076] As described above, the high-level voltage values ​​of the drive signals G1 to G4 increase in the order of drive signals G1 to G4. Therefore, each regulator 30 of gate drivers 9 to 12 generates an upper voltage Vh that increases in the order of gate drivers 9 to 12. Specifically, this is as follows:

[0077] The regulator 30 of gate driver 9 generates an upper voltage Vh corresponding to the high-level drive signal G1. The regulator 30 of gate driver 10 generates an upper voltage Vh corresponding to the high-level drive signal G2. The regulator 30 of gate driver 11 generates an upper voltage Vh corresponding to the high-level drive signal G3. The regulator 30 of gate driver 12 generates an upper voltage Vh corresponding to the high-level drive signal G4.

[0078] <Regarding the light-emitting device 2 according to the second embodiment> Next, the light-emitting device 2 according to the second embodiment will be described in detail. Note that the light-emitting device 2 of this embodiment has a basically the same configuration as the first embodiment. Therefore, components common to both the first and second embodiments will be denoted by the same reference numerals and their descriptions will be omitted. The description will focus on the components that differ from the first embodiment.

[0079] Figure 12 shows a light-emitting device 2 according to the second embodiment. As shown in Figure 12, the main control circuit 13 of this embodiment includes a driver control circuit 23 and a current detection circuit 24. In addition, a sense resistor R1 is externally connected to the light-emitting device 2 of this embodiment via terminals T6 and T7.

[0080] The first end of sense resistor R1 is connected to terminal T6 and the cathode of light-emitting element D1. The second end of sense resistor R1 is connected to terminal T7 and node n1.

[0081] When the drive current I1 is supplied to the light-emitting device 2, current flows from the cathode or terminal T1 of the light-emitting element D1 to the sense resistor R1. This generates a voltage V6 across the sense resistor R1, corresponding to the resistance value of the sense resistor R1.

[0082] The driver control circuit 23 receives an enable signal E1. Upon receiving a high-level enable signal E1, the driver control circuit 23 generates control signals S1 to S4 of arbitrary logic levels to control gate drivers 9 to 12 so that any light-emitting elements D1 to D4 enter any desired light-emitting state. The driver control circuit 23 also receives a low-level enable signal E1 and generates low-level control signals S1 to S4 to control gate drivers 9 to 12 so that the light-emitting elements D1 to D4 turn off.

[0083] The current detection circuit 24 is configured to detect whether or not current is flowing through the sense resistor R1 and to generate a current detection signal Vse according to the detection result. The current detection signal Vse is a digital signal that changes between two logic levels, high level or low level. The current detection circuit 24 inputs the current detection signal Vse to the charge pump 14.

[0084] In this embodiment, the charge pump 14 receives a high-level current detection signal Vse and generates a charge voltage Vcp based on the battery voltage Vb. The charge pump 14 also receives a low-level current detection signal Vse and terminates the generation of the charge voltage Vcp.

[0085] The specific configuration of the current detection circuit 24 is as follows. The current detection circuit 24 includes a threshold voltage generation circuit 25 and a comparator 26. The threshold voltage generation circuit 25 generates a threshold voltage Vth2, which is a predetermined constant voltage.

[0086] The non-inverting input terminal (+) of comparator 26 is connected to terminal T6. The inverting input terminal (-) of comparator 26 is connected to comparator 26.

[0087] The non-inverting input terminal (+) of comparator 26 is subjected to a voltage V6 via terminal T6. The inverting input terminal of comparator 26 is subjected to a threshold voltage Vth2 via terminal T7. Comparator 26 generates a current detection signal Vse based on the comparison result between voltage V6 and threshold voltage Vth2, and inputs it to charge pump 14.

[0088] For example, when the voltage V6 exceeds the threshold voltage Vth2 (i.e., when the drive current I1 exceeds a predetermined current value), the comparator 26 raises the current detection signal Vse to a high level. In this state, suppose the enable signal E1 falls from a high level to a low level. Then, as described above, the driver control circuit 23 drops the control signals S1 to S4 to a high level, turning on the switch elements SW1 to SW4. As a result, the light-emitting elements D1 to D4 enter a current-saving state and turn off. At this time, the drive current I1 flows into the sense resistor R1 via terminal T1.

[0089] Suppose, as described above, there is a discrepancy between the enable signal E1 and the enable signal E2. Furthermore, suppose that the enable signal E1 falls to a low level while the drive current I1 is being supplied to the light-emitting device 2. In this case, as long as the drive current I1 is supplied to the light-emitting device 2 in excess of a predetermined amount, the current detection signal Vse will remain at a high level as described above. Therefore, even if the enable signal E1 falls to a low level, the charge pump 14 will continue to generate the charge voltage Vcp until the current value of the drive current I1 falls below a predetermined value (= the voltage V6 falls below the threshold voltage Vth2) and the threshold voltage generation circuit 25 stops detecting the drive current I1. Consequently, the ON state of the switch elements SW1 to SW4 can be maintained while the drive current I1 is being supplied to the light-emitting device 2. This prevents the light-emitting elements D1 to D4 from momentarily lighting up at the stopping timing of the light-emitting system 100.

[0090] <Regarding the light-emitting device 2 according to the third embodiment> Next, the light-emitting device 2 according to the third embodiment will be described in detail. The light-emitting device 2 of this embodiment also has a basically common configuration with that of the first embodiment. Therefore, components common to both the first and third embodiments are denoted by the same reference numerals and their descriptions are omitted. The description will focus on the components that differ from those of the first embodiment.

[0091] Figure 13 shows a light-emitting device 2 according to the third embodiment. As shown in Figure 13, the light-emitting drive device 6 according to this embodiment includes a bypass circuit 7 and a separate bypass circuit 27. The bypass circuit 27 detects the falling edge of the enable signal E1 to a low level and causes the drive current I1 to flow through itself to the ground terminal, thereby putting the light-emitting elements D1 to D4 into a current-reduced state. Specifically, it is as follows.

[0092] The bypass circuit 27 comprises a switch element SW5 and a driver control circuit 28. The switch element SW5 is an N-channel MOSFET. The source of the switch element SW5 is connected to terminal T1, along with the source of the switch element SW1. The drain of the switch element SW5 is connected to terminal T5, along with the drain of the switch element SW4. The gate of the switch element SW5 receives the input of the drive signal G5.

[0093] Switch element SW5 turns on when a high-level drive signal G5 is input to its gate. Conversely, switch element SW5 turns off when a low-level drive signal G5 is input to its gate.

[0094] The driver control circuit 28 operates on the supply of battery voltage Vb. The driver control circuit 28 also receives an enable signal E1 as input. Upon receiving a high-level enable signal E1, the driver control circuit 28 lowers the drive signal G5 to a low level. Furthermore, when the driver control circuit 28 detects the falling edge of the enable signal E1 to a low level, it raises the drive signal G5 to a high level.

[0095] In this embodiment, the charge pump 14 generates a charge voltage Vcp when it receives a high-level enable signal E1. The charge pump 14 also stops generating the charge voltage Vcp when it receives a low-level enable signal E1.

[0096] The main control circuit 13 of this embodiment includes a driver control circuit 29. The driver control circuit 29 receives a high-level enable signal E1 and generates control signals S1 to S4 of arbitrary logic levels to control gate drivers 9 to 12 so that any light-emitting elements D1 to D4 enter any desired light-emitting state. The driver control circuit 29 also receives a low-level enable signal E1 and generates low-level control signals S1 to S4 so that the light-emitting elements D1 to D4 turn off, thereby controlling gate drivers 9 to 12.

[0097] Suppose the ECU200 drops the enable signal E to a low level. At this time, the charge pump 14, driver control circuit 28, and driver control circuit 29 receive the low-level enable signal E1. Then, as described above, the charge pump 14 stops generating the charge voltage Vcp.

[0098] At this time, the driver control circuit 28 raises the drive signal G5 to a high level. As described above, this turns on the switch element SW5. As a result, even if the charge pump 14 stops the charge voltage Vcp while the drive current I1 is being supplied to the light-emitting device 2, and it becomes impossible to maintain the ON state of the switch elements SW1 to SW4, the drive current I1 will flow to node n1 via the switch element SW5 and terminal T1, after retracting the light-emitting elements D1 to D4. Therefore, the momentary illumination of the light-emitting elements D1 to D4 as described above can be suppressed.

[0099] <Regarding the light-emitting system 100 equipped with multiple light-emitting devices 2> The light-emitting system 100 of each of the above embodiments can be configured to include a plurality of light-emitting devices 2. For example, a light-emitting system 100 comprising a plurality of light-emitting devices 2 according to the first embodiment has the following configuration.

[0100] Figure 14 shows a light-emitting system 100 comprising multiple light-emitting devices 2. As shown in Figure 14, the light-emitting system 100 in this example configuration comprises a first light-emitting device 2a and a second light-emitting device 2b. Both light-emitting devices 2a and 2b correspond to the previously described light-emitting device 2. The node n1 described above is a connection node between terminal T1 of light-emitting device 2a and terminal T5 of light-emitting device 2b. Terminal T1 of light-emitting device 2b is connected to the ground terminal together with the cathode of the light-emitting element D1.

[0101] The enable signal E1 is input to both the enable terminal Te of light-emitting device 2a and the enable terminal Te of light-emitting device 2b.

[0102] As in this example configuration, if the light-emitting system 100 is configured to include multiple light-emitting devices 2 (referred to as light-emitting devices 2a and 2b in Figure 14), the instantaneous illumination described above can be suppressed in the light-emitting system 100 which has a large number of light-emitting elements. Note that the light-emitting devices 2 here are not limited to those of the first embodiment, but may also be light-emitting devices 2 of the second embodiment or light-emitting devices 2 of the third embodiment.

[0103] <Variation> Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure. For example, although it is stated that an enable signal E is input to switch SWn (see Figure 9), a switch drive enable SE may be used instead of the enable signal E.

[0104] For example, the light-emitting element array 5 in each of the above embodiments includes light-emitting elements D1 to D4, but it may also be composed of, for example, two light-emitting elements or five or more light-emitting elements.

[0105] <Note> The light-emitting drive device (6) disclosed in the specification is configured to include a bypass circuit (7) configured to switch each of the multiple series-connected light-emitting elements (D1 to D4) individually between an inflow state in which a drive current (I1) is supplied, and an escape state in which the drive current (I1) is not supplied and is saved, and a bypass control circuit (8) configured to control the bypass circuit (7) such that when an externally input enable signal (E, E1, E2) is at a first logic level, the drive current (I1) is supplied to each light-emitting element (D1 to D4) individually or saved, and when the enable signal (E, E1, E2) is at a second logic level, the drive current (I1) is saved and does not flow to all light-emitting elements (D1 to D4) until the drive current (I1) falls below a predetermined current value (first configuration).

[0106] The first configuration of the light-emitting drive device (6) is preferably configured such that the bypass circuit (7) includes a plurality of switch elements (SW1 to SW4) connected in parallel to each light-emitting element (D1 to D4), such that when the ON state the drive current (I1) is saved from the light-emitting elements (D1 to D4) to itself so that the drive current (I1) does not flow to the light-emitting elements (D1 to D4), and when the OFF state the drive current (I1) flows to the light-emitting elements (D1 to D4) (second configuration).

[0107] The light-emitting drive device (6) according to the first or second configuration preferably includes a bypass control circuit (8) which comprises a delay control circuit (16) configured to generate a first control signal (SE) and a second control signal (CE) with a predetermined delay time (d1) added to the first control signal (SE) based on at least one of the logic levels of the enable signals (E, E1, E2) and the drive current (I1); an operating voltage generation circuit (14) configured to generate a first operating voltage (Vcp) in response to the second control signal (CE); and a drive control circuit (17) configured to receive the first operating voltage (Vcp) and drive the bypass circuit (7) to switch between an inflow state and a retracted state for each light-emitting element (D1 to D4) based on the first control signal (SE) (third configuration).

[0108] In the third configuration, the light-emitting drive device (6) is configured such that the delay control circuit (16) receives an enable signal (E, E1, E2) of the first logic level and sets the first control signal (SE) to the third logic level, receives an enable signal (E, E1, E2) of the second logic level and sets the first control signal (SE) to the fourth logic level, and after a delay time (d1) has elapsed from the timing when the enable signals (E, E1, E2) switch from the first logic level to the second logic level, the second control signal (CE) switches from the third logic level to the fourth logic level, and the operating voltage generation circuit (14) receives an input of the first control signal (SE) of the third logic level and generates a first operating voltage (Vcp), and receives an input of the first control signal (SE) of the fourth logic level and stops generating the first operating voltage (Vcp) (fourth configuration).

[0109] The first configuration of the light-emitting drive device (6) is preferably configured such that the bypass control circuit (8) includes a current detection circuit (24) configured to detect a drive current (I1) and generate a detection signal according to the detection result, and a drive control circuit (17) configured to receive a first operating voltage (Vcp) and drive the bypass circuit (7) to switch between an inflow state and a retracted state for each light-emitting element (D1 to D4) based on enable signals (E, E1, E2) (fifth configuration).

[0110] The first configuration of the light-emitting drive device (6) includes a second bypass circuit (27) connected in parallel to the light-emitting array (5) consisting of individual light-emitting elements (D1 to D4), configured to either supply a drive current (I1) to the light-emitting array (5) or to divert the drive current (I1) from the light-emitting array (5) so that no drive current (I1) flows to any of the light-emitting elements (D1 to D4), and a first bypass circuit (7) connected in parallel to each light-emitting element (D1 to D4), configured to switch each light-emitting element (D1 to D4) individually between a flow-in state and a diversion state when the drive current (I1) flows into the light-emitting array (5). The bypass control circuit (8) is preferably configured to include an operating voltage generation circuit (14) configured to generate a first operating voltage (Vcp) in response to enable signals (E, E1, E2), a first bypass drive control circuit (29) configured to receive the first operating voltage (Vcp) and drive the first bypass circuit (7) to switch between an inflow state and a retraction state for each light-emitting element (D1~D4), and a second bypass drive control circuit (28) configured to operate based on an externally supplied second operating voltage (Vcp) and drive the second bypass circuit (27) in response to enable signals (E, E1, E2) (sixth configuration).

[0111] The light-emitting drive device (6) according to any of the first to sixth configurations may be configured to integrate a bypass circuit (7) and a bypass control circuit (8) (seventh configuration).

[0112] The light-emitting device (2) disclosed in the specification may be configured to include a plurality of light-emitting elements (D1 to D4) and a light-emitting drive device (6) relating to any of the first to seventh configurations (eighth configuration).

[0113] The light-emitting device (2) according to the eighth configuration is preferably configured to include multiple light-emitting drive devices (6) (ninth configuration).

[0114] The light-emitting system (100) disclosed in the specification is configured to include a light-emitting device (2) according to the eighth or ninth configuration, and a power supply device (1) configured to generate a drive current (I1) based on enable signals (E, E1, E2) and supply it to the light-emitting device (2) (the tenth configuration).

[0115] The light-emitting system (100) according to the tenth configuration is preferably configured such that the power supply (1) includes a boost circuit (3) configured to generate a boosted voltage (Vo) by boosting an externally supplied power supply voltage (Vb) based on enable signals (E, E1, E2), and a drive current generation circuit (4) configured to generate a drive current (I1) by converting the boosted voltage (Vo) into a current-voltage (eleventh configuration). [Explanation of Symbols]

[0116] 1 Power supply 2, 2a, 2b Light-emitting devices 3. Boost Circuit 4. Drive current generation circuit 5. Light-emitting element array 6. Light-emitting drive device 7 Bypass Circuit (First Bypass Circuit) 8 Bypass control circuit 9-12 gate driver 13 Main control circuit 14. Charge pump (operating voltage generation circuit) 15 Internal power circuit 16. Delay control circuit 17 Driver control circuit 18 Signal Generation Unit 19 counters 20 constant current source 21 Comparator 22 Threshold voltage generation circuit 23 Driver control circuit 24 Current detection circuit 25. Threshold voltage generation circuit 26 Comparator 27 Bypass Circuit (Second Bypass Circuit) 28 Driver control circuit 29 Driver control circuit 30 Regulator 31 Drive Circuit 100 Light-Emitting Systems C1 Capacitor R1 Sense Resistor T1~T7 terminals Tb Battery terminal Tb Te Enable Terminal Tn terminal n1 node n2 node OG OR Gate D1~D4 Light-emitting elements SW1~SW5 Switching elements SWn Switch G1~G5 drive signals GND grounding end I1 Drive current I2 constant current E, E1, E2 Enable signals (first control signals) RE Power Enable BE Battery Enable CE Charge Enable (Second Control Signal) SE Switch Driven Enable S1~S4 Control signals V1~V6 Voltage Vb Battery voltage Vcp Charge Voltage (Operating Voltage) Vh Upper voltage Vl Lower voltage Vo Boost Voltage Vreg Internal power supply voltage Vse current detection signal Vth1 threshold voltage Vth2 threshold voltage d1 Delay time d2 delay time

Claims

1. A bypass circuit configured to individually switch each of the multiple light-emitting elements connected in series between an inflow state where drive current is supplied, and a retraction state where the drive current is not supplied. A bypass control circuit is configured to control the bypass circuit such that when an externally input enable signal is at a first logic level, the drive current is individually supplied to or retracted from each of the light-emitting elements, and when the enable signal is at a second logic level, the drive current is retracted from all of the light-emitting elements until it falls below a predetermined current value. A light-emitting drive device equipped with the following features.

2. The light-emitting drive device according to claim 1, wherein the bypass circuit includes a plurality of switch elements connected in parallel to each of the light-emitting elements, such that the drive current is diverted from the light-emitting element to itself when the circuit is ON, so that the drive current does not flow to the light-emitting element when the circuit is OFF, and the drive current flows to the light-emitting element when the circuit is OFF.

3. The bypass control circuit is A delay control circuit is configured to generate a first control signal and a second control signal with a predetermined delay time added to the first control signal, based on at least one of the logic level of the enable signal and the drive current. An operating voltage generation circuit configured to generate a first operating voltage based on the second control signal, A drive control circuit is configured to receive the first operating voltage and drive the bypass circuit to switch the inflow state or the retraction state for each of the light-emitting elements based on the first control signal, A light-emitting drive device according to claim 1, including the following:

4. The aforementioned delay control circuit is Upon receiving the enable signal of the first logic level, the first control signal is set to the third logic level. Upon receiving the enable signal of the second logic level, the first control signal is set to the fourth logic level. After the delay time has elapsed from the timing at which the enable signal switches from the first logic level to the second logic level, the second control signal is switched from the third logic level to the fourth logic level. The aforementioned operating voltage generation circuit is The first operating voltage is generated upon receiving the input of the first control signal of the third logic level. Upon receiving the input of the first control signal of the fourth logic level, the generation of the first operating voltage is stopped. The light-emitting drive device according to claim 3.

5. The bypass control circuit is A current detection circuit configured to detect the aforementioned drive current and generate a detection signal according to the detection result, An operating voltage generation circuit configured to generate a first operating voltage based on the detection signal, at least when the drive current is detected, A drive control circuit is configured to receive the first operating voltage and drive the bypass circuit to switch the inflow state or the retracted state for each of the light-emitting elements based on the enable signal, A light-emitting drive device according to claim 1, including the following:

6. The bypass circuit is A second bypass circuit is connected in parallel to the light-emitting element array, which consists of each of the aforementioned light-emitting elements, and is configured to either supply the drive current to the light-emitting element array, or to divert the drive current from the light-emitting element array so that the drive current does not flow to any of the aforementioned light-emitting elements. A first bypass circuit is connected in parallel to each of the light-emitting elements and configured to individually switch each of the light-emitting elements between the current inflow state and the retracted state while the drive current is flowing into the light-emitting element array. Includes, The bypass control circuit is An operating voltage generation circuit configured to generate a first operating voltage in response to the enable signal, A first bypass drive control circuit is configured to drive the first bypass circuit to switch between the inflow state or the retracted state for each of the light-emitting elements upon receiving the first operating voltage, A second bypass drive control circuit, configured to operate based on a second operating voltage supplied from an external source and to drive the second bypass circuit in response to the enable signal, A light-emitting drive device according to claim 1, including the following:

7. The light-emitting drive device according to claim 1, comprising the bypass circuit and the bypass control circuit integrated.

8. The plurality of light-emitting elements, The light-emitting drive device according to claim 1, A light-emitting device equipped with the following features.

9. The light-emitting device according to claim 8, comprising a plurality of the aforementioned light-emitting drive devices.

10. The light-emitting device according to claim 9, A power supply device configured to generate the drive current based on the enable signal and supply it to the light-emitting device, A light-emitting system equipped with the following features.

11. The aforementioned power supply device is A boost circuit configured to generate a boosted voltage by increasing the power supply voltage supplied from an external source based on the enable signal, A drive current generation circuit configured to generate the drive current by converting the boosted voltage into a current-voltage, The light-emitting system according to claim 10, including the following:

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