MEMORY DEVICE AND SYSTEM, AND DECODING CIRCUIT - Patent application

Abstract

Examples of the present application provide a memory device and system, and a decoding circuit, wherein the memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array, the memory cell array including at least one block, the block having a plurality of rows of word lines, a plurality of columns of bit lines, and memory cells coupled between the word lines and the bit lines, the peripheral circuitry including a column decoding circuit coupled to the plurality of columns of bit lines and configured to receive column address signals, perform multi-stage decoding on the column address signals, and output column select signals indicating enabling of respective bit lines of the block.

Description

[Technical Field]

[0001] Examples of this application relate to the field of semiconductors, and in particular to memory devices and systems, and decoding circuits. [Background technology]

[0002] 2. Description of the Related Art Memory devices and systems thereof are storage devices for storing information in modern information technology. As the demands on storage devices continue to increase, there is still room for improvement in memory devices and systems thereof. Summary of the Invention

[0003] Examples of the present application provide memory devices and systems, as well as decoding circuits.

[0004] In a first aspect, an example of the present application provides a memory device including a memory cell array and peripheral circuitry coupled to the memory cell array; The memory cell array includes at least one block, the block having a plurality of rows of word lines, a plurality of columns of bit lines, and memory cells coupled between the word lines and the bit lines; The peripheral circuitry includes a column decoding circuit coupled to the bit lines of a plurality of columns and configured to receive column address signals, perform multi-stage decoding on the column address signals, and output column select signals indicating enablement of respective bit lines of the block.

[0005] In some examples, the column decode circuitry includes: a first stage column decode circuitry having a first input interface and a first output interface, wherein the first input interface receives at least a column address signal, and the first output interface outputs a preliminary column decode signal, and the number of transmission lines corresponding to the column address signal is less than the number of transmission lines corresponding to the preliminary column decode signal; a second stage column decoding circuit having a second input interface and a second output interface, the second input interface being coupled to the first stage column decoding circuit and receiving a spare column decoding signal; the second output interface being coupled to a plurality of bit lines of the block and outputting a column decoding signal indicating enabling one of the plurality of bit lines of the block, wherein the number of transmission lines corresponding to the spare column decoding signal is less than the number of transmission lines corresponding to the column decoding signal;

[0006] In some examples, the memory cell array includes a plurality of banks, each including several blocks of rows and several blocks of columns; each of the banks corresponds to a plurality of first stage column decoding circuits and a plurality of second stage column decoding circuits, each of the first stage column decoding circuits corresponds to a column of blocks, and each of the second stage column decoding circuits corresponds to one of the columns of blocks; The second input interface of each of the second stage column decode circuits is coupled to the first stage column decode circuit, and the second output interface is coupled to a plurality of bit lines of one of the blocks, and the column decode signal indicates enabling of the respective bit lines of the selected block.

[0007] In some examples, the column address signal includes multiple bits of data, and the first stage column decoding circuitry includes: a first decoding circuit configured to perform a decoding process on data of a plurality of consecutive lower order bits of the column address signal to obtain a first decoded signal; and a second decoding circuit configured to perform a decoding process on the remaining plurality of consecutive most significant bits of data of the column address signal to obtain a second decoded signal, wherein the first decoded signal and the second decoded signal are configured to together form a preliminary column decoded signal.

[0008] In some examples, the first stage column decoding circuit further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than the clock periods corresponding to the first decoded signal and the second decoded signal; The second input interface of the second stage column decoding circuit further receives a synchronization control signal, and the second stage column decoding circuit is configured to output the column decoding signal in response to the enable state of the synchronization control signal and the normal output of the first decoding signal and the second decoding signal.

[0009] In some examples, the second stage column decoding circuit is configured to receive a synchronization control signal and a semiconductor device enable signal, and when both the synchronization control signal and the block enable signal are enabled, output a column decoding signal to enable bit lines of a selected block corresponding to enabled data bits of the spare column decoding signal, wherein an enabled block enable signal indicates that the block is selected.

[0010] In some examples, the first stage column decoding circuit further comprises a drive circuit including a plurality of drivers; Each driver is connected to one of a plurality of transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and is configured to perform power amplification processing on the decoded signal of the respective transmission line.

[0011] In some examples, the block includes a first region and a second region, and the number of bit lines arranged in the first region and the second region is the same; the first stage column decoding circuit further includes a third decoding circuit, a first region selection circuit, and a second region selection circuit; the third decoding circuit is configured to perform a decoding process on the remaining plurality of consecutive upper bits of the column address signal to obtain a third decoded signal, the third decoded signal being identical to the second decoded signal; the first region selection circuit is connected to the second decoding circuit and configured to output the second decoded signal when the first region enable signal is enabled; The second region selection circuit is connected to the third decoding circuit and configured to output a third decoding signal when the second region enable signal is enabled, and the first region enable signal / second region enable signal being enabled indicates that the first region / second region of the block is selected.

[0012] In some examples, the first stage column decoding circuitry further includes a buffer; The buffer is connected to the first decoding circuit and is configured to perform timing adjustment on the first decoded signal to synchronize with output signals of both the first region selection circuit and the second region selection circuit.

[0013] In some examples, the column address signal is 6 bits of binary data, the spare column decode signal corresponds to 24 transmission lines, the first region of the block includes 64 bit lines, and the second region of the block includes 64 bit lines.

[0014] In some examples, the memory comprises a plurality of address transmission lines and a plurality of data transmission lines; a first stage column decoding circuit corresponding to one column of blocks is connected to a second stage column decoding circuit corresponding to each block of the one column of blocks via a plurality of address transmission lines; Each block in a row is connected to a data transmission line, The plurality of address transmission lines and the plurality of data transmission lines are arranged on the same metal layer.

[0015] In some examples, the memory cell array is disposed in a first semiconductor structure and the peripheral circuitry is disposed in a second semiconductor structure, the first semiconductor structure and the second semiconductor structure being stacked and electrically connected by bonding; each of the first stage column decoding circuits is disposed on the side of each column of the block; Each of the second stage column decoding circuits is disposed at an orthogonal projection position of one respective block in the plane in which the second semiconductor structure is located, together with a sense amplifier and a word line driver corresponding to each block.

[0016] In some examples, the memory device comprises dynamic random access memory.

[0017] In a second aspect, the present application provides a memory device as described in the above solution, A memory system is provided that includes a memory controller coupled to the memory device and controlling the memory device.

[0018] In a second aspect, an example of the present application is a decoding circuit, comprising: a first stage decoding circuit including a first input interface and a first output interface, wherein the first input interface receives at least a signal to be decoded, and the first output interface outputs a pre-decoded signal, and the number of transmission lines corresponding to the signal to be decoded is less than the number of transmission lines corresponding to the pre-decoded signal; and a second stage decoding circuit having a second input interface and a second output interface, the second input interface being coupled to the first stage decoding circuit and receiving a preliminary column decoding signal, the second output interface being coupled to a plurality of structures selected in the semiconductor device and outputting a decoding signal indicating enabling one structure selected in the semiconductor device, wherein the number of transmission lines corresponding to the preliminary decoding signal is less than the number of transmission lines corresponding to the decoding signal.

[0019] In some examples, there are a plurality of second stage decoding circuits, each corresponding to a semiconductor device; The second input interface of each of the second stage decoding circuits is coupled to the first stage decoding circuit, and the second output interface is coupled to a plurality of structures to be decoded of one semiconductor device, and the decoding signal indicates that each structure of the selected semiconductor device is valid to be decoded.

[0020] In some examples, the signal to be decoded includes multiple bits of data, and the first stage decoding circuitry includes: a first decoding circuit configured to perform a decoding process on a plurality of consecutive least significant bit data of the signal to be decoded to obtain a first decoded signal; a second decoding circuit configured to perform a decoding process on the remaining plurality of consecutive most significant bits of data of the signal to be decoded to obtain a second decoded signal, wherein the first decoded signal and the second decoded signal are configured to together form a preliminary decoded signal;

[0021] In some examples, the first stage decoding circuit further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than the clock periods corresponding to the first decoded signal and the second decoded signal; The second input interface of the second stage decoding circuit further receives a synchronization control signal, and the second stage decoding circuit is configured to output a decoded signal in response to the enable state of the synchronization control signal and the normal output of the first decoded signal and the second decoded signal.

[0022] In some examples, the second stage decoding circuit is configured to receive a synchronization control signal and a semiconductor device enable signal, and when both the synchronization control signal and the semiconductor device enable signal are enabled, output a decoding signal to enable a structure to be selected in a selected semiconductor device corresponding to an enabled data bit of the preliminary decoding signal, wherein enabling the semiconductor device enable signal indicates that the semiconductor device is selected.

[0023] In some examples, the first stage decoding circuit further comprises a drive circuit including a plurality of drivers; Each driver is connected to one of a plurality of transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and is configured to perform power amplification processing on the decoded signal of the respective transmission line.

[0024] In some examples, the first stage decoding circuit further comprises a third decoding circuit, a first region selection circuit, and a second region selection circuit; the third decoding circuit is configured to perform a decoding process on the remaining plurality of consecutive most significant bits of data of the signal to be decoded to obtain a third decoded signal, the third decoded signal being identical to the second decoded signal; the first region selection circuit is connected to the second decoding circuit and configured to output the second decoded signal when the first region enable signal is enabled; The second region selection circuit is connected to the third decoding circuit and configured to output a third decoding signal when the second region enable signal is enabled, and the first region enable signal / second region enable signal being enabled indicates that the first region / second region of the semiconductor element is selected.

[0025] In some examples, the first stage decoding circuitry further includes a buffer; The buffer is connected to the first decoding circuit and is configured to perform timing adjustment on the first decoded signal to synchronize with output signals of both the first region selection circuit and the second region selection circuit.

[0026] In some examples, the first region selection circuit / second region selection circuit comprises a first NAND gate and a second NAND gate; an input terminal of the first NAND gate is connected to an output of the second decoding circuit / third decoding circuit, and another input terminal is configured to receive a partition enable signal, and an enabled partition enable signal indicates that the semiconductor device is assisting in partition selection; The input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the other input terminal is configured to receive the first region enable signal / second region enable signal, and the output terminal is connected to the first output interface.

[0027] In some examples, the decoded signal comprises a column address signal, the transmission line comprises an address transmission line, the semiconductor element comprises a block, the plurality of selected structures comprises a plurality of bit lines, and the decoded signal indicates a select one of the plurality of bit lines. [Brief explanation of the drawings]

[0028] In the drawings, unless otherwise specified, like reference numerals used throughout the drawings indicate the same or similar components or elements. The drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments in accordance with the present application and should not be considered limitations on the scope of the present application. [Figure 1] 1 is a block diagram of a typical electronic device configuration according to an example of the present application; [Figure 2A] FIG. 1 is a block diagram of a typical solid-state drive (SSD) or universal flash storage (UFS) configuration for an example of the present application. [Figure 2B] FIG. 2 is a block diagram of a typical internal memory configuration for an example of the present application. [Figure 3] 1 is a schematic diagram of a typical dynamic random access memory configuration according to an example of the present application; [Figure 4] 1 is a schematic diagram of the connections between word lines, bit lines, and memory cells of a typical dynamic random access memory according to an example of the present application. [Figure 5A]1 is a schematic distribution diagram of a memory cell array and peripheral circuits in a typical memory device of an example of the present application. [Figure 5B] FIG. 2 is a top view of the distribution of memory cell arrays and peripheral circuits in a typical memory device of an example of the present application. [Figure 5C] FIG. 10 is a top view of the distribution of block and column decoding circuits in a typical bank of an example of the present application. [Figure 6A] FIG. 10 is a top view of the distribution of block and column decoding circuits in a typical bank of another example of the present application. [Figure 6B] FIG. 10 is a top view of the distribution of block and column decoding circuits in a typical bank according to yet another example of the present application. [Figure 7A] FIG. 2 is a schematic diagram of the distribution of memory cell arrays and peripheral circuits in a typical memory device according to another example of the present application. [Figure 7B] FIG. 10 is a top view of the distribution of memory cell arrays and peripheral circuits in a typical memory device according to another example of the present application. [Figure 8A] FIG. 2 is a block diagram of a typical column decoding circuit configuration according to an example of the present application. [Figure 8B] FIG. 2 is a schematic diagram of an exemplary implementation of a typical column decoding circuit in accordance with an example of the present application. [Figure 8C] FIG. 2 is a schematic diagram of voltage timings of some signals in a typical column decoding circuit of an example of the present application. [Figure 9A] FIG. 10 is a block diagram of a typical column decoding circuit configuration according to another example of the present application. [Figure 9B] FIG. 10 is a schematic diagram of an exemplary implementation of an exemplary column decoding circuit according to another example of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0029] Exemplary embodiments of the present application will be described in detail below with reference to the drawings. Although the drawings illustrate exemplary embodiments of the present application, it should be understood that the present application may be implemented in any form without being limited to the exemplary embodiments described herein. Rather, these implementations are provided to provide a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0030] In the following description, many typical details are presented to provide a more thorough understanding of the present application. However, it is clear to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described to avoid confusion with the present application. That is, not all features of the actual example are described herein, and well-known functions and structures are not described in detail.

[0031] In the drawings, the sizes and relative sizes of layers, regions, and elements may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

[0032] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" another element or layer, it is understood that it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or that one or more intervening elements or layers may be present. In contrast, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. While terms such as first, second, and third may be used to describe various elements, components, regions, layers, and / or portions, it is understood that these elements, components, regions, layers, and / or portions are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion described below could be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not imply that the first element, component, region, layer or section is necessarily present in the present application.

[0033] Spatially relative terms such as "beneath," "below," "lower," "under," "over," and "upper" may be used herein for ease of description to describe the relationship of one element or feature to other elements or features, as shown in the figures. It should be understood that spatially relative terms are intended to encompass various orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures were turned upside down, an element or feature described as "below," "under," or "beneath" other elements would be oriented so as to be "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an up and down orientation. The device may be otherwise oriented (rotated 90 degrees or to other orientations), and the spatially descriptive terms used herein would be interpreted accordingly.

[0034] The terms used herein are intended to illustrate examples only and are not intended to limit the present application. As used herein, the singular forms "a," "one," and "the" are also intended to include the plural unless the context clearly dictates otherwise. It should also be understood that the terms "consist of" and / or "comprise," as used herein, determine the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items. The transmission line units "stick," "strip," and "piece" have the same meaning.

[0035] In order to more fully understand the features and technical contents of the examples of the present application, the embodiments of the examples of the present application will be described in detail below in conjunction with the drawings, and the accompanying drawings are not used to limit the examples of the present application, but are used for reference and illustration only.

[0036] FIG. 1 illustrates a block diagram of a typical electronic device configuration according to an example of the present application. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a pointing device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As shown in FIG. 1 , the electronic device 1 may include a host HOST and a memory system 30, which includes a memory controller 10 and one or more memory devices 20. The host HOST may be a processor (e.g., a central processing unit (CPU)) or a graphics processing unit (GPU) of the electronic device. The host HOST may be configured to transmit and receive data to and from the memory device 20. The memory controller 10 is coupled to the memory device 20 and the host HOST and configured to control the memory device 20. The memory controller 10 may manage data stored in the memory device 20 and communicate with the host HOST.

[0037] Memory controller 10 may be configured to control operations of memory device 20, such as read, erase, write, and refresh operations. In some implementations, memory controller 10 is further configured to process error correction codes (ECC) on data read from and written to memory device 20. Memory controller 10 may further perform any other suitable functions, such as formatting memory device 20.

[0038] In some examples, memory controller 10 and one or more memory devices 20 may all be integrated into various types of electronic devices. For example, memory controller 10 may be integrated into the northbridge of a computer motherboard or directly into a computer CPU, and multiple memory devices 20 may be integrated into a memory bar. That is, memory system 30 may be implemented and packaged into different types of final electronic products.

[0039] The memory controller 10 can transmit and receive data to and from a host HOST and can transmit a command CMD and an address ADDR to the memory device 20. The memory controller 10 can include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 can receive a command CMD and an address ADDR from the host HOST. The command generator 110 can generate an access command, a row hammer refresh command, and the like by decoding the command CMD received from the host HOST, and can provide the access command and the row hammer refresh command to the memory device 20 via the device interface 130. The access command can be a signal instructing the memory device 20 to access a row of the memory cell array 220 corresponding to the address ADDR and write or read data therefrom. The row hammer refresh command can be a signal instructing the memory device 20 to perform an additional refresh operation on a word line adjacent to a word line that is frequently accessed within a short period of time. In other words, an additional refresh operation can be performed on a word line adjacent to a word line that is accessed multiple times within a short period of time.

[0040] The address generator 120 of the memory controller 10 may generate a row address and a column address to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. Furthermore, the memory device 20 may generate the address of the bank to be accessed when the memory cell array 220 includes multiple banks.

[0041] Furthermore, memory controller 10 may control memory operations, such as writing and reading, by providing various signals to memory device 20 via device interface 130. For example, memory controller 10 may provide a write command to memory device 20. The write command is used to instruct memory device 20 to perform a write operation to store data in memory device 20.

[0042] In some examples, the memory device 20 includes a memory cell array 220 and a peripheral circuit 210. The memory cell array 220 includes multiple banks, each bank includes multiple blocks, and each block includes multiple rows of memory cells and multiple columns of memory cells. Each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line. The peripheral circuit 210 can write or read data to or from the memory cell array 220 based on a command CMD and an address ADDR received from the memory controller 10, and can provide control signals CTRL to a row decoding circuit and a column decoding circuit for refreshing memory cells included in the memory cell array 220. That is, the peripheral circuit 210 can perform all operations for processing data in the memory cell array 220. The peripheral circuit 210 can include control circuits corresponding to each block, such as a sense amplifier (SA) and a word line driver (WLD), control circuits corresponding to each bank, such as a row decoding circuit and a column decoding circuit, and control circuits corresponding to all banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, and a mode register.

[0043] The memory device 20 may be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), and a resistive RAM (RRAM), etc. In the following description, only DRAM is taken as an example.

[0044] 2A is a block diagram of a typical SSD / UFS configuration in the present application, where the SSD / UFS can be understood as one of the memory systems listed above in FIG. 1, and in this example, DRAM can be used as a buffer memory.

[0045] As shown in FIG. 2A , the SSD / UFS 30′ may include an SSD / UFS controller 10′, a buffer memory 20′, and a nonvolatile memory 40. The SSD / UFS controller 10′ may provide a physical connection between the host HOST and the SSD / UFS 30′. That is, the SSD / UFS controller 10′ may provide an interface between the host HOST and the SSD / UFS 30′ in accordance with the host's bus format. The SSD controller 10′ may decode commands provided by the host HOST. The SSD / UFS controller 10′ may access the nonvolatile memory 40 based on the decoding result. The buffer memory 20′ may temporarily store write data provided by the host HOST or data read from the nonvolatile memory 40. When the host HOST issues a read request, if data present in the nonvolatile memory 40 has been cached, the buffer memory 20′ may directly provide the cached data to the host HOST, thereby assisting the cache function. The data transfer rate via the host's bus format (e.g., SATA or SAS) is much faster than the data transfer rate of the SSD / UFS 30's memory channel. That is, if the host's interface speed is significantly faster, providing a large-capacity buffer memory 20' can minimize performance degradation due to the speed difference. Furthermore, the buffer memory 20' can store an address mapping table for the nonvolatile memory 40. The buffer memory 20' can include, but is not limited to, DRAM. The nonvolatile memory 40 can be disposed as a storage medium for the SSD / UFS 30'. The nonvolatile memory 40 can include, but is not limited to, NAND memory.

[0046] 2B is a block diagram of a typical internal memory configuration for an example of the present application, where the internal memory can be understood as one of the memory systems described above in FIG. 1, and in this example, DRAM can be used as the storage medium.

[0047] As shown in FIG. 2B , the internal memory 30″ can be easily attached or installed or detached to the electronic device 1 via the illustrated interface. The internal memory 30″ can include a plurality of volatile memories 20″ (e.g., DRAMs) and an internal memory controller 10″. The memory module memory 30″ can be used to write data, store data, retrieve (or read) data, and / or erase data under the control of a computer processor. In some examples, the memory controller 10″ of the controller can communicate with the DRAM using at least one communication protocol or technology standard commonly associated with, for example, dual in-line internal memory (DIMM), registered DIMM (RDIMM), load reduced DIMM (LRDIMM), and unregistered DIMM (UDIMM), etc.

[0048] It should be noted that the buffer memory 20′ in FIG. 2A and the volatile memory 20″ in FIG. 2B are each application scenarios of the memory device 20 in FIG. 1, and may also be applicable to other application scenarios, which are not limited here.

[0049] 3 is a schematic diagram of the configuration of a typical dynamic random access memory according to an example of the present application, and FIG. 4 is a schematic diagram of the connection relationship between bit lines, word lines, and memory cells of a typical dynamic random access memory according to an example of the present application.

[0050] FIG. 3 shows the circuitry of a DRAM memory cell on the right side. A DRAM includes at least one DRAM die, each of which includes a memory cell array. The memory cell array includes a plurality of memory cells 201 arranged in an array, each of which includes one transistor T and one capacitor C. The main functional principle of a memory cell is to represent a binary bit as 1 or 0 using a certain amount of charge stored in a capacitor. The memory cells are arranged in an array, which can be considered as a typical mesh structure, the details of which can be seen in FIG. 4. The memory cell array is addressed using rows and columns. By specifying the intersection of the rows and columns (specifying the row address and column address of the DRAM), a memory controller can independently access each memory cell of the DRAM die and perform read, write, or refresh operations on the data stored in the memory cell.

[0051] Figure 3 shows a portion of the DRAM memory cell array and peripheral circuitry on the left. Note that the row decoder circuit selects a word line to select a row of memory cells to be accessed in response to an address input to the row decoder circuit. The row decoder circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoder circuit selects one or more bit lines to input user output data to the portion of the row of memory cells corresponding to the selected word line.

[0052] 5A is a diagram of the distribution of memory cell arrays and peripheral circuits in a typical memory device of the present application, FIG. 5B is a top view of the distribution of memory cell arrays and peripheral circuits in a typical memory device of the present application, and FIG. 5C is a top view of the distribution of block and column decoding circuits in a typical bank of the present application.

[0053] As shown in FIG. 5A , the memory cell array 220 and the peripheral circuitry 210 are arranged side by side. In the example, the memory cell array includes M banks, each of which includes N blocks, with control circuitry corresponding to each block located on at least one side of the block and control circuitry corresponding to each bank located on at least one side of the bank. Each of K banks of the M banks constitutes a column of banks, and M banks constitute a column of M / K banks, with peripheral circuitry corresponding to all banks located between two intermediate columns of banks. Note that M, N, and K are all positive integers, and M is an integer multiple of K.

[0054] In the example shown in FIG. 5B , the memory cell array 220 includes 16 banks (Bank0 to Bank15), each of which includes a plurality of blocks. The SAs and WLDs corresponding to each block are arranged on opposite sides of the block, and the column and row decoding circuits corresponding to each bank are arranged on two sides of the bank. Each of the four banks forms a column of banks, and the 16 banks form a column of four banks. Control circuits corresponding to all the banks are arranged between the two middle columns of banks. Note that the number of banks and the circuit locations in FIG. 5B are used for illustrative purposes only and are not intended to limit the number of banks and the circuit locations in the memory of the present application.

[0055] As shown in FIG. 5C , each bank includes multiple row blocks and multiple column blocks, and each column of the blocks corresponds to one column decoding circuit (corresponding to YDEC in FIG. 5C ), which is configured to receive a column address signal, perform direct decoding or one-stage decoding on the column address signal, and output a column select signal indicating that each bit line of the selected block is enabled. The column decoding circuit is disposed on the side of each column of the blocks and is connected to each block of each column via a column address transmission line. For example, if one column includes multiple blocks each of which is selected together and includes 64 bit lines, the column decoding circuit must be coupled to the 64 bit lines of each block of each column via 64 column address transmission lines. If a column includes multiple blocks each selected by a sub-block (e.g., left and right blocks), and each sub-block includes 64 bit lines, the column decoding circuit needs to be coupled to the 64 bit lines of the left and right blocks of each block in each column via 128 column address transmission lines (Y128:0> in FIG. 5C indicates the case of 128 column address lines). Here, the column address transmission lines are also referred to as long column address transmission lines because they span the entire column of blocks in a long-span domain.

[0056] On the other hand, as shown in FIG. 5C , each block in a column must be similarly connected to data via a data transmission line. In this case, each block in a column is connected to data via a data transmission line pair DL<31:0> / DL_n<31:0>, i.e., 64 data transmission lines. It should be understood that in the current case of increasingly higher storage density requirements, the area of ​​a memory cell array is relatively small, and the area of ​​each column of blocks is also very small. When a large number of address transmission lines and data transmission lines are required to be connected to each column of blocks, as shown in FIG. 5C , where 128 column address transmission lines and 64 data transmission lines must be connected to each column of blocks, it is very difficult to arrange the column address transmission lines and data transmission lines in the same metal layer (or wiring layer) in view of the need to arrange a structure to prevent crosstalk between the transmission lines. For example, the column address transmission lines are arranged in the fourth metal layer, while the data transmission lines are arranged in the fifth metal layer (FIG. 5C uses solid and dashed lines to indicate that the column address transmission lines and the data transmission lines are not in the same metal layer). If the column address transmission lines and data transmission lines are not located on the same metal layer, delay mismatch and large deviations between the column address signals and data signals may occur under process voltage temperature (PVT). In some cases, trim bits such as compensation circuits may be added for improvement, but mismatch between the circuit and wiring delays still exists.

[0057] Based on this, in various examples of the present application, the column decoding circuit is improved from one-stage decoding to multi-stage decoding in order to reduce the total number of column address transmission lines, and area saving is achieved by rationally arranging the positions of the decoders of various stages.

[0058] An example of the present application provides a memory device including a memory cell array and peripheral circuits coupled to the memory cell array, The memory cell array includes at least one block, the block having a plurality of rows of word lines, a plurality of columns of bit lines, and memory cells coupled between the word lines and the bit lines; The peripheral circuitry includes a column decoding circuit coupled to the bit lines of a plurality of columns and configured to receive column address signals, perform multi-stage decoding on the column address signals, and output column select signals indicating enablement of respective bit lines of the block.

[0059] Here, the memory device can be understood with reference to the memory device shown in FIG. 1, and in some examples, the memory device 20 is a dynamic random access memory. All of the following descriptions will be made with reference to the memory device 20 being a DRAM. A typical compositional structure of a DRAM can be understood with reference to the compositional structure of the DRAM shown in FIG.

[0060] In some implementations, a column decoding circuit (which may also be referred to as a column decoder) is coupled to the bit lines of the memory cell array via sense amplifiers (which may also be referred to as sense amplifier circuits). The column decoding circuit may include multiple stages of decoding circuitry that jointly decode column address signals, i.e., accomplish the task of commanding the enablement of each bit line of a block. Here, multiple stages may include two, three, or more stages. In some examples, the column decoding circuit includes two stages of decoding circuitry.

[0061] It will be appreciated that the two-stage decoding circuitry can serve to reduce the number of column address transmission lines without adding excessive circuitry that incurs the burden of excessive area increase.

[0062] In some examples, the column decode circuitry includes: a first stage column decode circuitry having a first input interface and a first output interface, wherein the first input interface receives at least a column address signal, and the first output interface outputs a preliminary column decode signal, and the number of transmission lines corresponding to the column address signal is less than the number of transmission lines corresponding to the preliminary column decode signal; a second stage column decoding circuit having a second input interface and a second output interface, the second input interface being coupled to the first stage column decoding circuit and receiving a spare column decoding signal; the second output interface being coupled to a plurality of bit lines of the block and outputting a column decoding signal indicating enabling one of the plurality of bit lines of the block, wherein the number of transmission lines corresponding to the spare column decoding signal is less than the number of transmission lines corresponding to the column decoding signal;

[0063] Here, the first-stage column decoding circuit and the second-stage column decoding circuit are cascaded in series, a first output interface of the first-stage column decoding circuit is coupled to a second input interface of the second-stage column decoding circuit, and a second output interface of the second-stage column decoding circuit is coupled to a plurality of bit lines of the block. Each column of blocks in each bank of the memory device corresponds to one column decoding circuit, and each column decoding circuit includes one first-stage decoding circuit and one or more second-stage column decoding circuits. In some examples, the number of second-stage column decoding circuits included in each column decoding circuit is the same as the number of blocks in one column of the bank. In an example, the number of blocks in one column of the bank is 64, and the number of second-stage column decoding circuits included in each column decoding circuit is also 64, and the second-stage column decoding circuits correspond one-to-one to the blocks in one column of the block.

[0064] In some examples, the memory cell array includes a plurality of banks, each including several blocks of rows and several blocks of columns; each of the banks corresponds to a plurality of first stage column decoding circuits and a plurality of second stage column decoding circuits, each of the first stage column decoding circuits corresponds to a column of blocks, and each of the second stage column decoding circuits corresponds to one of the columns of blocks; The second input interface of each of the second stage column decode circuits is coupled to the first stage column decode circuit, and the second output interface is coupled to a plurality of bit lines of one of the blocks, and the column decode signal indicates enabling of the respective bit lines of the selected block.

[0065] Here, the first output interface of the first-stage column decoding circuit must be coupled to the second input interfaces of all second-stage column decoding circuits, and the second-stage column decoding circuits are arranged corresponding to the blocks arranged adjacent to the second-stage column decoding circuit. Thus, the first address transmission line between the first output interface of the first-stage column decoding circuit and the second input interfaces of all second-stage column decoding circuits spans the entire column of blocks, and the long span region has a length similar to that of the long column address transmission line.

[0066] Note that a certain number of first address transmission lines are required to represent each bit line entering a block. If the number of bit lines in each block is M and the address signal on each address transmission line can be a high logic level "1" or a low logic level "0," then 2N=M indicates that M bit lines can be represented by at least N address transmission lines, where M and N are both positive integers. For example, if each block is selected as a whole and includes 64 bit lines, the number of first address transmission lines is 16. If each block is selected by a sub-block (e.g., a left block or a right block) and each sub-block includes 64 bit lines, the number of first address transmission lines is 24. In this example, compared with the above-mentioned case of 64 or 128 long column address transmission lines, the number of lines is significantly reduced in the case of 16 or 24 first address transmission lines, which is advantageous for reducing area, and therefore, the column address transmission lines and data transmission lines corresponding to one column of blocks are all laid out on the same metal layer.

[0067] Here, since the second output interface of the second-stage column decoding circuit needs to be coupled to all bit lines of one block, the number of second address transmission lines between the second output interface of each second-stage column decoding circuit and each bit line of the block is related to the number of bit lines of each block. For example, if each block is selected as a whole and includes 64 bit lines, the number of second address transmission lines is 64. If each block is selected by sub-blocks (e.g., left and right blocks) and each sub-block includes 64 bit lines, the number of second address transmission lines is 128.

[0068] It should be noted that since the second stage column decoding circuit is arranged corresponding to the block arranged next to the second stage column decoding circuit, the second address transmission line does not extend to a long length, and the second address transmission line here does not belong to the same concept as the long address transmission line described above.

[0069] In some examples, each first stage column decoding circuit may be arranged on a side of a respective column of the block, and the first stage column decoding circuit may be arranged on a side of each column of the block along the extension direction of the columns of the block.

[0070] The column decoders in the second stage must be located near the corresponding blocks. The location of the column decoders in the second stage can be arranged in various ways, two examples of which are shown below.

[0071] In some examples, as shown in FIG. 6A, the first-stage column decoder circuit (corresponding to YDEC_1st in FIG. 6A) for each column of blocks is located on the side of each column of blocks. The second-stage column decoder circuit (corresponding to YDEC_2nd in FIG. 6A) is located alongside each block, on the side where the sense amplifier (SA) of the block is located for ease of wiring. For example, considering that SAs can be located on two sides of a block as shown in FIG. 5B, if a second-stage column decoder circuit is located (this case is not shown in FIG. 6A), it is also possible to design each second-stage column decoder circuit to be split into two to match the SAs.

[0072] When the second stage column decoding circuit is collocated with each block, the overall structure of the corresponding memory device can refer to the above structure shown in FIGS. 5A and 5B.

[0073] In some other examples, as shown in FIG. 6B, the first-stage column decoder circuit (corresponding to YDEC_1st in FIG. 6B) for each column of blocks is disposed beside each column of blocks. The second-stage column decoder circuit (corresponding to YDEC_2nd in FIG. 6B) and each block are disposed stacked. In examples, the second-stage column decoder circuit may be disposed above each block, or the blocks may be disposed above each second-stage column decoder circuit.

[0074] It should be noted that Figures 6A and 6B are merely illustrative of the relative orientation of the second stage column decoding circuitry with respect to each block, and are not intended to limit the typical placement of the second stage column decoding circuitry.

[0075] In some examples, the memory comprises a plurality of address transmission lines and a plurality of data transmission lines; a first stage column decoding circuit corresponding to one column of blocks is connected to a second stage column decoding circuit corresponding to each block of the one column of blocks via a plurality of address transmission lines; Each block in a row of blocks is connected to a data transmission line; The plurality of address transmission lines and the plurality of data transmission lines are arranged on the same metal layer.

[0076] As described above, the first address transmission lines between the first output interface of each first-stage column decoding circuit and the second input interfaces of all second-stage column decoding circuits are significantly reduced compared to the long column address transmission lines described above. As shown in FIG. 6A or 6B, the first address transmission lines between the first output interface of each first-stage column decoding circuit and the second input interfaces of all second-stage column decoding circuits are reduced from 128 lines as shown in FIG. 5C to 24 lines AY<23:0>, and can be arranged on the same metal layer as the 64 data transmission lines DL<31:0> / DL_n<31:0>. In this example, the first address transmission lines and data transmission lines are all arranged on the fifth metal layer. AY<23:0> and DL<31:0> / DL_n<31:0> in FIGS. 6A and 6B are shown using solid lines to indicate that they are located on the same metal layer. It will be appreciated that when the address transmission lines and data transmission lines are laid out in the same metal layer, the problem of inter-block asynchronism between the column address signals and the data signals can be improved, and the addition of compensation circuitry reduces the effects of PVT.

[0077] When the second stage column decoding circuit and each block are stacked, the layout of the overall structure of the memory device needs to be adjusted accordingly.

[0078] In some examples, the memory cell array is disposed in a first semiconductor structure and the peripheral circuitry is disposed in a second semiconductor structure, the first semiconductor structure and the second semiconductor structure being stacked and electrically connected by bonding; each of the first stage column decoding circuits is disposed on the side of each column of the block; Each of the second stage column decoding circuits is disposed at an orthogonal projection position of one respective block in the plane in which the second semiconductor structure is located, together with a sense amplifier and a word line driver corresponding to each block.

[0079] 7A and 7B are schematic diagrams of the distribution of a memory cell array and peripheral circuits in a typical memory according to another example of the present application, respectively, and a top view of the distribution of a memory cell array and peripheral circuits in a typical memory according to another example of the present application.

[0080] 7A, a first semiconductor structure 100 is disposed above a second semiconductor structure 200. The first semiconductor structure 100 includes a memory cell array 220, and the second semiconductor structure 200 includes a peripheral circuit 210.

[0081] 7A, the first semiconductor structure in FIG. 7B is located above the second semiconductor structure. Note that in FIG. 7B, the structures corresponding to the solid lines are located in the first semiconductor structure, and the structures corresponding to the dashed lines are located in the second semiconductor structure. For ease of understanding, a perspective view of the structure in the second semiconductor structure is presented. That is, in the enlarged view corresponding to each block in FIG. 7B, the solid line represents the enlarged portion of the block, and the dashed line represents the structure in the second semiconductor structure located directly below the block.

[0082] 7B, the memory cell array 220 includes 16 banks Bank0 to Bank15, each including a plurality of blocks. A sense amplifier (SA), a second-stage column decoding circuit YDEC_2nd, and a coupling circuit (Conjunction) between the sense amplifier (SA) and the second-stage column decoding circuit YDEC_2nd are arranged directly below each block. A word line driver is arranged directly below the gap between two adjacent blocks along the direction in which the columns of blocks extend. In some examples, the word line driver may include an odd word line driver Odd WLD and an even word line driver Even WLD arranged on two sides of the blocks, respectively.

[0083] It should be noted that the locations of the sense amplifier (SA), second stage column decoding circuit YDEC_2nd, coupling circuit Conjunction, odd word line driver Odd WLD, and even word line driver Even WLD in FIG. 7B are intended for illustration purposes only and do not limit the locations of each circuit in the memory of the present application.

[0084] In some examples, means for bonding the memory cell array 220 to the peripheral circuitry 210 include, but are not limited to, hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, and the like.

[0085] When the memory device adopts a stacked arrangement by bonding, the added circuits in the example of this application, such as the second stage address decoding circuit, SA and WLD related circuits, etc., can be arranged under the memory cell array. Due to the stacked arrangement, the added circuits do not cause extra area loss.

[0086] Exemplary circuit implementations of each of the two-stage decoding circuits are described in detail below.

[0087] In some examples, the column address signal includes multiple bits of data, and the first stage column decode circuit 231 a first decoding circuit 2311 configured to perform a decoding process on data of a plurality of consecutive lower order bits of the column address signal to obtain a first decoded signal; a second decoding circuit 2312 configured to perform a decoding process on the remaining plurality of consecutive most significant bits of data of the column address signal to obtain a second decoded signal, wherein the first decoded signal and the second decoded signal are configured to together form a preliminary column decoded signal.

[0088] Here, the column address signal is a signal representing column address information. In some examples, the column address signal is multi-bit binary data, and the number of bits of the column address signal is related to the number of bit lines included in the block. If the number of bit lines in each block is M and the column address signal is N-bit binary data, then 2N=M. In an example, if each block includes 64 bit lines, the column address signal may be 6-bit binary data.

[0089] Considering that the number of bit lines is generally large and one decoding circuit may be insufficient, here, the first decoding circuit 2311 and the second decoding circuit 2312 are respectively used to decode different parts of consecutive data bits of the column address signal, and then the two decoded signals are combined to form the output of the first-stage decoding circuit 231. In the example, the first decoding circuit 2311 and the second decoding circuit 2312 are responsible for decoding the same number of data bits. In the example, as shown in FIG. 8A , the column address signal AY_9_4_<9:4> is 6-bit binary data, and the first decoding circuit 2311 decodes the three least significant bits AY_9_4_<6:4> in the column address signal, and the second decoding circuit 2312 decodes the three most significant bits AY_9_4_<9:7> in the column address signal.

[0090] In some examples, the first decoding circuit 2311 and the second decoding circuit 2312 may each include one or more decoders, such as a 2-to-4 decoder and a 3-to-8 decoder. In some examples, the first decoding circuit 2311 and the second decoding circuit 2312 may each include one or more 3-to-8 decoders. Decoding of different numbers of data bits may be achieved using different combinations of 3 to 8 decoders.

[0091] In an example, as shown in FIG. 8B, the column address signal is 6-bit binary data, and the first decoding circuit 2311 and the second decoding circuit 2312 each include one 3-to-8 decoder, and the two 3-to-8 decoders can realize 6-to-16 bit decoding.

[0092] In an example, the column address signal is 12-bit binary data, and the first decoding circuit 2311 and the second decoding circuit 2312 each include two 3-to-8 decoders, each of which can achieve exactly 6-to-16-bit decoding, and the four 3-to-8 decoders can achieve 12-to-32-bit decoding.

[0093] In an example, the column address signal is 4-bit binary data, and the first decoding circuit 2311 and the second decoding circuit 2312 each include one 3-to-8 decoder, and the two 3-to-8 decoders each decode two of the 4 bits into 4 bits (discarding some bits), thereby realizing 4-to-8 bit decoding. Furthermore, the first decoding circuit 2311 and the second decoding circuit 2312 each may include one 2-to-4 decoder, and the two 2-to-4 decoders may realize 4-to-8 bit decoding.

[0094] In some examples, the first stage column decoding circuit 231 further includes a synchronization control signal generation circuit 2314 configured to generate a synchronization control signal corresponding to a clock period shorter than the clock period corresponding to the first decoded signal and the second decoded signal.

[0095] The second input interface of the second stage column decoding circuit 232 further receives a synchronization control signal, and the second stage column decoding circuit 232 is configured to output a column decoding signal in response to the enable state of the synchronization control signal and the normal output of the first decoding signal and the second decoding signal.

[0096] 8A, the synchronization control signal generation circuit 2314 is configured to implement timing constraints to synchronize the timing of the first-stage column decoding circuit 231 and the second-stage decoding circuit. The clock period corresponding to the synchronization control signal is shorter than the clock periods corresponding to the first and second decoded signals. In some examples, the clock period corresponding to the synchronization control signal is half the clock period corresponding to the first and second decoded signals.

[0097] In an example, as shown in FIG. 8B, the synchronization control signal generation circuit 2314 may be a rectangular signal generation circuit, and the waveform of the synchronization control signal may refer to Ypulse shown in FIG. 8C. FIG. 8B also shows a schematic diagram of the synchronization control signal generation circuit 2341. As shown in FIG. 8B, the synchronization control signal generation circuit 2341 may include an inverter, a time delay circuit, and an exclusive OR gate. An input terminal of the inverter receives a clock signal AY_CLK, where the clock period of the clock signal may be the same as the clock periods corresponding to the first decoded signal and the second decoded signal. An output terminal of the inverter is connected to an input terminal of the time delay circuit, and the time delay circuit is configured to perform a time delay process on the clock signal, for example, a half-period time delay. A first input terminal of the exclusive OR gate is connected to an output terminal of the time delay circuit, a second input terminal of the exclusive OR gate receives the clock signal, and an output terminal of the exclusive OR gate outputs the synchronization control signal.

[0098] 8C, the synchronization control signal Ypulse narrows the cycles of the spare column decode signals AY_6_4_BUF<7:0> and AY_9_7_BUF<7:0>, so that the cycles of the column decode signals AY_Y<63:0> and the synchronization control signal Ypulse are always narrowed to half the cycles of the spare column decode signals AY_6_4_BUF<7:0> and AY_9_7_BUF<7:0>. In other words, the synchronization control signal acts as a timing constraint.

[0099] It should be noted that FIG. 8B only provides an example of a synchronization control signal generating circuit, and is not intended to limit the typical circuit of the synchronization control signal generating circuit in the examples of the present application.

[0100] It will be appreciated that the column decoding circuitry includes a first stage column decoding circuitry and a second stage column decoding circuitry. The second stage column decoding circuitry adds synchronous control operations. Consistency of address and data timing for columns of a block is advantageous for timing adjustment during high speed operation.

[0101] In some examples, the second stage column decode circuit 232 is configured to receive a synchronization control signal and a semiconductor device enable signal, and when both the synchronization control signal and the block enable signal are enabled, output a column decode signal to enable bit lines of a selected block corresponding to enabled data bits of the spare column decode signal, where an enabled block enable signal indicates that the block is selected.

[0102] Here, the second-stage column decoding circuit 232 is configured to receive the first decoded signal, the second decoded signal, the synchronization control signal, and the block enable signal, and perform an operation on the first decoded signal, the second decoded signal, the synchronization control signal, and the block enable signal to obtain a decoded signal. For a bit line of a block, when the signal for each bit of the first decoded signal and the signal for each bit of the second decoded signal corresponding to the bit line are both in an enable state, and the synchronization control signal and the block enable signal are also both in an enable state, the decoded signal corresponding to the bit line is in an enable state, and at this time, the decoded signals corresponding to other bit lines are in a disable state. Note that the enable state and the disable state of the decoded signal referred to here can be understood as the signal being at a specific logic level indicating the activation or deactivation of a specific bit line.

[0103] A typical configuration circuit of the second-stage column decoder circuit 232 can be seen in FIG. 8B. Note that only one second-stage column decoder circuit 232 is shown in FIG. 8B. As described above, each block corresponds to one second-stage column decoder circuit 232, and each second-stage column decoder circuit is connected to the output of the first-stage column decoder circuit. Different blocks correspond to different block enable signals. For example, the block enable signal corresponding to a selected block is at a high logic level "1," and the block enable signal corresponding to an unselected block is at a ground logic level "0."

[0104] As shown in FIG. 8B, the second-stage column decode circuit 232 includes circuits, each represented by a dashed box, equal in number to the number of bit lines. The circuits represented by the dashed boxes include one NOR gate and two NAND gates. One of the NAND gates receives a block enable signal at its first input, and receives a data bit of the first decoded signal in the spare column decoded signal corresponding to the bit line at its second input. The other NAND gate receives a synchronous control operation signal lypulse corresponding to the synchronous control signal (where the synchronous control operation signal lypulse is obtained by ANDing the synchronous control signal Ypulse and the block enable signal Blk_en), and receives a data bit of the second decoded signal in the spare column decoded signal corresponding to the bit line at its first input. The outputs of the two NAND gates are connected to the inputs of a NOR gate, which outputs a column decoded signal. Each data bit of the column decoded signal corresponds to one bit line.

[0105] Note that in the present example, each second-stage column decoding circuit 232 includes the same number of circuits as the number of bit lines, as shown in the dashed boxes. The inputs of the circuits shown in the dashed boxes each receive a combined signal of any data bit included in the first decoded signal and any data bit included in the second decoded signal. In the example, the first decoded signal includes 8 bits of data, and the second decoded signal includes 8 bits of data. There are then 64 circuits, as shown in the dashed boxes, and the input of each circuit shown in the dashed boxes is a combination of any data bit of the 8 bits of data included in the first decoded signal and any data bit of the 8 bits of data included in the second decoded signal.

[0106] It should be noted that FIG. 8B only provides an example of the second stage column decoding circuit 232 and is not intended to limit the typical circuit of the second stage column decoding circuit 232 in the examples of the present application.

[0107] In some examples, the first stage column decoding circuit 231 further comprises a drive circuit 2315 including a plurality of drivers; Each driver is connected to one of a plurality of transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and is configured to perform power amplification processing on the decoded signal of the respective transmission line.

[0108] 8A, a driver may be arranged on each transmission line. Each transmission line may include the above-mentioned first address transmission line between the first output interface of each first-stage column decoding circuit 231 and the second input interfaces of all second-stage column decoding circuits, and may further include a transmission line for a synchronization control signal generated by a synchronization control signal generation circuit 2314.

[0109] In some examples, as shown in 8B, the driver may comprise an even number of inverters cascaded in series, with typical numbers being two, four, or more. The driver may be configured to increase the transmit power, thereby avoiding or ameliorating problems of transmission failure due to excessively long transmission lines and excessive power dissipation.

[0110] It will be understood that, since the drivers 2315 are arranged corresponding to each transmission line, in the example of the present application, the number of drivers can be reduced while the number of address transmission lines is reduced, thereby reducing the overall circuit area.

[0111] The blocks of the column decoder circuit 230 described above are jointly selected and deselected. In some examples, the blocks may also be partition-selected or may be referred to as being selected by the block. An exemplary implementation of the column decoder circuit 230 in a partition-selected block is described below.

[0112] In some examples, the block includes a first region and a second region, and the number of bit lines arranged in the first region and the second region is the same; The first stage column decoding circuit 231 further includes a third decoding circuit 2313, a first region selection circuit 2316, and a second region selection circuit 2317; the third decoding circuit 2313 is configured to perform a decoding process on the remaining plurality of consecutive upper bit data of the column address signal to obtain a third decoded signal, the third decoded signal being identical to the second decoded signal; the first region selection circuit 2316 is connected to the second decoding circuit 2312 and configured to output the second decoded signal when the first region enable signal is enabled; The second region selection circuit 2317 is connected to the third decoding circuit 2313 and configured to output a third decoding signal when the second region enable signal is enabled, and the first region enable signal / second region enable signal being enabled indicates that the first region / second region of the block is selected.

[0113] In some examples, the first stage column decoding circuit 231 further includes a buffer 2318; The buffer 2318 is connected to the first decoding circuit and is configured to perform timing adjustment on the first decoded signal to synchronize with the output signals of both the first region selection circuit and the second region selection circuit.

[0114] 9A , the first-stage column decoding circuit 231 may further include a third decoding circuit 2313, a first region selection circuit 2316, and a second region selection circuit 2317, and the third decoding circuit 2313 may be a duplicate of the second decoding circuit 2312, i.e., may decode the three most significant bits AY_9_4_<9:7> of the column address signal. A typical implementation circuit of the third decoding circuit 2313 may also be understood with reference to the second decoding circuit 2312 described above.

[0115] The first region selection circuit 2316 and the second region selection circuit 2317 are each configured to select a block region. The first region selection circuit 2316 is connected to the second decoding circuit 2312 and is configured to continue transmitting the second decoded signal backward through the first region selection circuit 2316 when the first region enable signal is in an enabled state. When the first region enable signal is in a disabled state, the second decoded signal transmits a fixed logic level, e.g., a signal with all data bits "0". The second region selection circuit 2317 is connected to the third decoding circuit 2313 and is configured to continue transmitting the third decoded signal backward through the second region selection circuit 2317 when the second region enable signal is in an enabled state. When the second region enable signal is in a disabled state, the third decoded signal transmits a fixed logic level, e.g., a signal with all data bits "0".

[0116] 9B , the first region selection circuit 2316 and the second region selection circuit 2317 may each include two NAND gates cascaded in series. One of the NAND gates has a first input connected to the output of the second decoding circuit 2312 or the output of the third decoding circuit 2313, and a second input receiving a partition enable signal, which indicates that the block supports partition-based selection. The other NAND gate has a first input connected to the output of the previous NAND gate, and a second input receiving a partition enable signal, which indicates that the block supports partition-based selection. The other NAND gate outputs the second decoded signal or the third decoded signal.

[0117] After adding the first region selection circuit 2316 and the second region selection circuit 2317, in order to align the timing of the branch circuit in which the first decoding circuit 2311 is located with the timing of the second decoding circuit 2312 and the third decoding circuit 2313, it is necessary to add a buffer 2318 as shown in Figure 9A to the branch circuit in which the first decoding circuit 2311 is located.

[0118] 9B, the buffer 2318 may include a NAND gate and an inverter cascaded in series, where the first input terminal of the NAND gate is connected to the output terminal of the first decoding circuit 2311, the second input terminal receives a fixed logic level signal, such as VDD2H, i.e., a high logic level "1", and the output terminal is connected to the input terminal of the inverter, which normally outputs the first decoded signal.

[0119] It should be noted that the outputs of the buffer 2318, the first area selection circuit 2316 and the second area selection circuit 2317 may be connected to the inputs of the driver circuit for power amplification.

[0120] Note that respective adjustments to the second-stage column decoding circuit 232 are also required. As shown in Figure 9B, for each partition of the block, a duplication of the circuit in the dashed box in Figure 8B above is required, with different partitions corresponding to different input signals. In the example, the inputs of the circuit shown in the dashed box corresponding to the first region each receive a combined signal of any data bits included in the first decoded signal and any data bits included in the second decoded signal. The inputs of the circuit shown in the dashed box corresponding to the second region each receive a combined signal of any data bits included in the first decoded signal and any data bits included in the third decoded signal.

[0121] In this example, the first region of the block includes 64 bit lines, and the second region of the block includes 64 bit lines. The column address signal is 6-bit binary data. The spare column decoded signal corresponds to 24 transmission lines, the first decoded signal includes 8-bit data, the second decoded signal includes 8-bit data, and the third decoded signal also includes 8-bit data. Next, there are 128 circuits, as shown in the dashed boxes. The inputs of the circuits shown in each dashed box corresponding to the first region are combinations of any data bit in the 8-bit data included in the first decoded signal and any data bit in the 8-bit data included in the second decoded signal. The inputs of the circuits shown in each dashed box corresponding to the second region are combinations of any data bit in the 8-bit data included in the first decoded signal and any data bit in the 8-bit data included in the third decoded signal.

[0122] In the example of the present application, the column decoder circuit includes a first-stage column decoder circuit and a second-stage column decoder circuit. A column address decoder circuit (second-stage column decoder circuit) is added after the column to transmit the final decoder circuit (second-stage column decoder circuit) of the column address to each block, and a synchronization control is added to the second-stage column decoder circuit. In this way, the decoder circuit provided in the embodiment of the present application can significantly reduce the number of long column address lines and can transmit both column addresses and data using the same metal layer. This synchronizes the column addresses and data in the block, reducing the effect of PVT and facilitating timing adjustment during high-speed operation.

[0123] Furthermore, if the memory device adopts a stacking arrangement in a bonding manner, the added circuits in the example of this application, such as the second stage address decoding circuit, SA and WLD related circuits, etc., can be arranged under the memory cell array. The stacking arrangement of the memory cells and peripheral circuits allows for closer alignment of column addresses and data, and the added circuits do not result in extra area loss.

[0124] An example of the present application is a memory system, one or more of the above memory devices provided in the examples of the present application; A memory system is provided that includes a memory controller coupled to the memory device and controlling the memory device.

[0125] Here, the internal configuration of the memory system can be understood with reference to Figure 1 above, and some application scenarios of the memory system can be understood with reference to Figures 2A and 2B above, which will not be repeated here.

[0126] An example of the present application is a decoding circuit, a first stage decoding circuit including a first input interface and a first output interface, wherein the first input interface receives at least a signal to be decoded, and the first output interface outputs a pre-decoded signal, and the number of transmission lines corresponding to the signal to be decoded is less than the number of transmission lines corresponding to the pre-decoded signal; and a second stage decoding circuit having a second input interface and a second output interface, the second input interface being coupled to the first stage decoding circuit and receiving a preliminary column decoding signal, the second output interface being coupled to a plurality of structures selected in the semiconductor device and outputting a decoding signal indicating enabling one structure selected in the semiconductor device, the number of transmission lines corresponding to the preliminary decoding signal being less than the number of transmission lines corresponding to the decoding signal.

[0127] Here, the decoding circuit is not limited to the column decoding circuit of the memory, but may be a decoding circuit of another electronic device, and is configured to perform a decoding process to indicate the activation of one structure selected in a semiconductor element included in the electronic device.

[0128] It should be noted that the first stage decoding circuitry here can be understood with reference to the first stage column decoding circuitry described above, the second stage decoding circuitry here can be understood with reference to the second stage column decoding circuitry described above, the decoded signals can be understood with reference to the column address signals described above, the semiconductor elements can be understood with reference to the blocks described above, and the selected structure can be understood with reference to the bit lines described above.

[0129] In some examples, there are a plurality of second stage decoding circuits, each corresponding to a semiconductor device; The second input interface of each of the second stage decoding circuits is coupled to the first stage decoding circuit, and the second output interface is coupled to a plurality of structures to be decoded of one semiconductor device, and the decoding signal indicates that each structure of the selected semiconductor device is enabled to be decoded.

[0130] In some examples, the signal to be decoded includes multiple bits of data, and the first stage decoding circuitry includes: a first decoding circuit configured to perform a decoding process on a plurality of consecutive least significant bit data of the signal to be decoded to obtain a first decoded signal; a second decoding circuit configured to perform a decoding process on the remaining plurality of consecutive most significant bits of data of the signal to be decoded to obtain a second decoded signal, wherein the first decoded signal and the second decoded signal are configured to together form a preliminary decoded signal;

[0131] In some examples, the first stage decoding circuit further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than the clock periods corresponding to the first decoded signal and the second decoded signal; The second input interface of the second stage decoding circuit further receives a synchronization control signal, and the second stage decoding circuit is configured to output a decoded signal in response to the enable state of the synchronization control signal and the normal output of the first decoded signal and the second decoded signal.

[0132] In some examples, the second stage decoding circuit is configured to receive a synchronization control signal and a semiconductor device enable signal, and when both the synchronization control signal and the semiconductor device enable signal are enabled, output a decoding signal to enable a structure to be selected in a selected semiconductor device corresponding to an enabled data bit of the preliminary decoding signal, wherein enabling the semiconductor device enable signal indicates that the semiconductor device is selected.

[0133] In some examples, the first stage decoding circuit further comprises a drive circuit including a plurality of drivers; Each driver is connected to one of a plurality of transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and is configured to perform power amplification processing on the decoded signal of the respective transmission line.

[0134] In some examples, the first stage decoding circuit further comprises a third decoding circuit, a first region selection circuit, and a second region selection circuit; the third decoding circuit is configured to perform a decoding process on the remaining plurality of consecutive most significant bits of data of the signal to be decoded to obtain a third decoded signal, the third decoded signal being identical to the second decoded signal; the first region selection circuit is connected to the second decoding circuit and configured to output the second decoded signal when the first region enable signal is enabled; The second region selection circuit is connected to the third decoding circuit and configured to output a third decoding signal when the second region enable signal is enabled, and the first region enable signal / second region enable signal being enabled indicates that the first region / second region of the semiconductor element is selected.

[0135] In some examples, the first stage decoding circuitry further includes a buffer; The buffer is connected to the first decoding circuit and is configured to perform timing adjustment on the first decoded signal to synchronize with output signals of both the first region selection circuit and the second region selection circuit.

[0136] In some examples, the first region selection circuit / second region selection circuit comprises a first NAND gate and a second NAND gate; an input terminal of the first NAND gate is connected to an output of the second decoding circuit / third decoding circuit, and another input terminal is configured to receive a partition enable signal, and an enabled partition enable signal indicates that the semiconductor device is assisting in selecting a partition unit; The input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the other input terminal is configured to receive the first region enable signal / second region enable signal, and the output terminal is connected to the first output interface.

[0137] A typical configuration circuit of the first stage decoding circuit here can be understood with reference to the typical configuration circuit of the first stage column decoding circuit described above, and a typical configuration circuit of the second stage decoding circuit in this specification can be understood with reference to the typical configuration circuit of the second stage column decoding circuit described above.

[0138] In some examples, the decoded signal comprises a column address signal, the transmission line comprises an address transmission line, the semiconductor element comprises a block, the plurality of selected structures comprises a plurality of bit lines, and the decoded signal indicates a select one of the plurality of bit lines.

[0139] It should be understood that references throughout this specification to "one example" or "an example" mean that exemplary features, structures, or characteristics associated with the example are included in at least one example of the present application. Thus, "in one example" or "in an example" appearing throughout this specification do not necessarily refer to the same example. Furthermore, these exemplary features, structures, or characteristics may be incorporated into one or more examples in any suitable manner. It should be understood that in the various examples of the present application, the sequence numbers of the above processes do not indicate an order of execution, and the order of execution of the various processes is determined by their functionality and inherent logic and does not constitute limitations on the implementation process of the examples of the present application. The above sequence numbers of the examples of the present application are for illustrative purposes and do not represent advantages or disadvantages of the examples.

[0140] The above description is only a preferred example of the present application and is not intended to limit the patent scope of the present application. Any equivalent structural transformation made under the inventive concept of the present application using the contents of the specification and drawings of the present application, or direct / indirect application to other related technical fields, falls within the patent protection scope of the present application.

Claims

1. 1. A memory device comprising: A memory cell array, a memory cell array including at least one block having a plurality of rows of word lines, a plurality of columns of bit lines, and memory cells coupled between the word lines and the bit lines; a peripheral circuit coupled to the memory cell array, a column decode circuit coupled to the bit lines of the plurality of columns, receiving a column address signal; performing multi-stage decoding of said column address signals; and peripheral circuitry, comprising a column decoding circuit, configured to output a column select signal indicating enabling of each bit line of the block.

2. The column decoding circuit a first stage column decode circuit having a first input interface and a first output interface, wherein the first input interface receives at least the column address signals and the first output interface outputs spare column decode signals, and wherein the number of transmission lines corresponding to the column address signals is less than the number of transmission lines corresponding to the spare column decode signals; 2. The memory device of claim 1, further comprising: a second stage column decode circuit having a second input interface and a second output interface, the second input interface coupled to the first stage column decode circuit to receive the spare column decode signal, the second output interface coupled to a plurality of bit lines of the block to output a column decode signal indicating enabling one of the plurality of bit lines of the block, the number of transmission lines corresponding to the spare column decode signal being less than the number of transmission lines corresponding to the column decode signal.

3. the memory cell array comprises a plurality of banks, each of which comprises several row blocks and several column blocks; each of the banks corresponds to a plurality of first stage column decoding circuits and a plurality of second stage column decoding circuits, each of the first stage column decoding circuits corresponds to a column of blocks, and each of the second stage column decoding circuits corresponds to one of the columns of blocks; 3. The memory device of claim 2, wherein the second input interface of each of the second stage column decode circuits is coupled to the first stage column decode circuit and the second output interface is coupled to a plurality of bit lines of one of the blocks, and the column decode signal indicates enabling of the respective bit lines of a selected block.

4. The column address signal includes multiple bits of data, and the first stage column decoding circuit a first decoding circuit configured to perform a decoding operation on a plurality of consecutive least significant bits of data of the column address signal to obtain a first decoded signal; and a second decoding circuit configured to perform a decoding operation on a remaining plurality of consecutive most significant bits of data of the column address signal to obtain a second decoded signal, the first decoded signal and the second decoded signal being configured to together form the spare column decoded signal.

5. the first stage column decoding circuit further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than a clock period corresponding to the first decoded signal and the second decoded signal; 5. The memory device of claim 4, wherein the second input interface of the second stage column decoding circuit further receives the synchronization control signal, and the second stage column decoding circuit is configured to output the column decoding signal in response to an enable state of the synchronization control signal and normal output of the first decoding signal and the second decoding signal.

6. The second stage column decoding circuit comprises: receiving the synchronization control signal and a semiconductor device enable signal; 6. The memory device of claim 5, configured to output a column decode signal to enable bit lines of a selected block corresponding to enabled data bits of the spare column decode signal when both the synchronization control signal and the block enable signal are enabled, wherein the block enable signal being enabled indicates that the block is selected.

7. the first stage column decoding circuit further comprises a drive circuit including a plurality of drivers; 5. The memory device of claim 4, wherein each driver is connected to one of a plurality of transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and configured to perform power amplification processing on the decoded signal on the respective transmission line.

8. the block includes a first region and a second region, the number of bit lines arranged in the first region and the number of bit lines arranged in the second region are the same; The first stage column decoding circuit comprises: a third decoding circuit configured to perform a decoding process on the remaining plurality of consecutive most significant bits of data of the column address signal to obtain a third decoded signal, wherein the third decoded signal and the second decoded signal are the same; a first region selection circuit coupled to the second decoding circuit and configured to output the second decoded signal when a first region enable signal is enabled; 5. The memory device of claim 4, further comprising: a second region select circuit connected to the third decoding circuit and configured to output the third decoding signal when a second region enable signal is enabled, wherein the first region enable signal or the second region enable signal being enabled indicates that the first region or the second region of the block is selected.

9. The first stage column decoding circuit comprises:

9. The memory device of claim 8, further comprising a buffer connected to the first decoding circuit and configured to perform timing adjustments on the first decoded signal to synchronize it with output signals of both the first region selection circuit and the second region selection circuit.

10. 9. The memory device of claim 8, wherein the column address signal is 6-bit binary data, the spare column decode signal corresponds to 24 transmission lines, the first region of the block includes 64 bit lines, and the second region of the block includes 64 bit lines.

11. the memory includes a plurality of address transmission lines and a plurality of data transmission lines; the first stage column decoding circuit corresponding to one column of blocks is connected to the second stage column decoding circuit corresponding to each block of the one column of blocks via the plurality of address transmission lines; Each block in the row of blocks is connected to the data transmission line; 4. The memory device according to claim 3, wherein the plurality of address transmission lines and the plurality of data transmission lines are arranged in the same metal layer.

12. the memory cell array is disposed in a first semiconductor structure, the peripheral circuit is disposed in a second semiconductor structure, the first semiconductor structure and the second semiconductor structure are stacked and electrically connected by junctions; each of the first stage column decoding circuits is disposed beside each column of the block; 4. The memory device of claim 3, wherein each of the second stage column decoding circuits is arranged at an orthogonal projection position of one respective block in a plane in which the second semiconductor structure is located, together with a sense amplifier and a word line driver corresponding to each block.

13. A memory device according to any preceding claim, comprising a dynamic random access memory.

14. 1. A memory system comprising: One or more memory devices according to any one of claims 1 to 13; a memory controller coupled to the memory device and controlling the memory device.

15. A decoding circuit, comprising: A first stage decoding circuit, a first input interface for receiving at least the signal to be decoded; a first stage decoding circuit including a first output interface for outputting a pre-decoded signal, wherein the number of transmission lines corresponding to the signal to be decoded is less than the number of transmission lines corresponding to the pre-decoded signal; A second stage decoding circuit, a second input interface coupled to the first stage decoding circuitry for receiving the pre-decoded signal; a second output interface coupled to a plurality of selected structures in a semiconductor device and outputting a decoded signal indicating that a structure in the semiconductor device is to be selected, wherein the number of transmission lines corresponding to the preliminary decoded signals is less than the number of transmission lines corresponding to the decoded signals; and a second stage decoded circuit including: a second output interface coupled to a plurality of selected structures in the semiconductor device and outputting a decoded signal indicating that a structure in the semiconductor device is to be selected, wherein the number of transmission lines corresponding to the preliminary decoded signals is less than the number of transmission lines corresponding to the decoded signals.

16. a plurality of second stage decoding circuits are present, each of the second stage decoding circuits corresponding to one semiconductor device; 16. The decoding circuit of claim 15, wherein the second input interface of each of the second stage decoding circuits is coupled to the first stage decoding circuit, the second output interface is coupled to multiple structures to be decoded in a single semiconductor device, and the decode signal indicates that a respective structure is enabled to be decoded in a selected semiconductor device.

17. The signal to be decoded includes multiple bits of data, and the first stage decoding circuit a first decoding circuit configured to perform a decoding process on a plurality of consecutive least significant bits of data of the signal to be decoded to obtain a first decoded signal; and a second decoding circuit configured to perform a decoding process on a remaining plurality of consecutive most significant bits of data of the signal to be decoded to obtain a second decoded signal, the first decoded signal and the second decoded signal being configured to together form the preliminary decoded signal.

18. The first stage decoding circuit comprises: further comprising a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than clock periods corresponding to the first decoded signal and the second decoded signal; 18. The decoding circuit of claim 17, wherein the second input interface of the second stage decoding circuit further receives the synchronization control signal, and the second stage decoding circuit is configured to output the decoded signal in response to an enable state of the synchronization control signal and normal output of the first decoded signal and the second decoded signal.

19. The second stage decoding circuit comprises: receiving the synchronization control signal and a semiconductor device enable signal; 20. The decoding circuit of claim 18, configured to output the decoding signal to enable a structure to be selected in a selected semiconductor device corresponding to an enabled data bit of the pre-decoding signal when both the synchronization control signal and the semiconductor device enable signal are enabled, wherein the enabling of the semiconductor device enable signal indicates that the semiconductor device is selected.

20. the first stage decoding circuit further comprises a drive circuit including a plurality of drivers; 18. The decoding circuit of claim 17, wherein each driver is connected to one of a plurality of transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and configured to perform power amplification processing on the decoded signal of the respective transmission line.

21. The first stage decoding circuit comprises: a third decoding circuit configured to perform a decoding process on data of a remaining plurality of consecutive most significant bits of the signal to be decoded to obtain a third decoded signal, wherein the third decoded signal and the second decoded signal are the same; a first region selection circuit coupled to the second decoding circuit and configured to output the second decoded signal when a first region enable signal is enabled; 18. The decoding circuit of claim 17, further comprising: a second region selection circuit coupled to the third decoding circuit and configured to output the third decoded signal when a second region enable signal is enabled, wherein the first region enable signal or the second region enable signal being enabled indicates that a first region or a second region of the semiconductor device is selected.

22. The first stage decoding circuit comprises:

22. The decoding circuit of claim 21, further comprising a buffer connected to the first decoding circuit and configured to perform timing adjustments on the first decoded signal to synchronize it with output signals of both the first region selection circuit and the second region selection circuit.

23. The first area selection circuit or the second area selection circuit a first NAND gate, an input terminal of the first NAND gate being connected to an output of the second decoding circuit or the third decoding circuit, and the other input terminal being configured to receive a partition enable signal, wherein an enable of the partition enable signal indicates that the semiconductor device supports partition unit selection; a second NAND gate, an input of the second NAND gate connected to the output of the first NAND gate, the other input configured to receive the first region enable signal or the second region enable signal, and an output connected to the first output interface.

24. 16. The decoding circuit of claim 15, wherein the decoded signal comprises a column address signal, the transmission line comprises an address transmission line, the semiconductor device comprises a block, the plurality of structures to be selected comprises a plurality of bit lines, and the decoded signal indicates a select one of the plurality of bit lines.

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