Rotating Data Blocks

Abstract

The execution unit performs a byte-wise rotate operation on an input data block. The input data array receives the input data block. Two first-tier multiplexer arrays receive first-tier data blocks each containing a subset of bytes of the input data block and a first-tier control signal, and rotate the first-tier data block by an amount indicated by the first-tier control signal. The second-tier multiplexer array receives a second control signal and selects corresponding bytes of either the first rotated first-tier data block or the second rotated first-tier data block based on the second control signal. The execution unit includes a control signal generator configured to generate the first-tier control signal and the second-tier control signal based on received computer program instructions. In this way, the results of rotating smaller blocks are used as partial results for rotating larger blocks, avoiding the need for a large multiplexer array with complex wiring.

Description

[Technical Field]

[0001] The present disclosure relates to logic circuits for performing byte-wise rotation of data blocks. [Background technology]

[0002] A processing device may include an execution unit and a memory. The execution unit may execute one or more program threads to perform operations on data loaded from the memory and generate results. The execution results are then stored in the memory. The execution results may be used for subsequent processing by the execution unit or may be output from the processing device. Summary of the Invention

[0003] Data loaded from memory by a processing unit may have one of several predetermined block sizes. Each block size may have a fixed number of bytes (e.g., 4, 8, or 16 bytes). In various contexts, an execution unit may need to rotate data blocks of various block sizes stored in memory by any number of bytes up to the block size. As the name suggests, "rotating" a data block by any number of bytes involves moving bytes from the beginning of the block (i.e., having the highest index) to the end of the block. For example, rotating a 4-byte data block [A, B, C, D] by one block results in [B, C, D, A]. Block rotation may be necessary, for example, in the process of aligning misaligned data.

[0004] Such rotation operations must meet associated timing requirements, which can be problematic in the context of high-performance processing devices (e.g., processors for machine learning applications) that have relatively short clock cycles.

[0005] It is an object of the present disclosure to provide logic circuitry that can perform rotate operations within the timing requirements of such high performance processing devices. It is a further object of the present disclosure to provide a means for performing rotate operations in a manner that reduces area cost and minimizes power consumption.

[0006] According to a first aspect of the present disclosure, there is provided an execution unit configured to execute computer program instructions for performing a byte-wise rotate operation on an input data block, said execution unit comprising: a logic circuit and a control signal generator; The logic circuit comprises: an input data array for receiving an input data block containing N bytes; two first-tier multiplexer arrays; a second layer multiplexer array; and Each first layer multiplexer array is receiving a first-tier data block containing each subset of bytes of the input data block; receiving a layer 1 control signal; configured to rotate the first layer data blocks by an amount indicated by the first layer control signal; the two first-layer multiplexer arrays are configured to output the first rotated first-layer data block and the second rotated first-layer data block, respectively; a second layer multiplexer array configured to receive a second control signal and comprising N multiplexers; each multiplexer configured to select corresponding bytes of either the first rotated first-layer data block or the second rotated first-layer data block based on the second control signal, and output a rotated second-layer data block; The control signal generator is configured to generate the first-layer control signals and the second-layer control signals based on the computer program instructions. Each first-layer data block may include N / 2 bytes, where N may be equal to 8.

[0007] The logic circuit may be expanded by adding additional layers to perform rotations of larger input data blocks. In one example, the input data array is configured to receive an input data block containing M bytes (M>N, preferably M=2N). M may be equal to 16. The logic circuit may include four first-layer multiplexer arrays to output first through fourth rotated first-layer blocks. The logic circuit may include two second-layer multiplexer arrays and a third-layer multiplexer array. A first of the two second-layer multiplexer arrays is configured to receive the first rotated first-layer block and the second rotated first-layer block and output the first rotated second-layer data block, and a second of the two second-layer multiplexer arrays is configured to receive the third rotated first-layer block and the fourth rotated first-layer block and output the second rotated second-layer block. The layer 3 multiplexer array may be configured to receive a layer 3 control signal and may include M multiplexers. The M multiplexers may be configured to select corresponding bytes of either the first rotated second-layer data block or the second rotated second-layer data block based on the third control signal and output a rotated third-layer data block. The control signal generator may be configured to generate the layer 3 control signal. A block herein may include a number of bytes that is a power of two. For example, N and / or M may be a power of two.

[0008] The logic circuit may include an intermediate result array configured to receive the output of the first-tier multiplexer array. The second-tier multiplexer array may receive the first rotated first-tier data block and the second rotated first-tier data block from the intermediate result array. In examples where the logic circuit includes additional layers, additional intermediate result arrays may be disposed between successive layers.

[0009] Each first-tier multiplexer array may comprise multiple S:1 multiplexers, preferably S S:1 multiplexers, where S may be equal to the size of the subset of bytes in the input block. Input j of the ith S:1 multiplexer in the array may be connected to (i+j) mod S bytes of the subset of bytes in the input data array corresponding to each subset of bytes.

[0010] The second-tier control signal may include an N-bit bit mask, with each bit of the bit mask serving as a control signal for each of the N multiplexers of the second-tier multiplexer array. The logic circuit may include circuitry to split the bit mask and provide each bit to a respective multiplexer.

[0011] The control signal generator may be configured to rotate the bit mask such that the output of the rotated second-layer data block is rotated by the same amount. The bit mask may be 0xF0.

[0012] The control signal generator may be configured to rotate the bit mask by selecting a stored rotated bit mask from a lookup table. The control signal generator may include circuitry (e.g., bit shifting circuitry) configured to rotate the bit mask.

[0013] The layer 3 control signal may be an M-bit bit mask, and the layer 3 multiplexer array may be controlled in the same way as the layer 2 control signal. The layer 3 control signal bit mask may be 0xFF00.

[0014] The control signal generator may generate a layer-2 control signal that causes the layer-2 multiplexer array to operate as a pass-through. Thus, the layer-2 multiplexer array can output the first and second rotated layer-1 data blocks. In examples with additional layers, the control signal generator may generate control signals that cause the additional layers to operate as pass-throughs. For example, the control signal generator may generate a layer-3 control signal that causes the layer-3 to operate as a pass-through.

[0015] The logic circuit may include one or more clock gates configured to disable one or more elements of the logic circuit. The logic circuit may include multiple data path lanes (preferably N data path lanes). Each clock gate may be configured to disable one or more data path lanes. Each clock gate may be configured to disable N / 2 or M / 4 data path lanes in appropriate response to an input to one of the first tier multiplexer arrays. The clock gate may be configured to disable one of the first tier multiplexer arrays and the second tier multiplexer array. The control signal generator may be configured to generate clock gate control signals to control one or more clock gates.

[0016] The logic circuit may include a pipeline register disposed between the first layer multiplexer array and the second layer multiplexer array.

[0017] The computer program instructions may be a rotate instruction configured to rotate an input data block. The computer program instructions may include multiple operations, with the rotate operation being one of the multiple operations. The computer program instructions may include a pack instruction configured to copy a sequence of contiguous bytes from a first location in a first data block to a second location in a second data block. The rotate operation may align the bytes of the first data block to the output location. The computer program instructions may be an extract instruction configured to extract a sequence of contiguous bytes from a concatenation of the first data block and the second data block.

[0018] The execution unit may generate the first-tier control signals, the second-tier control signals, and / or the third-tier control signals based on values ​​indicated by the computer program instruction. The values ​​may be indicated in one or more operands of the computer program instruction, the opcode of the computer program instruction, or may be read from one or more registers associated with the computer program instruction. The values ​​may include a rotation amount and / or a block size. The values ​​may include one or more values ​​from which the execution unit can calculate the rotation amount and / or the block size.

[0019] According to a second aspect of the present disclosure, there is provided a processing unit comprising an execution unit as defined in the first aspect. The processing unit may be a tile processor. The processing unit may comprise a local memory. The execution unit may receive input data blocks from the local memory.

[0020] According to a third aspect of the present disclosure, there is provided a processing device comprising the processing unit according to the second aspect. The processing device may comprise a plurality of processing units. At least one of the processing units may comprise an execution unit. The processing units may communicate via a switching fabric that implements time-deterministic switching.

[0021] According to a fourth aspect of the present disclosure, there is provided a method implemented in an execution unit, the method comprising: receiving an input data block containing N bytes; providing first-tier data blocks containing respective subsets of bytes of the input data block to a first first-tier multiplexer array and a second first-tier multiplexer array; providing tier 1 control signals to the first tier 1 multiplexer array and to a second tier 1 multiplexer array; rotating the first-layer data block by an amount indicated by the first-layer control signal to output a first rotated first-layer data block and a second rotated first-layer data block; providing the first rotated first-layer data block and the second rotated first-layer data block to a second-layer multiplexer array comprising N multiplexers; and providing a second control signal to the second-layer multiplexer array to select corresponding bytes of either the first rotated first-layer data block or the second rotated first-layer data block based on the second control signal.

[0022] Further optional features of the method of the fourth aspect are described above in relation to the first, second and third aspects and may be combined in any combination. For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings in which: [Brief explanation of the drawings]

[0023] [Figure 1A] FIG. 1 is a schematic block diagram of a processor in which examples of the present disclosure are implemented. [Figure 1B] FIG. 1 is a schematic diagram of an example of a processor chip on which examples of the present disclosure are implemented. [Figure 2] FIG. 1 is a schematic block diagram of a simple exemplary logic circuit. [Figure 3]FIG. 1 is a schematic block diagram of an exemplary logic circuit of the present disclosure. [Figure 4] 4 is a schematic block diagram illustrating a first processing level of the exemplary logic circuit of FIG. 3 in greater detail. [Figure 5] FIG. 4 is a schematic block diagram illustrating a second processing level of the exemplary logic circuit of FIG. 3 in greater detail. [Figure 6] FIG. 4 is a schematic block diagram illustrating a third processing level of the exemplary logic circuit of FIG. 3 in greater detail. [Figure 7] FIG. 2 is another schematic block diagram of an exemplary logic circuit. [Figure 8] FIG. 2 is another schematic block diagram of an exemplary logic circuit. [Figure 9] 1 is an exemplary code sample illustrating a pack instruction. [Figure 10] 10 is an exemplary code sample showing an extraction instruction.

[0024] In the drawings, corresponding reference characters indicate corresponding components. As will be appreciated by those skilled in the art, elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the various examples. Also, common but well-understood elements useful or necessary in commercially feasible examples are often not shown to facilitate a less obscured view of these various examples. DETAILED DESCRIPTION OF THE INVENTION

[0025] In summary, examples of the present disclosure provide logic circuitry for performing byte-wise rotation of data blocks. The logic circuitry is logically arranged in layers, with each layer configured to perform operations on blocks of successively larger size. The results of a previous layer serve as input to a subsequent layer, and the results of the rotation of a smaller block are used as partial results for computing the rotation of a larger block. In some examples, the logic circuitry is incorporated into a processing unit, e.g., an execution unit thereof, of a processing device, such as a tile processor of a processor having multiple tiles.

[0026] Advantageously, examples of the present disclosure provide a means of rotating relatively large blocks while avoiding large multiplexer arrays with complex wiring. Thus, smaller, faster multiplexers are used, eliminating the need for a large number of long datapath wires. This helps keep timing paths short. Furthermore, examples herein help minimize the area cost of processor functions by using hardware resources that are reused across all sizes of rotate operations, rather than requiring different hardware resources for each different block size.

[0027] Examples are implemented in a processing unit that may take the form of a processor 4, which is described in more detail with reference to FIG. 1A. In some examples, the processor 4 may take the form of a tile 4 of a multi-tile processing device. Examples of such multi-tile processing devices are described in more detail in the inventors' prior U.S. Patent Application No. US2020 / 0319861A1 (incorporated by reference).

[0028] Referring to FIG. 1A, an example processor 4 is shown, including details of the execution units 18 and context registers 26. The illustrated processor 4 includes a weight register file 26W, making it particularly suitable for machine learning applications in which machine learning models are trained by adjusting the weights for those models. However, the example application is not limited to machine learning applications and has broader applicability. Additionally, the illustrated processor 4 is a multi-threaded processor capable of simultaneously executing M threads. The processor 4 can support the execution of M worker threads and one supervisor thread. The worker threads perform arithmetic operations on data to generate results, and the supervisor thread coordinates the worker threads and controls the synchronization, send and receive functions of the processor 4.

[0029] The processor 4 includes a respective instruction buffer 53 for each of the M threads that can be simultaneously executed. The context registers 26 include a respective main register file (MRF) 26M for each of the M worker contexts and the supervisor context. The context registers further include a respective auxiliary register file (ARF) 26A for at least each worker context. The context registers 26 also include a common weight register file (WRF) 26W, accessible for reading from by all currently executing worker threads. The WRF may be associated with the supervisor context in that the only thread that can write to the WRF is the supervisor thread. The context registers 26 may also include a respective group of control status registers 26CSR for each of the supervisor and worker contexts. The execution units 18 include a main execution unit 18M and a secondary execution unit 18A. The main execution unit 18M includes a load-store unit (LSU) 55 and an integer arithmetic logic unit (IALU) 56. The secondary execution unit 18A includes at least a floating point unit (FPU).

[0030] In each of the J interleaved time slots S0...SJ-1, scheduler 24 controls fetch stage 14 to fetch at least one instruction for each thread from instruction memory 11 and input it into one of J instruction buffers 53 corresponding to the current time slot. In the example, each time slot is one execution cycle of the processor, although other schemes are not excluded (e.g., weighted round robin). In each execution cycle of processor 4 (i.e., each cycle of the processor clock that clocks the program counter), fetch stage 14 fetches either a single instruction or a small "instruction bundle" (e.g., a two-instruction bundle or a four-instruction bundle), depending on the implementation. Each instruction is then issued via decode stage 16 to either LSU 55 or IALU 56 of primary execution unit 18M or to FPU of secondary execution unit 18A, depending on whether the instruction (according to its opcode) is a memory access instruction, an integer arithmetic instruction, or a floating-point arithmetic instruction, respectively. The LSU 55 and IALU 56 of the primary execution unit 18M execute their instructions using registers from the MRF 26M. The particular registers in the MRF 26M are specified by the operands of the instruction. The FPU of the secondary execution unit 18A executes operations using registers in the ARF 26A and WRF 26W. The particular registers in the ARF are specified by the operands of the instruction. In an example, the registers in the WRF may be implicit in the instruction type (i.e., may be predetermined for that instruction type). The secondary execution unit 18A may also include circuitry in the form of logical latches internal to the secondary execution unit 18A to hold some internal state 57 for use in executing one or more operations of the floating-point arithmetic instruction types.

[0031] In an example of fetching and executing instructions in bundles, the individual instructions in a given instruction bundle are executed simultaneously in parallel along independent pipelines 18M, 18A (shown in FIG. 1A). In an example of executing two bundles of instructions, the two instructions may be executed simultaneously along each of the secondary and main pipelines. In this case, the main pipeline is arranged to execute instructions of a type that uses the MRF, and the secondary pipeline is used to execute instructions of a type that uses the ARF. Combining instructions into appropriate complementary bundles may be handled by the compiler.

[0032] Each worker thread context has its own instance of a main register file (MRF) 26M and an auxiliary register file (ARF) 26A (i.e., one MRF and one ARF per barrel thread slot). Any functionality described herein with reference to an MRF or ARF should be understood to operate per context. However, there is a single shared weight register file (WRF) shared among threads. Each thread can only access the MRF and ARF in its own context registers 26. However, all currently executing worker threads can access a common WRF. The WRF therefore provides a common set of weights for use by all worker threads. In the example, only the supervisor can write to the WRF, and workers can only read from it.

[0033] The instruction set of the processor 4 includes at least one type of load instruction. When the opcode of a load instruction is executed, the LSU 55 loads data from the data memory 22 into each ARF 26A of the thread in which the load instruction was executed. The destination location within the ARF is specified by an operand of the load instruction. Another operand of the load instruction specifies an address register within each MRF 26M. This address register holds a pointer to the address in data memory 22 where the data is to be loaded. The instruction set of the processor 4 also includes at least one type of store instruction. When the opcode of a store instruction is executed, the LSU 55 stores data from each ARF of the thread in which the store instruction was executed into the data memory 22. The source location within the ARF is specified by an operand of the store instruction. Another operand of the store instruction specifies an address register within the MRF. This address register holds a pointer to the address in data memory 22 where the data is to be stored. Generally, the instruction set may include separate load and store instruction types, and / or at least one load-store instruction type that combines a load operation and a store operation into a single instruction.

[0034] In response to the opcode of the associated type of arithmetic instruction, the arithmetic unit (e.g., FPU) in secondary execution unit 18A performs the arithmetic operation specified by the opcode, including operating on the values ​​of specified source registers in the ARF of each of the threads and, optionally, on the values ​​of source registers in the WRF, and outputs the result of the arithmetic operation to a destination register in the ARF of each of the threads explicitly specified by the destination operand of the arithmetic instruction.

[0035] The processor 4 may also include an exchange interface 51 for exchanging data between the memory 11 and one or more other resources (e.g., other instances of the processor and / or external devices (e.g., a network interface or network-attached storage (NAS) device)). As previously mentioned, in the example, the processor 4 may form one of an array of interconnected processor tiles. Each tile may execute a portion of a broader program. Thus, individual processors 4 (tiles) constitute part of a broader processor or processing system 6. The tiles 4 may be connected to each other via an interconnection subsystem and to the interconnection subsystem via their respective exchange interfaces 51. The tiles 4 may be implemented on the same chip (i.e., die), on different chips, or in combination (i.e., an array may be formed from multiple chips, each comprising multiple tiles 4). Thus, the interconnection system and exchange interface 51 may include internal (on-chip) interconnection mechanisms and / or external (inter-chip) exchange mechanisms accordingly.

[0036] FIG. 2 shows a simple logic circuit 100 for performing a data block rotation operation that is not within the scope of the claims.

[0037] Logic circuit 100 is configured to rotate input data blocks that are either 4, 8, or 16 bytes in size. The logic circuit has a 16-byte input data array 101. If a 4-byte block needs to be rotated, a subset 101a of input data array 101 receives the 4-byte block. If an 8-byte block needs to be rotated, subset 101a is used for 4 of the 8 bytes and another subset 101b is used for the remaining 4 bytes.

[0038] The logic circuitry includes a 16:1 multiplexer array 102, an 8:1 multiplexer array 103, and a 4:1 multiplexer array 104. Each of the multiplexer arrays receives a respective block of size S and a control signal (not shown) indicating a rotation amount, which represents the number of bytes by which the block should be rotated.

[0039] Each of arrays 102-104 includes a bank of S multiplexers, with input j of each multiplexer i connected to byte (i+j) mod S of the input data array. Thus, the 0th input of the 0th multiplexer in 4:1 array 104 is connected to byte (0+0)%4=0 of the input data array, the 1st input is connected to byte (0+1)%4=1, and so on. The 0th input of the 1st multiplexer in 4:1 array 104 is connected to byte (1+0)%4=1, the 1st input of the 1st multiplexer is connected to byte (1+1)%4=2, and so on for all inputs of all multiplexers in the array. Both "%" and "mod" in this context are abbreviations for the modulo operator. Thus, by arranging the inputs in this manner, control signals can be applied to each multiplexer in the array to select the associated byte from the input data array to produce the desired rotation.

[0040] In some contexts herein (e.g., when describing arrays of data or multiplexer arrays), a zero-based indexing convention is followed. Thus, the zeroth element of an array may be the first element appearing in said array, the first element may be the second element appearing, and so on. In other contexts, terms such as first, second, third, etc. may also be used simply as labels to distinguish between similar elements. The intended meaning will be clear from the relevant context.

[0041] A result multiplexer array 105 is then used to select a result from the associated S:1 array 102-104 to provide result 106 based on another suitable control signal, referred to as a select signal. For example, the least significant log2(S) bits of the rotation amount may be used as the select signal.

[0042] While this approach is simple, using large multiplexers for large block sizes may be too slow to meet the timing constraints of the relatively short processor clock cycle. In addition, many long wires are required to connect the multiplexer inputs, resulting in wiring congestion. It will be appreciated that the difficulty of meeting the timing constraints may be affected to some extent by the amount of logic and available timing margin before and / or after circuit 100, as well as other constraints related to the placement of circuit 100 within the processing unit and wiring congestion within the processing unit. Furthermore, the wiring for each of the initial multiplexer arrays 102-104 only supports a single, fixed block size.

[0043] 3 illustrates an improved logic circuit 20 according to an example of the present disclosure. The logic circuit 20 comprises circuitry 200 configured to perform a rotate operation on each of 16, 8, and 4 byte blocks.

[0044] The logic circuitry comprises an input data array 201 configured to receive either a 16, 8, or 4 byte block of data to be rotated. Each input byte in the input data array 201 can be thought of as a data "lane."

[0045] The circuit 200 is arranged into multiple processing levels 202, 203, 204. Each level is configured to calculate rotations associated with successively larger block sizes (4, 8, 16). The first level 202 operates on an input data array 201. Subsequent levels 203, 204 operate on the output from the previous level as a partial result.

[0046] Thus, rotation operations for larger block sizes are effectively decomposed across multiple processing levels 202-204. It is understood that "level" in this context is a construct used to describe the logical arrangement of components of circuit 200 and does not imply any particular physical layout of circuit 200.

[0047] First processing level 202 includes four rotators 210a-d. Each rotator 210 is configured to compute a rotation of a block of four bytes. Thus, each rotator 210 is connected to a different respective one of four bytes of input data array 201. For example, rotator 210a is connected to bytes 0-3 of array 201, rotator 210b is connected to bytes 4-7, and so on. Each rotator 210 provides its output to a corresponding byte of first intermediate result array 205. That is, rotator 210a is connected to bytes 0-3 of first intermediate result array 205, rotator 210b is connected to bytes 4-7, and so on. As a result, first processing level 202 effectively includes four parallel four-byte rotators, each operating on four data lanes of the input array.

[0048] 4 shows in detail the structure and operation of rotator 210a of first processing level 202. Rotator 210a takes the form of a multiplexer array including four multiplexers 211a-d. Each multiplexer 211 has four inputs, which are connected to four respective bytes that form the subset of input data array 201 on which rotator 210a operates.

[0049] The multiplexer array operates similarly to the 4:1 array described above with respect to Figure 2, with input j of each multiplexer i connected to byte (i+j) mod 4 of each 4-byte subset of input data array 201 to which rotator 210a is connected. Thus, the 0th input of multiplexer 211a (i.e., the 0th multiplexer) is connected to byte (0+0)%4=0 of the input data array, the 1st input is connected to byte (0+1)%4=1, and so on. The 0th input of multiplexer 211b (i.e., the 1st multiplexer) is connected to byte (1+0)%4=1, the 1st input of the 1st multiplexer is connected to byte (1+1)%4=2, and so on for all inputs of all multiplexers in the array.

[0050] The output of each multiplexer 211 in the array is provided to a corresponding byte of the first intermediate result array 205. That is, the 0th multiplexer 211 is connected to byte 0 of the intermediate result array 205, the 1st multiplexer 211 is connected to byte 1 of the intermediate result array 205, and so on.

[0051] Rotator 210a is configured to receive control signal 212 indicating the desired amount of rotation. For example, control signal 212 may include a 2-bit signal representing a rotation amount between 0 and 3 (i.e., up to block size minus 1). Control signal 212 is provided to each multiplexer 211, which selects the input corresponding to the rotation amount. This causes each multiplexer in the array to select the associated byte from the input data array and perform the desired rotation. If the rotation amount is 0, the multiplexer array acts as a pass-through.

[0052] Rotators 210b-d operate substantially identically, except that they receive inputs from, and provide outputs to, different bytes of input array 201 and intermediate result array 205.

[0053] In terms of expressing the relationship between any given multiplexer 211 of the rotator 210 and the complete input data array 201, the input j of the ith S:1 multiplexer should be connected to the following byte of the input data array 201: (floor(i / S)*S)+(j%S)

[0054] In the above equation, i is the index of the multiplexer 211 across the first processing level 202. Multiplexers 211a-d in rotator 210a are indexed from 0 to 3, multiplexers 211 in rotator 210b are indexed from 4 to 7, and so on.

[0055] Returning to FIG. 3, second processing level 203 includes two 8-byte rotators 220a, b. Each of the 8-byte rotators is connected to a different 8-byte portion of first intermediate result array 205. For example, rotator 220a receives input from bytes 0 through 7 of array 205, and rotator 220b receives input from bytes 8 through 15 of array 205. Each rotator 220a outputs a rotated 8-byte block to second intermediate result array 215. Thus, rotator 220a generates a rotated 8-byte block (i.e., rotated relative to the corresponding 8 bytes of input array 201) from the two rotated 4-byte blocks output by first level 202.

[0056] Figure 5 shows in more detail the rotator 220a of the second processing level 203. The rotator takes the form of an array of eight multiplexers 221a-h.

[0057] Each multiplexer is a 2:1 multiplexer. Input 0 of the ith multiplexer is connected to byte i mod 4 of array 205. Input 1 of the ith multiplexer is connected to byte (i mod 4)+4 of array 205. Thus, each multiplexer 221 connects input 0 to a byte of the first rotated block and input 1 to a byte of the second rotated block, effectively selecting the corresponding byte of the first rotated block (i.e., output by rotator 210a to bytes 0-3 of array 205) or the second rotated block (i.e., output by rotator 210b to bytes 4-7 of array 205).

[0058] The output of each multiplexer 221 in the array is provided to a corresponding byte of the second intermediate result array 215. That is, the 0th multiplexer 221 is connected to byte 0 of the intermediate result array 215, the 1st multiplexer 221 is connected to byte 1 of the intermediate result array 215, and so on.

[0059] Rotator 220a is configured to receive control signal 222. Control signal 222 takes the form of an 8-bit bitmask 0xF0 (i.e., 11110000) to be rotated by an amount corresponding to the desired rotation amount, which is a value between 0 and 7. Thus, for a rotation amount of 1, the bitmask is 11100001, for a rotation amount of 2, the bitmask is 11000011, and so on.

[0060] The bit mask is split by splitter 223. Each bit of the bit mask of control signal 222 is sent to a respective multiplexer 221. That is, bit 0 of the bit mask is provided to the 0th multiplexer 221a, bit 1 of the bit mask is provided to the 1st multiplexer 221b, and so on. Splitter 223 may comprise appropriate circuitry, for example, wires for communicating each of the bits to their respective multiplexers 221. In some examples, splitter 223 may be embodied solely by wires.

[0061] Thus, rotator 220a receives two 4-byte blocks rotated by an arbitrary amount and outputs an 8-byte block rotated by the same arbitrary amount. If the rotation amount is 0 (i.e., the bit mask is 11110000), rotator 220a acts as a pass-through.

[0062] Rotator 220b operates substantially the same, except that it receives inputs from and provides outputs to different bytes of first intermediate result array 201 and second intermediate result array 215.

[0063] 3, the third processing level includes a 16-byte rotator 230. Rotator 230 receives as input all 16 bytes of second intermediate result array 215, which contains the two rotated 8-byte blocks output by rotator 220. Rotator 230 outputs the rotated 16-byte blocks to final result array 225.

[0064] Figure 6 shows rotator 230 in more detail. Again, rotator 230 takes the form of a multiplexer array, in this case including sixteen 2:1 multiplexers 231a-p. Some of the multiplexers 231 have been omitted to improve clarity of the illustration.

[0065] The structure and operation of rotator 230 is similar to rotator 220, but is adapted to operate on 8-byte input blocks rather than 4-byte input blocks. Thus, input 0 of the ith multiplexer is connected to byte i mod 8 of array 215. Input 1 of the ith multiplexer is connected to byte (i mod 8)+8 of array 215. Thus, each multiplexer 231 connects input 0 to a byte of the first rotated block and input 1 to a byte of the second rotated block, effectively selecting the corresponding byte of the first rotated block (i.e., output by rotator 220a to bytes 0-7 of array 215) or the second rotated block (i.e., output by rotator 220b to bytes 8-15 of array 215).

[0066] Similar to rotator 220, rotator 230 is configured to receive a control signal in the form of a rotation bit mask. However, in this case, the bit mask is a 16-bit bit mask 0xFF00. As before, the rotation of the bit mask reflects the desired amount of rotation. The received bit mask is split by splitter 233, which distributes the bits of the bit mask to their respective multiplexers 230.

[0067] In some examples, the circuit 200 may include pipeline registers 206 located between at least some of the processing levels 202. These are shown in Figure 8. This may help meet timing requirements.

[0068] 7 shows that logic circuit 20 may further comprise control signal generator 250 (including circuitry configured to generate control signals 212, 222, 232 to control the rotator to effect the desired rotation). To generate such signals, the control signal generator may be provided with the size 251 of the block to be rotated, as well as the desired amount of rotation 252.

[0069] As described in more detail below, these may form part of the rotate instruction 253 or may form part of another instruction that involves a rotate operation (e.g., a pack instruction or an extract instruction). That is, the rotate amount 252 and the block size 251 may be indicated by the instruction. For example, one or both of the rotate amount 252 and the block size 251 may be an operand or may be indicated by an opcode. In other examples, the rotate amount 252 and / or the block size 251 may be read from one or more registers as part of the execution of the instruction. In some cases, the instruction may indicate a value from which the block size or the rotate amount can be calculated.

[0070] As mentioned above, the control signal 212 for controlling the rotator 210 of the first level 202 is the desired rotation amount 252. If a block of size 251 greater than 4 bytes is to be rotated by a rotation amount 252 greater than 3, the signal 212 is the desired rotation amount mod 4.

[0071] Also, as previously mentioned, the control signal 222 for controlling the rotator 220 of the second level 203 is the bit mask 0xF0 rotated by the rotation amount 252. Accordingly, the control signal generator 250 may include appropriate circuitry for rotating the bit mask 0xF0 by the rotation amount 252. For example, the control signal generator 250 may include (or otherwise access) a lookup table that stores rotated versions of the bit masks. The control signal generator 250 may then select the stored rotated bit mask based on the desired rotation amount 252. In another example, the control signal generator 250 may include circuitry for performing a bit shifting operation to rotate the bit mask by the desired amount. When rotating a block of size 251 greater than 8 bytes by a rotation amount 252 greater than 7, the bit mask is rotated by the rotation amount 252 mod 8.

[0072] As further described above, the control signal 232 for controlling the third-level rotator 230 is the bit mask 0xFF00 rotated by the rotation amount 252. Accordingly, the control signal generator 250 may also include circuitry (e.g., appropriate look-up tables or bit-shifting circuitry) similar to that described above in connection with rotating the bit mask 0xF0 to perform this rotation.

[0073] To further facilitate understanding of the operation of logic circuit 20, an example of circuit 20 in use will now be described.

[0074] To rotate a block of four bytes, the block of four bytes is provided as input to bytes 0-3 of input data array 205. Control signal generator 250 generates control signal 212 corresponding to the desired amount of rotation, which is provided to rotator 210a. Rotator 210a performs the rotation and outputs the result to bytes 0-3 of intermediate result array 205.

[0075] Because only a 4-byte block needs to be rotated, control signal generator 250 generates unrotated bit masks as control signals 222, 232 for levels 203, 204, causing them to function as pass-throughs. Thus, the rotated blocks in bytes 0-3 of intermediate result array 201 pass through levels 203, 204 and are output to bytes 0-3 of output array 225. Generally, if one level is to function as a pass-through, subsequent levels are also made to function as pass-throughs.

[0076] If desired, logic circuit 20 can perform rotations of up to four 4-byte blocks in parallel by inputting each 4-byte block to each rotator 210 via the associated byte of input data array 201.

[0077] Similarly, if fewer than four 4-byte blocks need to be rotated in parallel, circuitry not used for the desired rotation may be disabled using clock gating. For example, if only one 4-byte block is to be rotated, rotators 210b-d and 220b may be disabled. Control signal generator 250 may generate appropriate control signals 242 for enabling or disabling clock gates 207 (see FIG. 8) that may be included within circuit 200.

[0078] To rotate an 8-byte block, the 8-byte block is provided as input to bytes 0-7 of input data array 205. Control signal generator 250 generates control signals 212 from the instruction based on the desired amount of rotation, which are provided to rotators 210a and 210b. Rotators 210a and 210b perform the rotation and output the results to bytes 0-3 and 4-7, respectively, of first intermediate result array 205.

[0079] Control signal generator 250 also generates control signal 222 based on the desired amount of rotation, which is provided to rotator 220a, which outputs the rotated 8-byte blocks into bytes 0-7 of second intermediate result array 215.

[0080] Control signal generator 250 also generates control signals 232 for level 204, which causes rotator 230 to function as a pass-through. Thus, the rotated 8-byte block is output to bytes 0-7 of output array 225.

[0081] In a similar manner as described above for 4-byte blocks, two 8-byte blocks can be rotated in parallel using logic circuitry 20. Additionally, control signal 242 may provide clock gating control signals 242 that disable circuitry not used to rotate a single 8-byte block.

[0082] To rotate a 16-byte block, the 16-byte block is provided as input to data array 205. Control signal generator 250 generates control signals 212 based on the desired amount of rotation, which are provided to rotators 210a-d. Rotators 210a-d perform their respective rotations of the 4-byte block, and each of the results is output to bytes 0-3, 4-7, 8-11, and 12-15, respectively, of first intermediate result array 205.

[0083] Control signal generator 250 also generates control signal 222 based on the desired amount of rotation, which is provided to rotators 220a and 220b. Rotator 220a outputs the rotated 8-byte block to bytes 0 through 7 of second intermediate result array 215. Rotator 220b outputs the rotated 8-byte block to bytes 7 through 15 of second intermediate result array 215.

[0084] Control signal generator 250 also generates control signals 232 based on the desired amount of rotation, which are provided to rotator 230. Rotator 230 outputs rotated blocks of 16 bytes to output array 225.

[0085] The above examples may be incorporated into the processing units described above in connection with Figure 1A. For example, execution unit 18 of processor 4 may include logic circuitry 20. Circuitry 20 may be implemented in, for example, FPU 18A of processor 4.

[0086] More specifically, execution unit 18 may receive instructions (i.e., computer program instructions) to perform a rotation of a data block. In one example, the instruction is a rotate instruction, the sole purpose of which is to rotate the data block. However, in some cases, a separate instruction may be provided along with the data block rotation, which involves further processing of the rotated data block. That is, the instruction may include multiple operations, including the rotate operation, to be performed by the logic circuitry.

[0087] As previously mentioned, the received instruction 253 indicates the block size 251 and the required rotation amount 252 (which may be read from a register, for example, as an operand, as part of an opcode, or as part of the execution of the instruction). Although not shown in FIG. 6, the instruction 253 may also include an indication of the memory location of the block to rotate. This may take the form of an address or a pointer to a register storing an address. In other examples, the memory address storing the block to rotate may be implicit. The instruction 253 may optionally include an indication of the memory location for storing the rotated block. Similarly, this may include an address or a pointer to a register storing an address. Similarly, it may be implicit in the instruction.

[0088] Upon receiving an instruction, execution unit 18 loads a data block into input data array 201. For example, execution unit 18 may receive an instruction as described herein with respect to FIG. 1A. In particular, fetch stage 14 may fetch an instruction from instruction memory 11 and then issue the instruction to execution unit 18 via decode stage 16.

[0089] Based on the required amount of rotation 252, control signal generator 250 generates appropriate control signals 212, 222, 232 to control circuit 200. The data block is then processed through circuit 200 and the output is read from output array 225. If the instruction includes a memory location for storing the rotated block, the rotated block may be stored in that memory location.

[0090] 8 shows in more detail the incorporation of clock gates 207 and pipeline registers 206. In this diagram, the input and output arrays have been omitted for clarity.

[0091] Pipeline registers 206 are located between successive processing levels. For example, a first pipeline register 206-1 is located between the first processing level 202 and the second processing level 203. A second pipeline register 206-2 is located between the second processing level 203 and the third processing level 204. It is understood that in some implementations, no pipeline registers 206 may be required, or only one pipeline register 206 may be required. By providing a layered structure including levels 202, 203, and 204, insertion of pipeline registers 206 for retiming logic circuit 20 is simplified. Furthermore, pipeline registers 206 are shared between operations applied to different block sizes.

[0092] In some examples, one or both of intermediate result arrays 205, 215 may comprise pipeline registers 206. That is, intermediate result arrays 205 and / or 215 are, in some cases, each pipeline register 206. However, in other examples, one or both of intermediate result arrays 205, 215 may be wires. As noted herein, whether arrays 205 and 215 are pipeline registers or wires may depend on timing requirements.

[0093] 8 further illustrates a plurality of clock gates 207. The clock gates 207 in this example are configured to disable one or more data path lanes of the logic circuit 20. For example, each gate 207 may be arranged to disable four lanes. In the illustrated example, the first clock gate 207-1 may disable lanes 0 through 3, the second clock gate 207-2 may disable lanes 4 through 7, the third clock gate 207-3 may disable lanes 8 through 11, and the fourth clock gate 207-4 may disable lanes 11 through 15.

[0094] Thus, if only one 4-byte block is to be rotated, clock gates 207-2, 207-3, and 207-4 may disable their corresponding lanes. Similarly, if one 8-byte block is to be rotated, clock gates 207-3 and 207-4 may disable their corresponding lanes. If some of the lanes of a multiplexer are disabled, the remaining lanes may function as pass-throughs.

[0095] It is understood that this is one example configuration of clock gate 207. In other examples, gate 207 may disable more or fewer lanes (e.g., two or eight lanes). Additionally, in some examples, gate 207 may be arranged to disable particular multiplexers.

[0096] 9 and 10, which show a first and second code sample, respectively, of instructions involving a rotate operation.

[0097] The rotate operations described above may be particularly useful in a class of instructions referred to herein as data movement instructions, which may be used to accelerate the movement of arbitrarily aligned data in processor 4.

[0098] For example, the architecture of an execution unit may impose certain constraints on accessing data in memory. Assume that the execution unit is configured to execute load instructions on 4-byte-wide data units. In this case, each load instruction may only load data from memory addresses that indicate 4-byte subdivisions of memory. For example, if the starting address of memory is 0x80000, a load instruction may result in the loading of 4 bytes of data starting at memory address 0x80000, or it may be used to load 4 bytes of data starting at memory address 0x80004. However, given the architectural constraints of the processing unit, it is not possible to load data starting at memory address 0x80002 because this memory address does not match the size of the memory access. Similar constraints may apply to store operations. Such constraints may cause problems in "worker" programs (i.e., programs executed by worker threads) that are collectively used to process large batches of application data, for example, in training machine learning models. Data movement instructions may be used to align misaligned data, thereby accelerating the processing of application data.

[0099] Although described in more detail above with respect to FIG. 1, relevant aspects of an exemplary processing pipeline are summarized below: Data movement instructions may be available in "worker" programs. "Worker" programs are used to process large batches of application data together. Worker programs are executed sequentially by tile processors (e.g., processor 4, FIG. 1) via a fixed-length pipeline. Pipeline latency is hidden by having multiple worker threads reside per tile 4 and scheduling these in a barrel-threaded manner across multiple clock cycles.

[0100] In the first pipeline stage, the instruction fetch stage 14 fetches raw instruction words from the executable region of the tile combined memory 11 into a local buffer 53 inside the tile 4 .

[0101] In the second pipeline stage, decode logic (e.g., decode stage 16) converts the fetched instruction word into an internal data structure that describes how the rest of the pipeline needs to be controlled to execute the instruction. For data movement instructions, fields in this data structure signal to enable the FPU (and internal data movement pipeline) of secondary execution unit 18A, describe the operation to be performed via the opcode, and provide the source and destination operand addresses.

[0102] The third stage is where the operands are read. For instructions that use the logic circuitry 20 described herein, the operand address is decoded from the instruction index in a set of registers in the ARF 26A. The read operand data is presented to a data movement pipeline within the FPU.

[0103] Over the next several stages, the data movement pipeline executes instructions that process blocks of data (operand data). Data movement instructions are, for example, "pack" or "extract" operations with block sizes of 4, 8, or 16 bytes. The data blocks are data operands read from ARF 26A. The "pack" and "extract" operations may also be controlled by per-worker state registers, described below.

[0104] After the instruction is executed, the output is written back to the ARF 26A location specified in the instruction's operands.

[0105] Figure 9 shows a code sample that executes the pack instruction. The pack instruction copies any sequence of contiguous bytes from a first block to any position in a second block, with wrapping. Logic circuitry 200 is used to align the bytes of the first block to the correct output positions. The rotation amount is derived from a field in the $PACK worker state register, which is implicitly used by the pack instruction. Masking is used to select any number of contiguous bytes from either the second data block or the rotated first data block, according to the configuration of the $PACK worker state register.

[0106] In particular, reference numeral 91 indicates loading a first data block of 8 bytes into memory location $a0:1. Two ldconst instructions are used to load each of the 4 bytes of the block into $a0 and $a1. That is, the first operand of the ldconst instruction indicates the location where the data is to be loaded, and the second operand indicates the data. In this example, the ldconst instruction is used to load dummy data into location $a0:1. It can be seen that in reality, application data is loaded into the memory location.

[0107] Reference numeral 92 indicates the corresponding instruction used to load the second data block into location $a2:3.

[0108] Next, a pack instruction is configured. In the example, the pack instruction is intended to insert 3 bytes from position 1 of the first block into position 5 of the second block. To do this, a register $m0 is set to a value that reflects the desired configuration, indicated by reference numeral 93. In the example, the setzi instruction is an instruction configured to set a register. The instruction takes a first operand that indicates a register ($m0) and a second operand that contains the value to be stored in the register.

[0109] In the example, the two least significant bytes (0x03) indicate the number of bytes to insert. The next two bytes (0x01) indicate the position in the first block from which to read these bytes. The last byte (0x5) indicates the position in the second block where the bytes should be inserted.

[0110] This value is then copied from register $m0 to the aforementioned $PACK worker state register using the put instruction in step 94.

[0111] Finally, the pack instruction is executed, as indicated by reference numeral 95. The first operand indicates where the result of the instruction should be output, and the second and third operands indicate the locations in memory of the first and second blocks, respectively. Thus, in the example, the result is written back to $a0:1 (where the first block was read from).

[0112] The opcode of the pack instruction indicates the block size. In the example, the opcode is "pack64", indicating a block size of 8 bytes (i.e., 64 bits). Different opcodes may be provided for blocks of different sizes (e.g., pack128 for 16-byte blocks and pack32 for 4-byte blocks).

[0113] When a pack instruction is executed, the execution unit determines the amount of rotation required based on the value in $PACK, and determines the block size to rotate based on the opcode. Control signal generator 250 therefore generates the appropriate control signals to configure the logic circuitry to perform the required rotation. In the example above, the block size is 8, and the bytes of the first block are rotated by 4 to fit into the output locations.

[0114] Figure 10 shows a code sample that performs the extract instruction. The extract instruction extracts a block of contiguous bytes at any position from the concatenation of two input blocks, with wrapping. The $EXTRACT worker state register indicates the "pivot point," which represents the starting index for selecting bytes from the concatenated double block. Masking is used to select relevant bytes from either input block. The resulting bytes are then rotated to the correct output position using logic circuitry 200.

[0115] In particular, reference numeral 1001 indicates loading a first data block of 16 bytes into memory location $a0:3. Four ldconst instructions are used to load each of the four bytes of the block into $a0-$a3, respectively. Reference numeral 1002 indicates the corresponding instructions used to load a second data block into locations $a4:7.

[0116] Reference numerals 1003 and 1004 indicate setting the $EXTRACT register with the value 0x7, reflecting the fact that the output should be extracted starting from byte 7 of the concatenation of the two input blocks.

[0117] Reference numeral 1005 indicates the execution of the extract operation. As with the pack instruction, the first operand indicates where the result of the instruction should be output, and the second and third operands indicate the locations in memory of the first and second blocks, respectively. Thus, in the example, the result is written back to $a0:3 (where the first block was read from).

[0118] The opcode of the extract instruction also indicates the block size. In the example, the opcode is "extract128," indicating a block size of 16 bytes (i.e., 128 bits). Different opcodes may be provided for blocks of different sizes (e.g., extract64 for 8-byte blocks and extract32 for 4-byte blocks).

[0119] When an extract instruction is executed, the execution unit determines the amount of rotation required based on the value in $EXTRACT, and the block size to rotate based on the opcode. Accordingly, control signal generator 250 generates the appropriate control signals to configure the logic circuits to perform the required rotation.

[0120] Both pack and extract instructions are described in more detail in co-pending U.S. patent application Ser. No. 18 / 053,948, the contents of which are incorporated herein by reference in their entirety.

[0121] A further description of the multi-tile processing unit follows. As previously mentioned, processor 4 may form part of a multi-tile processing device. A suitable processing device can take many different forms, including a chip. Graphcore has developed an intelligent processing unit (IPU), as described, for example, in U.S. Patent Applications US2019 / 0121387A1, US2019 / 0121388A1, US2019 / 0121777A1, and US2020 / 0319861A1, the contents of which are incorporated herein by reference. FIG. 1B is a highly schematic diagram of an IPU. The IPU comprises multiple tiles 1103 on a silicon die, each comprising a processing unit (e.g., the processing unit 4 described above) with local memory. The tiles communicate with each other using time-deterministic exchanges. A switching fabric 1101 (sometimes referred to as a switching or exchange fabric) is connected to each of the tiles by their respective sets of output wires and is connectable to each of the tiles by their respective sets of input wires via switching circuitry controllable by each tile. A synchronization module (not shown) is operable to generate synchronization signals for switching between the computation phase and the exchange phase. The tiles execute their local programs in the computation phase according to a common clock generated on or received by the die. At predetermined times in the exchange phase, a tile may execute a transmit instruction from its local program to transmit a data packet to its set of output connection wires. The data packet is intended for at least one receiving tile but does not have a destination identifier that identifies the receiving tile. At predetermined switch times, the receiving tile executes a switch control instruction from its local program to control the switching circuitry to connect its set of input wires to the switching fabric and receive the data packet at the receive time. The transmit times at which data packets are scheduled to be transmitted from the transmitting tile and the predetermined switch times are controlled by the common clock relative to the synchronization signal.

[0122] Time-deterministic exchanges allow for efficient transfers between tiles on a die. Each tile has its own local memory that provides data and instruction storage. As described herein, the IPU is further connected to external memory, from which data can be transferred onto the IPU for use by the tiles via the fabric chip.

[0123] The tiles 1103 of an IPU may be programmed so that data packets sent by SEND instructions from their local programs are intended to access memory (memory access packets) or have another IPU connected within the cluster or system as their destination. In such cases, the data packets are transmitted onto the switching fabric by the transmitting tile 1103 but are not received by a receiving tile within the IPU. Instead, the switching fabric provides the tile with the appropriate connectors C1, C2, etc. for external communication from the IPU. Packets for off-chip communication are generated to include information that specifies their ultimate off-chip destination, but not the external port from which they should be transmitted. When code is compiled for a tile, it may send the packet to an external port using the principle of time-deterministic switching to identify the external port for the packet. For example, a memory access packet may identify a memory address. A packet intended for another IPU may include an identifier for that IPU. This information is used by routing logic on the fabric chip to correctly route off-chip packets generated by the IPU.

[0124] The diagram in Figure 1B shows five exemplary regions of a typical IPU chip, separated by four boundaries 1105 represented by dashed lines. Note that the dashed lines represent abstract boundaries 1105 of abstract regions on the processor chip and are shown for illustrative purposes only. The boundaries 1105 do not necessarily represent physical boundaries on the IPU chip.

[0125] It will be appreciated that in addition to incorporating logic circuitry into a processing unit in the form of a tile processor, logic circuitry may be incorporated into a wide variety of processing units or devices.

[0126] Various modifications may be made to the examples described herein within the scope of the present disclosure.

[0127] For example, it will be appreciated that the example provided above can be easily extended to larger power-of-two block sizes. For example, to rotate blocks of 32 bytes, the existing circuitry can be replicated (i.e., replicated horizontally so that each layer 202 contains twice the amount of rotators 210, 220, 230) so that the input / output / intermediate arrays contain 32 bytes. A further layer can then be added with 32 2:1 multiplexers controlled by a bitmask twice as wide as the previous layer (i.e., 0xFFFF0000). This pattern can be replicated to provide circuitry for rotating power-of-two blocks of any size. Similarly, layer 204 can be omitted to provide circuitry for rotating only 4-byte and 8-byte blocks.

[0128] Advantageously, the examples described herein provide a means of rotating relatively large blocks of size S, avoiding complex S:1 ordering, thus allowing for the use of smaller, faster multiplexers and eliminating the need for numerous long datapath wires, which helps keep timing paths short.

[0129] Additionally, the examples described herein help minimize the area cost of processor functions and provide optimal performance per unit area. These examples involve hardware resources being reused across all sizes of rotate instructions, rather than requiring different hardware resources for different block sizes. Because the techniques described herein naturally decompose into levels, it is very easy to break them down into pipeline stages by inserting appropriate pipeline registers.

[0130] Additionally, these examples allow for simple clock gating of unused hardware resources, minimizing power consumption by enabling only required hardware resources.

Claims

1. an execution unit configured to execute computer program instructions for performing a byte-wise rotate operation on an input data block, a logic circuit and a control signal generator; The logic circuit comprises: an input data array for receiving an input data block containing N bytes; two first layer multiplexer arrays; a second layer multiplexer array; and Each first layer multiplexer array comprises: receiving a first-tier data block containing each subset of bytes of the input data block; receiving a layer 1 control signal; configured to rotate the first-layer data blocks by an amount indicated by the first-layer control signal; the two first-layer multiplexer arrays are configured to output the first rotated first-layer data block and the second rotated first-layer data block, respectively; the second layer multiplexer array is configured to receive a second control signal and comprises N multiplexers; each multiplexer configured to select corresponding bytes of either the first rotated first-layer data block or the second rotated first-layer data block based on the second control signal, and output a rotated second-layer data block; the control signal generator is configured to generate the first-layer control signals and the second-layer control signals based on the computer program instructions. Execution unit.

2. 2. The execution unit of claim 1, wherein each first-tier data block can include N / 2 bytes.

3. the input data array is configured to receive an input data block containing M bytes, where M>N; The logic circuit comprises: four first-layer multiplexer arrays that output the first through fourth rotated first-layer blocks; two second layer multiplexer arrays; a third layer multiplexer array; and a first of the two second-layer multiplexer arrays configured to receive the first rotated first-layer block and the second rotated first-layer block and to output a first rotated second-layer data block; a second of the two second-layer multiplexer arrays configured to receive the third rotated first-layer block and the fourth rotated first-layer block and to output a second rotated second-layer block; the layer 3 multiplexer array is configured to receive layer 3 control signals and comprises M multiplexers; the M multiplexers are configured to select corresponding bytes of either the first rotated second-layer data block or the second rotated second-layer data block based on the third control signal, and output a rotated third-layer data block; 3. An execution unit as claimed in claim 1 or 2, wherein the control signal generator is configured to generate the third layer control signals.

4. 4. An execution unit according to claim 1, wherein the logic circuitry has an intermediate result array configured to receive the output of the first tier multiplexer array.

5. 5. An execution unit as claimed in any preceding claim, wherein each first tier multiplexer array comprises a plurality of S:1 multiplexers.

6. the layer 2 control signal includes an N-bit bit mask; 6. An execution unit as claimed in any preceding claim, wherein each bit of the bitmask serves as a control signal for each of the N multiplexers of the second layer multiplexer array.

7. 7. The execution unit of claim 6, wherein the logic circuitry comprises a splitter that splits the bit mask and provides each bit to a respective multiplexer.

8. the control signal generator is configured to rotate the bit mask; 8. An execution unit as claimed in claim 6 or 7, wherein the amount of rotation of the bit mask causes the output of the rotated second-tier data block to be rotated by the same amount.

9. 9. The execution unit of claim 8, wherein the control signal generator is configured to rotate the bit mask by selecting a stored rotated bit mask from a lookup table.

10. 4. The execution unit of claim 3, wherein the layer 3 control signal is an M-bit bitmask.

11. 11. An execution unit according to claim 1, wherein the control signal generator is capable of generating second layer control signals that cause the second layer multiplexer array to operate as a pass-through.

12. The logic circuit comprises: a plurality of data path lanes; one or more clock gates configured to disable one or more of the data path lanes; and 12. An execution unit as claimed in any preceding claim, wherein the control signal generator is configured to generate a clock gate control signal to control the one or more clock gates.

13. 13. An execution unit according to claim 1, wherein the logic circuit comprises a pipeline register arranged between the first layer multiplexer array and the second layer multiplexer array.

14. Execution unit according to any one of claims 1 to 13, wherein the computer program instruction is a rotate instruction configured to rotate the input data block.

15. Execution unit according to any one of claims 1 to 14, wherein the computer program instructions comprise a plurality of operations, and a rotation operation is one of the plurality of operations.

16. The computer program instructions include: a pack instruction configured to copy a sequence of contiguous bytes from a first location in a first data block to a second location in a second data block; or 16. An execution unit as claimed in claim 15, comprising an extract instruction configured to extract a sequence of contiguous bytes from a concatenation of a first data block and a second data block.

17. 11. The execution unit of claim 3 or 10, wherein the execution unit is configured to generate the first layer control signals, the second layer control signals, and / or the third layer control signals based on values ​​indicated by the computer program instructions.

18. The values ​​indicated by the computer program instructions are: one or more operands of said computer program instruction; and an opcode of the computer program instruction; values ​​stored in one or more registers associated with said computer program instructions; and 18. The execution unit of claim 17, wherein the value is included in one or more of:

19. A processing unit comprising the execution unit according to any one of claims 1 to 18.

20. A processing apparatus comprising a plurality of processing units, at least one of said plurality of processing units being the processing unit of claim 19.

21. 21. The processing device of claim 20, wherein the processing units are tile processors that communicate via a switching fabric that implements time-deterministic switching.

22. 1. A method implemented in an execution unit, comprising: receiving an input data block comprising N bytes; providing first-tier data blocks containing respective subsets of bytes of the input data block to a first first-tier multiplexer array and a second first-tier multiplexer array; providing first layer control signals to the first first layer multiplexer array and the second first layer multiplexer array; rotating the first-layer data block by an amount indicated by the first-layer control signal to output a first rotated first-layer data block and a second rotated first-layer data block; providing the first rotated first-layer data block and the second rotated first-layer data block to a second-layer multiplexer array comprising N multiplexers; providing a second control signal to the second-layer multiplexer array and selecting corresponding bytes of either the first rotated first-layer data block or the second rotated first-layer data block based on the second control signal.

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