Physical adjustments to system memory using chipset memory

Abstract

Physical adjustments to system memory using on-chip memory are described. According to the described technique, an indication to make one or more physical adjustments to system memory of a device is received. The contents of the system memory are transferred to the on-chip memory via a chipset link. The device is operated using the content from the on-chip memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the content is transferred from the on-chip memory back to the adjusted system memory via the chipset link.

Description

[Technical Field]

[0001] (Related Applications) This application claims priority to U.S. patent application Ser. No. 18 / 146,920, filed Dec. 27, 2022, and entitled "Physical Adjustment to System Memory with Chipset Attached Memory," the entire disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002] Computer games and other applications are constantly evolving, resulting in larger programs, higher resolution graphics, new features, etc. To accommodate these advancements, computer hardware is also evolving to provide new types of memory with faster data rates, faster clock rates, etc. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a diagram of a non-limiting exemplary system employing on-chipset memory to continue system operation during physical adjustments of system memory. [Figure 2] FIG. 1 illustrates a non-limiting example of on-chipset memory continuing system operation during physical adjustments of system memory. [Figure 3] FIG. 1 illustrates a procedure in an exemplary embodiment for physical adjustments to system memory using on-chip memory. [Figure 4] FIG. 1 is a diagram of another non-limiting exemplary system employing on-chipset memory to continue system operation during physical adjustments of system memory. [Figure 5] FIG. 1 is a diagram of another non-limiting exemplary system employing on-chipset memory to continue system operation while system memory is inoperable. DETAILED DESCRIPTION OF THE INVENTION

[0004] (overview) Physical adjustments to system memory using chipset-mounted memory are described. According to the described techniques, a computing system uses chipset-mounted memory to continue operation while adjustments, e.g., physical adjustments, are made to the system memory. For example, a system uses chipset-mounted memory to continue running an operating system while the system memory is inoperable. To do so, the system memory is disabled (e.g., by gating the system memory so that it is powered down and "offline"), thereby allowing the system memory to be physically adjusted. Examples of such physical adjustments that may be made while the system memory is inoperable include, but are not limited to, removing, adding, or replacing one or more components of the system memory, such as dual in-line memory modules (DIMMs), small-outline dual in-line memory modules (SO-DIMMs), or registered dual in-line memory modules (RDIMMs).

[0005] In one or more embodiments, the contents of system memory are transferred to on-chipset memory. This transfer may occur, for example, in response to a user request made via the system's user interface. Once the content is transferred to on-chipset memory, various operations are performed using the content now accessible in the on-chipset memory. For example, a processing unit of the system may use the content from the on-chipset memory to perform (and / or continue to seamlessly perform) one or more tasks of the operating system and / or applications. In particular, the processing unit uses the same content that was in main system memory, but now the content is transparently available to the operating system or applications in the on-chipset memory.

[0006] Such operations are performed using content from the on-chipset memory, while the system memory is disabled and inoperable. Thus, because the system memory is not being used, physical adjustments to the system memory may be made, for example, because power to the system memory is gated or otherwise disconnected. Disconnecting power to the system memory (and other components) allows the system memory to be safely physically handled (e.g., touched), such as by adding one or more components (e.g., DIMMs, SODIMMs, or RDIMMs) to the system memory, removing one or more components from the system memory, and / or replacing one or more components of the system memory. After the physical adjustments to the system memory are made, the content is transferred from the on-chipset memory to the reconditioned system memory. Once the content is transferred back to the system memory, the processing unit executes (and / or continues to execute) one or more tasks of the operating system and / or applications using the content from the system memory.

[0007] The ability to continue operating by performing memory-based tasks while system memory is inoperable and physically adjusted contrasts with conventional techniques, which, for example, do not continue running an operating system or applications on the processing unit while system memory is physically adjusted, but rather power down the processing unit (and / or the entire system) so that system memory can be physically adjusted in a safe manner. However, by continuing to operate using on-chipset memory, the described techniques allow memory-based tasks to continue to execute during physical adjustments to system memory. As a result, system "down time" is reduced and / or eliminated, thereby reducing interruptions to various tasks (e.g., background tasks) and improving the user experience.

[0008] In some aspects, the techniques described herein relate to an apparatus that includes a system memory; a memory controller configured to provide a transfer request to the system memory to cause content maintained by the system memory to be transferred from the system memory to a chipset on-chip memory; and a processing unit for performing one or more tasks using the content from the chipset on-chip memory.

[0009] In some aspects, the technology described herein relates to an apparatus, the apparatus further including a processing unit package including a processing unit and a memory controller, wherein the system memory is coupled to the processing unit package.

[0010] In some aspects, the techniques described herein relate to an apparatus, the apparatus further including a chipset link coupling the processing unit package to a chipset-mounted memory, wherein content is transferred from the system memory to the chipset-mounted memory via the chipset link.

[0011] In some aspects, the techniques described herein relate to an apparatus in which a system memory is inoperable while a processing unit performs one or more tasks using content from a chipset on-chip memory.

[0012] In some aspects, the techniques described herein relate to an apparatus in which power to a system memory is gated while a processing unit performs one or more tasks using content from a chipset on-chip memory.

[0013] In some aspects, the techniques described herein relate to an apparatus that enables one or more physical adjustments to be made to system memory by gating the system memory while a processing unit is performing one or more tasks using content from a chipset on-chip memory, wherein the one or more physical adjustments that may be made to the system memory include one or more of replacing a physical component of the system memory, removing a physical component of the physical memory, or substituting a physical component of the physical memory.

[0014] In some aspects, the technology described herein relates to an apparatus, wherein the physical memory module comprises a dual in-line memory module.

[0015] In some aspects, the techniques described herein relate to an apparatus, wherein the memory controller is further configured to provide an additional transfer request to the on-chip memory to transfer content from the on-chip memory back to the system memory.

[0016] In some aspects, the techniques described herein relate to an apparatus, wherein a memory controller is configured to provide a transfer request in response to receiving an indication that one or more physical adjustments are to be made to a system memory.

[0017] In some aspects, the techniques described herein relate to a method, the method including receiving an indication to make one or more physical adjustments to a system memory of a device; transferring contents of the system memory to a chipset-mounted memory via a chipset link; operating the device using the contents from the chipset-mounted memory while the one or more physical adjustments are being made to adjust the system memory; and transferring the contents from the chipset-mounted memory back to the adjusted system memory via the chipset link after the one or more physical adjustments.

[0018] In some aspects, the techniques described herein relate to a method, the method further including disconnecting power to the system memory while one or more physical adjustments are made to adjust the system memory.

[0019] In some aspects, the techniques described herein relate to a method, the method further including operating a device using content from the adjusted system memory after the content is transferred back from the on-chipset memory.

[0020] In some aspects, the techniques described herein relate to a method, the method further including operating a device using content from a system memory before the content is transferred to a chipset on-chip memory.

[0021] In some aspects, the techniques described herein relate to a method, wherein the one or more physical adjustments include one or more of: replacing a physical component of the system memory, removing a physical component of the physical memory, or substituting a physical component of the physical memory.

[0022] In some aspects, the technology described herein relates to a method, wherein the physical component comprises a physical memory module.

[0023] In some aspects, the technology described herein relates to a method, wherein the physical memory module comprises a dual in-line memory module.

[0024] In some aspects, the techniques described herein relate to a method, the method further including training the coordinated physical memory before transferring content from the on-chipset memory back to the coordinated system memory.

[0025] In some aspects, the technology described herein relates to a system that includes system memory slots into which system memory can be installed, a chipset-mounted memory, a memory controller configured to cause content stored in the system memory to be transferred to the chipset-mounted memory, and a processing unit configured to perform one or more tasks using content from the chipset-mounted memory while one or more system memory components are added to or removed from one or more of the system memory slots.

[0026] In some aspects, the technology described herein relates to a system, wherein one or more system memory components include one or more physical memory modules.

[0027] In some aspects, the technology described herein relates to a system, wherein one or more system memory components include one or more dual in-line memory modules.

[0028] 1 is a diagram of a non-limiting, exemplary system 100 employing on-chipset memory to continue system operation during physical adjustments of system memory. System 100 includes a processing unit package 102, a system memory 104, an I / O expander 106, on-chipset memory 108, and a chipset link 110. Processing unit package 102, system memory 104, I / O expander 106, on-chipset memory 108, and chipset link 110 may be located on or part of, for example, a motherboard or other printed circuit board. In one or more embodiments, I / O expander 106 (including on-chipset memory controller 116), chipset link 110, one or more memory channels between processing unit package 102 and system memory 104, and one or more memory channels between I / O expander 106 and on-chipset memory 108, are referred to as the chipset of the motherboard or other printed circuit board. In one or more variations, chipset links 110 may be routed entirely on the motherboard itself. In one or more other variations, I / O expander 106 (including on-chipset memory controller 116) and on-chipset memory 108 may be implemented on an add-in card that is connected to the motherboard via a socket.

[0029] Processing unit package 102 includes a processing unit 112 and a memory controller 114. Processing unit 112 may be any of a variety of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a parallel accelerated processor, a digital signal processor, an artificial intelligence (AI) or machine learning accelerator, etc. Although a single processing unit 112 is shown in system 100, processing unit package 102 optionally includes any number of processing units of the same or different types.

[0030] System memory 104 may be any of a variety of types of physical RAM. Examples of system memory 104 include dynamic random-access memory (DRAM), phase-change memory (PCM), memristors, static random-access memory (SRAM), etc. System memory 104 may be coupled to or mounted on processing unit package 102 via one or more memory channels. System memory 104 may be packaged or configured in any of a variety of different ways. Examples of such packaging or configurations include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), registered dual in-line memory modules (RDIMMs), non-volatile DIMMs (NVDIMMs), ball grid array (BGA) memory permanently mounted (e.g., soldered) to a motherboard (or other printed circuit board), etc.

[0031] Examples of DIMM types include, but are not limited to, synchronous dynamic random-access memory (SDRAM), double data rate (DDR) SDRAM, double data rate 2 (DDR2) SDRAM, double data rate 3 (DDR3) SDRAM, double data rate 4 (DDR4) SDRAM, and double data rate 5 (DDR5) SDRAM. In at least one variation, system memory 104 is configured as or includes an SO-DIMM or an RDIMM according to any of the above-mentioned standards, e.g., DDR, DDR2, DDR3, DDR4, and DDR5.

[0032] Further example memory configurations include low-power double data rate (LPDDR), also known as LPDDR SDRAM, which is a type of synchronous dynamic random access memory. In variations, LPDDR consumes less power than other types of memory and / or has a form factor suitable for devices such as mobile computers and mobile phones. Examples of LPDDR include, but are not limited to, low-power double data rate 2 (LPDDR2), low-power double data rate 3 (LPDDR3), low-power double data rate 4 (LPDDR4), and low-power double data rate 5 (LPDDR5). It should be understood that system memory 104 can be configured in a variety of ways without departing from the spirit or scope of the described technology.

[0033] Memory controller 114 manages access to system memory 104, such as by sending read and write requests to and receiving responses from system memory 104. In one or more embodiments, system memory 104 is physical memory that is managed by an operating system running on processing unit 112 (e.g., CPU), such as by allocating portions of system memory 104 to applications running on processing unit 112, managing virtual memory space and memory pages for applications running on processing unit 112, etc.

[0034] Processing unit package 102 optionally includes one or more additional controllers for linking to additional devices, such as a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller, a Universal Serial Bus (USB) controller, a Serial Peripheral Interface (SPI) controller, a Low Pin Count (LPC) controller, etc. Additionally or alternatively, one or more of these additional controllers are implemented separately from processing unit package 102, such as in a chip that is part of a chipset on a motherboard or other printed circuit board (e.g., an integrated circuit optionally referred to as a northbridge).

[0035] The processing unit package 102 communicates with the I / O expander 106 via a chipset link 110. The chipset link 110 can be any of a variety of communication links, such as a high-speed bus. In one example, the chipset link 110 is one or more PCIe lanes.

[0036] I / O expander 106 includes a chipset-based memory controller 116. I / O expander 106 optionally includes or is coupled to one or more additional controllers for linking to other devices, such as a PCIe controller, a SATA controller, a USB controller, an SPI controller, an LPC controller, etc. In one or more embodiments, I / O expander 106 is referred to as a southbridge.

[0037] The chipset on-chip memory controller 116 manages access to the chipset on-chip memory 108, such as by sending read and write requests to and receiving responses from the chipset on-chip memory 108. The chipset on-chip memory 108 is referred to as "chipset attached" because the chipset on-chip memory 108 is mounted on the I / O expander 106 rather than directly on the processing unit package 102, and because the chipset on-chip memory 108 is controlled by a memory controller in the I / O expander 106 rather than a memory controller in the processing unit package 102. The chipset on-chip memory 108 is coupled to or mounted on the I / O expander 106 through one or more memory channels.

[0038] On-chipset memory 108 is physical memory managed by applications or programs other than the operating system running on processing unit 112. On-chipset memory 108 is separate from system memory 104, allowing it to be used in a variety of ways, such as to speed up access to frequently used data, without reducing the amount of system memory 104 available to the operating system running on processing unit 112.

[0039] The chipset on-chip memory 108 may be any of a variety of types of physical memory. Examples of the chipset on-chip memory 108 include random-access memory (RAM), such as DRAM, PCM, memristor, and SRAM. The chipset on-chip memory 108 may be volatile or non-volatile memory. The chipset on-chip memory 108 may be packaged or configured in any of a variety of different ways. Examples of such packaging or configurations include DIMM, SO-DIMM, RDIMM, NVDIMM, BGA, three-dimensional (3D) stacked memory, on-package memory (e.g., memory included in the I / O expander 106), memory permanently mounted (e.g., soldered) to the motherboard, etc.

[0040] As mentioned above, example DIMM types include, but are not limited to, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, and DDR5 SDRAM. In at least one variation, the chipset-on-chip memory 108 is configured as or includes an SO-DIMM or an RDIMM according to any of the above-mentioned standards, e.g., DDR, DDR2, DDR3, DDR4, and DDR5. Further examples of chipset-on-chip memory configurations include LPDDR, such as LPDDR2, LPDDR3, LPDDR4, and LPDDR5. It should be understood that the chipset-on-chip memory 108 can be configured in various manners without departing from the spirit or scope of the described technology.

[0041] In accordance with the described techniques, system 100 uses chipset-based memory 108 to continue operation while adjustments, e.g., physical adjustments, are made to system memory 104. For example, system 100 uses chipset-based memory 108 to continue running the operating system while system memory 104 is physically adjusted, and thus powered down and “offline.” Examples of such physical adjustments include, but are not limited to, removing system memory 104 (or one or more components of system memory 104, such as DIMMs, SODIMMs, or RDIMMs), replacing system memory 104 (or one or more components of system memory 104, such as DIMMs, SODIMMs, or RDIMMs), substituting system memory 104 (or one or more components of system memory 104, such as DIMMs, SODIMMs, or RDIMMs), and adding to system memory 104 (e.g., adding one or more components, such as DIMMs, SODIMMs, or RDIMMs).

[0042] In one or more embodiments, an indication (instruction) 118 to make a physical adjustment to system memory 104 is received. By way of example, a user provides input via a user interface of a system or memory management application (not shown) being executed by processing unit 112, the input indicating that the user intends to physically adjust system memory 104. This allows system 100 to transition to a state in which the person may physically adjust system memory 104 without endangering themselves or damaging components of system 100. If power to system memory 104 is not disconnected, for example, a person attempting to physically adjust system memory 104 risks receiving an electric shock, which can have a variety of harmful consequences, and in some circumstances, may be fatal.

[0043] In the depicted example, memory controller 114 is shown receiving an indication 118 to make a physical adjustment. In one or more embodiments, the indication 118 is received, for example, from an operating system and / or an application executing on processing unit 112 or a portion of which executes on processing unit 112. In at least one variation, the indication 118 is received from another component of system 100 or from a different component (not shown) coupled to system 100. Additionally, in one or more scenarios, the indication 118 is not received based on user input; rather, the indication 118 is received based on a different trigger.

[0044] In accordance with the described techniques, the contents 120 of the system memory 104 are transferred to the on-chip memory 108 via the chipset link 110. For example, the memory controller 114, based on or in response to receiving the indicator 118, causes the contents 120 of the system memory 104 to be transferred via the chipset link 110 to the on-chip memory 108.

[0045] Once the content 120 is transferred to the on-chipset memory 108, various operations are performed using the content 120 from the on-chipset memory 108. For example, the processing unit 112 uses the content 120 from the on-chipset memory 108 to execute (and / or continue to execute) one or more tasks of the operating system and / or applications. Such tasks are performed using the content 120 from the on-chipset memory 108 rather than using the content 120 from the system memory 104. While such operations are being performed using the content 120 from the on-chipset memory 108, physical adjustments to the system memory 104 may be made because the system memory 104 is not being used, e.g., power to the system memory 104 is gated or otherwise cut off. In one or more embodiments, one or more components of the system 100 perform one or more actions in addition to cutting power to the system memory 104 to enable safe physical modification of the system memory 104 and / or portions of the system memory. By disconnecting power to system memory 104 (and other components), system 100 allows system memory 104 to be safely physically handled (e.g., touched) so that one or more components (e.g., DIMMs, SODIMMs, or RDIMMs) can be added to system memory 104, one or more components can be removed from system memory 104, and / or one or more components of system memory 104 can be replaced.

[0046] Continuing to operate by performing memory-based tasks while system memory 104 is physically adjusted contrasts with conventional techniques, which do not continue to run an operating system or applications on a processing unit while system memory is physically adjusted, but rather power down the processing unit (and / or the entire system 100) so that system memory can be physically adjusted in a safe manner. By continuing to operate using on-chip memory 108, the described techniques allow memory-based tasks to continue to execute (thereby continuing to run the operating system, applications, etc.) during physical adjustments to system memory 104. As a result, "downtime" of system 100 is reduced and / or eliminated, thereby reducing interruptions to various tasks (e.g., background tasks) and improving the user experience.

[0047] After the physical adjustments to the system memory 104 are made, the content 120 is transferred from the on-chipset memory 108 back to the system memory 104 via the adjusted system memory 104. In one or more embodiments, before transferring the content 120 back to the system memory 104, the new physical configuration of the system memory (e.g., with new DIMMs) is trained and brought back online, and then the active content 120 in the on-chipset memory 108 is transferred back to the system memory 104. Once the content 120 has been transferred back to the system memory 104, various operations are performed using the content 120 from the adjusted system memory 104, rather than performing the operations using the content 120 from the on-chipset memory 108. For example, the processing unit 112 uses the content 120 from the system memory 104 to execute (and / or resume execution of) one or more tasks of the operating system and / or applications.

[0048] Thus, in one or more scenarios, the processing unit 112 operates using the content 120 from the system memory 104, for example, before the content 120 is transferred to the on-chip memory 108. The content 120 is then transferred from the system memory 104 to the on-chip memory 108 via the chipset link 110. The processing unit 112 then operates (or continues to operate) using the content 120 from the on-chip memory 108, for example, while the system memory 104 is being physically adjusted. The content 120 is transferred from the on-chip memory 108 to the system memory 104 via the chipset link 110, for example, after the physical adjustment to the system memory 104. The processing unit 112 then operates (or continues to operate) using the content 120 from the system memory 104.

[0049] In one or more embodiments, system 100 outputs one or more indicators when it is safe for a user to physically adjust system memory 104. For example, system 100 may output one or more visual or tactile indicators after content 120 has been transferred to on-chip memory 108 and system 100 continues to operate using content 120 from on-chip memory 108. By way of example and not limitation, system 100 may output a signal (e.g., flash, color change, strobe, on, off, etc.) via a light emitting diode (LED) on a component (e.g., near the processing unit package 102 or a socket for system memory 104), output one or more sounds (e.g., beep, chime, etc.) via a speaker, output a tactile signal (e.g., vibration) via one or more components, etc. Alternatively or additionally, a system or memory management application (not shown) running on processing unit 112 outputs a notification via a user interface indicating that it is safe for the user to physically adjust system memory 104, which is possible because system operation continues using content 120 from on-chip memory 108. In one or more embodiments, the notification may be output via one or more devices connected to system 100. For example, the notification may be communicated from system 100 to the device via a wireless connection. By way of example and not limitation, the notification may be communicated from system 100 to the device via a Bluetooth® connection, a Wi-Fi® connection, or over the Internet (e.g., as an email message). The device connected to the system may then output a notification, for example, via a user interface of an application associated with system 100. One or more of these various indicators notify the user that it is safe to physically adjust system memory 104, thereby reducing or eliminating potentially harmful consequences from manipulating system memory at the wrong time.

[0050] System 100 can be implemented in a device or apparatus. By way of example and not limitation, examples of different types of devices or apparatuses in which system 100 can be implemented include personal computers (e.g., desktop or tower computers), smartphones or other wireless phones, tablet or phablet computers, notebook computers, laptop computers, wearable devices (e.g., smart watches, augmented reality headsets or devices, virtual reality headsets or devices), entertainment devices (e.g., game consoles, portable gaming devices, streaming media players, digital video recorders, music or other audio playback devices, televisions, set-top boxes), Internet of Things (IoT) devices, automobile computers, etc.

[0051] 2 illustrates a non-limiting example 200 in which on-chip memory continues system operation during a physical adjustment of system memory. Example 200 includes system memory 104, memory controller 114, chipset link 110, on-chip memory controller 116, and on-chip memory 108.

[0052] Example 200 includes various exemplary communications and operations over time between system memory 104, memory controller 114, chipset link 110, on-chip memory controller 116, and on-chip memory 108. In this example 200, the communications and operations are arranged vertically based on time, with communications and operations closer to the top of the example occurring before communications or operations further from the top of the example. Also, communications or operations closer to the bottom of the example occurring after communications or operations further from the bottom. Example 200 also illustrates various phases and / or states of system 100 or portions of system 100. These phases and / or states are arranged vertically based on time in example 200, with phases or states closer to the top of the example occurring before phases, states, or communications further from the top.

[0053] Here, the illustrated example 200 shows system memory 104 receiving one or more access requests 202(a) (e.g., read requests and / or write requests) from memory controller 114. The illustrated example 200 also shows memory controller 114 receiving one or more serviced requests 204(a) from system memory 104. If access request 202(a) corresponds to a read request, for example, each serviced request 204(a) includes or otherwise indicates data for one or more memory addresses associated with access request 202(a). In contrast, if access request 202(a) corresponds to a write request, each serviced request 204(a) involves updating system memory 104 at one or more memory addresses associated with the write request to maintain one or more indicated values.

[0054] The transmission of access request 202(a) and its servicing by memory controller 114 and system memory 104 (e.g., as indicated by serviced request 204(a)) represents a first phase 206 of operation of the device (and / or system 100) using content 120 from system memory 104. The transmission of access request 202(b) between memory controller 114, on-chip memory controller 116, and on-chip memory 108 and its servicing (e.g., as indicated by serviced request 204(b)) represents a second phase 208 of operation of the device (and / or system 100) using content 120 from on-chip memory 108. The subsequent transmission of access request 202(c) and its servicing (e.g., as indicated by serviced request 204(c)) by memory controller 114 and system memory 104 represents a third phase 210 of operation of the device (and / or system 100) using content 120 from system memory 104.

[0055] In this example 200, memory controller 114 is shown receiving indicator 118 at some point during a first phase 206 of operation. It should be understood that in various scenarios, indicator 118 may be received interleaved with indicators of one or more transmitted access requests 202(a) and serviced requests 204(a). As discussed above, in one or more embodiments, indicator 118 is received based on user input, e.g., via a user interface, and indicates that a physical adjustment to system memory 104 is to be made.

[0056] In one or more embodiments, the memory controller 114 provides a transfer request 212 (e.g., one or more write requests) to the system memory 104, for example, to transfer the content 120 maintained by the system memory 104 to the on-chipset memory 108. In variations, the transferred content 120 ranges from a subset of the data maintained in the system memory 104 to the entirety of the data maintained in the system memory 104. In terms of data flow, the content 120 is transferred from the system memory 104 to the memory controller 114 (e.g., via one or more memory interfaces), which communicates the content 120 over the chipset link 110 to the on-chipset memory controller 116 (e.g., of the I / O expander 106), which communicates the content 120 (e.g., via one or more memory interfaces) to the on-chipset memory 108, where the content is stored. In one or more embodiments, the on-chip memory controller 116 stores the content 120 in the on-chip memory 108 using one or more write requests.

[0057] After the content is transferred, operation of the device (and / or system 100) uses the content 120 from the on-chipset memory 108. This example 200 illustrates an overlap 214 between when the on-chipset memory 108 includes the content 120, thereby enabling the system 100 to operate using the content in the on-chipset memory 108, and when the system 100 is still able to operate using the system memory 104. In one or more variations, one or more components of the system 100 are configured to test the on-chipset memory 108 during such an overlap, for example, to ensure that the on-chipset memory 108 can operate properly if the system memory 104 is powered down and / or taken offline. However, in at least one other variation, the on-chipset memory 108 is not tested before powering down and / or otherwise taking offline the system memory 104.

[0058] In the illustrated example 200, operability of the system memory 104 is indicated by black bars positioned perpendicular to the blocks of the system memory 104, while inoperability or a powered-down state is indicated by white bars positioned between the black bars and perpendicular to the blocks of the system memory 104. Similarly, operability of the on-chipset memory 108 is indicated by black bars positioned perpendicular to the blocks of the on-chipset memory 108 that are positioned on dashed lines extending from the blocks of the on-chipset memory 108.

[0059] During the second phase 208 of operation, the device (and / or system 100) operates using content 120 from on-chipset memory 108, for example, rather than using system memory 104. Thus, on-chipset memory 108 services read / write requests previously serviced by system memory 104 during the first phase 206 of operation. In other words, during the second phase 208, on-chipset memory 108 services one or more of the access requests 202(b), resulting in serviced requests 204(b) while system memory 104 is inoperable. In this example 200, subsequent access requests 202(b) are shown as being communicated from memory controller 114 to on-chipset memory controller 116 via chipset link 110 and then to on-chipset memory 108. By way of example, access request 202(b) may be initiated by processing unit 112, for example, to execute one or more tasks of an operating system and / or an application. Additionally, serviced request 204 ( b ) is shown as being provided from on-chipset memory 108 to on-chipset memory controller 116 and via chipset link 110 to memory controller 114 .

[0060] During a second phase 208 of operation, the device operates using content 120 from on-chipset memory 108, while system memory 104 is inoperable. As described throughout, during this period when system memory 104 is inoperable, one or more physical adjustments 216 may be made to system memory 104. In the illustrated example 200, physical adjustments 216 are shown to be made while system memory 104 is powered down or otherwise inoperable, as indicated, for example, by the white bar positioned vertically below the box for system memory 104. Examples of physical adjustments made to system memory 104 during this time interval are described in more detail above. In one or more embodiments, system memory 104 may be rendered inoperable for other reasons. For example, system memory 104 may be rendered inoperable due to a system failure or corruption. In these scenarios, content 120 may be transferred from system memory 104 to on-chipset memory 108 while a system-level reboot is performed.

[0061] After the physical adjustment, the content 120 is transferred from the on-chipset memory 108 back to the system memory 104 via the chipset link 110. In one or more embodiments, the system memory 104, once adjusted, is trained before the content 120 is transferred back to the system memory 104. In one or more embodiments, the on-chipset memory controller 116 receives an indication (not shown) that the system memory 104 is again operational and therefore able to service read / write requests. In at least one variation, such an indication instructs the on-chipset memory controller 116 to begin transferring the content 120 back to the adjusted system memory 104. In variations, the transferred content 120 ranges from a subset of the data held in the system memory 104 to the entirety of the data held in the system memory 104. In terms of data flow, content 120 is transferred from chipset on-chip memory 108 (e.g., via one or more memory interfaces) to chipset on-chip memory controller 116, which communicates content 120 over chipset link 110 to memory controller 114 (e.g., of processing unit package 102), which communicates content 120 (e.g., via one or more memory interfaces) to system memory 104, where content 120 is stored. In one or more embodiments, memory controller 114 stores content 120 in system memory 104 using one or more write requests.

[0062] After the content is transferred, operation of the device (and / or system 100) uses the content 120 from the system memory 104. This example 200 illustrates an overlap 218 between when the system memory 104 includes the content 120, thereby allowing the system 100 to operate using the content in the system memory 104, and when the system 100 is still able to operate using the on-chip memory 108. In one or more variations, one or more components of the system 100 are configured to test or train the system memory 104 during such an overlap, for example, to ensure that the system memory 104 will be able to operate properly when operation of the system reverts to using the system memory 104 instead of using the on-chip memory 108. However, in at least one other variation, the system memory 104 is not tested before switching operation back from the on-chip memory 108 to the system memory 104.

[0063] During the third phase 210 of operation, the device (and / or system 100) operates using content 120 from the physically coordinated system memory 104, for example, rather than using the on-chip memory 108. Thus, the coordinated system memory 104 services the read / write requests that were serviced by the on-chip memory 108 during the second phase 208 of operation. In other words, during the third phase 210, the system memory 104 again services one or more of the access requests 202(c), resulting in serviced requests 204(c).

[0064] FIG. 3 illustrates a procedure in an embodiment of an illustrative example 300 of physical adjustments to system memory with on-chip memory.

[0065] An indication (instruction) to make one or more physical adjustments to the device's system memory is received (block 302). By way of example, an indication 118 to make a physical adjustment to system memory 104 is received. In one or more embodiments, the indication 118 is received in response to user input provided via a user interface of a system or memory management application (not shown) being executed by processing unit 112, the input indicating that the user intends to physically adjust system memory 104.

[0066] The contents of the system memory are transferred to the on-chip memory via the chipset link (block 304). By way of example, the contents 120 of the system memory 104 are transferred to the on-chip memory 108 via the chipset link 110. For example, based on or in response to receiving the indicator 118, the memory controller 114 causes the contents 120 of the system memory 104 to be transferred to the on-chip memory 108 via the chipset link 110.

[0067] The device is operated using content from the on-chipset memory while one or more physical adjustments are made to adjust the system memory (block 306). By way of example, once the content 120 is transferred to the on-chipset memory 108, various operations are performed using the content 120 from the on-chipset memory 108. For example, the processing unit 112 executes (and / or continues to execute) one or more tasks of the operating system and / or applications using the content 120 from the on-chipset memory 108. Such tasks are performed using the content 120 from the on-chipset memory 108 rather than using the content 120 from the system memory 104. While such operations are performed using the content 120 from the on-chipset memory 108, physical adjustments to the system memory 104 may be made because the system memory 104 is not being used, e.g., power to the system memory 104 is gated or otherwise disconnected.

[0068] After one or more physical adjustments, the content is transferred from the on-chipset memory back to the adjusted system memory via the chipset link (block 308). By way of example, after physical adjustments are made to the system memory 104, the content 120 is transferred from the on-chipset memory 108 back to the system memory 104 via the adjusted system memory 104. Once the content 120 is transferred back to the system memory 104, various operations are performed using the content 120 from the adjusted system memory 104, rather than performing the operations using the content 120 from the on-chipset memory 108. For example, the processing unit 112 uses the content 120 from the system memory 104 to perform (and / or resume execution of) one or more tasks of the operating system and / or applications.

[0069] 4 is a diagram of another non-limiting exemplary system 400 employing on-chipset memory to continue system operation during physical adjustments to the system memory. Similar to system 100 of FIG. 1, system 400 includes processing unit package 102, system memory 104, I / O expander 106, on-chipset memory 108, and chipset link 110. System 400 also includes a network I / O controller 402 and chipset link 404, which enable processing unit package 102 to communicate with network I / O controller 402 using any of a variety of communication links similar to chipset link 110.

[0070] The processing unit package 102, system memory 104, I / O expander 106, on-chipset memory 108, chipset link 110, network I / O controller 402, and chipset link 404 may be located on or part of, for example, a motherboard or other printed circuit board. In one or more embodiments, the I / O expander 106 (including on-chipset memory controller 116), chipset link 110, chipset link 404, one or more memory channels between the processing unit package 102 and system memory 104, and one or more memory channels between the I / O expander 106 and on-chipset memory 108 are referred to as a chipset of the motherboard or other printed circuit board.

[0071] Processing unit package 102 includes processing unit 112 and memory controller 114. While a single processing unit 112 is shown in system 400, processing unit package 102 optionally includes any number of processing units of the same or different types and / or other types of components, such as artificial intelligence accelerators. Given this architecture, such other optional components access system memory 104 directly (e.g., via memory controller 114) or through an operating system running on processing unit 112. These components are configured to access on-chipset memory 108 (e.g., via I / O expander 106 or network I / O controller 402).

[0072] The network I / O controller 402 manages communications on the network, such as by sending data or control signals to one or more other devices over the network and receiving data or control signals from one or more other devices over the network. The network may be implemented in any of a variety of manners, such as an Ethernet network, an InfiniBand network, etc. The network I / O controller 402 is coupled to or is integrated with the on-chipset memory 108 via one or more memory channels. In one or more embodiments, the on-chipset memory 108 is an address space (e.g., PCIe address space) addressable by other server nodes and components of the system 400 (e.g., the processing unit 112). Thus, the network I / O controller 402, like the on-chipset memory controller 116, can send read and write requests to and receive responses from the on-chipset memory 108.

[0073] In one or more embodiments, the chipset on-chip memory 108 is mounted on or coupled to only either the network I / O controller 402 or the I / O expander 106, rather than being mounted on or coupled to both the network I / O controller 402 and the I / O expander 106.

[0074] The network I / O controller 402 mounted on or coupled to the on-chipset memory 108 supports a variety of different usage scenarios. In one or more embodiments, the processing unit package 102 can access the on-chipset memory 108 via the network I / O controller 402, allowing the on-chipset memory 108 to be used in situations where the on-chipset memory 108 is not mounted on or coupled to the I / O expander 106. Such situations may arise, for example, when board routing limitations prevent the on-chipset memory 108 from being mounted on or coupled to the I / O expander 106.

[0075] In one or more embodiments, the network I / O controller 402 enables the on-chipset memory 108 to be accessed by other devices over a network. This access is granted using any of a variety of public or proprietary remote direct memory access (RDMA) technologies. For example, assume that the system 400 is implemented in a server node connected to multiple other server nodes (e.g., some of which include their own on-chipset memory and, optionally, some of which do not). The other server nodes communicate read and write requests to the on-chipset memory 108 via the network I / O controller 402 and receive responses from the on-chipset memory 108 via the network I / O controller 402. Thus, the other server nodes can utilize the on-chipset memory 108 without interfering with the system memory 104 or even the processing unit package 102. For example, the processing unit package 102 does not need to have knowledge of the other server nodes accessing the on-chipset memory 108.

[0076] As another example, assume that system 400 is implemented in a server node connected to multiple other server nodes, at least one of which includes its own on-chipset memory. In at least one variation, processing unit 112 (or other components of processing unit package 102) can communicate read and write requests to the on-chipset memory of the other server nodes via network I / O controller 402, and receive responses from the on-chipset memory of the other server nodes via network I / O controller 402. Thus, processing unit 112 or other components of processing unit package 102 can utilize the on-chipset memory of another server node without interfering with system memory 104 or on-chipset memory 108.

[0077] 5 is a diagram of another non-limiting exemplary system 500 employing on-chipset memory to continue system operation while system memory is inoperable. System 500 may be, for example, a motherboard or other printed circuit board. System 500 includes an I / O expander 502 that includes a on-chipset memory controller 504 and a chipset link 506. System 500 also includes a processing unit package socket 508, system memory slots 510, and chipset-mounted memory slots 512. Processing unit package socket 508 is designed to have a processing unit package, such as processing unit package 102 of FIG. 1 or FIG. 4, installed or inserted therein. In one or more embodiments, the I / O expander 502 (including the chipset-mounted memory controller 504), the chipset link 506, the one or more memory channels between the processing unit package socket 508 and the system memory slots 510, and the one or more memory channels between the I / O expander 502 and the chipset-mounted memory slots 512 are referred to as a chipset of a motherboard or other printed circuit board. In one or more embodiments, physically adjusting the system memory 104 involves removing one or more memory components from one or more system memory slots 512 and / or inserting one or more memory components into one or more system memory slots 512.

[0078] I / O expander 502 is an I / O expander similar to I / O expander 106 in Figure 1 or 4. Chipset-mounted memory controller 504 is a chipset-mounted memory controller similar to chipset-mounted memory controller 116 in Figure 1 or 4. Chipset link 506 is similar to chipset link 110 in Figure 1 or 4.

[0079] System memory slots 510 include multiple (“x”) memory slots 510(1), 510(2), ..., 510(x). System memory slots 510 are designed to have system memory, such as system memory 104 of FIG. 1 or FIG. 4, installed or inserted therein. System memory slots 510 are, for example, DIMM or SO-DIMM slots. Although multiple memory slots 510(1), 510(2), ..., 510(x) are shown, system 500 optionally includes a single memory slot 510 or any other number of memory slots 510.

[0080] The chipset-mounted memory slots 512 include multiple (“y”) slots 512(1), 512(2), ..., 512(y). The chipset-mounted memory slots 512 are designed to have a chipset-mounted memory, such as the chipset-mounted memory 108 of FIG. 1 or 4 , installed or inserted therein. The chipset-mounted memory slots 512 are, for example, DIMM or SO-DIMM slots. While multiple memory slots 512(1), 512(2), ..., 512(y) are shown, the system 500 optionally includes a single memory slot 512 or any other number of memory slots 512. In one or more embodiments, the number of chipset-mounted memory slots 512 is equal to or greater than the number of system memory slots 510 of the system memory 104. In one or more embodiments, if the number of chipset-mounted memory slots 512 is less than the number of system memory slots 510, the system may determine that some of the contents of the system memory 104 do not need to be transferred to the chipset-mounted memory. In one or more embodiments, multiple on-chip memories are included in the system, in which case the contents of system memory 104 may be transferred to different ones of the multiple on-chip memories.

[0081] With a processing unit package installed or inserted into processing unit package socket 508, system memory installed or inserted into system memory slot 510, chipset-mounted memory installed or inserted into chipset-mounted memory slot 512, and additional I / O devices (e.g., chipset-mounted non-volatile memory and / or chipset-mounted disk drives) optionally installed or otherwise coupled to I / O expander 502, system 500 becomes system 100 of FIG. 1 or a system with a tiered memory option.

[0082] It should be understood that many variations are possible based on the disclosure herein, and although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0083] The various functional units shown in the figures and / or described herein (including, as appropriate, the processing unit package 102, system memory 104, on-chip memory 108, chipset link 110, processing unit 112, memory controller 114, and on-chip memory controller 116) may be implemented in any of a variety of different ways, such as hardware circuits, software or firmware running on a programmable processor, or any combination of two or more of hardware, software, and firmware. The provided methods may be performed in any of a variety of devices, such as a general-purpose computer, a processor, or a processor core. Suitable processors include, by way of example, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), a graphics processing unit (GPU), a parallel-accelerated processor, multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine.

[0084] In one or more embodiments, the methods and procedures provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. System memory; a memory controller configured to provide a transfer request to the system memory to cause content maintained by the system memory to be transferred from the system memory to an on-chip memory; a processing unit that performs one or more tasks using the content from the chipset on-board memory. Device.

2. a processing unit package including the processing unit and the memory controller; the system memory is coupled to the processing unit package; 10. The apparatus of claim 1.

3. a chipset link coupling the processing unit package to the chipset-mounted memory; the content is transferred from the system memory to the chipset on-chip memory via the chipset link; 3. The apparatus of claim 2.

4. the system memory is inoperable while the processing unit performs the one or more tasks using the contents from the on-chip memory; 10. The apparatus of claim 1.

5. power to the system memory is gated while the processing unit performs the one or more tasks using the contents from the on-chip memory; 5. The apparatus of claim 4.

6. gating the system memory to allow one or more physical adjustments to be made to the system memory while the processing unit is performing the one or more tasks using the contents from the on-chip memory; the one or more physical adjustments made to the system memory include one or more of: replacing a physical component of the system memory; removing a physical component of the physical memory; or substituting a physical component of the physical memory.

6. The apparatus of claim 5.

7. the physical components include dual in-line memory modules; 7. The apparatus of claim 6.

8. the memory controller is configured to provide an additional transfer request to the on-chip memory to transfer the content from the on-chip memory back to the system memory.

10. The apparatus of claim 1.

9. the memory controller is configured to provide the transfer request in response to receiving an indication that one or more physical adjustments will be made to the system memory.

10. The apparatus of claim 1.

10. receiving an indication to make one or more physical adjustments to a system memory of the device; transferring the contents of the system memory to a chipset on-chip memory via a chipset link; operating the device using the content from the on-chip memory while the one or more physical adjustments are being made to adjust the system memory; and transferring the content from the on-chip memory back to the adjusted system memory via the chipset link after the one or more physical adjustments. method.

11. disconnecting power to the system memory while the one or more physical adjustments are being made to adjust the system memory. The method of claim 10.

12. and operating the device using the content from the adjusted system memory after the content has been transferred back from the chipset on-board memory. The method of claim 10.

13. operating the device using the content from the system memory before the content is transferred to the on-chip memory; The method of claim 10.

14. the one or more physical adjustments include one or more of: replacing a physical component of the system memory; removing a physical component of the physical memory; or substituting a physical component of the physical memory. The method of claim 10.

15. the physical components include physical memory modules; 15. The method of claim 14.

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