Chip testing device and testing method

Abstract

The present invention provides a chip testing apparatus and a testing method, the testing apparatus including a processor for acquiring pin connection control information of a target chip, the pin connection control information being used to indicate a connection order between at least some pins of the target chip and a power supply module, and the processor for controlling the connection between the at least some pins and the power supply module based on the connection order. The testing apparatus and the testing method of the present invention can improve the efficiency of chip testing.

Description

[Technical Field]

[0001] The present application relates to the field of chip testing, and more particularly to a chip testing apparatus and method. [Background technology]

[0002] As chip complexity increases, the corresponding failure modes also increase, making chip testing technology particularly important. Current chip testing methods mainly rely on manual testing, which is not very smart and results in low test efficiency. Summary of the Invention

[0003] The present application provides a chip testing apparatus and method that can improve chip testing efficiency.

[0004] According to a first aspect, there is provided a chip testing apparatus including a processor used to acquire pin connection control information of a target chip, the pin connection control information being used to indicate a connection order between at least some pins of the target chip and a power supply module, and the processor being further used to control connections between the at least some pins and the power supply module based on the connection order.

[0005] In this embodiment, the processor obtains pin connection control information of the target chip, thereby controlling the connection order between at least some of the pins of the target chip and the power supply module, thereby realizing smart testing of the chip, and thereby improving the testing efficiency of the chip.

[0006] In a possible implementation, the power supply module includes a plurality of power supply units, and based on the connection order, the processor is specifically used to control the at least some of the pins to be respectively connected to the positive and negative poles of at least some of the power supply units in the plurality of power supply units based on the connection order.

[0007] In a possible implementation, the at least some power supply units include a first power supply unit and a second power supply unit, and the processor specifically controls, according to the connection order, to connect two pins of the at least some pins to the positive pole of the first power supply unit and the negative pole of the second power supply unit, respectively, so that the voltage between the two pins is U, where U is used to be the sum of the voltages of the multiple power supply units.

[0008] In this embodiment, at least two of the pins are controlled to be connected to the positive pole of the first power supply unit and the negative pole of the second power supply unit according to the connection order, so that the voltage between these two pins is the sum of the voltages of the power supply units corresponding to the target chip. This allows the target chip to be tested under the operating conditions most likely to be damaged, which is advantageous in preventing the release of defective chips.

[0009] In a possible implementation, the positive pole of the first power supply unit is the positive pole of the power supply module, and the negative pole of the second power supply unit is the negative pole of the power supply module.

[0010] In a possible implementation, the two pins include a power pin and a ground pin of the target chip.

[0011] In a possible implementation, the connection order includes connecting the two pins to the power supply module first.

[0012] In this embodiment, by controlling at least two of the pins of the target chip to be connected to the power supply module first, the voltage between the two pins becomes the sum of the voltages of the multiple power supply units corresponding to the target chip, which allows the target chip to be tested under the operating conditions that are most likely to damage it, and is advantageous in avoiding the release of abnormal chips.

[0013] In a possible implementation, the connection order further includes, after connecting the two pins to the power supply module, connecting pins other than the two pins among the at least some of the pins to the power supply module in a random order.

[0014] In a possible implementation, the connection order includes connecting the at least some of the pins to the power supply module in a random order.

[0015] In a possible implementation, the pin connection control information is further used to indicate a connection delay between two pins among the at least some of the pins that are sequentially connected to the power supply module, and the processor is specifically used to control the connection of the at least some of the pins to the power supply module based on the connection order and the connection delay.

[0016] In a possible implementation, the connection delay is a random value.

[0017] In a possible implementation, the test apparatus further includes a switch matrix, wherein pins of the target chip are connected to the power supply module via the switch matrix, and the pin connection control information is used to indicate the order in which switches of the switch matrix are turned on.

[0018] In this embodiment, the pins of the target chip are connected to the power supply module through a switch matrix, so that by obtaining the on-order of the switches of the switch matrix and sequentially turning on the switches in the switch matrix according to the on-order of the switches, it is possible to control at least some of the pins of the target chip to be connected to the power supply module, thereby improving the flexibility of testing the target chip.

[0019] In a possible implementation, the target chip includes a first target chip and a second target chip, the power supply module includes a first power supply sub-module and a second power supply sub-module, the switch matrix includes a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector, and a fourth connector, the first connector is connected to the first power supply sub-module, the second connector is connected to the second power supply sub-module, the third connector is connected to the first target chip, and the fourth connector is connected to the second target chip, the first connector and the third connector are connected via the plurality of first switches, and the second connector and the fourth connector are connected via the plurality of second switches, and the power supply pin and the ground pin of the first target chip are connected to the positive and negative poles of the first power supply sub-module, respectively, and the power supply pin and the ground pin of the second target chip are connected to the positive and negative poles of the second power supply sub-module, respectively.

[0020] In a possible implementation, the order in which the switches are turned on includes: two first switches among the plurality of first switches that are connected to the power pins and ground pins of the first target chip are turned on first; and then other first switches among the plurality of first switches are turned on randomly; and / or two second switches among the second switches that are connected to the power pins and ground pins of the second target chip are turned on first; and then other second switches among the plurality of second switches are turned on randomly.

[0021] In a possible implementation, the on-order of the switches includes the plurality of first switches being turned on randomly and / or the plurality of second switches being turned on randomly.

[0022] In a possible implementation, the target chip includes a first target chip or a second target chip, the power supply module includes a first power supply sub-module and a second power supply sub-module connected in series, the switch matrix includes a plurality of third switches, a first connector, a second connector and a third connector, the first connector is connected to the first power supply sub-module, the second connector is connected to the second power supply sub-module, the third connector is connected to the first target chip or the second target chip, and the first connector and the second connector are connected to the third connector via the plurality of third switches.

[0023] In a possible implementation, the order in which the switches are turned on includes: some of the third switches of the plurality of third switches connected to the first connector are turned on first; and some of the other third switches of the plurality of third switches connected to the second connector are turned on later; or some of the third switches of the plurality of third switches connected to the second connector are turned on first; and some of the other third switches of the plurality of third switches connected to the first connector are turned on later.

[0024] In a possible implementation, a power pin and a ground pin of the first target chip or the second target chip are respectively connected to the positive and negative poles of the power supply module, the part of the third switches includes a third switch connected to the power pin of the first target chip or the second target chip, and the other part of the third switches includes a third switch connected to the ground pin of the first target chip or the second target chip, and the order of turning on the switches is as follows: after the part of the third switches is turned on, the third switch connected to the ground pin of the first target chip or the second target chip among the other part of the third switches is turned on first, and then the other part of the third switches is turned on. or the part of the third switches includes a third switch connected to a ground pin of the first target chip or the second target chip, and the other part of the third switches includes a third switch connected to a power pin of the first target chip or the second target chip, and the order of turning on the switches includes that after the part of the third switches is turned on, the third switch connected to the power pin of the first target chip or the second target chip among the other part of the third switches is turned on first, and then the other part of the third switches is turned on randomly.

[0025] In a possible implementation, the target chip includes a first target chip and a second target chip, the switch matrix includes a plurality of fourth switches, a plurality of fifth switches, a first connector, and a second connector, the first connector is connected to the power supply module, the first target chip and the second target chip are both connected to the second connector, the first connector and the second connector are connected via the plurality of fourth switches and the plurality of fifth switches, the power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative poles of some power supply units of the power supply module, and the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative poles of other power supply units of the power supply module.

[0026] In a possible implementation, the order in which the switches are turned on includes first turning on a fourth switch among the plurality of fourth switches that is connected to a power pin of the first target chip and a fifth switch among the plurality of fifth switches that is connected to a ground pin of the second target chip, then turning on a fourth switch among the plurality of fourth switches that is connected to a ground pin of the first target chip and a fifth switch among the plurality of fifth switches that is connected to a power pin of the second target chip, and finally turning on another fourth switch among the plurality of fourth switches and another fifth switch among the plurality of fifth switches randomly.

[0027] In a possible implementation, the switch on sequence includes the plurality of fourth switches and the plurality of fifth switches being turned on randomly.

[0028] In a possible implementation, a power pin of the first target chip is connected to a ground pin of the second target chip.

[0029] In a possible implementation, the order in which the switches are turned on includes turning on the plurality of fourth switches first, then turning on a fifth switch among the plurality of fifth switches that is connected to a power pin of the second target chip, and finally turning on other fifth switches among the plurality of fifth switches randomly, or turning on the plurality of fifth switches first, then turning on a fourth switch among the plurality of fourth switches that is connected to a ground pin of the first target chip, and finally turning on other fourth switches among the plurality of fourth switches randomly.

[0030] In a possible implementation, the switch matrix includes a plurality of discharge units, each of which is arranged between two pins on the target chip, and the processor is further used to control the plurality of discharge units to discharge the peripheral circuits of the target chip before obtaining the pin connection control information of the target chip.

[0031] In a possible implementation, one discharge unit is provided between every two adjacent pins of the target chip.

[0032] In a possible implementation, one discharge unit is provided between each of all pins other than the ground pin of the target chip and the ground pin.

[0033] In a possible implementation, the discharge unit includes a discharge switch and a resistor connected in series with the discharge switch, and the processor is specifically used to control the discharge switch in each discharge unit among the plurality of discharge units to be turned on to discharge the peripheral circuits of the target chip.

[0034] Optionally, the test equipment may be used to perform hot-plug tests on the target chip.

[0035] In this embodiment, the switch matrix is ​​provided with multiple discharge units, which enable the peripheral circuits of the target chip to be discharged after each hot-plug test is completed, ensuring that the initial state of each hot-plug test is consistent. This avoids the problem that the target chip is already partially charged after the first hot-plug test, which weakens the stress of subsequent hot-plugs and makes the test meaningless. Furthermore, by adding the discharge units, each test of the target chip is closer to the actual situation, thereby improving the accuracy of the test.

[0036] In a possible implementation, the processor is specifically used for controlling the at least some pins to be connected to the power supply module multiple times according to a preset number of times based on the connection order.

[0037] In this embodiment, the test can be repeated multiple times under the same operating conditions to improve the reliability of the test.

[0038] Optionally, the preset number is 30 or more.

[0039] In a possible implementation, the processor is further used to perform functional verification on the target chip after controlling the connection of at least some of the pins to the power supply module multiple times according to the preset number of times based on the connection order.

[0040] Optionally, in the process of controlling the connection of at least some of the pins to the power supply module based on the connection order, the processor may further be used to determine whether the circuit function of the target chip is normal based on the report information of the target chip.

[0041] In a possible implementation, the target chip is an analog front-end AFE chip.

[0042] In this embodiment, performing a hot-plug test on the AFE chip at the AFE chip design end is advantageous to avoid the release of abnormal AFE chips, thereby reducing losses in terminal applications, accelerating terminal design and application, and promoting the healthy development of the new energy industry.

[0043] According to a second aspect, a method for testing a chip is provided, the method including: obtaining pin connection control information of a target chip, the pin connection control information being used to indicate a connection order between at least some pins of the target chip and a power supply module; and controlling a connection between the at least some pins and the power supply module based on the connection order.

[0044] In a possible implementation, the power supply module includes a plurality of power supply units, and controlling the connection of at least some of the pins to the power supply module based on the connection order includes controlling the connection of at least some of the pins to positive and negative poles of at least some of the power supply units, respectively, based on the connection order.

[0045] In a possible implementation, the at least some of the power supply units include a first power supply unit and a second power supply unit, and controlling the at least some of the pins to be connected to the positive and negative poles of at least some of the power supply units based on the connection order includes controlling two pins of the at least some of the pins to be connected to the positive pole of the first power supply unit and the negative pole of the second power supply unit, respectively, based on the connection order, such that a voltage between the two pins becomes U, where U is a sum of voltages of the multiple power supply units.

[0046] In a possible implementation, the positive pole of the first power supply unit is the positive pole of the power supply module, and the negative pole of the second power supply unit is the negative pole of the power supply module.

[0047] In a possible implementation, the two pins include a power pin and a ground pin of the target chip.

[0048] In a possible implementation, the connection order includes connecting the two pins to the power supply module first.

[0049] In a possible implementation, the connection order further includes, after connecting the two pins to the power supply module, connecting pins other than the two pins among the at least some of the pins to the power supply module in a random order.

[0050] In a possible implementation, the connection order includes connecting the at least some of the pins to the power supply module in a random order.

[0051] In a possible implementation, the pin connection control information is further used to indicate a connection delay between two pins among the at least some of the pins that are sequentially connected to the power supply module, and controlling the at least some of the pins to be connected to the power supply module based on the connection order includes controlling the at least some of the pins to be connected to the power supply module based on the connection order and the connection delay.

[0052] In a possible implementation, pins of the target chip are connected to the power supply module through the switch matrix, and the pin connection control information is used to direct the turn-on sequence of switches in the switch matrix.

[0053] In a possible implementation, the switch matrix includes a plurality of discharge units, each of which is arranged between two pins on the target chip, and the test method further includes controlling the plurality of discharge units to discharge the peripheral circuits of the target chip before acquiring pin connection control information of the target chip.

[0054] In a possible implementation, the discharge unit includes a discharge switch and a resistor connected in series to the discharge switch, and controlling the plurality of discharge units to discharge the peripheral circuits of the target chip includes controlling a discharge switch in each discharge unit among the plurality of discharge units to be turned on to discharge the peripheral circuits of the target chip.

[0055] In a possible implementation, controlling the connection of at least some of the pins to the power supply module based on the connection order includes controlling the connection of at least some of the pins to the power supply module multiple times according to a preset number of times based on the connection order.

[0056] In a possible implementation, the preset number is 30 or more.

[0057] In a possible implementation, the test method further includes performing functional verification on the target chip after controlling the connection of at least some of the pins to the power supply module multiple times according to the preset number of times based on the connection order.

[0058] In a possible implementation, the test method further includes determining whether the circuit function of the target chip is normal based on reported information of the target chip during the process of controlling the connection of at least some of the pins to the power supply module based on the connection order.

[0059] In a possible implementation, the target chip is an analog front-end AFE chip.

[0060] According to a third aspect, there is provided a chip including a processor for retrieving and executing a computer program from a memory to cause a device to which the chip is attached to perform the method of the second aspect and any possible embodiment of the second aspect.

[0061] According to a fourth aspect, there is provided a computer program, which when run on a computer, causes the method of the second aspect and any possible embodiment thereof to be carried out.

[0062] According to a fifth aspect, there is provided a computer readable storage medium, adapted to store a computer program, the computer program causing a computer to carry out the method of the second aspect and any possible embodiment of the second aspect.

[0063] According to a sixth aspect there is provided a computer program product, comprising computer program commands for causing a computer to carry out the method of the second aspect and any possible embodiment of the second aspect. [Brief explanation of the drawings]

[0064] In order to more clearly describe the technical solutions in the embodiments of the present application, the following briefly describes the drawings required for the embodiments of the present application. It should be understood that the drawings shown below are only some embodiments of the present application, and those skilled in the art can further obtain other drawings based on the drawings without any creative efforts.

[0065] [Figure 1] 1 is a schematic block diagram of a chip testing method according to an embodiment of the present application;

[0066] [Figure 2] 1 is a schematic diagram illustrating a connection relationship between a target chip and a power supply module according to an embodiment of the present application.

[0067] [Figure 3] 1 is a schematic connection diagram of a chip test system according to an embodiment of the present application;

[0068] [Figure 4] FIG. 2 is another schematic connection diagram of a chip test system according to an embodiment of the present application.

[0069] [Figure 5] FIG. 10 is yet another schematic connection diagram of a chip test system according to an embodiment of the present application.

[0070] [Figure 6] FIG. 10 is yet another schematic connection diagram of a chip test system according to an embodiment of the present application.

[0071] [Figure 7] 1 is a schematic block diagram of a chip test device according to an embodiment of the present application;

[0072] [Figure 8] FIG. 2 is another schematic block diagram of a chip testing device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0073] The embodiments of the present application will be described in more detail below with reference to the drawings and examples. The detailed description of the following examples and the drawings are used to exemplify the principles of the present application, but are not intended to limit the scope of the present application, and the present application is not limited to the described examples.

[0074] It should be explained that in the description of this application, unless otherwise stated, "plurality" means two or more, and further, terms such as "first," "second," "third," etc. are used for descriptive purposes only and should not be understood to denote or imply relative importance.

[0075] As chips become increasingly complex, the number of modules inside the chip increases, the manufacturing process becomes more and more advanced, and the corresponding failure modes increase. Therefore, how to fully and effectively test the entire test chip becomes an increasingly important consideration in the design stage. Current chip testing methods mainly rely on manual testing. For example, in the hot plug test of a chip, the connection and disconnection between the chip pins and the power supply module must be manually controlled, and various operating conditions of the chip must be simulated, which greatly wastes time and manpower and greatly reduces test efficiency.

[0076] In view of this, an embodiment of the present application provides a chip testing method, which obtains pin connection control information of a target chip, thereby controlling the connection order between at least some of the pins of the target chip and a power supply module, thereby realizing smart testing of the chip, and thereby improving chip testing efficiency.

[0077] 1 is a schematic block diagram of a chip testing method 100 according to an embodiment of the present application. Optionally, the method 100 may be performed by a test device, for example, the test device may include a host computer. As shown in FIG. 1, the method 100 may include some or all of the following:

[0078] In step 110, pin connection control information of the target chip is obtained, which is used to instruct the connection order between at least some pins of the target chip and the power supply module.

[0079] Step 120: Controlling the connection between at least some pins of the target chip and a power supply module based on the connection order.

[0080] Optionally, the method 100 may be a chip hot-plug test method. Hot-plugging, or hot swapping, refers to inserting or removing a chip into or from a system without powering off the system. Because hot-plugging a chip has a significant impact on the system, a hot-plug test is generally performed on the chip before shipping to prevent chips that do not meet hot-plug requirements from entering the market.

[0081] Alternatively, the hot-plug test method of the present embodiment may be applied to the field of a battery management system (BMS). For example, the hot-plug test method of the present embodiment may perform a hot-plug test on an analog front end (AFE) chip in a BMS. The AFE chip is a multi-sampling channel monitoring chip and can monitor the voltage and temperature of batteries connected in series. When the AFE chip is connected to a battery, the pin order is not fixed, so a voltage difference may exist between two pins, which may cause damage to the AFE chip. Therefore, a hot-plug test is required for the AFE chip, and only AFE chips that meet requirements can be released to the market after being verified through the hot-plug test.

[0082] Optionally, in an embodiment of the present application, the test equipment may acquire pin connection control information of a target chip (also referred to as a chip under test), which may be used to indicate the connection order between at least some of the pins of the target chip and the power supply module. For example, the pin connection control information may be used to indicate the connection order between all of the pins of the target chip and the power supply module. Furthermore, for example, the pin connection control information may be used to indicate the connection order between some of the power and ground pins of the target chip and the power supply module. When the pin connection control information is used to indicate the connection order between some of the pins of the target chip and the power supply module, the pin connection control information may also be used to indicate the random connection order between other pins of the target chip and the power supply module. Optionally, the connection order indicated by the pin connection control information may be one of multiple connection orders preset within the test equipment. For example, the target chip may include pins 1 to 3, and multiple connection orders may be preset according to various arrangement combinations of pins 1 to 3, as shown in Table 1. The pin connection control information may be used to indicate one of the 15 connection orders in Table 1. After the tester obtains the pin connection control information, the tester can control the connection of at least some pins of the target chip to the power supply module according to the connection order indicated by the pin connection control information. For example, if the pin connection control information is used to indicate connection order 10 in Table 1, the tester controls the pins of the target chip to be connected to the power supply module in the order of pin 1-pin 2-pin 3.

[0083] [Table 1]

[0084] Optionally, in the embodiment of the present application, the power supply module may be a real battery or a cell simulator. Optionally, the power supply module may include multiple power supply units connected in series, each power supply unit corresponding to one battery cell. There is a correspondence between the number of power supply units in the power supply module and the number of pins of the target chip.

[0085] In this embodiment, by obtaining the pin connection control information of the target chip, the connection order between at least some of the pins of the target chip and the power supply module can be controlled to realize smart testing of the chip, thereby improving the testing efficiency of the chip.

[0086] Optionally, in an embodiment of the present application, the power supply module includes a plurality of power supply units, and step 120, i.e., controlling to connect at least some pins of the target chip to the power supply module based on the connection order, includes controlling to connect the at least some pins to positive poles and negative poles of at least some of the power supply units among the plurality of power supply units, respectively, based on the connection order.

[0087] As described above, the power supply module may include multiple power supply units, which may be connected in series. A lead wire may be drawn from each of the positive and negative terminals of each power supply unit, and the leads drawn from the multiple power supply units may correspond to pins on the target chip. The tester's control of the connection between at least some pins on the target chip and the power supply module actually controls the connection between at least some pins on the target chip and at least some of the leads drawn from the multiple power supply units. For example, as shown in FIG. 2, the power supply module may include three power supply units connected in series, designated 1, 2, and 3, respectively. Six leads may be drawn from the power supply module, designated 11, 12, 13, 14, 15, and 16, respectively. The leads drawn from the positive and negative terminals of the power supply module, i.e., lead 11 and lead 16, correspond to the power pin 101 and ground pin 106 of the target chip 7, respectively. The other leads 12-15 of the power supply module correspond to the other pins 102-105 of the target chip 7, respectively. If the connection order indicated by the pin connection control information is power pin 101-ground pin 106-pin 102-pin 103-pin 104-pin 105, the test device can sequentially control the connection between power pin 101 and lead wire 11, the connection between ground pin 106 and lead wire 16, the connection between pin 102 and lead wire 12, the connection between pin 103 and lead wire 13, the connection between pin 104 and lead wire 14, and the connection between pin 105 and lead wire 15 based on the connection order.

[0088] Optionally, in an embodiment of the present application, the at least some of the power supply units include a first power supply unit and a second power supply unit, and controlling the at least some of the pins to be connected to the positive pole and the negative pole of at least some of the power supply units according to the connection order includes controlling two pins of the at least some of the pins to be connected to the positive pole of the first power supply unit and the negative pole of the second power supply unit according to the connection order, respectively, so that the voltage between the two pins becomes U, where U is the sum of the voltages of the multiple power supply units.

[0089] Specifically, as shown in FIG. 2, the power supply module includes power supply unit 1, power supply unit 2, and power supply unit 3, and power supply unit 1, power supply unit 2, and power supply unit 3 are connected in series, and lead wire 11 and lead wire 12 are connected to the positive pole of power supply unit 1, and lead wire 15 and lead wire 16 are connected to the negative pole of power supply unit 3. The test device controls the power pin 101 and ground pin 106 of the target chip 7 to be first connected to the positive pole of power supply unit 1 and the negative pole of power supply unit 3, that is, the target By controlling the connection of the power supply pin 101 of the chip 7 to the lead wire 11 and the connection of the ground pin 106 to the lead wire 16, the voltage between the power supply pin 101 and the ground pin 106 is set to the sum of the voltages of the power supply unit 1, the power supply unit 2 and the power supply unit 3, i.e., the voltage between the power supply pin 101 and the ground pin 106 is set to the sum of the voltages of the multiple power supply units corresponding to the target chip 7, thereby making the voltage between the power supply pin 101 and the ground pin 106 the maximum voltage among the voltages between any two pins of all the pins of the target chip 7.

[0090] Alternatively, two of the at least some pins may be any two pins on the target chip 7, that is, no matter which two pins on the target chip 7 have a voltage between them that is the maximum voltage among the voltages between any two pins of all pins on the target chip 7, the test equipment only needs to control these two pins of the target chip 7 to be inserted into the power supply module based on the connection order, and there is no limitation on whether other pins are connected to the power supply module.

[0091] In this embodiment, at least two of the pins are controlled to be connected to the positive pole of the first power supply unit and the negative pole of the second power supply unit according to the connection order, so that the voltage between these two pins is the sum of the voltages of the power supply units corresponding to the target chip. This allows the target chip to be tested under the operating conditions most likely to be damaged, which is advantageous in preventing the release of defective chips.

[0092] Optionally, in the embodiment of the present application, the positive pole of the first power supply unit is the positive pole of the power supply module, and the negative pole of the second power supply unit is the negative pole of the power supply module. For example, as shown in Fig. 2, the power supply module includes power supply unit 1, power supply unit 2, and power supply unit 3, and power supply unit 1, power supply unit 2, and power supply unit 3 are connected in series, the positive pole of power supply unit 1 is the positive pole of the power supply module, and the negative pole of power supply unit 3 is the negative pole of the power supply module. Based on the connection order, the test device controls two pins of at least some of the pins of the target chip 7 to be connected to the positive pole of power supply unit 1 and the negative pole of power supply unit 3, respectively, so that the voltage between the two pins is the voltage of the power supply module, i.e., the sum of the voltages of power supply unit 1, power supply unit 2, and power supply unit 3.

[0093] Optionally, in other embodiments of the present application, the power supply module may include power supply sub-modules 1 to N, each power supply sub-module including a plurality of serially connected power supply units, each power supply sub-module corresponding to one target chip, i.e., the power supply sub-modules 1 to N correspond to the target chips 1 to N, and the test device controls, based on the connection order, to connect two pins of at least some of the pins of any one of the target chips i (i is any one value from 1 to N) to the positive and negative poles of the power supply sub-module i, respectively, so that the voltage between the two pins of the target chip i can be the voltage of the power supply sub-module i.

[0094] Optionally, in an embodiment of the present application, the two pins include a power pin and a ground pin of the target chip, that is, the test device controls the power pin and the ground pin of the target chip to be connected to the positive pole of the first power supply unit and the negative pole of the second power supply unit respectively according to the connection order, so that the voltage between the power pin and the ground pin of the target chip is the sum of the voltages of the multiple power supply units corresponding to the target chip.

[0095] Optionally, in one embodiment of the present application, the connection order includes first connecting the two pins to the power supply module, in other words, the test apparatus controls two pins of at least some pins of the target chip to be first connected to the positive pole of the first power supply unit and the negative pole of the second power supply unit, so that the voltage between the two pins is the sum of the voltages of the multiple power supply units corresponding to the target chip.

[0096] For example, at least some of the pins of the target chip may include only the two pins, and the test apparatus can control the two pins to be connected to the power supply module, and then control the other pins of the target chip not to be connected to the power supply module.Further, for example, at least some of the pins of the target chip may include pins other than the two pins, and the test apparatus can control the two pins to be first connected to the power supply module, and then control the other pins of the at least some of the pins to be connected to the power supply module.

[0097] It should be understood that the embodiment of the present application does not limit the order in which the two pins are first connected to the power supply module.

[0098] In this embodiment, by controlling at least two of the pins of the target chip to be connected to the power supply module first, the voltage between the two pins becomes the sum of the voltages of the multiple power supply units corresponding to the target chip, so that the target chip can be tested under the operating conditions that are most likely to be damaged, which is advantageous in avoiding the release of abnormal chips.

[0099] Optionally, the connection order may further include first connecting the two pins to the power supply module, and then connecting pins other than the two pins among at least some of the pins of the target chip to the power supply module in a random order. That is, if at least some of the pins of the target chip include pins other than the two pins, the test apparatus can control the two pins to be connected to the power supply module first, and then control the other pins among the at least some of the pins to be connected to the power supply module in a random order. For example, as shown in FIG. 2, the at least some pins include pins 101-103 and 106, and the test apparatus can control the power pin 101 and ground pin 106 to be connected to the power supply module first, and then control the pins 102 and 103 to be connected to the power supply module in a random order. For example, the random order may be connecting pin 102 to the power supply module first, and then connecting pin 103 to the power supply module. Further, for example, the random order may be to first connect pin 103 to the power supply module, and then connect pin 102 to the power supply module. In the present embodiment, the random order means that the connection order of any two consecutive tests may be different.

[0100] Optionally, in another embodiment of the present application, the connection order may include connecting at least some pins of the target chip to the power supply module in a random order. For example, as shown in FIG. 2, the at least some pins may include pins 101-103 and 106, and the test device may control pins 101-103 and 106 to be connected to the power supply module in a random order. For example, the random order may be pin 101-pin 102-pin 103-pin 106. For example, the random order may be pin 101-pin 106-pin 102-pin 103. For example, the random order may be pin 106-pin 102-pin 101-pin 103. In this embodiment, the random order may mean that the connection order between any two consecutive tests may be different.

[0101] Optionally, in an embodiment of the present application, if the pin connection control information is further used to indicate a connection delay between two pins among the at least some of the pins that are sequentially connected to a power supply module, step 120, i.e., controlling the connection of the at least some of the pins to the power supply module based on the connection order, includes controlling the connection of the at least some of the pins to the power supply module based on the connection order and the connection delay.

[0102] Optionally, the connection delay, like the connection order, may be preset within the tester. For example, multiple connection delays may be preset within the tester, and the pin connection control information may indicate at least one of the multiple connection delays. For example, six connection delays, 500 ms, 600 ms, 700 ms, 800 ms, 900 ms, and 1 s, may be preset within the tester. Optionally, the pin connection control information may indicate only one of the six connection delays. That is, the delay between any two consecutive pins on the target chip that are connected to the power supply module is the same. For example, if the pin connection control information indicates a connection delay of 500 ms, the delay between any two consecutive pins on the target chip that are connected to the power supply module is also 500 ms. That is, the tester controls the connection of one pin of the target chip to the power supply module every 500 ms. Optionally, the pin connection control information indicates multiple connection delays among the six connection delays. 2, the test device controls pins 101 to 103 and 106 to be connected to the power supply module in the following connection order: pin 101-pin 106-pin 102-pin 103. The pin connection control information is used to specify three connection delays: 500 ms, 800 ms, and 1 s. The pin connection control information is further used to specify that the connection delay between pin 102 and pin 106 is 500 ms, the connection delay between pin 106 and pin 102 is 800 ms, and the connection delay between pin 102 and pin 103 is 1 s. That is, the test device controls pin 101 to be connected to the power supply module, then controls pin 106 to be connected to the power supply module after an interval of 500 ms, then controls pin 102 to be connected to the power supply module after an interval of 800 ms, and finally controls pin 103 to be connected to the power supply module after an interval of 1 s.

[0103] Optionally, in the embodiment of the present application, the connection delay may be a random value. For example, the connection delay may be a random value between 500 ms and 1 s. The connection delay being a random value means that the connection delay between any two consecutive connections of the target chip to the power supply module is a random value determined by the test device and is not a preset value.

[0104] Optionally, in an embodiment of the present application, the pins of the target chip are connected to the power supply module through a switch matrix, and the pin connection control information is used to indicate the turn-on sequence of the switches in the switch matrix.

[0105] In this embodiment, the pins of the target chip are connected to the power supply module through a switch matrix, so that by obtaining the on-order of the switches of the switch matrix and sequentially turning on the switches in the switch matrix according to the on-order of the switches, it is possible to control at least some of the pins of the target chip to be connected to the power supply module, thereby improving the flexibility of testing the target chip.

[0106] Alternatively, the switch matrix may be relays or semiconductor switches or the like.

[0107] The chip testing method of the embodiment of the present application will be described in detail below with reference to FIGS. 3 to 6. Specifically, in FIGS. 3 to 6, the target chip is an AFE chip, and two AFE chips form one cell monitor unit (CMU). The test object is one CMU, that is, the method can be used to perform a hot-plug test on the CMU. In addition to the test device and the test object, the test system may further include a power supply module. The test device may include a switch matrix, which may include switches and connectors. Turning on and off the switches in the switch matrix is ​​equivalent to inserting or removing the connector. Optionally, in FIGS. 3 to 6, the control function of the test device may be realized by a host computer. The power supply module may use an actual battery or may be a cell simulator. Optionally, the number of AFE chips included in one CMU may vary, and the number of battery cells included in the power supply module may also vary in actual application.

[0108] Optionally, in a first embodiment, the target chip includes a first target chip and a second target chip, the power supply module includes a first power supply sub-module and a second power supply sub-module, the switch matrix includes a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector, and a fourth connector, the first connector is connected to the first power supply sub-module, the second connector is connected to the second power supply sub-module, the third connector is connected to the first target chip, and the fourth connector is connected to the second target chip, the first connector and the third connector are connected via the plurality of first switches, and the second connector and the fourth connector are connected via the plurality of second switches, and the power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative poles of the first power supply sub-module, and the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative poles of the second power supply sub-module.

[0109] Optionally, in one implementation, the order in which the switches are turned on may include: first turning on two first switches among the plurality of first switches that are connected to the power pins and ground pins of the first target chip; and then randomly turning on other first switches among the plurality of first switches; and / or first turning on two second switches among the second switches that are connected to the power pins and ground pins of the second target chip; and then randomly turning on other second switches among the plurality of second switches.

[0110] Optionally, in another implementation, the plurality of first switches are turned on randomly and / or the plurality of second switches are turned on randomly.

[0111] 3, the target chip includes a first AFE chip 210 and a second AFE chip 220, which form a CMU 200. The power supply module 300 includes a first power supply sub-module 310 and a second power supply sub-module 320. The switch matrix 400 includes a first switch group 410 and a second switch group 420, where the first switch group 410 includes K1 to Km, and the second switch group 420 includes Km+1 to K2m. The switch matrix 400 further includes a first connector 411 for connecting the first power supply sub-module 310, a second connector 412 for connecting the second power supply sub-module 320, a third connector 413 for connecting the first AFE chip 210, and a fourth connector 414 for connecting the second AFE chip 220. The first connector 411 and the third connector 413 are connected via a first switch group 410, and the second connector 412 and the fourth connector 414 are connected via a second switch group.

[0112] 3 , the number of battery cells in the first power supply sub-module 310 matches the number of sampling channels in the first AFE chip 210, and the sampling lead wires of the first power supply sub-module 310 all converge to the first connector 411, and all sampling channel wires of the first AFE chip 210 all converge to the third connector 413. The number of battery cells in the second power supply sub-module 320 matches the number of sampling channels in the second AFE chip 220, and the sampling lead wires of the second power supply sub-module 320 all converge to the second connector 412, and all sampling channel wires of the second AFE chip 220 all converge to the fourth connector 414. The positive electrode of the first power supply sub-module 310 is connected to the power pin (power) of the first AFE chip 210 via Km, the negative electrode of the first power supply sub-module 320 is connected to the ground pin (GND) of the first AFE chip 210 via K1, the positive electrode of the second power supply sub-module 320 is connected to the power pin (Power) of the second AFE chip 220 via K2m, and the negative electrode of the second power supply sub-module 320 is connected to the ground pin (GND) of the second AFE chip 220 via Km+1.

[0113] Operating condition 1 (worst operating condition of the first AFE chip 210 and / or the second AFE chip 220): K1 and Km are turned on first (K1 may be turned on first and then Km, or Km may be turned on first and then K1), then the other switches K2 to Km-1 of the first switch group 410 are turned on randomly, and / or Km+1 and K2m are turned on first (Km+1 may be turned on first and then K2m, or K2m may be turned on first and then Km+1), then the other switches Km+2 to K2m-1 of the second switch group 420 are turned on randomly. Turning on randomly includes random turn-on order and random time delay.

[0114] Operating condition 2 (the closest situation to the actual one of the first AFE chip 210 and / or the second AFE chip 220): K1 to Km are randomly turned on, and / or Km+1 to K2m are randomly turned on. Turning on randomly includes randomly turning on the order and randomly delaying the order.

[0115] Optionally, in a second embodiment, the target chip includes a first target chip or a second target chip, the power supply module includes a first power supply sub-module and a second power supply sub-module connected in series, the switch matrix includes a plurality of third switches, a first connector, a second connector and a third connector, the first connector is connected to the first power supply sub-module, the second connector is connected to the second power supply sub-module, the third connector is connected to the first target chip or the second target chip, and the first connector and the second connector are connected to the third connector via the plurality of third switches.

[0116] Optionally, the order in which the switches are turned on includes that some of the third switches connected to the first connector among the plurality of third switches are turned on first, and some of the other third switches connected to the second connector among the plurality of third switches are turned on later, or that some of the third switches connected to the second connector among the plurality of third switches are turned on first, and some of the other third switches connected to the first connector among the plurality of third switches are turned on later.

[0117] Further optionally, a power pin and a ground pin of the first target chip or the second target chip are respectively connected to a positive electrode and a negative electrode of the power supply module, the part of the third switches includes a third switch connected to a power pin of the first target chip or the second target chip, and the other part of the third switches includes a third switch connected to a ground pin of the first target chip or the second target chip, and the order of turning on the switches is such that after the part of the third switches is turned on, the third switch connected to the ground pin of the first target chip or the second target chip among the other part of the third switches is turned on first, and then the other part of the third switches is turned on. Other third switches of the three switches are turned on randomly, or the some of the third switches include a third switch connected to a ground pin of the first target chip or the second target chip, and the other some of the third switches include a third switch connected to a power pin of the first target chip or the second target chip, and the order in which the switches are turned on includes that after the some of the third switches are turned on, the third switch of the other some of the third switches connected to the power pin of the first target chip or the second target chip is turned on first, and then the other third switches of the other some of the third switches are turned on randomly.

[0118] 4, the target chip includes a first AFE chip 210 and a second AFE chip 220, which form a CMU 200. The power supply module 300 includes a first power supply sub-module 310 and a second power supply sub-module 320. The switch matrix 400 includes a third switch group 430, which includes K1 to K2m. The switch matrix 400 further includes a first connector 411 for connecting the first power supply sub-module 310, a second connector 412 for connecting the second power supply sub-module 320, and a third connector 413 for connecting the first AFE chip 210 or the second AFE chip 220. The power pin of the first AFE chip 210 is connected to the positive electrode of the power supply module 300 via K2m, and the ground pin of the first AFE chip 210 is connected to the negative electrode of the power supply module 300 via K1. Alternatively, the power pin of the second AFE chip 220 is connected to the positive terminal of the power supply module 300 via K2m, and the ground pin of the second AFE chip 220 is connected to the negative terminal of the power supply module 300 via K1.

[0119] As shown in FIG. 4 , the sum of the number of battery cells in the first power supply sub-module 310 and the second power supply sub-module 320 is equal to the number of sampling channels in the first AFE chip 210 or the second AFE chip, and all the sampling lead wires of the first power supply sub-module 310 are concentrated in the first connector 411, all the sampling lead wires of the second power supply sub-module 320 are concentrated in the second connector 412, and all the sampling channel wires of the first AFE chip 210 or the second AFE chip 220 are concentrated in the third connector 413.

[0120] Operating condition 3: K1 to Km are turned on first, and Km+1 to K2m are turned on after a certain delay. During the turn-on process of Km+1 to K2m, K2m is turned on first, and then Km+1 to K2m-1 are turned on randomly. "Randomly turned on" includes both random turn-on order and random time delay.

[0121] Operating condition 4: Km+1 to K2m are turned on first, and then K1 to Km are turned on after a certain delay. During the turn-on process of K1 to Km, K1 is turned on first, and then K2 to Km are turned on randomly. "Randomly turned on" includes the random order of turning on and the random time delay.

[0122] Optionally, in a third embodiment, the target chip includes a first target chip and a second target chip, the switch matrix includes a plurality of fourth switches, a plurality of fifth switches, a first connector, and a second connector, the first connector is connected to the power supply module, the first target chip and the second target chip are both connected to the second connector, the first connector and the second connector are connected via the plurality of fourth switches and the plurality of fifth switches, the power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative poles of some power supply units of the power supply module, and the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative poles of other power supply units of the power supply module.

[0123] Optionally, in one implementation, the order of turning on the switches includes first turning on a fourth switch among the plurality of fourth switches that is connected to a power pin of the first target chip and a fifth switch among the plurality of fifth switches that is connected to a ground pin of the second target chip, then turning on a fourth switch among the plurality of fourth switches that is connected to a ground pin of the first target chip and a fifth switch among the plurality of fifth switches that is connected to a power pin of the second target chip, and finally randomly turning on another fourth switch among the plurality of fourth switches and another fifth switch among the plurality of fifth switches.

[0124] Optionally, in another implementation, the switch on sequence includes the plurality of fourth switches and the plurality of fifth switches being turned on randomly.

[0125] 5, the target chip includes a first AFE chip 210 and a second AFE chip 220, and the first AFE chip 210 and the second AFE chip 220 form a CMU 200. The power supply module 300 includes a first power supply sub-module 310, and the switch matrix 400 includes a fourth switch group 440 and a fifth switch group 450, where the fourth switch group 440 includes switches K1 to Km, and the fifth switch group 450 includes switches Km+1 to K2m. The switch matrix 400 further includes a first connector 411 for connecting the first power supply sub-module 310 and a second connector 412 for connecting the first AFE chip 210 and the second AFE chip 220. The power pin of the first AFE chip 210 is connected to the positive electrode of the battery cells connected in series in the first part of the first power supply submodule 310 via Km, the ground pin of the first AFE chip 210 is connected to the negative electrode of the battery cells connected in series in the first part of the first power supply submodule 310 via K1, the power pin of the second AFE chip 210 is connected to the positive electrode of the battery cells connected in series in the second part of the first power supply submodule 310 via K2m, and the ground pin of the second AFE chip 220 is connected to the negative electrode of the battery cells connected in series in the second part of the first power supply submodule 310 via Km+1. The positive electrode of the battery cells connected in series in the first part is connected to the negative electrode of the battery cells connected in series in the second part.

[0126] As shown in FIG. 5 , the number of battery cells in the battery cells connected in series in the first part is the same as the number of sampling channels of the first AFE chip 210, and the sampling lead wires of the first power supply sub-module 310 are all converged to the first connector 411, and all sampling channel wires of the first AFE chip 210 and the second AFE chip 220 are all converged to the second connector 412.

[0127] Operating condition 5: Km and Km+1 are turned on first, K1 and K2m are turned on after a delay, and the remaining switches are turned on randomly. Turning on randomly includes randomly turning on the order and randomly delaying the time.

[0128] Operating condition 6: All of the K1 to K2m switches are turned on randomly. Turning on randomly includes randomly turning on the switches in a random order and randomly delaying them.

[0129] Optionally, in a fourth embodiment, the target chip includes a first target chip and a second target chip, the switch matrix includes a plurality of fourth switches, a plurality of fifth switches, a first connector, and a second connector, the first connector is connected to the power supply module, the first target chip and the second target chip are both connected to the second connector, the first connector and the second connector are connected via the plurality of fourth switches and the plurality of fifth switches, the power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative poles of some power supply units of the power supply module, the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative poles of other power supply units of the power supply module, and the power supply pin of the first target chip is connected to the ground pin of the second target chip.

[0130] In the embodiment, optionally, the order in which the switches are turned on includes turning on the plurality of fourth switches first, then turning on a fifth switch among the plurality of fifth switches that is connected to a power pin of the second target chip, and finally turning on other fifth switches among the plurality of fifth switches randomly, or turning on the plurality of fifth switches first, then turning on a fourth switch among the plurality of fourth switches that is connected to a ground pin of the first target chip, and finally turning on other fourth switches among the plurality of fourth switches randomly.

[0131] 6, the target chip includes a first AFE chip 210 and a second AFE chip 220, and the first AFE chip 210 and the second AFE chip 220 form a CMU 200. The power supply module 300 includes a first power supply sub-module 310, and the switch matrix 400 includes a fourth switch group 440 and a fifth switch group 450, where the fourth switch group 440 includes switches K1 to Km, and the fifth switch group 450 includes switches Km+1 to K2m. The switch matrix 400 further includes a first connector 411 for connecting the first power supply sub-module 310 and a second connector 412 for connecting the first AFE chip 210 and the second AFE chip 220. The power pin of the first AFE chip 210 is connected to the positive electrode of the battery cells connected in series to the first portion of the first power supply submodule 310 via Km, the ground pin of the first AFE chip 210 is connected to the negative electrode of the battery cells connected in series to the first portion of the first power supply submodule 310 via K1, the power pin of the second AFE chip 210 is connected to the positive electrode of the battery cells connected in series to the second portion of the first power supply submodule 310 via K2m, and the ground pin of the second AFE chip 220 is connected to the negative electrode of the battery cells connected in series to the second portion of the first power supply submodule 310 via Km+1. The positive electrode of the battery cells connected in series to the first portion is connected to the negative electrode of the battery cells connected in series to the second portion. The power pin of the first AFE chip 210 is connected to the ground pin of the second AFE chip 220.

[0132] As shown in FIG. 6 , the number of battery cells in the battery cells connected in series in the first part is the same as the number of sampling channels of the first AFE chip 210, and the sampling lead wires of the first power supply sub-module 310 are all converged to the first connector 411, and all sampling channel wires of the first AFE chip 210 and the second AFE chip 220 are all converged to the second connector 412.

[0133] Operating condition 7: Km+1 to K2m are turned on preferentially, then K1 is turned on with a delay, and finally K2 to Km are turned on randomly.

[0134] Operating condition 8: K1 to Km are turned on preferentially, then K2m is turned on with a delay, and finally Km+1 to K2m-1 are turned on randomly.

[0135] Optionally, in an embodiment of the present application, the switch matrix includes a plurality of discharge units, each of which is respectively arranged between two pins on the target chip, and the processor is further used to control the plurality of discharge units to discharge the peripheral circuits of the target chip before obtaining the pin connection control information of the target chip.

[0136] In one embodiment, one discharge unit is provided between every two adjacent pins of the target chip.

[0137] In another embodiment, one discharge unit is provided between each of all pins other than the ground pin of the target tip and the ground pin.

[0138] Further optionally, the discharge unit includes a discharge switch and a resistor connected in series with the discharge switch, and controlling the plurality of discharge units to discharge the peripheral circuits of the target chip includes controlling the discharge switch in each discharge unit among the plurality of discharge units to be turned on, thereby discharging the peripheral circuits of the target chip.

[0139] For example, as shown in Figures 3 to 6, the switch matrix 400 further includes a plurality of discharge units 460, each of which is arranged between two pins of the AFE chip. Each discharge unit 460 includes one discharge switch 461 and one discharge resistor 462, and the discharge switch 461 and the discharge resistor 462 are connected in series. After each hot plug simulation power-down, the discharge switches 461 in all the discharge units 460 are turned on to discharge the peripheral circuits of the first AFE chip 210 and / or the second AFE chip 220, thereby restoring the first AFE chip 210 and / or the second AFE chip 220 to their initial states.

[0140] In this embodiment, the switch matrix is ​​provided with multiple discharge units, which enable the peripheral circuits of the target chip to be discharged after each hot-plug test is completed, ensuring that the initial state of each hot-plug test is consistent. This avoids the problem that the target chip is already partially charged after the first hot-plug test, which weakens the stress of subsequent hot-plugs and makes the test meaningless. Furthermore, by adding the discharge units, each test of the target chip is closer to the actual situation, thereby improving the accuracy of the test.

[0141] Optionally, in other embodiments, one discharge unit may be provided between each pin and the ground pin in the AFE chips of FIGS.

[0142] In the present embodiment, the target chip is an AFE chip, as described above.

[0143] In this embodiment, performing a hot-plug test on the AFE chip at the AFE chip design end is advantageous to avoid the release of abnormal AFE chips, thereby reducing losses in terminal applications, accelerating terminal design and application, and promoting the healthy development of the new energy industry.

[0144] Optionally, in an embodiment of the present application, step 220, i.e., controlling the connection of at least some of the pins to the power supply module based on the connection order, includes controlling the connection of at least some of the pins to the power supply module multiple times according to a preset number of times based on the connection order.

[0145] Specifically, the process of the test device connecting the pins of the target chip to the power supply module according to a connection sequence and then disconnecting all pins of the target chip from the power supply module can be considered as one test of the target chip. The test device can perform multiple tests on the target chip according to the same or different connection sequences. For example, the preset number of times is 30 or more.

[0146] 3 as an example, under operating condition 1, the switch matrix is ​​controlled 30 times in the following order: first, turn on K1 and Km, and then randomly turn on the other switches. Optionally, among these 30 times, K1 and Km are turned on first in each turn-on order, but the turn-on orders of the other switches may be the same or different. Optionally, the switch matrix may be controlled 30 times in the same turn-on order each time the turn-on order is changed until all turn-on orders are obtained.

[0147] In this embodiment, the test can be repeated multiple times under the same operating conditions to improve the reliability of the test.

[0148] Optionally, in an embodiment of the present application, the method further includes performing functional verification on the target chip after controlling the at least some of the pins to be connected to the power supply module multiple times according to the preset number of times based on the connection order.

[0149] For example, after completing the CMU test using the test system of Figures 3 to 6, the CMU's power supply voltage range can be verified. The verification of the power supply voltage range can include the following steps: Place the CMU in an incubator, then adjust the incubator temperature to reach a specified temperature. Apply power to the CMU, adjust the voltage of each cell to a specified value, and check whether the CMU functions in accordance with the specified requirements. After the CMU temperature stabilizes, maintain the specified operating time under the same conditions. During the operation, monitor in real time whether the CMU's operating status complies with the specified requirements. The number of CMU chips is six, the operating time is 24 hours, and the combinations of environmental temperature and power supply voltage are as shown in Table 2.

[0150] [Table 2]

[0151] where N is the number of configurable sampling channels of the AFE chip, and N_min is the minimum number of configurable sampling channels of the AFE chip.

[0152] In this embodiment, after the target chip is tested, functional verification is further performed on the target chip, and only if the functional status level meets certain requirements can the target chip be released into market applications, thereby reducing losses in application terminals.

[0153] Optionally, in an embodiment of the present application, the method further includes, in the process of controlling the connection of at least some of the pins to the power supply module based on the connection order, determining whether the circuit function of the target chip is normal based on the report information of the target chip.

[0154] That is, the test device may have two functions: a function to control the connection of the pins of the target chip to the power supply module based on the acquired pin connection control information, and a function to receive report information from the target chip and determine whether the circuit function of the target chip is normal based on the report information. For example, the host computer reads information from the CMU and determines whether the circuit function is normal after the CMU is hot-plugged.

[0155] The hot-plug test method for a CMU including an AFE chip according to an embodiment of the present application is described in detail below. Specifically, the CMU undergoes a hot-plug test according to the following test method. Test requirements: There are six CMUs, and the AFE chip has N sampling channels (i.e., N configured strings). (a) After the CMU undergoes power supply voltage range verification, all functions and parameters of the DUT meet the design specification requirements, and the battery cell voltage is 4.25V. This is determined through consultation between the manufacturer and the application side, and any discrepancies must be explained in the test report. The number of hot-plug cycles is 30 or more. The hot-plug operating conditions can be any of the above operating conditions 1 to 8, depending on the connection relationship between the power supply module and the CMU. The test steps are as follows: (a) A simulation test bench is constructed for the CMU according to the requirements of the hot-plug test bench. (b) Power is applied to the CMU, the individual cell voltage is adjusted to a specified value, and the CMU's functions are checked to see if they meet the specified requirements. (c) The CMU is turned off and any residual charge is discharged. (d) Simulate the hot-plug situation and corresponding operating conditions, connect to the corresponding battery channels in order, and after connecting to all channels, check whether the CMU functions normally. (e) Repeat steps c to d to complete the number of hot-plug tests required under the operating conditions. (f) Repeat steps c to e to complete the test requirements for the remaining hot-plug operating conditions.

[0156] The above describes in detail the chip testing method of the present application, and below we will describe in detail the chip testing device of the present application with reference to Figures 7 and 8, and the technical features described in the method embodiment are applied to the following device embodiment.

[0157] 7 is a schematic block diagram of a chip testing device 500 according to an embodiment of the present application. As shown in FIG. 7, the testing device 500 includes some or all of the following:

[0158] The processor 510 is used to obtain pin connection control information of a target chip, the pin connection control information is used to indicate a connection order between at least some pins of the target chip and a power supply module, and the processor 510 is further used to control the connection between the at least some pins and the power supply module based on the connection order.

[0159] Optionally, in an embodiment of the present application, the power supply module includes a plurality of power supply units, and the processor 510 is specifically used for controlling the at least some pins to be respectively connected to the positive poles and negative poles of at least some of the power supply units in the plurality of power supply units based on the connection order.

[0160] Optionally, in an embodiment of the present application, the at least some power supply units include a first power supply unit and a second power supply unit, and the processor 510 specifically controls, according to the connection order, to connect two pins of the at least some pins to the positive pole of the first power supply unit and the negative pole of the second power supply unit, respectively, so that the voltage between the two pins is U, where U is used to represent the sum of the voltages of the multiple power supply units.

[0161] Optionally, in the embodiment of the present application, the positive pole of the first power supply unit is the positive pole of the power supply module, and the negative pole of the second power supply unit is the negative pole of the power supply module.

[0162] Optionally, in the present embodiment, the two pins include a power pin and a ground pin of the target chip.

[0163] Optionally, in the embodiment of the present application, the connection sequence includes first connecting the two pins to the power supply module, respectively.

[0164] Optionally, in an embodiment of the present application, the connection order further includes, after connecting the two pins to the power supply module, connecting pins other than the two pins among the at least some of the pins to the power supply module in a random order.

[0165] Optionally, in an embodiment of the present application, the connection order includes the at least some pins being connected to the power supply module in a random order.

[0166] Optionally, in an embodiment of the present application, if the pin connection control information is further used to indicate a connection delay between two pins among the at least some of the pins that are sequentially connected to the power supply module, the processor 510 is specifically used to control the connection of the at least some of the pins to the power supply module based on the connection order and the connection delay.

[0167] Optionally, in the present embodiment, the connection delay is a random value.

[0168] Optionally, as shown in FIG. 8, the test apparatus 500 further includes a switch matrix 520, in which pins of the target chip are connected to the power supply module through the switch matrix 520, and the pin connection control information is used to indicate the turn-on order of the switches of the switch matrix 520.

[0169] Optionally, in an embodiment of the present application, the power supply module includes a first power supply sub-module and a second power supply sub-module, the target chip includes a first target chip and a second target chip, the switch matrix 520 includes a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector, and a fourth connector, the first connector is connected to the first power supply sub-module, the second connector is connected to the second power supply sub-module, the third connector is connected to the first target chip, and the fourth connector is connected to the second target chip, the first connector and the third connector are connected via the plurality of first switches, and the second connector and the fourth connector are connected via the plurality of second switches, and the power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative poles of the first power supply sub-module, and the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative poles of the second power supply sub-module.

[0170] Optionally, in an embodiment of the present application, the order in which the switches are turned on includes: two first switches among the plurality of first switches that are connected to the power supply pins and ground pins of the first target chip are turned on first, and then other first switches among the plurality of first switches are turned on randomly; and / or two second switches among the second switches that are connected to the power supply pins and ground pins of the second target chip are turned on first, and then other second switches among the plurality of second switches are turned on randomly.

[0171] Optionally, in the embodiment of the present application, the on-order of the switches includes: the plurality of first switches being turned on randomly; and / or the plurality of second switches being turned on randomly.

[0172] Optionally, in an embodiment of the present application, the power supply module includes a first power supply sub-module and a second power supply sub-module connected in series, the target chip includes a first target chip or a second target chip, the switch matrix 520 includes a plurality of third switches, a first connector, a second connector and a third connector, the first connector is connected to the first power supply sub-module, the second connector is connected to the second power supply sub-module, the third connector is connected to the first target chip or the second target chip, and the first connector and the second connector are connected to the third connector via the plurality of third switches.

[0173] Optionally, in the embodiment of the present application, the order in which the switches are turned on is such that some of the third switches connected to the first power supply sub-module among the plurality of third switches are turned on first, and some of the other third switches connected to the second power supply sub-module among the plurality of third switches are turned on later, or some of the third switches connected to the second power supply sub-module among the plurality of third switches are turned on first, and some of the other third switches connected to the first power supply sub-module among the plurality of third switches are turned on later.

[0174] Optionally, in an embodiment of the present application, the power supply pin and the ground pin of the first target chip or the second target chip are respectively connected to the positive and negative poles of the power supply module, the part of the third switches includes a third switch connected to the power supply pin of the first target chip or the second target chip, and the other part of the third switches includes a third switch connected to the ground pin of the first target chip or the second target chip, and the order of turning on the switches is such that after the part of the third switches is turned on, the third switch connected to the ground pin of the first target chip or the second target chip among the other part of the third switches is turned on first, and then the other part of the third switches is turned on. Alternatively, the some of the third switches may include a third switch connected to a ground pin of the first target chip or the second target chip, and the other some of the third switches may include a third switch connected to a power pin of the first target chip or the second target chip, and the order in which the switches are turned on may include, after the some of the third switches are turned on, a third switch connected to a power pin of the first target chip or the second target chip among the other some of the third switches is turned on first, and then the other third switches of the other some of the third switches are turned on randomly.

[0175] Optionally, in an embodiment of the present application, the target chip includes a first target chip and a second target chip, the switch matrix 520 includes a plurality of fourth switches, a plurality of fifth switches, a first connector, and a second connector, the first connector is connected to the power supply module, the first target chip and the second target chip are both connected to the second connector, the first connector and the second connector are connected via the plurality of fourth switches and the plurality of fifth switches, the power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative poles of some power supply units of the power supply module, and the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative poles of other power supply units of the power supply module.

[0176] Optionally, in an embodiment of the present application, the order of turning on the switches includes first turning on a fourth switch among the plurality of fourth switches that is connected to a power pin of the first target chip and a fifth switch among the plurality of fifth switches that is connected to a ground pin of the second target chip, then turning on a fourth switch among the plurality of fourth switches that is connected to the ground pin of the first target chip and a fifth switch among the plurality of fifth switches that is connected to a power pin of the second target chip, and finally turning on another fourth switch among the plurality of fourth switches and another fifth switch among the plurality of fifth switches randomly.

[0177] Optionally, in an embodiment of the present application, the on-order of the switches includes the plurality of fourth switches and the plurality of fifth switches being turned on randomly.

[0178] Optionally, in this embodiment, the power pin of the first target chip is connected to the ground pin of the second target chip.

[0179] Optionally, in an embodiment of the present application, the order of turning on the switches includes turning on the plurality of fourth switches first, then turning on a fifth switch among the plurality of fifth switches that is connected to a power pin of the second target chip, and finally turning on other fifth switches among the plurality of fifth switches randomly, or turning on the plurality of fifth switches first, then turning on a fourth switch among the plurality of fourth switches that is connected to a ground pin of the first target chip, and finally turning on other fourth switches among the plurality of fourth switches randomly.

[0180] Optionally, in an embodiment of the present application, the switch matrix 520 includes a plurality of discharge units, each of which is respectively arranged between two pins on the target chip, and before obtaining the pin connection control information of the target chip, the processor 510 is further used to control the plurality of discharge units to discharge the peripheral circuits of the target chip.

[0181] Optionally, in the present embodiment, one discharge unit is provided between every two adjacent pins of the target chip.

[0182] Optionally, in the embodiment of the present application, one discharge unit is provided between each of all pins other than the ground pin of the target chip and the ground pin.

[0183] Optionally, in an embodiment of the present application, the discharge unit includes a discharge switch and a resistor connected in series with the discharge switch, and the processor 510 is specifically used to control the discharge switch in each discharge unit among the plurality of discharge units to be turned on so as to discharge the peripheral circuits of the target chip.

[0184] Optionally, in the embodiment of the present application, the processor 510 is specifically used to control the at least some pins to be connected to the power supply module multiple times according to a preset number of times based on the connection order.

[0185] Optionally, in the present embodiment, the preset number is 30 or more.

[0186] Optionally, in an embodiment of the present application, the processor 510 is further used to perform functional verification on the target chip after controlling the at least some pins to be connected to the power supply module multiple times according to the preset number of times based on the connection order.

[0187] Optionally, in an embodiment of the present application, the processor 510 is further used to determine whether the circuit function of the target chip is normal based on the reported information of the target chip during the process of controlling the connection of at least some of the pins to the power supply module based on the connection order.

[0188] Optionally, in the embodiment of the present application, the target chip is an analog front-end AFE chip.

[0189] Optionally, the test device further includes a memory, the memory is used to store commands, and the processor 510 is used to read the commands and perform the methods described in each embodiment of the present application based on the commands.

[0190] The memory may be a separate, stand-alone device independent of the processor 510 or may be integrated into the processor 510 .

[0191] Optionally, the test device may further include a transceiver, and the processor 510 may control the transceiver to communicate with other devices, specifically, to transmit information or data to other devices or to receive information or data transmitted by other devices.

[0192] It is understood that each module or unit in the test apparatus 500 can realize a corresponding flow in the chip testing method according to the embodiment of the present application, and the description thereof will be omitted here for the sake of brevity.

[0193] An embodiment of the present application further provides a chip, including a processor for retrieving and executing a computer program from the memory to cause a device in which the chip is attached to perform a method according to an embodiment of the present application.

[0194] It should be understood that the processor in the embodiments of the present application may be an integrated circuit chip capable of processing signals. In the course of implementation, each step described in the method embodiments can be completed by a hardware integrated logic circuit in the processor or a command in software form. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc. Each method, step, and logic block diagram disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be combined and directly implemented and executed in a hardware decoding processor, or may be executed and completed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium established in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an erasable programmable memory, a register, etc. The storage medium is located in a memory, and a processor reads the information in the memory and, in combination with its hardware, completes the steps of the above method.

[0195] It will be appreciated that the memory in the present embodiments may be volatile or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. By way of example and not limitation, many forms of RAM may be utilized, such as static random access memory (Static RAM, SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronously linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct Rambus random access memory (Direct Rambus RAM, DR RAM). It should be noted that memory in the systems and methods described herein includes, but is not limited to, these and any other suitable types of memory.

[0196] An embodiment of the present application further provides a computer storage medium, which can be used to store a computer program, and the computer program can be used to perform the method of each embodiment described herein.

[0197] Optionally, the computer-readable storage medium may be applied to a test device in the embodiments of the present application, and the computer program causes a computer to execute the corresponding flow implemented by the test device in each method of the embodiments of the present application, but for the sake of brevity, the description here is omitted.

[0198] Embodiments of the present application further provide a computer program product including computer program commands.

[0199] Optionally, the computer program product may be applied to a test device in the embodiments of the present application, and the computer program commands cause a computer to execute the corresponding flow implemented by the test device in each method of the embodiments of the present application, but for the sake of brevity, the description thereof will be omitted here.

[0200] Embodiments of the present application further provide a computer program.

[0201] Optionally, the computer program may be applied to the test device in the embodiments of the present application, and when the computer program is executed on a computer, it causes the computer to execute the corresponding flow realized by the test device in each method of the embodiments of the present application, but for the sake of brevity, the description here is omitted.

[0202] The above are only specific embodiments of the present application, and the scope of protection of the present application is not limited thereto. Those skilled in the art can easily think of modifications or substitutions within the technical scope disclosed in the present application, all of which should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection set forth in the claims.

Claims

1. A chip test apparatus comprising: a processor used to obtain pin connection control information of the target chip; the pin connection control information is used to instruct a connection order between at least some pins of the target chip and a power supply module; The test apparatus, wherein the processor is further used to control connections between the at least some of the pins and the power supply module based on the connection order.

2. the power supply module includes a plurality of power supply units; 2. The test device according to claim 1, wherein the processor is specifically used for controlling the connection of at least some of the pins to the positive and negative poles of at least some of the power supply units in the plurality of power supply units, respectively, based on the connection order.

3. the at least some of the power supply units include a first power supply unit and a second power supply unit; 3. The test device of claim 2, wherein the processor specifically controls, according to the connection order, to connect two pins among the at least some of the pins to the positive pole of the first power supply unit and the negative pole of the second power supply unit, respectively, so that the voltage between the two pins becomes U, where U is used as the sum of the voltages of the multiple power supply units.

4. 4. The test device according to claim 3, wherein the positive pole of the first power supply unit is the positive pole of the power supply module, and the negative pole of the second power supply unit is the negative pole of the power supply module.

5. 5. The test device according to claim 3, wherein the two pins include a power supply pin and a ground pin of the target chip.

6. 6. The test device according to claim 3, wherein the connection order includes connecting the two pins to the power supply module first.

7. 7. The test apparatus of claim 6, wherein the connection order further includes, after connecting the two pins to the power supply module, connecting pins other than the two pins among the at least some of the pins to the power supply module in a random order.

8. 3. The test device according to claim 1, wherein the connection sequence includes connecting the at least some of the pins to the power supply module in a random order.

9. further comprising a switch matrix; pins of the target chip are connected to the power supply module through the switch matrix; 9. The test device according to claim 1, wherein the pin connection control information is used to instruct an order in which the switches of the switch matrix are turned on.

10. 10. The test apparatus of claim 9, wherein the power supply module includes a first power supply sub-module and a second power supply sub-module, the target chip includes a first target chip and a second target chip, the switch matrix includes a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector, and a fourth connector, the first connector is connected to the first power supply sub-module, the second connector is connected to the second power supply sub-module, the third connector is connected to the first target chip, and the fourth connector is connected to the second target chip, the first connector and the third connector are connected via the plurality of first switches, and the second connector and the fourth connector are connected via the plurality of second switches, a power supply pin and a ground pin of the first target chip are respectively connected to a positive electrode and a negative electrode of the first power supply sub-module, and a power supply pin and a ground pin of the second target chip are respectively connected to a positive electrode and a negative electrode of the second power supply sub-module.

11. The on-order of the switches is such that two first switches connected to a power supply pin and a ground pin of the first target chip among the plurality of first switches are turned on first, and then other first switches among the plurality of first switches are turned on randomly; and / or 11. The test apparatus of claim 10, further comprising: first turning on two of the second switches connected to a power supply pin and a ground pin of the second target chip, and then randomly turning on other second switches among the plurality of second switches.

12. 11. The test apparatus according to claim 10, wherein the on-sequence of the switches includes randomly turning on the first switches and / or randomly turning on the second switches.

13. 10. The test apparatus of claim 9, wherein the power supply module includes a first power supply sub-module and a second power supply sub-module connected in series, the target chip includes a first target chip or a second target chip, the switch matrix includes a plurality of third switches, a first connector, a second connector, and a third connector, the first connector is connected to the first power supply sub-module, the second connector is connected to the second power supply sub-module, the third connector is connected to the first target chip or the second target chip, and the first connector and the second connector are connected to the third connector via the plurality of third switches.

14. The on-order of the switches is such that some of the third switches connected to the first connector among the plurality of third switches are turned on first, and other some of the third switches connected to the second connector among the plurality of third switches are turned on later, or 14. The test device according to claim 13, further comprising: a part of the third switches connected to the second connector among the plurality of third switches being turned on first, and another part of the third switches connected to the first connector among the plurality of third switches being turned on later.

15. a power pin and a ground pin of the first target chip or the second target chip are respectively connected to a positive electrode and a negative electrode of the power supply module; the some of the third switches include a third switch connected to a power pin of the first target chip or the second target chip, and the other some of the third switches include a third switch connected to a ground pin of the first target chip or the second target chip, and the on-order of the switches includes that after the some of the third switches are turned on, the third switch of the other some of the third switches connected to the ground pin of the first target chip or the second target chip is turned on first, and then the other third switches of the other some of the third switches are turned on randomly; or 15. The test apparatus of claim 14, wherein the some of the third switches include a third switch connected to a ground pin of the first target chip or the second target chip, and the other some of the third switches include a third switch connected to a power pin of the first target chip or the second target chip, and the order in which the switches are turned on includes, after the some of the third switches are turned on, turning on a third switch connected to a power pin of the first target chip or the second target chip among the other some of the third switches first, and then turning on other third switches among the other some of the third switches randomly.

16. 10. The test apparatus of claim 9, wherein the target chips include a first target chip and a second target chip; the switch matrix includes a plurality of fourth switches, a plurality of fifth switches, a first connector, and a second connector; the first connector is connected to the power supply module; the first target chip and the second target chip are both connected to the second connector; the first connector and the second connector are connected via the plurality of fourth switches and the plurality of fifth switches; a power supply pin and a ground pin of the first target chip are respectively connected to positive and negative poles of some power supply units of the power supply module; and a power supply pin and a ground pin of the second target chip are respectively connected to positive and negative poles of other power supply units of the power supply module.

17. 17. The test apparatus of claim 16, wherein the order of turning on the switches includes first turning on a fourth switch among the plurality of fourth switches connected to a power pin of the first target chip and a fifth switch among the plurality of fifth switches connected to a ground pin of the second target chip, then turning on a fourth switch among the plurality of fourth switches connected to the ground pin of the first target chip and a fifth switch among the plurality of fifth switches connected to a power pin of the second target chip, and finally turning on another fourth switch among the plurality of fourth switches and another fifth switch among the plurality of fifth switches in a random order.

18. 17. The test device of claim 16, wherein the switch-on sequence includes randomly turning on the fourth switches and the fifth switches.

19. 17. The test device of claim 16, wherein a power pin of the first target chip is connected to a ground pin of the second target chip.

20. The order of turning on the switches is such that the plurality of fourth switches are turned on first, then the fifth switch connected to the power pin of the second target chip among the plurality of fifth switches is turned on, and finally the other fifth switches among the plurality of fifth switches are turned on randomly; or 20. The test apparatus of claim 19, further comprising: first turning on the plurality of fifth switches, then turning on a fourth switch among the plurality of fourth switches that is connected to a ground pin of the first target chip, and finally turning on other fourth switches among the plurality of fourth switches randomly.

21. The switch matrix includes a plurality of discharge units, each of which is disposed between two pins of the target chip; The test apparatus of any one of claims 9 to 20, characterized in that the processor is further used to control the plurality of discharge units to discharge peripheral circuits of the target chip before obtaining pin connection control information of the target chip.

22. 22. The test apparatus according to claim 21, wherein one discharge unit is provided between every two adjacent pins of the target chip.

23. 22. The test apparatus according to claim 21, wherein one discharge unit is provided between each of all pins other than the ground pin of the target chip and the ground pin.

24. the discharge unit includes a discharge switch and a resistor connected in series with the discharge switch; The test apparatus according to any one of claims 21 to 23, characterized in that the processor is further used to specifically control the discharge switch in each discharge unit to turn on so as to discharge the peripheral circuit of the target chip.

25. Specifically, the processor: The test device according to any one of claims 1 to 24, characterized in that it is used to control the connection of at least some of the pins to the power supply module multiple times according to a preset number of times based on the connection order.

26. The processor:

26. The test apparatus of claim 25, further comprising: a test device for performing a functional verification on the target chip after controlling the connection of at least some of the pins to the power supply module multiple times according to the preset number of times based on the connection order.

27. A method for testing a chip, comprising: obtaining pin connection control information of the target chip, which is used to instruct a connection order between at least some pins of the target chip and a power supply module; and controlling connections between the at least some of the pins and the power supply module based on the connection order.

28. The power supply module includes a plurality of power supply units, and controlling the connection between the at least some of the pins and the power supply module based on the connection order includes:

28. The testing method according to claim 27, further comprising controlling the at least some of the pins to be connected to positive and negative terminals of at least some of the power supply units in the plurality of power supply units, respectively, based on the connection order.

29. The at least some of the power supply units include a first power supply unit and a second power supply unit, and the control to connect the at least some of the pins to the positive and negative electrodes of at least some of the power supply units in the plurality of power supply units based on the connection order is 29. The testing method of claim 28, further comprising: controlling, based on the connection order, two pins among the at least some of the pins to be connected to the positive pole of the first power supply unit and the negative pole of the second power supply unit, respectively, so that a voltage between the two pins becomes U, where U is a sum of voltages of the plurality of power supply units.

30. 30. The test method of claim 29, wherein the connection order includes first connecting each of the two pins to the power supply module.

31. 31. The test method of claim 30, wherein the connection order further comprises, after connecting the two pins to the power supply module, connecting pins other than the two pins among the at least some of the pins to the power supply module in a random order.

32. 29. The test method according to claim 27 or 28, wherein the connection order includes connecting the at least some of the pins to the power supply module in a random order.

33. the pin connection control information is further used to indicate a connection delay between two pins that are sequentially connected to the power supply module among the at least some of the pins; Controlling the connection between the at least some of the pins and the power supply module based on the connection order The test method according to any one of claims 27 to 32, further comprising controlling connections between the at least some of the pins and the power supply module based on the connection order and the connection delay.

34. The test method according to any one of claims 27 to 33, wherein pins of the target chip are connected to the power supply module through a switch matrix, and the pin connection control information is used to indicate the order in which switches of the switch matrix are turned on.

35. The switch matrix includes a plurality of discharge units, each of which is disposed between two pins of the target chip; 35. The test method of claim 34, further comprising controlling the plurality of discharge units to discharge peripheral circuits of the target chip before obtaining pin connection control information of the target chip.

36. The discharge unit includes a discharge switch and a resistor connected in series with the discharge switch, and the discharge unit controls the plurality of discharge units to discharge the peripheral circuits of the target chip, 36. The test method of claim 35, further comprising controlling a discharge switch in each of the plurality of discharge units to be turned on, thereby discharging a peripheral circuit of the target chip.

37. The step of controlling the connection between the at least some of the pins and the power supply module based on the connection order includes: The test method according to any one of claims 27 to 36, further comprising controlling the at least some of the pins to be connected to the power supply module a plurality of times according to a preset number of times based on the connection order.

38. 38. The test method of claim 37, further comprising: performing a functional verification on the target chip after controlling the at least some of the pins to be connected to the power supply module a plurality of times according to the preset number of times based on the connection order.

39. The test method of any one of claims 27 to 38, characterized in that, in the process of controlling the connection of at least some of the pins to the power supply module based on the connection order, it further comprises: determining whether the circuit function of the target chip is normal based on the report information of the target chip.

40. A chip comprising a processor that calls up and executes a computer program from a memory to cause a device to which the chip is attached to perform the test method according to any one of claims 27 to 39.

41. A computer-readable storage medium used to store a computer program for causing a computer to execute the test method according to any one of claims 27 to 39.

42. A computer program product comprising computer program commands for causing a computer to carry out the testing method according to any one of claims 27 to 39.

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