Encryption of data exchanged between components at the link layer with automatic locking between sending and receiving components

Abstract

Encryption of data exchanged between components at the link layer with automatic locking between sending and receiving components A method for encrypting frames to be transmitted from a transmitter to a receiver comprises transmitting a set of unencrypted training frames from the transmitter to the receiver, each training frame being scrambled before transmission against an output of a counter at the transmitter and the training frames, wherein each scrambled training frame is unencrypted. A control signal from the transmitter is transmitted from the transmitter to the receiver after the training frames. After transmitting the control signal to the receiver, a frame modified to include error detection information is encrypted using an encrypted counter block generated from the output of the counter. The encrypted modified frame is transmitted from the transmitter to the receiver.

Description

[Technical Field]

[0001] The field of the invention is data processing, or more particularly, methods, apparatus and products for encrypting data exchanged between processing cores. [Background technology]

[0002] The development of the EDVAC computer system in 1948 is often cited as the beginning of the computer age. Since that time, computer systems have evolved into extremely complex devices. Today's computers are far more sophisticated than earlier systems such as the EDVAC. A computer system typically includes a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input / output devices, etc. As advances in semiconductor processing and computer architectures have pushed computer performance ever higher, more sophisticated computer software has evolved to take advantage of the higher performance hardware, resulting in today's computer systems being far more powerful than they were just a few years ago.

[0003] Many computing system configurations include one or more servers. A server includes multiple nodes connected to each other through links. For example, certain nodes of a server are processing cores, other nodes are storage, while other nodes provide other functions. Different nodes are often in different physical locations and are connected to each other. For example, a node is connected to another node through a network cable or other wired connector. Other types of connections between nodes may be implemented in different configurations.

[0004] However, connections between server nodes are relatively accessible to third parties for investigating or breaking into the computing system. For example, network cables between nodes are relatively accessible to third parties and provide an entry point for third parties to obtain data from the computing system. Data communicated through the connections often contains confidential information, such as customer or user information, making the connections between nodes a potential vulnerability for the computing system.

[0005] To protect data communicated over connections between nodes, the data exchanged over the connections is encrypted in various configurations. However, conventional methods for encrypting data increase the latency of data transmission over the connection by introducing additional time to perform the encryption. Furthermore, conventional encryption methods involve retraining a counter used in scrambling data for transmission over the link every time the link is re-established or retrained, and lack an authentication mechanism for the data exchanged. Summary of the Invention

[0006] A method and system for encrypting frames transmitted from a transmitter to a receiver comprises transmitting a set of unencrypted training frames from the transmitter to the receiver, each training frame being scrambled before transmission against an output of a counter at the transmitter and the training frame, wherein each scrambled training frame is unencrypted. A control signal from the transmitter is transmitted from the transmitter to the receiver after the training frame. After transmitting the control signal to the receiver, a modified frame containing error detection information is encrypted using an encrypted counter block generated from the output of the counter. The encrypted modified frame is transmitted from the transmitter to the receiver.

[0007] The foregoing and other objects, features and advantages of the present invention will become apparent from the following more particular description of exemplary embodiments of the invention as illustrated in the accompanying drawings, in which like reference numerals generally represent like parts of exemplary embodiments of the invention. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of an exemplary computing environment according to some embodiments of the present invention.

[0009] [Figure 2] FIG. 1 is a block diagram of an exemplary interconnect architecture according to some embodiments of the present invention.

[0010] [Figure 3] FIG. 2 is a block diagram of a transmitter of a security-implementing module according to some embodiments of the present invention.

[0011] [Figure 4] FIG. 2 is a block diagram of a transmitter scrambler including encryption according to some embodiments of the present invention.

[0012] [Figure 5] FIG. 2 is a block diagram of a receiver of a security-implementing module according to some embodiments of the present invention.

[0013] [Figure 6] FIG. 2 is a block diagram of a descrambler with transmitter decryption according to some embodiments of the present invention.

[0014] [Figure 7] 1 is a flowchart of a method for transmitting encrypted frames using a counter employed by a transmitter according to some embodiments of the present invention.

[0015] [Figure 8]1 is a flowchart of a method for decrypting a received frame after locking a counter at a receiver to a counter at a transmitter, according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Various aspects of the present invention are described through text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. With respect to any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in the reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0017] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media") collectively included in a set of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as punch cards or pits / lands formed on a major surface of a disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals communicated through wires, and / or other transmission media.As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but this does not make the storage device temporary, as the data is not temporary while it is stored.

[0018] 1 illustrates an example of an environment for the execution of at least a portion of computer code involved in performing the methods of the present invention, such as a security implementation module 127. In addition to the security implementation module 127, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a set of processors 110 (including processing circuitry 120 and cache 121), a communications fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and a security implementation module 127 as identified above), a set of peripheral devices 114 (including a set of user interface (UI) devices 123, storage 124, and a set of Internet of Things (IoT) sensors 125), and a network module 115. The remote server 104 includes a remote database 130. Public cloud 105 includes gateway 140, cloud orchestration module 141, set of host physical machines 142, set of virtual machines 143, and set of containers 144. Computing environment 100 includes an example environment for execution of at least a portion of computer code involved in performing the methods of the present invention, such as security implementation module 127. Security implementation module 127 includes instructions and data for encrypting data sent to another device or component and decrypting data received from another device or component. Security implementation module 127 also includes instructions for synchronizing counters used for encryption and decryption of data by computer 101 and another device (e.g., another computer 101, processor).In addition to security implementation module 127, computing environment 100 includes, for example, computer 101, wide area network (WAN) 102, end user device (EUD) 103, remote server 104, public cloud 105, and private cloud 106. In this embodiment, computer 101 includes a set of processors 110 (including processing circuitry 120 and cache 121), a communications fabric 111, volatile memory 112, persistent storage 113 (including operating system 122 and test module 127 as identified above), a set of peripheral devices 114 (including a set of user interface (UI) devices 123, storage 124, and a set of Internet of Things (IoT) sensors 125), and a network module 115. Remote server 104 includes a remote database 130. Public cloud 105 includes a gateway 140, a cloud orchestration module 141, a set of host physical machines 142, a set of virtual machines 143, and a set of containers 144.

[0019] Computer 101 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 130. As is well understood in the art of computer technology, and depending on the technology, execution of a computer-implemented method may be distributed among multiple computers and / or among multiple locations. While in this presentation of computing environment 100, to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 101. Although computer 101 is not depicted in the cloud of FIG. 1 , it may be located in a cloud. However, computer 101 is not required to reside within a cloud except to any extent that may be expressly indicated.

[0020] Processor set 110 includes one or more computer processors of any type now known or later developed. Processing circuitry 120 may be distributed across multiple packages, e.g., multiple coordinated integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on processor set 110. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all caches for a processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to operate with qubits and perform quantum computing.

[0021] Computer-readable program instructions are typically loaded onto computer 101 to cause processor set 110 of computer 101 to perform a series of operational steps, thereby realizing a computer-implemented method, whereby the instructions so executed instantiate the method specified in the flowcharts and / or descriptions of the computer-implemented method contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by processor set 110 to control and direct the execution of the methods of the present invention. In computing environment 100, at least some of the instructions for performing the methods of the present invention may be stored in security implementation module 127 in persistent storage 113.

[0022] Communications fabric 111 is the signal-conducting pathway that allows various components of computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as those that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways may be used, such as fiber optic and / or wireless communication pathways.

[0023] Volatile memory 112 may be any type of volatile memory now known or later developed. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory 112 is characterized by random access, although this is not required unless expressly indicated. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 101.

[0024] Persistent storage 113 is any form of non-volatile storage for a computer, now known or later developed. The non-volatility of this storage means that stored data remains regardless of whether power is supplied to computer 101 and / or to persistent storage 113 directly. While persistent storage 113 may be read-only memory (ROM), typically at least a portion of persistent storage allows data to be written, data to be deleted, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems employing a kernel. The code included in security implementation module 127 typically includes at least a portion of the computer code involved in performing the methods of the present invention.

[0025] The peripheral device set 114 includes a set of peripheral devices of the computer 101. Data communication connections between the peripheral devices and other components of the computer 101 may be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cable (such as a universal serial bus (USB)-type cable), insertion-type connections (e.g., a secure digital (SD) card), connections made through a local area communication network, and even connections made through a wide area network such as the Internet. In various embodiments, the UI device set 123 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. The storage 124 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. The storage 124 may be persistent and / or volatile. In some embodiments, storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (e.g., computer 101 stores and manages large databases locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. IoT sensor set 125 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.

[0026] Network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers over WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention can be downloaded to computer 101 from an external computer or external storage device, typically through a network adapter card or network interface included in network module 115.

[0027] Wide area network (WAN) 102 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances by any technology for communicating computer data, now known or later developed. In some embodiments, WAN 102 may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0028] End-user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and may take any of the forms discussed above in connection with computer 101. EUD 103 typically receives useful and useful data from the operation of computer 101. For example, in the hypothetical case where computer 101 is designed to provide recommendations to the end user, the recommendations would typically be communicated from network module 115 of computer 101 over WAN 102 to EUD 103. In this manner, EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0029] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 101 from remote database 130 of remote server 104.

[0030] Public cloud 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer functionality, particularly data storage (cloud storage) and computing power, without direct active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of public cloud 105's computing resources is performed by computer hardware and / or software in cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments (VCEs) running on various computers that comprise host physical machine set 142, the universe of physical computers in and / or available to public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It is understood that these VCEs may be stored as images and can be transferred among and between various physical machine hosts, either as images or after instantiation of the VCEs. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCE, and manages active instantiations of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that enables public cloud 105 to communicate over WAN 102.

[0031] Some further description of a virtualized computing environment (VCE) is now provided. A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from the image. Two well-known types of VCE are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows for the existence of multiple isolated user space instances called containers. These isolated user space instances typically behave as actual computers from the perspective of programs running in them. A computer program running on a normal operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0032] A private cloud 106 is similar to a public cloud 105, except that the computing resources are available only for use by a single enterprise. While the private cloud 106 is shown as communicating with the WAN 102, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often each implemented by a different vendor. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both the public cloud 105 and the private cloud 106 are part of a larger hybrid cloud.

[0033] To further illustrate, FIG. 2 shows an example of a layered protocol stack used by one or more computers, such as computer 101, to send and receive data. Examples of layered protocol stacks include a Peripheral Component Interconnect Express (PCIe) stack, a Quick Path Interconnect (QPI) stack, or other types of layered protocol stacks. In the example shown by FIG. 2, the layered protocol stack includes a transaction layer 205, a link layer 210, and a physical layer 215. In other embodiments, additional layers may be included in the layered protocol stack. An interface for computer 101, or for a processing core of computer 101 (e.g., a processor in processor set 110) to exchange data with another device (e.g., another computer 101, another processing core), may be represented as a layered protocol stack as shown by FIG. 2.

[0034] Data packets that carry information from a sending device to a receiving device are formed by transaction layer 205 and link layer 210. Different layers add different information to the data packet. After formation in transaction layer 205 and link layer 210, the data packet is transmitted from the sending device to the receiving device using physical layer 215. The receiving device receives the data packet from physical layer 215, and layers after physical layer 215 modify the data packet based on the information in the data packet until it reaches transaction layer 205. Transaction layer 205 of the receiving device then processes the data packet.

[0035] Transaction layer 205 provides an interface between a device's processing core (e.g., processor set 110 of computer 101) and an interconnect architecture that includes link layer 210 and transaction layer 215. Transaction layer 215 assembles packets for transmitting data and disassembles packets of received data. For example, transaction layer 215 assembles packet headers and packet payloads for data. In some embodiments, transaction layer 215 assembles packets based on a specification that describes the contents and structure of the packets. An example specification for assembling packets is the PCIe specification.

[0036] Link layer 210 lies between transaction layer 205 and physical layer 215. Link layer 210 provides mechanisms for exchanging packets between different components over a link. In various embodiments, the mechanisms provided by link layer 210 have at least a threshold reliability. As further described below in conjunction with FIG. 3, a portion of the link layer receives data packets from transaction layer 205, applies information to those packets that identifies the sequence of those packets, generates and includes error correction information in the packets, and transmits the packets, including the sequencing and error correction information, to physical layer 215.

[0037] The physical layer 215 transmits packets from the link layer 210 across a physical medium to another component or device. The physical layer 215 prepares outgoing packets for transmission and identifies and prepares incoming packets before routing them to the link layer 210. Thus, the physical layer 215 provides a transmitter and a receiver. The transmitter of the physical layer 215 serializes data packets from the link layer 210 and transmits the serialized packets to another device or component. For example, the physical layer 215 transmits serialized packets from a processing core to another processing core through a network cable or another type of physical connection. In addition, the physical layer 215 includes a receiver that receives packets from the physical connection (e.g., from another device or component through a physical connection), where the packets are then deserialized and distributed into frames that are provided to the link layer 210.

[0038] Thus, in various embodiments, the layered protocol stack described in conjunction with Figure 2 includes a layer that assembles packets from data received from a processor core, transaction layer 205. Another layer, link layer 210, sequences the assembled packets. An additional layer, physical layer 215, transmits the assembled sequence of packets to another processor core or other device using a physical connection. As described further below in conjunction with Figures 3-7, encrypting data at link layer 210 allows data to be secured as it is transmitted through physical layer 215.

[0039] Security implementation module 127 includes a transmitter and a receiver. The transmitter enables security implementation module 127 to send data from a processor core, such as a processor from processor set 110, and the receiver enables security implementation module 127 to receive data from a device or component. As described further below in conjunction with FIG. 3, the transmitter encrypts data from transaction layer 205 to prevent unauthorized access to the data as it is transmitted over a physical connection. As described further below in conjunction with FIG. 4, the receiver decrypts data from physical layer 215 and routes the decrypted data to transport layer 205.

[0040] 3, a block diagram of an example transmitter of security implementation module 127 is shown. The transmitter shown in FIG. 3 includes a frame buffer 305, an error detection module 310, and one or more lane transmission modules 315. The lane configuration module 315 includes a scrambler 320 and a synchronization module 325. In other embodiments, the transmitter includes different or additional modules than those described in conjunction with FIG. 3.

[0041] For illustrative purposes, the transmitter shown in Figure 3 receives data from a processing core, such as a processor, while in other embodiments, the transmitter receives data from another component. Data received by the transmitter is received by frame buffer 305, which creates a queue of packets received by the transmitter. This allows the transmitter to form frames that include data packets received from the transmitter. In different embodiments, frame buffer 305 includes a different number of data packets in a frame.

[0042] The output of frame buffer 305, which is a frame (e.g., group) of packets, is received by error detection module 310. Error detection module 310 generates error detection information for the frame that is included in the frame. The error detection information is included in the frame along with the data from the packet to enable detection of changes to the data included in the frame during transmission. In various embodiments, the error detection information is a cyclic redundancy check (CRC) code, and error detection module 310 appends the CRC code to the frame. In other embodiments, error detection module 310 generates other types of error detection information that enable a receiving device to identify errors in the frame and appends the error detection information to the frame.

[0043] The frame including the error detection information is received as input by the lane transmission module 315. In various embodiments, the frame is transmitted over a physical layer having multiple lanes, each lane capable of transmitting data. For example, a lane corresponds to a different pair of wires in a network cable or a different wire in a network cable. In other examples, a lane is a set of signal traces, wires, or other conductive paths coupling a transmitter to a physical connection (e.g., a network cable). Different numbers of lanes may be used to transmit frames, with increasing numbers of lanes transmitting more frames and providing higher data transfer rates. In some embodiments, the transmitter includes a lane configuration module 315 for each lane.

[0044] The lane configuration module 315 includes a scrambler 320 and a synchronization module 325. The scrambler 320 receives frames containing error detection information from the error detection module 310. The scrambler 320 modifies the frames before transmission to simplify recovery of timing information and data from the frames by a receiving device. In various embodiments, the scrambler increases the number of transitions from logic high to logic low values ​​or logic low to logic high values ​​within the frames. Increasing the number of transitions between values ​​allows the receiver to better recover data and clock information from the frames. For example, the scrambler 320 is an additive scrambler in which a linear feedback shift register generates a pseudo-random binary sequence that is a seed value. The scrambler performs a serial XOR operation, and the seed value is output from the linear feedback shift register, and the frame contains error detection information.

[0045] In contrast to conventional scramblers, the scrambler 320 of FIG. 3 encrypts data. In various embodiments, the scrambler 320 encrypts the data using the Advanced Encryption Standard (AES). In other embodiments, other block cipher encryption methods or other encryption methods are used to encrypt the data. In various embodiments, the scrambler uses block cipher encryption in counter mode, where the counter generates a key stream that is combined with unencrypted data from a frame to encrypt the frame. For example, the counter is a linear feedback shift register. In various embodiments, the counter is combined with a start value using a reversible operation (e.g., XOR, concatenation, addition) to generate a unique counter block. The counter block is encrypted with a key using AES or another block cipher encryption method, and the encrypted counter block is used to encrypt the frame. For example, the encrypted counter block is combined with the frame using an XOR operation to generate an encrypted frame.

[0046] 4, there is shown a block diagram of one embodiment of a scrambler 320. In the example of FIG. 4, the scrambler 320 includes a linear feedback shift register (LFSR) 405, an encryption module 410, a selector 415, and an XOR module 425. However, in other embodiments, the scrambler includes different or additional components than those described in conjunction with FIG. 4.

[0047] In various embodiments, the scrambler 320 encrypts data, such as frames, using block cipher encryption. For example, the scrambler 320 encrypts data using the Advanced Encryption Standard (AES). In other embodiments, other block cipher encryption methods or other encryption methods are used to encrypt the data. The scrambler 320 shown in FIG. 4 encrypts data using block cipher encryption in counter mode, where the counter generates a keystream that is combined with unencrypted data from the frame to encrypt the frame. The example in FIG. 4 includes an LFSR 405 as the counter. The LFSR 405 of the scrambler 320 is free-running, so that the LFSR 405 is continuously incremented to provide new values ​​to use for encryption, with the number of possible values ​​based on the bit width of the LFSR 405. In other embodiments, other types of counters may be used, where the counter is continuously incremented.

[0048] The output of LFSR 405 (or other counter) is received by encryption module 410, which combines the output of LFSR 405 with a starting value using a reversible operation (e.g., XOR, concatenation, addition) to generate a unique counter block. Encryption module 410 encrypts the counter block with a key using AES or another block cipher encryption method. The encrypted counter block is output from encryption module 410 and used to encrypt frames, as described further below.

[0049] LFSR 405 and encryption module 410 are coupled to selector 415. Based on control signal 420, selector 415 selects the output of LFSR 405 or encryption module 410 to be received as input to XOR module 425. In response to control signal 420 having a first value, selector 415 couples the output of LFSR 405 to XOR module 425, while in response to control signal 420 having a second value, selector 415 couples the output of encryption module 410 to XOR module 425. In various embodiments, control signal 420 has a first value when scrambler 320 operates in a training mode in which frame data is transmitted without encryption (i.e., transmitted in the clear). In training mode, scrambler 320 does not encrypt frames, and frames transmitted during training mode are from a set of training frames. Instead, during training mode, the output of LFSR 405 is combined with the frame using XOR module 425, which performs an exclusive-OR operation on the bits of the LFSR 405 output and the bits of the frame to increase the number of transitions between logic high and logic low values ​​in the frame before transmission, simplifying recovery of timing information and data from the frame by the receiving device. The training frames of the set are transmitted in a particular sequence determined by the order of the training frames in the set, which, in various embodiments, allows the receiving device to maintain expected values ​​for different frames. As described further below, transmitting training frames with expected values ​​allows a counter (e.g., an LFSR) of the receiving device to synchronize or lock with LFSR 405 during training mode. This allows training mode to simplify synchronization of LFSR 405 and the counter of the receiving device.

[0050] If a counter is used to encrypt a frame without synchronizing the transmitter counter and the receiver counter, the receiver will not be able to accurately decrypt the encrypted frame. Such synchronization of the transmitter counter and the receiver counter is referred to as "locking" the transmitter counter and the receiver counter. In conventional implementations, the transmitter counter and the receiver counter are renegotiated or refreshed when the link between the transmitter and the receiver is retrained, introducing additional complexity and computational resources. The training mode described above allows training frames to be transmitted in the clear while being scrambled using the output of the LFSR 405, allowing the receiver to determine the value of the receiver counter, which is synchronized with the scrambler's LFSR 405, based on the received training frames and the expected value of the frames.

[0051] In response to the control signal 420 having a second value, the selector 415 couples the output of the encryption module 410 to the XOR module 425, which combines the output of the encryption module 410 with the frame using an exclusive-OR operation on the bits of the frame and the bits of the output of the encryption module 410. This causes the encrypted counter block output by the encryption module 410 to be combined with the frame using the XOR module 425 to generate an encrypted frame. The encrypted frame is then output from the scrambler 320 and transmitted via the physical layer 215 to a receiving device or component, as further described above in conjunction with FIG. 2.

[0052] Using the output of the LFSR 405 (or another counter) as an input to the encryption module 410 allows frames to be encrypted before transmission while simplifying retraining the link between the transmitter and receiver through a training mode that uses the output of the LFSR 405 to modify the frame rather than using the output of the encryption module 410. Additionally, using a continuously incrementing (or "free-running") LFSR 405 prevents the encryption module 410 from receiving repeated inputs. Additionally, having the LFSR 405 input as an input to the encryption module 410 allows encryption of frame data without introducing additional encryption delays.

[0053] Referring back to FIG. 3 , the frames output by the scrambler 320 are input to a synchronization module 325. The synchronization module 325 appends a synchronization header to the frame. Additionally, in various embodiments, the synchronization module 325 encodes information identifying the boundaries between packets within a frame to simplify identification of the packets that comprise a frame. When the scrambler 320 operates in training mode, the synchronization module 325 receives unencrypted frames containing error detection information from the scrambler 320. On the other hand, when the scrambler 320 does not operate in training mode, the synchronization module 325 receives encrypted frames containing error detection information. The output of the synchronization module 325 is transmitted via the physical layer 215 to a receiving device, such as a processor core.

[0054] While Figures 3 and 4 illustrate a transmitter of security implementing module 127 for transmitting data from security implementing module 127, security implementing module 127 also includes a receiver for receiving data from another device. Figure 5 is a block diagram of a receiver of security implementing module 127. In the example illustrated by Figure 5, the receiver includes a set of lane receivers 500, an error detection module 515, and a layer preparation module 505. While in other embodiments, the receiver includes different or additional modules than those illustrated in Figure 5.

[0055] In various embodiments, the receiver includes a lane receiver 500 for each lane that comprises the physical layer. This allows the receiver to receive multiple frames of data in parallel from different lanes. One or more lanes may not include frames. The lane receiver 500, in the example illustrated by FIG. 5, includes a synchronization module 505 and a descrambler 510. In other embodiments, the lane receiver includes additional or different components than those illustrated in FIG. 5. The descrambler 510 receives frames of data from the physical layer.

[0056] The synchronization module 505 aligns frames received from the transmitter. In various embodiments, the transmitter synchronization module 505 extracts a synchronization header appended to the frame by the transmitter synchronization module 325. The transmitter synchronization module 505 uses information from the synchronization header to identify boundaries between packets and to identify the packet that contains the frame.

[0057] Additionally, the synchronization module 505 compensates for propagation delays in receiving frames. Propagation delays may be introduced from different path lengths of different lanes of the communication channel from which the receiver receives the frames, or from control signals added to the frames received by the receiver. These delays introduce skew into the received frames, and the synchronization module 505 includes one or more deskew methods applied to the received frames. The one or more deskew methods align the received frames to compensate for the propagation delays from the reception of the frames. Different embodiments may use different deskew methods, and the one or more deskew methods are applied to the frames before they are communicated to the descrambler 510.

[0058] 6, there is shown a block diagram of one embodiment of a descrambler 510. In the example of FIG. 6, the descrambler 510 includes an XOR module 605, a linear feedback shift register (LFSR) 615, an encryption module 620, and a selector 625. In other embodiments, the descrambler 510 includes different or additional components than those described in conjunction with FIG.

[0059] The XOR module 605 receives the frame from the physical layer and the output of the selector 625. The XOR module 605 performs an exclusive OR operation on the bits of the received frame and the bits of the output of the selector 625. The output of the XOR module 605 is the output of the descrambler 510 and is routed through the synchronization module 520 to the error detection module 515.

[0060] A selector 625 selects the output of the LFSR 615 or the output of the encryption module 620 based on an encryption status signal 610. The encryption status signal 610 is received by the receiver from the transmitter. A first value of the encryption status signal 610 indicates that the receiver is receiving an unencrypted or plaintext frame, while a second value of the encryption status signal 610 indicates that the receiver is receiving an encrypted frame. The encryption status signal has a first value to indicate that the transmitter is transmitting encrypted data. In various embodiments, the first value, indicating receipt of an unencrypted frame, is the default for the encryption status signal 610, and the encryption status signal 610 changes to a second value, indicating receipt of encrypted data, in response to receiving a control packet from the transmitter. In some embodiments, the transmitter passes a control packet on all lanes between the transmitter and the receiver, and the receiver determines that a control packet has been received in response to at least a threshold number of lanes receiving the control packet. For example, in response to a majority of lanes receiving the control packet, the receiver sets the encryption status signal 610 to a second value indicating receipt of encrypted data. When the encryption status signal 610 has the second value, the descrambler 510 determines that the received frame is encrypted and couples the output of the encryption module 620 to the XOR module 605.

[0061] When the encryption status signal 610 has a first value indicating that the frame is not encrypted, the descrambler 510 operates in a training mode in which unencrypted frames are received. As further described above in conjunction with FIG. 5, frame data is transmitted without encryption in training mode, so the descrambler 510 receives unencrypted training frames from a set of training frames. The transmitter and receiver have a stored set of training frames and the order in which the training frames are transmitted, allowing the receiver to maintain an expected value for each training frame in the set. During training mode, the descrambler performs an exclusive-OR operation on the bits of the received initial training frame and the expected value of the initial training frame. The result of the exclusive-OR operation of the received initial training frame and the expected value of this initial training frame is provided to the LFSR 615 (or other counter) to provide an initial value for the LFSR 615. The LFSR continuously increments from the initial value. For subsequently received training frames during training mode, descrambler 510 provides the output of LFSR 615 to XOR module 605, which performs an exclusive-OR operation on the output of LFSR 615 and the received training frame. Descrambler 510 compares the output of exclusive-OR module 605, which is the descrambled received training frame, with an expected value for the received training frame. In response to a threshold number of training frames received after the initial training frame matching the corresponding expected value for the training frame after descrambling, descrambler 510 determines that LFSR 615 is locked with LFSR 405 of scrambler 320. With LFSR 615 of descrambler 510 locked with LFSR 405 of scrambler 320, descrambler 510 is able to decode subsequently received frames from the physical layer.When the training mode ends, the scrambler 320 sends a control packet to the descrambler 510 using multiple lanes, along with receiving a control packet that sets the encryption status signal 610 to a value indicating that an encrypted frame has been received (e.g., the second value in the example above).

[0062] LFSR 615 is also coupled to encryption module 620, which is also coupled to selector 625. Encryption module 620 combines the output of LFSR 615 with a start value using a reversible operation (e.g., XOR, concatenation, addition) to generate a unique counter block. Encryption module 620 encrypts the counter block with a key using AES or another block cipher encryption method. The encrypted counter block is output from encryption module 620 and used to decrypt received frames. To decrypt received frames, selector 625 couples the output of encryption module 620, which is the encrypted counter block, to XOR module 605, which performs an exclusive-OR operation on the received frame and the encrypted counter block. Once the received frame is encrypted, the exclusive-OR operation decrypts the received frame using the encrypted counter block. 3 and 4, the received frame includes error detection information, so that decoding the received frame provides the decoded data from the frame and the error detection information from the frame. The decoded frame including the error correction information is output from the XOR module 605 to the error detection module 515.

[0063] Referring back to FIG. 5 , the error detection module 515 receives a decrypted frame from the descrambler, where the decrypted frame includes error detection information. The error detection module 515 applies one or more error detection methods to the error detection information to determine whether the decrypted frame contains errors. For example, the error detection module 515 generates a check value from the decrypted frame and compares the check value to the error detection information included in the frame. If the check value differs from the error detection information included in the frame, the error detection module 515 determines that the frame contains one or more errors from the transmission. In contrast, if the check value matches the error detection information included in the frame, the error detection module 515 determines that the frame was received without errors from the transmission. In another embodiment, the error detection module 515 determines whether the remainder when the frame including the error detection information is divided by a divisor used by the error detection module 310 of the transmitter is zero. If the remainder is zero, the error detection module 515 determines that the frame does not contain errors, while if the remainder is non-zero, the error detection module 515 determines that the frame contains errors. In some embodiments, the error detection module 515 performs one or more error correction processes on the frame in which an error is detected, or in other embodiments, the error detection module 515 initiates a request to the transmitter for retransmission of the frame containing the error.

[0064] Frames that are determined to be error-free are sent from the error detection module 515 to the layer preparation module 520. Layer Preparation Module 520.

[0065] It checks the integrity of the packets contained in the frames from the layer preparation module 520 and sends the packets and descriptions of the packets to the transaction layer 205 for routing to a processing core or another receiving device.

[0066] For further illustration, FIG. 7 shows a flowchart of an exemplary method for transmitting encrypted frames using a counter used by the transmitter. The method shown in FIG. 7 includes a training mode that synchronizes the transmitter counter and the receiver counter. In contrast to conventional methods in which the receiver counter and the receiver counter are refreshed to a common value for synchronization when the link between the transmitter and receiver is refreshed, the method of FIG. 7 allows for automatic synchronization of the receiver counter and the transmitter counter when the link is retrained. In addition, the method of FIG. 7 encrypts data after error detection information is added to the data, providing increased security from active attacks that modify data transmitted between the transmitter and receiver because such modifications introduce errors into the data.

[0067] A transmitter, such as the transmitter described in conjunction with FIG. 3, transmits an initial training frame to a receiver during training mode (705). The initial training frame is unencrypted and is included in a set of training frames, where the training frame has a value known to the transmitter and the receiver. The training frames are also transmitted in an order specified by the set, allowing the receiver to determine expected values ​​for the training frame. The transmitter scrambles the initial training frame before transmission, as further described above in conjunction with FIGS. 3 and 4. For example, the transmitter combines the training frame with the output of a counter, such as a linear feedback shift register (LFSR), to increase the number of transitions between values ​​of the initial training frame. Because the counter is free-running, the counter is continuously incremented. For example, the transmitter performs an exclusive-OR operation on the initial training frame and the output of the counter, and the result of the exclusive-OR operation is transmitted from the transmitter to the receiver (705).

[0068] As described further below in conjunction with FIG. 8, the receiver uses the initial training frame to determine an initial value for the receiver's counter. The transmitter then transmits (710) additional training frames from the set after scrambling each additional training frame. While the additional training frames of the set are unencrypted, each additional training frame is scrambled based on the output of the transmitter's counter. As the transmitter's counter is successively incremented, different additional training frames transmitted (710) at different times are scrambled using different values ​​of the transmitter's counter. In various embodiments, the initial training frame and the additional training frames each include error detection information that was added to the initial training frame and one or more additional training frames before scrambling the training frames.

[0069] After transmitting the set of training frames, or after transmitting at least a threshold amount of the sets of training frames, the transmitter transmits a control signal to the receiver (715). The control signal identifies when the transmitter begins transmitting encrypted frames to the receiver. As described further below in conjunction with FIG. 8, in response to receiving the control signal, the receiver configures itself to decrypt frames received after the control signal is received. In various embodiments, the transmitter transmits the control signal over multiple lanes that form a communication link between the transmitter and the receiver (715). Transmitting the control signal over multiple lanes provides redundancy for bit errors in the control signal that occur during transmission, increasing the likelihood that the receiver will receive the control signal.

[0070] The transmitter modifies the frame to include error detection information (720). For example, the transmitter appends the error detection information to the data included in the frame. In various embodiments, the error detection information comprises a cyclic redundancy check code that is appended to the frame, creating a modified frame that includes the data and error detection information that comprise the frame.

[0071] After transmitting the control signal, the transmitter encrypts the modified frame, including the error detection information, using the output of a counter, such as an LFSR output. As further described above in conjunction with FIGS. 3 and 4, the transmitter combines the output of the counter with a starting value using a reversible operation (e.g., XOR, concatenation, addition) to generate a unique counter block. The counter block is encrypted with a key using AES or another block cipher encryption method, and the encrypted counter block is combined with the modified frame to generate a modified encrypted frame. For example, after transmitting the control signal to the receiver (715), the transmitter separates the output of the counter from the exclusive-OR operation and combines the output of an encryption block, such as encryption module 410 in FIG. 4, with the exclusive-OR operation. Such an arrangement encrypts the modified frame, including the error detection information, by performing an exclusive-OR operation on the modified frame, including the error detection information, and the encrypted counter block that the encryption module generated from the output of the transmitter's counter. Because the modified frame includes error detection information, the transmitter encrypts both the data comprising the frame and the error detection information by encrypting the modified frame. The transmitter transmits the encrypted modified frame to the receiver 725. By encrypting the error detection information along with the data comprising the frame, the transmitter provides additional protection against modification of data transmitted over a communications link (e.g., over a network cable or other connection) during transmission and against transmission of the modified data, because the modified data would cause the receiver to detect errors based on the error detection information.

[0072]

[0023] Figure 8 is a flow chart of one embodiment of a method for decrypting received frames after locking a counter at the receiver to a counter at the transmitter. Like the method described in conjunction with Figure 7, the method described in conjunction with Figure 8 includes a training mode that synchronizes the receiver counter with the transmitter counter. In contrast to conventional methods in which the receiver counter and the receiver counter are refreshed to a common value for synchronization when the link between the transmitter and receiver is refreshed, the method of Figure 8 allows for automatic synchronization of the receiver counter and the transmitter counter when the link is retrained.

[0073] During training mode, the receiver receives an initial training frame (805). The initial training frame is unencrypted and is included in a set of training frames, where the training frame has a value known to the transmitter and the receiver. The training frames are also transmitted in an order specified by the set, allowing the receiver to determine an expected value for the training frame. In various embodiments, the initial training frame is scrambled by the transmitter prior to transmission based on the output of a counter, such as a linear feedback shift register (LFSR), at the transmitter. The receiver uses the initial training frame and the expected value for the initial training frame to determine (810) the output of the transmitter counter to be used to scramble the initial training frame, which is used as the initial value for a receiver counter, such as the receiver's LFSR.

[0074] To determine 810 the initial value of the receiver's counter from the initial training frame, the receiver determines the difference between the initial training frame and the expected value for that initial training frame. For example, the receiver determines the difference between the initial training frame and the expected value for that initial training frame by performing an exclusive OR on the initial training frame and the expected value for that initial training frame, with the output of the exclusive OR identifying the difference between the initial training frame and the expected value for that initial training frame, which is the initial value for the receiver's counter. In other embodiments, the receiver performs a different operation to determine the difference between the initial training frame and the expected value for that initial training frame to use as the initial value of the receiver's counter. The receiver sets 815 the receiver's counter to the determined initial value, allowing the receiver to estimate the value of the transmitter's counter when transmitting the initial training frame and set the receiver's counter to an initial value that matches the estimated value of the transmitter's counter.

[0075] The receiver's counter is continuously incremented (i.e., the counter is free-running), with the counter set (815) to an initial value determined (810) from the difference between the initial training frame and the expected value for this initial training frame. While the counter is incrementing, the receiver receives (820) a training frame from a set of training frames. Each training frame in the set is unencrypted but is scrambled by the transmitter before transmission. Based on incrementing the counter from the initial value using the value from the counter, the receiver descrambles (825) the training frame and determines whether the training frame matches the expected value for the training frame. For example, the receiver descrambles (825) the training frame by performing an exclusive OR on the output of the receiver's counter and the training frame when the training frame was received, and the result is a descrambled training frame. As further described above, the receiver determines the expected value for the training frame based on its position within the set of training frames. In response to determining that a threshold number of training frames received from the transmitter matches a corresponding expected value for the training frames after descrambling (825) by the receiver, the receiver determines that the receiver counter is locked or synchronized with the transmitter counter. For example, in response to a threshold number of consecutive training frames matching a corresponding expected value for the training frames after descrambling (825) by the receiver, the receiver determines that the receiver counter and the transmitter counter are synchronized. In various embodiments, the above-described synchronization of the transmitter counter and the transmitter counter is performed for each of multiple lanes of the communication link between the transmitter and receiver, allowing synchronization of the transmitter counter and the receiver counter for each individual lane.

[0076] The receiver then receives (830) a control signal from the transmitter indicating that the training mode has ended. In response to receiving (830) the control signal, the receiver modifies one or more configuration settings to decrypt subsequently received frames. For example, in response to receiving (830) the control signal, the receiver separates the output of the receiver's counter from the exclusive-OR operation and combines the output of an encryption module, such as encryption module 620 in FIG. 6, into the exclusive-OR operation. This causes the receiver to determine an exclusive-OR between the output of the encryption module, which is an encrypted counter block as further described above in conjunction with FIG. 6, and frames received after the control signal. Thus, the receiver decrypts frames received after receiving (830) the control signal.

[0077] After receiving the control signal (830), the receiver receives a frame from the transmitter (835). The frame includes data and error detection information, as further described above in conjunction with Figures 3, 4, and 7. The receiver decrypts the received frame (840) using an encrypted counter block generated from the output of the receiver's counter. As further described above, in various embodiments, the receiver decrypts the received frame (840) by performing an XOR operation on the received frame and the encrypted counter block that the encryption block generates from the output of the receiver's counter. The result of the XOR operation is the decrypted frame from the transmitter, including the error detection information.

[0078] In various embodiments, the communication link between the transmitter and the receiver includes multiple lanes, and frames are transmitted on different lanes. Thus, the transmitter, in some embodiments, transmits the encrypted modified frame using multiple lanes of the communication link. The receiver receives the encrypted modified frame from the multiple lanes and decrypts the encrypted modified frame, as further described above in conjunction with FIGS. 5, 6, and 8. In various embodiments, the transmitter modifies the number of lanes used to transmit frames to the receiver. For example, the transmitter transmits frames subsequent to a particular frame using a set of lanes that is fewer than these multiple frames. This reduction in the number of lanes used for transmission may conserve power used for transmission or may remove lanes from use for transmission when errors or performance issues occur on one or more of the lanes. Such a reduction in the lanes used to transmit data may occur without resynchronizing the transmitter and receiver counters because the synchronization of the transmitter and receiver counters described further above in conjunction with Figures 2-8 is performed for different lanes of the communication link, thereby allowing synchronization of the transmitter and receiver counters for individual lanes, thereby allowing the number of lanes used by the transmitter to be dynamically altered (e.g., reduced) without renegotiating the synchronization of the transmitter and receiver counters.

[0079] Encrypting a frame of data while the frame is scrambled prior to transmission over a communications link allows the data to be protected during transmission. To provide additional protection, error detection information is appended to the frame before transmission so that the frame includes error detection information when encrypted. Including the error detection information when encrypting the frame allows the receiver to detect errors caused by alteration of the data during transmission. To simplify encryption, the transmitter encrypts the frame using a counter used to scramble the frame prior to transmission. The output of the counter is provided to an encryption module, which outputs encrypted data for encrypting the frame. The receiver similarly provides the output of the counter used to descramble the frame to an encryption module, which outputs encrypted data for decrypting the frame. During training mode, unencrypted training frames are transmitted between the transmitter and receiver, and the receiver uses known values ​​from the training frames to determine an initial value for the receiver's counter. The initial value infers the value of the transmitter's counter used for encryption, allowing the transmitter and receiver counters to be synchronized without having to specifically negotiate starting values ​​for both the transmitter and receiver counters. Additionally, by encrypting and decrypting frames using the outputs of the transmitter counter and the receiver counter, encryption and decryption can be performed without increasing the latency of data transmission between the transmitter and receiver.

[0080] Exemplary embodiments of the present invention are described primarily in the context of a fully functional computer system for performing a context switch by replacing the address translation context used by a computer processor. However, readers skilled in the art will recognize that the present invention may also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact discs for optical drives, magnetic tape, and others as would occur to one skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means will be capable of performing the steps of the method of the present invention as embodied in a computer program product. Those skilled in the art will also recognize that while some of the exemplary embodiments described herein are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or hardware nevertheless fall well within the scope of the present invention.

[0081] It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true scope. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims.

Claims

1. 1. A method for encrypting a frame, comprising: scrambling each training frame of the set for transmission from a transmitter to a receiver, each training frame of the set being scrambled based on an output of a counter at the transmitter and the training frame, wherein each scrambled training frame is unencrypted; transmitting a control signal from the transmitter to the receiver; modifying the frame to include error detection information; after transmitting the control signal to the receiver, encrypting the modified frame including the error detection information using an encrypted counter block generated from the output of the counter; and transmitting the encrypted modified frame from the transmitter to the receiver. A method comprising:

2. The method of claim 1 , wherein the counter is incremented continuously.

3. scrambling each training frame of the set based on the output of the counter and the training frame, performing an exclusive OR operation on the training frame and the output of the counter.

2. The method of claim 1, comprising:

4. The step of transmitting the control signal to the receiver comprises: transmitting the control signal on each of a plurality of lanes comprising a connection between the transmitter and the receiver; 2. The method of claim 1, comprising:

5. encrypting the modified frame including the error detection information using the encrypted counter block generated from the output of the counter, combining the output of the counter with a start value; generating the encrypted counter block from a key and the combination of the output of the counter and the starting value; and combining the encrypted counter block with the modified frame containing the error detection information to generate the encrypted modified frame.

2. The method of claim 1, comprising:

6. combining the encrypted counter block with the modified frame including the error detection information to generate the encrypted modified frame, performing an exclusive-OR operation on the encrypted counter block and the modified frame containing the error detection information. The method of claim 5 , comprising:

7. The method of claim 1 , wherein the counter comprises a linear feedback shift register.

8. transmitting the encrypted modified frame from the transmitter to the receiver, transmitting the encrypted modified frame from the transmitter to the receiver using a plurality of lanes comprising a connection between the transmitter and the receiver; and transmitting a subsequent encrypted modified frame from the transmitter to the receiver using a set of lanes that is less than the plurality of lanes.

2. The method of claim 1, comprising:

9. 1. A method for decrypting a frame, comprising: receiving an initial training frame at a receiver from a transmitter, wherein said initial training frame is unencrypted; determining an initial value for a counter based on a difference between the initial training frame and an expected value for the initial training frame; setting the counter to the initial value; receiving a set of training frames while the counter is successively incremented from the initial value, wherein each training frame is unencrypted; descrambling each of said set of training frames using an output of said counter; receiving a control signal from the transmitter indicating a subsequent transmission of an encrypted frame including error detection information; receiving a frame including error detection information after receiving the control signal; and decrypting the frame containing error detection information using an encrypted counter block generated from the output of the counter. A method comprising:

10. determining the initial value for the counter based on the difference between the initial training frame and an expected value for the initial training frame, performing an exclusive OR operation on the initial training frame and the predicted value for the initial training frame.

10. The method of claim 9, comprising:

11. receiving a control signal from the transmitter indicating a subsequent transmission of an encrypted frame including error detection information, receiving the control signal on each of a plurality of lanes comprising a connection between the transmitter and the receiver; 10. The method of claim 9, comprising:

12. receiving the control signal from the transmitter indicating a subsequent transmission of an encrypted frame including error detection information, determining that the control signal has been received in response to the receiver determining that the control signal has been received from at least a threshold number of the plurality of lanes. The method of claim 11 further comprising:

13. The method of claim 12 , wherein the threshold number of the plurality of lanes comprises a majority of the plurality of lanes.

14. decrypting the frame containing error detection information using the encrypted counter block generated from the output of the counter, combining the output of the counter with a start value; generating the encrypted counter block from a key and the combination of the output of the counter and the starting value; and combining the encrypted counter block with the frame containing the error detection information to generate a decrypted frame containing the error detection information.

10. The method of claim 9, comprising:

15. combining the encrypted counter block with the frame including the error detection information to generate a decrypted frame including error detection information, performing an exclusive-OR operation on the encrypted counter block and the frame containing error detection information; 15. The method of claim 14, comprising:

16. receiving the frame including error detection information after receiving the control signal, receiving the frame including error detection information using a plurality of lanes comprising a connection between the transmitter and the receiver; and receiving a subsequent frame from the receiver using a set of lanes that is less than the plurality of lanes; 10. The method of claim 9, comprising:

17. 1. An apparatus for decrypting data, comprising: a computer processor; a computer memory operatively coupled to the computer processor; the computer memory having computer program instructions disposed therein, the computer program instructions, when executed by the computer processor, causing the apparatus to: receiving an initial training frame at a receiver from a transmitter, wherein said initial training frame is unencrypted; determining an initial value for a counter of the receiver based on a difference between the initial training frame and an expected value for the initial training frame; setting the counter to the initial value; receiving a set of training frames while the counter at the receiver is successively incremented from the initial value, wherein each training frame is unencrypted; descrambling each of the set of training frames using an output of the counter in the receiver; receiving a control signal from the transmitter indicating a subsequent transmission of an encrypted frame including error detection information; receiving a frame including error detection information after receiving the control signal; and decrypting the frame containing error detection information using an encrypted counter block generated from the output of the counter of the receiver. A device that performs the following.

18. decrypting the frame containing error detection information using the encrypted counter block generated from the output of the counter of the receiver, combining the output of the counter with a start value; generating the encrypted counter block from a key and the combination of the output of the counter at the receiver and the starting value; and combining the encrypted counter block with the frame containing the error detection information to generate a decrypted frame containing the error detection information.

18. The apparatus of claim 17, comprising:

19. 18. The apparatus of claim 17, wherein the frames including error detection information include frames encrypted by the transmitter based on a value determined from an output of a counter at the transmitter.

20. 20. The apparatus of claim 18, wherein the value determined from the output of the counter at the transmitter comprises an encrypted counter block generated from the output of the counter at the transmitter.

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