Chip package with embedded core chiplets - Patent Application 20070122997

Abstract

Described herein is a chip package that includes a chiplet embedded in a core of a substrate of the chip package, such as a package substrate or interposer. In one example, the chiplet includes a voltage regulation circuit coupled to an integrated circuit (IC) die attached to the substrate through a substrate core embedded inductor.

Description

[Technical Field]

[0001] Embodiments of the present invention relate generally to chip packages having chiplets embedded in a substrate core, and more particularly to chip packages having voltage regulator chiplets embedded in a core of a chip package substrate, such as a package substrate or interposer. [Background technology]

[0002] Electronic devices such as tablets, computers, copiers, digital cameras, smartphones, control systems, automated teller machines, data centers, artificial intelligence systems, and machine learning systems, among others, often use electronic components that utilize chip-package assemblies for increased functionality and component density. Traditional chip packaging methods often utilize a package substrate, often in conjunction with a through-silicon via (TSV) interposer substrate, to enable multiple integrated circuit (IC) dies to be attached to a single package substrate. The IC dies are attached to the upper side (i.e., top side) of the package substrate, and the lower side (i.e., bottom side) of the package substrate is attached to a printed circuit board (PCB). The IC dies may include memory, logic, or other IC devices.

[0003] Chip packages, especially those used in AI / ML and server applications, are attempting to include integrated voltage regulator systems. Delivering power through voltage regulators within the chip package often requires multiple voltage regulators to support each power rail, which significantly increases cost and requires a significant number of package pins to deliver power at input voltages around 1V.

[0004] To improve voltage regulator performance, some chip packages incorporate the voltage regulator (power field-effect transistor (FET)) as part of the system-on-chip (SOC) and place the inductor in the core area of ​​the package substrate. This solution is inefficient due to the IR drop connecting the SOC to the embedded inductor and the return path from the inductor to the SoC. Unfortunately, this solution requires custom SoC development for each product because the power FET is part of the SOC design.

[0005] Other chip packages place the inductor or voltage regulator chiplet on the backside of the package or on the backside of the printed circuit board (PCB). Such solutions increase the package footprint and undesirably reduce the number of available package pins. Also, placing the inductor or voltage regulator chiplet on the backside of the package or PCB creates heat dissipation challenges that require custom backside cooling solutions.

[0006] Therefore, there is a need for a chip package with an improved voltage regulation power supply design. Summary of the Invention [Means for solving the problem]

[0007] Described herein is a chip package that includes a chiplet embedded in a core of a substrate of the chip package, such as a package substrate or interposer. In one example, the chiplet includes a voltage regulation circuit coupled to an integrated circuit (IC) die attached to the substrate through a substrate core embedded inductor.

[0008] In one example, a chip package is provided that includes an integrated circuit (IC) die having functional circuitry, a substrate, and a chiplet. The IC die is mounted on the substrate. The substrate includes a core sandwiched between an upper buildup layer and a lower buildup layer. The core includes at least a first cavity, a plurality of signal transmission vias, a plurality of ground routing vias, and a plurality of power routing vias. The upper buildup layer is disposed on the core between the core and the IC die. The upper buildup layer includes routing that couples the inductor routing vias, the signal transmission vias, the ground routing vias, and the power routing vias to the functional circuitry of the IC die. The lower buildup layer is disposed on a side of the core opposite the upper buildup layer. The lower buildup layer includes routing that couples the inductor routing vias, the signal transmission vias, the ground routing vias, and the power routing vias to the functional circuitry of the IC die through the vias in the core and routing in the upper buildup layer. The chiplet is disposed in a first cavity formed in the core. The chiplet is coupled to the functional circuitry of the IC die through the upper buildup layer.

[0009] In some examples, the chiplet includes a voltage regulator circuit.

[0010] In some examples, the voltage regulator circuitry of the chiplet is coupled to an inductor disposed within the substrate.

[0011] Inductors may be made from a magnetic material that surrounds a conductor.

[0012] The chiplet may include a backside metal layer.

[0013] The backside metal layer may be connected to thermal vias that conduct heat from the chiplet to either the IC die or a stiffener connected to a lid covering the IC die.

[0014] The chiplets and inductors may reside in the same or different cavities formed in the core of the substrate.

[0015] In another example, a chip package is provided that includes an integrated circuit (IC) die having functional circuitry, a substrate, and a chiplet. The IC die is mounted on the substrate. The substrate includes a core, an upper build-up layer, and a lower build-up layer. The core has one or more cavities, a plurality of signal transmission vias, a plurality of ground routing vias, and a plurality of power routing vias. The upper build-up layer is disposed on the core between the core and the IC die. The upper build-up layer includes routing that couples the inductor routing vias, the signal transmission vias, the ground routing vias, and the power routing vias to the functional circuitry of the IC die. The lower build-up layer is disposed on a side of the core opposite the upper build-up layer. The lower build-up layer includes routing coupled to the functional circuitry of the IC die through vias in the core and routing in the upper build-up layer. The chiplet is disposed in one or more cavities formed in the core. The chiplet has a voltage regulation circuit coupled to the functional circuitry of the IC die through the upper build-up layer. In addition, an inductor is disposed in one or more cavities formed in the core. The inductor has an input and an output, the input of the inductor being coupled to an outlet of the voltage regulator circuit and the output of the inductor being coupled to functional circuitry on the IC die.

[0016] In yet another example, a method of manufacturing a chip package is provided that includes fixing chiplets and inductors in cavities formed in a substrate, forming a build-up layer on the substrate over the chiplets and inductors, the build-up layer including routing electrically coupled to the chiplets and inductors, and attaching an integrated circuit (IC) die on the build-up layer, the IC die including functional circuitry coupled by the build-up layer routing to the chiplets and inductors.

[0017] So that the above-mentioned features of the present invention can be understood in detail, a more particular description of the invention briefly summarized above will be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the invention and therefore should not be considered as limiting its scope, as the invention may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a schematic cross-sectional view of an example chip package having chiplets disposed within a core of a substrate. [Figure 2] 1 is a schematic cross-sectional view of another example of a chip package having chiplets disposed within a core of a substrate. [Figure 3A] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 3B] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 3C] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 3D] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 3E] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 3F] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 3G] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 3H] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 3I] 2A-2C illustrate substrates that can be used in the chip package of FIG. 1 during different stages of manufacture. [Figure 4] FIG. 1 is a block diagram of a method for manufacturing a chip package. [Figure 5A] 3A-3C illustrate magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 5B] 3A-3C illustrate magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 5C] 3A-3C illustrate magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 5D] 3A-3C illustrate magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 5E] 3A-3C illustrate magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 5F] 3A-3C illustrate magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 6] FIG. 1 is a block diagram of a method for manufacturing an inductor. [Figure 7A] 3A-3C show substrates with magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 7B] 3A-3C show substrates with magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 7C] 3A-3C show substrates with magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 7D] 3A-3C show substrates with magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 8] FIG. 1 is a block diagram of a method for manufacturing a substrate having a magnetic inductor. [Figure 9A]3A-3C show alternative substrates with magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 9B] 3A-3C show alternative substrates with magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 9C] 3A-3C show alternative substrates with magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 9D] 3A-3C show alternative substrates with magnetic inductors that can be used in the chip package of FIGS. 1-2 during different stages of manufacture. [Figure 10] FIG. 1 is a block diagram of a method for manufacturing a substrate having a magnetic inductor. DETAILED DESCRIPTION OF THE INVENTION

[0019] A chip package and method for manufacturing the same are provided, which includes a chiplet embedded in a core of a substrate of the chip package, such as a package substrate or interposer. The embedded chiplet may include a voltage regulation circuit that is routed through an associated inductor before connecting to an IC die of the chip package. The voltage regulation circuit includes a power routing field effect transistor (FET). The associated inductor may be embedded in the core of the substrate. The associated inductor may be an air core inductor, a magnetic inductor, or other suitable inductor.

[0020] The integrated voltage regulator solutions described herein have various different components, most or all of which are embedded in the substrate core of the package. The embedded components include at least an inductor and a voltage regulator (VR) chiplet. The capacitors of the integrated voltage regulator solution may also be embedded in the substrate core of the package, or alternatively, may be surface-mounted nearby within the chip package or PCB to which the chip package is attached. These components are interspersed within the substrate core to optimize power delivery to the chips mounted on the substrate. By having multiple VR chiplets and inductors, heat dissipation is managed to avoid hot spots. A novel multi-layer core architecture is used to optimize the embedding process and incorporate silicon chiplets into a thick core package. The thickness of the multi-layer core is tailored to improve the manufacturability of the embedding process while meeting the thermomechanical warpage requirements of the overall package. The use of a multi-layer core architecture provides short lateral connections between the inductor and the VR chiplet. In one example, the inductor is fabricated using a magnetic material to improve the efficiency of the voltage regulator and maximize current density.

[0021] In some embodiments, the magnetic material is embedded in the substrate core after the inductor is fabricated, thereby avoiding leaching of the magnetic material. For example, the inductor may be fabricated using a pre-hardened magnetic block through which routing is formed and then placed into a cavity formed in the substrate as a finished inductor.

[0022] In some embodiments, a novel backside thermal via solution is provided to improve heat conduction from the embedded VR chiplet. For example, after a backside metal layer is deposited on the VR chiplet and embedding the VR chiplet in the core of the substrate, thermal vias are formed in the backside metal layer through the upper build-up layer of the substrate to allow heat generated by the VR chiplet to reach the top surface of the substrate. From the top surface of the substrate, the heat can be dissipated through the IC die and / or through a stiffener to the lid of the package substrate. The stiffener may be integrated into the lid to improve thermal conduction.

[0023] In some embodiments, the VR chiplets and inductors are positioned side-by-side within the same cavity in the substrate core, and the resulting close proximity of the VR chiplets and inductors beneficially provides very short lateral paths between the VR chiplets and inductors, thereby improving performance.

[0024] The multi-layer core and embedding technology allows silicon components to be embedded in a thick core package, which provides high inductance while meeting the thermo-mechanical warpage requirements of the package.

[0025] Some additional benefits include one or more of: enabling high power (750-1000W) delivery while maintaining package footprint; reducing the number of on-board voltage regulators, thereby reducing the overall cost of the graphics card; improving overall power delivery efficiency and product performance by moving power delivery components closer to the IC die within the chip package; enabling modular chiplet designs where the number and location of VR chiplets can be optimized for each product without requiring a new SoC tapeout; enabling embedding of silicon components such as VR chiplets, inductors, and silicon capacitors by using a multi-layer core architecture where the thickness of the internal core is tailored to match the thickness of the embedded components; enabling efficient heat dissipation by incorporating thermal vias on the backside of the VR chiplets; enabling improved performance by using short lateral connections between inductors and VR chiplets using a multi-layer core architecture; improving the efficiency of the power delivery solution through the use of magnetic material inductors embedded within the core of the substrate; and increasing current density through the use of high-inductance magnetic inductors.

[0026] In some examples, improved voltage regulator efficiency is enabled by optimal placement of VR chiplets and inductors directly beneath the IC die within the chip package. The increased package size resulting from other solutions, such as on-board VR or backside VR, is substantially avoided. The modular solution described herein allows the same VR chiplet to be used on multiple products, thus avoiding the need for custom SOC tapeouts. Furthermore, the use of pre-fabricated magnetic slabs improves inductance and efficiency and reduces the risk of contamination of the board manufacturing line due to leaching of uncured magnetic material.

[0027] Referring to FIG. 1 , a chip package 100 is shown having at least one IC die 102 mounted on a substrate 104. The substrate 104 shown in FIG. 1 is a package substrate 104. However, the substrate 104 may alternatively be an interposer mounted to the package substrate. While only one IC die 102 is shown in FIG. 1 , the number of IC die 102 may range from one to as many as can fit within the chip package 100. The IC die 102 may be a programmable logic device such as a field programmable gate array (FPGA), a memory device, an optical device, a logic device, a processor, a mathematical engine, or other IC logic structure. Optical devices include photodetectors, lasers, light sources, etc. In the embodiment shown in FIG. 1 , the IC die 102 is attached to a top surface 140 of the substrate 104 by a solder connection that enables communication between the IC die 102 and a printed circuit board (PCB) 106 after the chip package 100 is mounted within an electronic device (not shown).

[0028] The chip package 100 further includes a stiffener 108 and a lid 110. The lid 110 is disposed on the top surface 130 of the IC die 102. The stiffener 108 is bonded to the substrate 104 and surrounds the IC die 102. The stiffener 108 may extend to a peripheral edge 142 of the substrate 104 to provide mechanical support that helps prevent the chip package 100 from bending and warping. The stiffener 108 may have a single-layer structure or a multi-layer structure. The stiffener 108 may also be part of the lid 110. To facilitate heat transfer from the IC die 102 and other components of the chip package 100 to the lid 110, the lid 110 and stiffener 108 may be fabricated from a thermally conductive material such as copper, aluminum, copper-clad aluminum, nickel-plated copper, or aluminum, among other suitable materials.

[0029] The substrate 104 generally includes a core 112 sandwiched between an upper build-up layer 114 and a lower build-up layer 116. The core 112 is generally fabricated from silicon or other rigid dielectric material. In one example, the core 112 is fabricated from an inorganic material. The core 112 includes conductive vias 124 for transferring power, ground, and data signals between the substrate 104 and the IC die 102.

[0030] The upper build-up layer 114 includes pattern routing 118 formed from multiple metal layers separated by dielectric layers. The pattern routing 118 generally includes conductive lines 120 formed from the metal layers connected by conductive vias 122. The routing 118 in the upper build-up layer 114 generally couples vias 124 formed in the core 112 with exposed pads 126 formed on the top surface 140 of the substrate 104. The exposed pads 126 are connected to the IC die 102 by solder balls 128 or other suitable connections so that functional circuitry 132 present on the IC die 102 can receive power, ground, and data signals through the substrate 104.

[0031] The lower build-up layer 116 is generally fabricated in the same manner as the upper build-up layer 114. Routing 134 in the lower build-up layer 116 generally couples vias 124 formed in the core 112 to exposed pads 146 formed on the bottom surface 144 of the substrate 104. The exposed pads 146 are connected to the PCB 106 by solder balls 148 or other suitable connections so that the functional circuitry 132 of the IC die 102 can communicate with circuitry on the PCB 106 through the substrate 104, i.e., through the circuitry of the substrate 104 formed from the routings 118, 134 in the upper and lower build-up layers 114, 116 and the vias 124 formed in the core 112.

[0032] The core 112 of the substrate 104 has one or more cavities 150 in which one or more chiplets 152 are embedded. The chiplets 152 are configured to provide a predetermined function utilized by the IC die 102. In the example shown in FIG. 1 , the chiplets 152 have an integrated voltage regulator circuit 154. The voltage regulator circuit 154 includes a power routing field effect transistor (power FET). An integrated voltage regulator (IVR) chiplet 152 is pre-formed and installed in the cavity 150 formed in the core 112 of the substrate 104. The IVR chiplet 152 is connected to Vin provided by the PCB 106 through routing 134 in the lower buildup layer 116. The output of the IVR chiplet 152 is connected to the input of an inductor 160. The output of the inductor 160 is connected to the functional circuit 132 of the IC die 102 through routing 118 in the upper buildup layer 114. Inductor 160 may be an air-core inductor formed within substrate 104 or a pre-formed inductor disposed within a cavity in core 112 of substrate 104. In one example, inductor 160 is fabricated from a pre-formed magnetic material.

[0033] A dielectric fill 156 fills one or more cavities 150, holding the inductor 160 and the chiplets 152. The dielectric fill 156 may be epoxy or other suitable potting compound. The inductor 160 and the connected IVR chiplets 152 may reside in the same or different cavities 150. In the example shown in FIG. 1, the inductor 160 and the connected IVR chiplets 152 reside in a common cavity 150 located directly below the IC die 102 to minimize routing length and improve performance.

[0034] Additionally, capacitor 158 is coupled to routing extending between the output of the inductor and IC die 102. Capacitor 158 may be disposed within a cavity formed in core 112 of substrate 104, may be surface mounted external to substrate 104, or may be attached or formed at another location on chip package 100. In FIG. 1 , capacitor 158 is shown in both alternative locations: within core 112 of substrate 104 and surface attached to top surface 140 of substrate 104.

[0035] The IVR chiplet includes a backside material layer that is connected to electrically floating routing formed in the top build-up layer 114 that functions as thermal vias. The thermal vias efficiently transfer heat from the backside material layer to the silicon of the IC die 102, where it can travel through the thermal vias to the lid 110 and cool the IVR chiplet.

[0036] FIG. 2 shows another example of a chip package 200 having at least one IC die 102 mounted on a substrate 204, the substrate 204 having a core-embedded chiplet 152. The chip package 200 of FIG. 2 is constructed essentially the same as the chip package 100 of FIG. 1, except that the IVR chiplet 152 is positioned laterally outward of the IC die 102. An inductor 160 coupled to the IVR chiplet 152 may optionally be positioned in the same cavity 150 as the IVR chiplet 152, or, as shown in FIG. 2, the inductor 160 may be positioned directly below the IC die 102. While the capacitor 158 is not shown in FIG. 2, it should be understood that the capacitor 158 is connected to the output of the inductor 160 of FIG. 2 in any of the manners described with reference to FIG. 1.

[0037] 2 , the IVR chiplet 152 is disposed below the stiffener 108, and in one example, is directly below the stiffener 108 well outside of the IC die 102. The IVR chiplet 152 includes a backside material layer 210. Electrically floating routing 212 is formed in the upper buildup layer 114 that connects to the backside material layer 210 disposed above the IVR chip 152. The electrically floating routing 212 extends upward through the upper buildup layer 114 to the stiffener 108. Thus, the electrically floating routing 212 provides a conductive heat transfer path from the backside material layer 210 disposed above the IVR chip 152, through the stiffener 108, and directly to the lid 110. This improves thermal regulation of the IVR chip 152, although in some examples, performance may not be as robust as the configuration of FIG. 1 .

[0038] Figures 3A-3I show the substrate 104 used in the chip package 100 of Figure 1 at different stages of the manufacturing method 400 shown in Figure 4. The chip package 200 of Figure 2 may be similarly manufactured, except that the inductor 160 and the IVR chiplet 152 do not share a common cavity 150 in the core 112 of the substrate 104. The method 400 may be utilized for other substrates used in chip packages having different configurations.

[0039] Step 402 of manufacturing method 400 begins with a pre-patterned core 112, as shown in Figure 3A. The pre-patterned core 112 includes the core 112 itself, with conductive vias 124 formed therein. The portion of the core 112 above the conductive vias includes a patterned metal layer that will later become part of the routing of the upper and lower build-up layers 116.

[0040] Step 402 of manufacturing method 400 continues by laminating pre-patterned core 112 with tape 302, such as die attach tape, and forming cavity 150 in core 112, as shown in FIG. 3B. Cavity 150 may be formed by drilling, milling, laser ablation, or other suitable technique. While one cavity 150 is shown in FIG. 3B, many cavities may be formed in substrate 104.

[0041] The manufacturing method 400 continues at step 404 by securing the IVR chiplet 152 (or other type of chiplet) within the cavity 150 by attaching the IVR chiplet 152 to the portion of the tape 302 exposed at the bottom of the cavity 150, as shown in FIG. 3C. Similarly, at step 404, the inductor 160 is secured within the cavity 150 by attaching the inductor 160 to the tape 302 alongside the chiplet 152. In FIG. 3C, both the inductor 160 and the IVR chiplet 152 are disposed within the same cavity 150. It is also contemplated that the inductor 160 and the IVR chiplet 152 may be disposed within separate cavities 150, such as when constructing a substrate 104 for use in the chip package 200 shown in FIG. 2.

[0042] The manufacturing method 400 continues at step 406 by filling the cavity with a dielectric fill 156, as shown in FIG. 3D. The dielectric fill 156 also extends over the core 112 of the substrate 104 and the portion of the metal layer exposed above the via 124. The dielectric fill 156 secures the IVR chiplet 152 and the inductor 160 within the cavity 150. The manufacturing method 400 continues at step 408 by removing the tape 302 from the substrate 104, as shown in FIG. 3E, thereby exposing the terminal 304 of the IVR chiplet 152 and the input 306 of the inductor 160 disposed within the cavity 150.

[0043] The manufacturing method 400 continues at step 410 by disposing a dielectric layer 308 on the bottom surface 410 of the substrate core 112, as shown in FIG. 3F. The dielectric layer 308 covers the terminals 404 of the IVR chiplets 152 and the input 406 of the inductor 160 that were previously covered by the tape 302.

[0044] 3G , the manufacturing method 400 continues with step 412 of forming a via opening 312 in the dielectric fill 156 and the dielectric layer 408. The via opening 312 may be formed by drilling or other suitable techniques. The via opening 312 exposes a portion of the metal layer formed over the via 124 on the bottom surface 144 of the substrate 104, a terminal 404 of the IVR chiplet 152, and an input 406 of the inductor 160 on the bottom surface 144 of the substrate 104. The via opening 312 also exposes a portion of the metal layer formed over the via 124 on the top surface 140 of the substrate 104, a backside metal layer 210 disposed over the IVR chiplet 152, and an output 314 of the inductor 160 exposed on the top surface 140 of the substrate 104.

[0045] 3H , the fabrication method 400 continues at step 414 by depositing a conductive seed layer 316 over the via opening 312 and the exposed surfaces of the fill material 156 and the dielectric layer 308. The conductive seed layer 316 contacts the portions of the metal layer formed over the vias 124 on the bottom surface 310 of the substrate 104, the terminals 404 of the IVR chiplets 152, and the inputs 406 of the inductors 160 exposed through the via openings 312 on the bottom surface 310 of the substrate 104. The conductive seed layer 316 also contacts the portions of the metal layer formed over the vias 124 on the top surface 140 of the substrate 104, the backside metal layer 210 disposed on the IVR chiplets 152, and the outputs 314 of the inductors 160 exposed through the via openings 312 on the top surface 140 of the substrate 104.

[0046] After seed layer deposition, lithographic patterning and plating processes are performed in step 416 to form metal lines and vias, as shown in FIG. 3I. Some of the metal lines and vias contact the backside metal layer 210 of the IVR chiplet 152 to form thermal vias. Some of the other metal lines and vias form routing 118, 134 in the upper and lower buildup layers 116. At least some of the other metal lines and vias form routing connecting the output terminal 304 of the IVR chiplet 152 to the input 406 of the inductor 160. At this point, the IC die 102 may be secured to the upper buildup layer 114 in step 416 to form the chip package 100, 200, as shown in FIGS. 1-2.

[0047] 5A-5F show a magnetic inductor 500 for use in the chip package 100 of FIG. 1 at different stages of the manufacturing method 600 shown in FIG. 6. The magnetic inductor 500 may be used as the inductor 160 shown in either of the chip packages 100, 200 shown in FIGS. 1-2. The inductor 500 manufactured using method 600 may be applied to other substrates for use in chip packages having different configurations or for other desired applications.

[0048] A method 600 for manufacturing a magnetic inductor 500 begins with a sheet 502 of magnetic material, as shown in FIG. 5A. In one example, the magnetic material is a pre-hardened ferrite sheet 502, although other magnetic materials may be used. In step 602, holes 504 are formed through the sheet 502. The holes 504 may be formed by drilling, laser, milling, or other suitable techniques.

[0049] In step 604, a seed layer 506 is deposited on the sheet of magnetic material 502, as shown in Figure 5C. The seed layer 506 also covers the sidewalls 508 of the holes 504 through the sheet 502.

[0050] In step 606, the seed layer 506 is patterned and etched, leaving the seed layer 506 covering the sidewalls 508 of the holes 504 through the sheet 502. In step 608, a first conductive material 510 is subsequently deposited on the seed layer 506, as shown in FIG. 5D. In one example, the first conductive material 510 is then plated onto the seed layer 506. The first conductive material 510 plated onto the seed layer 506 may be copper or other suitable conductive material.

[0051] In step 610, the plated through-holes 504 are then filled with a dielectric material 512. The dielectric material 512 is then ground flat to expose the ends 514 of the first conductive material 510 disposed within the through-holes 504 on the top side 516 and bottom side 518 of the sheet 502. A second conductive layer 520 is then deposited on both sides of the sheet 502. In one example, the second conductive layer 520 is plated on both sides of the sheet 502. The second conductive layer 520 disposed on the top side 516 and bottom side 518 of the sheet of magnetic material 502 contacts the exposed ends 514 of the plated conductive material 510 disposed within the through-holes 504. Thus, the second conductive layer 520 on the top side 516 and bottom side 518 of the sheet of magnetic material 502 are electrically connected by the first conductive material 510 disposed within the through-holes, as shown in FIG. 5E .

[0052] 5F, the plated sheet 502 is cut to form magnetic inductors 500, with a second conductive layer 520 disposed on a bottom 518 of the sheet of magnetic material 502 forming an input terminal of the inductor 500 and a second conductive layer 520 disposed on a top side 516 of the sheet of magnetic material 502 forming an output terminal of the inductor, the input and output terminals being connected by plated holes surrounded by the magnetic material. Optionally, the plugs may be removed.

[0053] Once the inductor 500 is formed, it may be disposed within a substrate as described above with reference to the manufacturing method 400 above, or by any suitable alternative technique.

[0054] Figures 7A-7D show a substrate 700 having a magnetic inductor 710 that can be used in the chip packages 100, 200 of Figures 1-2 during different stages of a manufacturing method 800 shown in Figure 8. The substrate 700 can alternatively be used in other chip packages.

[0055] 7A, the method 800 begins at step 802 by forming a cavity 750 in the core 730 of the substrate 700. The cavity 750 may be formed as described above with reference to the cavity 150. The cavity 750 may also be formed by alternative suitable techniques.

[0056] In step 804, as shown in Figure 7B, a block of magnetic material 710 is placed within cavity 750. Block 710 may be secured within cavity 750 by any suitable technique, for example, using a potting compound.

[0057] In step 806, vias 712 are formed through the block of magnetic material 710, as shown in Figure 7C. Vias 702 are also formed through the core 730 of the substrate 700. The vias 702, 712 may be formed by drilling or other suitable techniques. The vias 702, 712 may be formed simultaneously or at different times. The vias 702 are used to route signal transmission, ground, and power through the substrate to the IC die of the chip package.

[0058] In operation 808, as shown in FIG. 7D , the vias 702, 712 are filled with conductive material 704, 714. The vias 702, 712 may be filled with the conductive material 704, 714 by plating. A seed layer, not shown, may be disposed between the conductive material 704, 714 and the core 730 and block of magnetic material 710. In one example, the conductive material 704, 714 is copper. Alternatively, the conductive material 704, 714 may be another metal suitable for signal and / or power transmission.

[0059] After operation 808, the chiplets are similarly secured to the core 730 of the substrate 700, and then build-up layers are formed on the core 730 of the substrate 700, for example, as described above with reference to Figure 4. After the build-up layers and routing are formed on the core, the substrate 700 is used to manufacture chip packages, such as, but not limited to, the chip packages 100, 200 described above.

[0060] 9A-9D show a substrate 900 having a magnetic inductor 910 that can be used in the chip packages 100, 200 of Figures 1-2 during different stages of the manufacturing method 1000 shown in Figure 10. The substrate 900 can alternatively be used in other chip packages.

[0061] The method 1000 begins at step 1002 by forming a cavity 950 in the core 930 of the substrate 900, as shown in Figure 9A. The cavity 950 may be formed as described above.

[0062] 9B, a block of magnetic material 910 is placed within cavity 950. Block 910 may be secured within cavity 950 by any suitable technique, for example, using a potting compound. Block 910 of magnetic material includes pre-formed vias 912.

[0063] In step 1006, vias 902 are formed through core 930 of substrate 900, as shown in Figure 9C. Vias 902 may be formed by drilling or other suitable techniques. Vias 902 may be formed before or after block 910 is secured within cavity 950 of core 930 of substrate 900.

[0064] 9D, the vias 902, 912 are filled with conductive material 904, 914. The vias 902, 912 may be filled with the conductive material 904, 914 by plating. A seed layer, not shown, may be disposed between the conductive material 904, 914 and the core 930 and block of magnetic material 910. In one example, the conductive material 904, 914 is copper. Alternatively, the conductive material 904, 914 may be another metal suitable for signal and / or power transmission.

[0065] Chiplets are similarly secured to core 930 of substrate 900 before or after any one or more of steps 1002, 1004, 1006, and / or 1008. After the chiplets are secured to core 930 of substrate 900, build-up layers are formed on core 930 of substrate 900, for example, as described above with reference to Figure 4. After build-up layers and routing are formed on the core, substrate 900 is used to manufacture chip packages, such as, but not limited to, chip packages 100, 200 described above.

[0066] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, the scope of which is determined by the following claims.

Claims

1. A chip package comprising: an integrated circuit (IC) die having functional circuitry; a substrate having the IC die attached thereto; a chiplet; The substrate is a core having at least a first cavity, an inductor routing via, a plurality of signal transmission vias, a plurality of ground routing vias, and a plurality of power routing vias; an upper build-up layer disposed on the core between the core and the IC die, the upper build-up layer including routing that couples the inductor routing vias, the signal transmission vias, the ground routing vias, and the power routing vias to the functional circuitry of the IC die; a lower build-up layer disposed on a side of the core opposite the upper build-up layer, the lower build-up layer including routing coupled to the functional circuitry of the IC die through the vias of the core and the routing of the upper build-up layer; the chiplet is disposed in a first cavity formed in the core, the chiplet being coupled to the functional circuitry of the IC die through the upper build-up layer; Chip package.

2. the chiplet includes a voltage regulator circuit; The chip package of claim 1.

3. an inductor having an input and an output; the input is coupled to an outlet of the voltage regulator circuit, and the output is coupled to the functional circuitry of the IC die; The chip package of claim 2.

4. the inductor is coupled to the voltage regulator circuit through the routing of the lower build-up layer. The chip package of claim 3.

5. the inductor is disposed within the first cavity.

5. The chip package of claim 4.

6. the inductor is disposed in a second cavity formed in the core; the chiplet comprises a backside metal layer; 5. The chip package of claim 4.

7. the upper build-up layer includes a thermal via formed on the backside metal layer; 7. The chip package of claim 6.

8. a reinforcement material disposed on the substrate directly above the thermal via; a lid disposed over the IC die and the stiffener, the stiffener and the thermal vias providing an operable conductive path for conducting heat from the backside metal layer to the lid. The chip package of claim 7.

9. the chiplet comprises a backside metal layer; The chip package of claim 5.

10. the upper build-up layer is formed on the backside metal layer and includes a thermal via extending to the top surface of the substrate; 10. The chip package of claim 9.

11. the inductor is a pre-fabricated component and is secured to the substrate by a dielectric filler; The chip package of claim 5.

12. a capacitor having one terminal coupled to both the functional circuitry of the IC die and the output of the inductor; The chip package of claim 3.

13. A chip package comprising: an integrated circuit (IC) die having functional circuitry; a substrate having the IC die attached thereto; Chiplets and an inductor; The substrate is a core having one or more cavities, a plurality of signal transmission vias, an inductor routing via, a plurality of ground routing vias, and a plurality of power routing vias; an upper build-up layer disposed on the core between the core and the IC die, the upper build-up layer including routing that couples the inductor routing vias, the signal transmission vias, the ground routing vias, and the power routing vias to the functional circuitry of the IC die; a lower build-up layer disposed on a side of the core opposite the upper build-up layer, the lower build-up layer including routing coupled to the functional circuitry of the IC die through the vias of the core and the routing of the upper build-up layer; the chiplets are disposed within the one or more cavities formed in the core, the chiplets being coupled to the functional circuitry of the IC die through the upper build-up layer; the inductor is disposed within the one or more cavities formed in the core, the inductor having an input and an output, the input coupled to an outlet of the voltage regulator circuit and the output coupled to the functional circuitry of the IC die; Chip package.

14. the inductor and the chiplet are disposed within a common cavity among the one or more cavities formed in the core, the common cavity being disposed directly below the IC die; 14. The chip package of claim 13.

15. a stiffener disposed on the substrate directly above any one of the one or more cavities in which the chiplet resides; a backside metal layer formed on the chiplet; a thermal via formed on the back surface metal layer and disposed directly below the reinforcing material; a lid disposed over the IC die and the stiffener, the stiffener and the thermal vias providing an operable conductive path for conducting heat from the backside metal layer to the lid.

14. The chip package of claim 13.

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