SIN gap filling by suppressing nucleation.

Abstract

The present disclosure generally relates to a method for forming a silicon nitride layer and a silicon nitride structure on a substrate. In one embodiment, the method includes: positioning a substrate having at least one feature thereon in a process chamber; depositing a first silicon layer on the substrate and the at least one feature; nitriding the first silicon layer to form a first silicon nitride layer on the substrate and the at least one feature; selectively inhibiting silicon nucleation on a portion of the first silicon nitride layer to form an inhibited profile; selectively depositing a second silicon layer on the first silicon nitride layer according to the inhibited profile; and nitriding the second silicon layer to form a second silicon nitride layer directly on the first silicon nitride layer.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate generally to the manufacture of semiconductor components and devices. Specifically, embodiments described herein provide methods for forming silicon nitride layers on semiconductor surfaces. [Background technology]

[0002]

[0002] In semiconductor processing, the dimensions of features in fabricated devices continue to shrink. The features utilized to fabricate devices at these latest technology nodes often contain high aspect ratio structures, often requiring the trenches between the high aspect ratio structures to be filled with a gap filler. Examples of applications for gap filler layers include shallow trench isolation (STI), horizontal interconnects, vias between adjacent metal layers, intermetal dielectric layers (ILDs), pre-metal dielectric layers (PMDs), passivation layers, patterning applications, and the like. As device geometries shrink and thermal budgets decrease, filling high aspect ratio spaces without voids or seams becomes increasingly challenging due to limitations of existing deposition processes.

[0003]

[0003] Reliably filling gaps between such high-aspect-ratio structures while avoiding filler voids and seams is particularly challenging at these dimensions. Current processes for depositing gap filler materials include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), and high-density plasma chemical vapor deposition (HDP CVD), each of which has some challenges for filling small-dimension high-aspect-ratio features. Depositing gap filler materials into small, especially high-aspect-ratio features, can cause seams and voids to form within the filled features. Large seams can lead to high resistance, contamination, and loss of filler material, and can otherwise degrade the performance of integrated circuits. For example, seams can extend near field areas after the fill process and subsequently open during chemical-mechanical planarization.

[0004] Therefore, there is a need for improved methods for forming gap fill layers in trenches between high aspect ratio structures. Summary of the Invention

[0005]

[0005] The present disclosure generally relates to methods for forming silicon nitride layers and silicon nitride structures on a substrate. In one embodiment, a method for forming a silicon nitride structure on a substrate is provided. The method includes positioning a substrate having at least one feature thereon in a process chamber; depositing a first silicon layer on the substrate and the at least one feature; nitriding the first silicon layer to form the first silicon nitride layer on the substrate and the at least one feature; selectively inhibiting silicon nucleation on a portion of the first silicon nitride layer to form an inhibited profile; selectively depositing a second silicon layer on the first silicon nitride layer according to the inhibited profile; and nitriding the second silicon layer to form the second silicon nitride layer disposed directly on the first silicon nitride layer.

[0006] In one embodiment, a method for forming a silicon nitride gap fill is provided. The method includes: positioning a substrate having at least one feature thereon in a process chamber, the at least one feature extending a depth from a surface of the substrate to a bottom surface and having a width defined by a first sidewall and a second sidewall; depositing a first amorphous silicon layer over the substrate and the at least one feature; nitriding the first amorphous silicon layer to form a first silicon nitride layer over the substrate and the at least one feature; selectively oxidizing one or more portions of the first silicon nitride layer disposed on the substrate surface and on tops of the first and second sidewalls near an opening of the at least one feature in the substrate surface to form a silicon oxide layer over one or more portions of the substrate and inhibiting silicon nucleation on the oxidized portions of the first silicon nitride layer; selectively depositing a second silicon layer on the remaining unoxidized portions of the first silicon nitride layer on the substrate; and nitriding the second silicon layer to form a second silicon nitride layer disposed directly on the remaining unoxidized portions of the first silicon nitride layer.

[0007] In another embodiment, a method for forming a silicon nitride gap fill is provided, the method including: positioning a substrate having at least one feature thereon in a process chamber, the at least one feature extending a depth from a surface to a bottom surface of the substrate and having a width defined by a first sidewall and a second sidewall; performing a deposition process to deposit a first amorphous silicon layer on the substrate and the at least one feature; performing a plasma nitridation process on the substrate to convert the first amorphous silicon layer into a first silicon nitride layer; and performing a plasma oxidation process to convert one or more of the substrate and the at least one feature into a first silicon nitride layer. performing a deposition process to selectively deposit a second amorphous silicon layer on the remaining, unoxidized portions of the first silicon nitride layer on the substrate; performing a plasma nitridation process on the substrate to convert the second amorphous silicon layer to a second silicon nitride layer disposed directly on the remaining, unoxidized portions of the first silicon nitride layer; and sequentially repeating the selective plasma oxidation, selective deposition, and plasma nitridation processes to fill at least one feature with silicon nitride and form a silicon nitride gapfill. [Brief explanation of the drawings]

[0008]

[0008] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and therefore should not be considered as limiting the scope thereof, as other equally effective embodiments may also be permitted.

[0009] [Figure 1A] FIG. 1A is a schematic diagram of an exemplary process chamber that can be used to perform the method illustrated in FIG. 2, according to some embodiments of the present disclosure. [Figure 1B]

[0010] FIG. 1B is a schematic cross-sectional view of an electrostatic chuck that can be used in the apparatus of FIG. 1A, according to some embodiments of the present disclosure. [Figure 2]

[0011] FIG. 2 is a flow diagram of one embodiment of a method for forming a silicon nitride gap fill in a feature formed on a substrate using the process chamber shown in FIG. 1A, according to some embodiments of the present disclosure. [Figure 3A-D]

[0012] 3A-3D are cross-sectional views of silicon nitride gap-fill features formed by the method of FIG. 2 according to some embodiments of the present disclosure. [Figure 3E-H] 3E-3H are cross-sectional views of silicon nitride gap-fill features formed by the method of FIG. 2 according to some embodiments of the present disclosure. [Figure 3I] FIG. 3I is a cross-sectional view of a silicon nitride gap-fill feature formed by the method of FIG. 2 according to some embodiments of the present disclosure. [Figure 4]

[0013] FIG. 4 is a graph showing the incubation delay of amorphous silicon deposition on a silicon oxide surface. [Figure 5]

[0014] FIG. 5 is a flow diagram of one embodiment of a method for forming a silicon nitride gap fill in a gap feature according to some embodiments of the present disclosure.

[0010]

[0015] To facilitate understanding, wherever possible, like reference numerals have been used to designate like elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0016] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to apparatus and methods for the deposition of thin films to form interconnect structures on a substrate. To provide a thorough understanding of various implementations of the present disclosure, specific details are set forth in the following description and in Figures 1-5. Other details describing well-known methods and systems often associated with the deposition of thin films are not presented in the following disclosure to avoid unnecessarily obscuring the description of various implementations.

[0012]

[0017] Many of the details, components, and other features described herein are merely illustrative of particular implementations. Thus, other implementations may have other details, components, and features without departing from the spirit or scope of the present disclosure. Additionally, further implementations of the present disclosure may be practiced without some of the details described below.

[0013]

[0018] The development of thin film materials that can completely and efficiently fill high aspect ratio features (trenches between high aspect ratio structures) remains an elusive goal. Thin films deposited by plasma-enhanced CVD typically exhibit poor conformality, which can lead to the formation of voids inside high aspect ratio features. Thin films deposited by thermal CVD typically exhibit conformality greater than 90%. However, current methods for filling high aspect ratio features using thermal CVD typically result in the formation of seams.

[0014]

[0019] Implementations of the present disclosure improve the gap-filling capabilities of silicon nitride thin films formed in high-aspect-ratio features compared to silicon nitride thin films deposited using currently known thermal CVD techniques. Implementations described herein include suppression of silicon nucleation. In some embodiments, the method includes selective suppression (suppressed profile) of deposited silicon along a portion of the high-aspect-ratio feature and adjacent structures, followed by selective deposition with the suppressed profile. The method for selectively suppressing silicon nucleation can include exposing the silicon deposited on the feature to a direct current or remote plasma. In some embodiments, the methods described herein can be used to fill vertical features (e.g., vias) from the bottom up.

[0015]

[0020] Selective inhibition, sometimes referred to as preferential inhibition, preferential passivation, selective passivation, differential inhibition, or differential passivation, involves inhibiting subsequent silicon nucleation in a portion of a feature or structure while not inhibiting (or inhibiting nucleation to a lesser extent) nucleation in the remainder of the feature or structure. After the features and structures have been selectively inhibited, selective deposition with an inhibited profile is selective in the sense that silicon preferentially deposits in the less inhibited and uninhibited portions of the features and structures. By utilizing selective inhibition and deposition of silicon, the methods disclosed herein enable the formation of seamless silicon nitride gapfills from the bottom up. In some embodiments, the methods described herein use only relatively inexpensive precursor gases, such as silane and disilane, as opposed to the customized and expensive precursor gases of other processes. Accordingly, the disclosures described herein offer several advantages over conventional methods and techniques.

[0016]

[0021] 1A is a schematic cross-sectional view of an exemplary processing system 132 suitable for performing a deposition process according to at least one embodiment disclosed herein. Suitable chambers are available from the inventors, who have an address in Santa Clara, California. It should be understood that the system described below is an exemplary process chamber, and that other chambers, including chambers from other manufacturers, may be used with or modified to achieve embodiments of the present disclosure (e.g., method 200 described below). In some embodiments, processing system 132 may be configured to deposit thin films on substrates using chemical vapor deposition (plasma-enhanced and / or thermal) processes.

[0017]

[0022] The processing system 132 includes a process chamber 100 and a controller 110 coupled to a gas panel 130. The process chamber 100 typically includes a top wall 124, a sidewall 101, and a bottom wall 122 that define a processing space 126. A substrate support assembly 146 is disposed within the processing space 126 of the process chamber 100. The substrate support assembly 146 typically includes an electrostatic chuck 150 supported by a stem 160. The electrostatic chuck 150 may typically be fabricated from aluminum, ceramic, or other suitable materials. The electrostatic chuck 150 may be moved vertically within the process chamber 100 using a displacement mechanism (not shown).

[0018]

[0023] A vacuum pump 102 is connected to a port formed in the bottom of the process chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure within the process chamber 100. The vacuum pump 102 also evacuates post-treatment gases and process by-products from the process chamber 100.

[0019]

[0024] The substrate processing system 132 may further include additional equipment for controlling the chamber pressure, such as valves (e.g., throttle valves and isolation valves) positioned between the process chamber 100 and the vacuum pump 102 to control the chamber pressure.

[0020]

[0025] A gas distribution assembly 120 having a plurality of apertures 128 is disposed at the top of the process chamber 100 above the electrostatic chuck 150. The apertures 128 of the gas distribution assembly 120 are utilized to introduce process gases into the process chamber 100. The apertures 128 may have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for different process requirements. The gas distribution assembly 120 is connected to a gas panel 130 that allows various gases to be supplied to the processing space 126 during processing. A plasma is formed from the process gas mixture exiting the gas distribution assembly 120 to enhance the thermal decomposition of the process gases, resulting in the deposition of material on the surface 191 of the substrate 190.

[0021]

[0026] The gas distribution assembly 120 and the electrostatic chuck 150 may form a pair of spaced-apart electrodes within the process space 126. One or more RF power sources 140 provide a bias potential to the gas distribution assembly 120 through an optional matching network 138 to facilitate generation of a plasma between the gas distribution assembly 120 and the electrostatic chuck 150. Alternatively, the RF power sources 140 and the matching network 138 may be coupled to the gas distribution assembly 120, the electrostatic chuck 150, or both the gas distribution assembly 120 and the electrostatic chuck 150, or may be coupled to an antenna (not shown) located outside the process chamber 100. In some implementations, the RF power sources 140 may generate power at frequencies of 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 Mhz, or 100 MHz. In one implementation, the RF power source 140 can provide from about 100 watts to about 3000 watts at a frequency of from about 50 kHz to about 13.6 MHz, and in another implementation, the RF power source 140 can provide from about 500 watts to about 1800 watts at a frequency of from about 50 kHz to about 13.6 MHz.

[0022]

[0027] The controller 110 includes a central processing unit (CPU) 112, memory 116, and support circuits 114 that are utilized to control the process sequence and regulate gas flow from the gas panel 130. The CPU 112 may be any form of general-purpose computer processor that may be used in an industrial environment. Software routines may be stored in the memory 116, such as random access memory, read-only memory, floppy, or hard disk drive, or other form of digital storage. The support circuits 114 are conventionally coupled to the CPU 112 and may include cache, clock circuits, input / output systems, power supplies, and the like. Bidirectional communication between the controller 110 and the various components of the substrate processing system 132 is handled through a number of signal cables collectively referred to as a signal bus 118, some of which are shown in FIG. 1 .

[0023]

[0028] 1B is a schematic cross-sectional view of a substrate support assembly 146 used in the processing system of FIG. 1A. As shown in FIG. 2, the electrostatic chuck 150 may include a heater element 170 suitable for controlling the temperature of a substrate 190 supported on an upper surface 192 of the electrostatic chuck 150. The heater element 170 may be embedded in the electrostatic chuck 150. The electrostatic chuck 150 may be resistively heated by applying a current from a heater power supply 106 to the heater element 170. The heater power supply 106 may be coupled through an RF filter 158. The RF filter 158 may be used to protect the heater power supply 106 from RF energy. The heater element 170 may be fabricated from a nickel-chromium wire enclosed within a sheathed tube of a nickel-iron-chromium alloy (e.g., INCOLOY®). The current supplied by the heater power supply 106 is regulated by the controller 110 to control the heat generated by the heater element 170 and thus maintain the substrate 190 and electrostatic chuck 150 at a substantially constant temperature during film deposition. The current supplied can be adjusted to selectively control the temperature of the electrostatic chuck 150 between about −50 degrees Celsius and about 600 degrees Celsius.

[0024]

[0029] 1, in a conventional manner, a temperature sensor 172, such as a thermocouple, may be embedded in the electrostatic chuck 150 to monitor the temperature of the electrostatic chuck 150. The measured temperature is used by the controller 110 to control the power supplied to the heater element 170 to maintain the substrate at a desired temperature.

[0025]

[0030] The electrostatic chuck 150 includes a chucking electrode 152, which may be a mesh of conductive material. The chucking electrode 152 may be embedded in the electrostatic chuck 150. The chucking electrode 152 is coupled to a chucking power supply 154, which, when energized, electrostatically clamps a substrate 190 to an upper surface 192 of the electrostatic chuck 150.

[0026]

[0031] The chuck electrode 152 may be configured as a monopolar or bipolar electrode, or may have another suitable configuration. The chuck electrode 152 may be coupled to a chuck power supply 154 through an RF filter 156, which provides direct current (DC) power for electrostatically clamping the substrate 190 to the upper surface 192 of the electrostatic chuck 150. The RF filter 156 prevents the RF power utilized to form a plasma inside the process chamber 100 from damaging electrical equipment outside the chamber or causing electrical disturbances outside the chamber. The electrostatic chuck 150 may be fabricated from a ceramic material such as AlN or Al2O3. Alternatively, the electrostatic chuck 150 may be fabricated from a polymer such as polyimide, polyetheretherketone (PEEK), polyaryletherketone (PAEK), and the like.

[0027]

[0032] A power application system 162 is coupled to the substrate support assembly 146. The power application system 162 may include the heater power supply 106, the chuck power supply 154, a first radio frequency (RF) power supply 180, and a second RF power supply 182. Additionally, an implementation of the power application system 162 may include the controller 110, a sensor device 164 in communication with the controller 110, and both the first RF power supply 180 and the second RF power supply 182.

[0028]

[0033] The controller 110 may also be utilized to control a plasma from the processing gas by application of RF power from the first RF power source 180 and the second RF power source 182 to deposit a layer of material on the substrate 190.

[0029]

[0034] As described above, the electrostatic chuck 150 includes a chucking electrode 152, which in one embodiment functions to chuck the substrate 190 and also functions as a first RF electrode. The electrostatic chuck 150 may also include a second RF power source 166, which, in conjunction with the chucking electrode 152, may apply RF power to tune the plasma. The first RF power source 180 may be coupled to the second RF electrode 166, and the second RF power source 182 may be coupled to the chuck electrode 152. The first RF power source 180 and the second RF power source 182 may be provided with a first matching network and a second matching network, respectively. The second RF electrode 166 may be a solid metal plate of a conductive material as shown. Alternatively, the second RF electrode 166 may be a mesh of a conductive material.

[0030]

[0035] The first RF power source 180 and the second RF power source 182 may generate power at the same frequency or at different frequencies. In some implementations, one or both of the first RF power source 180 and the second RF power source 182 may individually generate power at a frequency between about 350 KHz and about 100 MHz (e.g., 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, or 100 MHz). In some implementations, the first RF power source 180 may generate power at a frequency of 13.56 MHz, and the second RF power source 182 may generate power at a frequency of 2 MHz, or vice versa. The RF power from one or both of the first RF power source 180 and the second RF power source 182 may be varied to tune the plasma. For example, the sensor device 164 may be used to monitor the RF energy from one or both of the first RF power source 180 and the second RF power source 182. Data from the sensor device 164 is communicated to the controller 110 , which can be utilized to vary the power applied by the first RF power source 180 and the second RF power source 182 .

[0031]

[0036] Other deposition chambers may also benefit from the present disclosure, and the parameters listed above may vary depending on the particular deposition chamber used to form the amorphous carbon layer. For example, other deposition chambers may have larger or smaller volumes and require greater or lesser gas flow rates than those described for deposition chambers available from the applicant.

[0032]

[0037] FIG. 2 is a flow diagram of an exemplary method 200 for forming a silicon nitride gapfill in a feature on a substrate using the process chamber 100 shown in FIG. 1A , according to some embodiments described herein. The term “feature,” as used in this context, refers to any irregular shape intentionally formed on a surface. The feature shape can be any suitable shape, including, but not limited to, trenches and cylindrical vias. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom, and generally cylindrical sidewalls. Other examples of features include, but are not limited to, lines, contact holes, through-holes, or other feature definitions utilized in semiconductor devices, solar devices, or other electronic devices, such as high-ratio contact plugs. The features can have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1 or greater.

[0033]

[0038] However, one skilled in the art will appreciate that the described precursors and methods are not limited to gap-fill applications and can be used for other films as well.

[0034]

[0039] In one embodiment, method 200 begins in step 202 by positioning a substrate having features, such as substrate 302 shown in FIG. 3, within the interior processing space 126 of process chamber 100 for processing. In one embodiment, the substrate, such as substrate 302, is transferred into process chamber 100 and onto substrate support assembly 146 by any suitable means, such as by a substrate transfer port (not shown). The substrate support assembly 146 can be adjusted to a processing position by an actuator (not shown). In one embodiment, substrate support assembly 146 can include an electrostatic chuck 150 for securing substrate 302. Substrate 302 can include one or more materials, such as nitrides, oxides, silicon, and / or metals (e.g., tungsten, molybdenum, titanium, etc.). While FIG. 3A shows substrate 302 with a single feature for illustrative purposes, one skilled in the art will understand that multiple features may be present.

[0035]

[0040] 3A, substrate 302 has a substrate surface 304 that includes at least one feature that forms an opening in substrate surface 304. In one embodiment, the at least one feature includes a trench 305 that extends a depth D from substrate surface 304 to a bottom surface 306. Trench 305 has a first sidewall 308 and a second sidewall 310 that define a width W of trench 305. The open area formed by sidewalls 308, 310 and bottom surface 306 is also referred to as a gap.

[0036]

[0041] In step 204, one cycle of a deposition process is performed on the substrate 302 in the process chamber 100 to deposit a first amorphous silicon layer 312 on the substrate 302. In one embodiment, the process chamber 100 can be a CVD chamber such as that shown in FIG. 1A, and the first amorphous silicon layer 312 can be deposited on the substrate 302 using a thermal CVD process. The thermal CVD process for depositing the first amorphous silicon layer 312 includes flowing a raw material-containing precursor gas from the gas panel 130 into the interior processing space 126 of the chamber 100. In one embodiment, the raw material-containing precursor gas for forming the first amorphous silicon layer 312 can include silicon-precursor gases, such as silane, disilane, tetrasilane, and other higher silanes, dichlorosilane, trichlorosilane, and silicon tetrachloride. The raw material-containing precursor gas is provided to the processing space 126, for example, through the gas distribution assembly 120, such that the raw material-containing precursor gas is uniformly distributed within the processing space 126. In one embodiment, the plurality of apertures 128 of the gas distribution assembly 120 are radially distributed, and the gas flow to each of the plurality of apertures 128 can be separately controlled to further promote gas uniformity within the processing space 126.

[0037]

[0042] The source-containing precursor gas is then thermally decomposed in the interior processing space 126, and a first amorphous silicon layer 312 is deposited on the substrate surface 304 and in the trenches 305. For the deposition of the first amorphous silicon layer 312, during the thermal deposition process, the temperature of the substrate support assembly 146 in the chamber 100 can be set between about 100 degrees Celsius and about 1,000 degrees Celsius, for example, between about 400 degrees Celsius and about 600 degrees Celsius, and the pressure in the chamber can be between about 10 mTorr and about 760 Torr, for example, about 300 Torr.

[0038]

[0043] 3B, the CVD process may deposit a first amorphous silicon layer 312 over the substrate surface 304 and trench 305, including the bottom surface 306 and the first and second sidewalls 308, 310. The deposited amorphous silicon layer may have a thickness between about 2 Å and about 5,000 Å.

[0039]

[0044] In step 206, an amorphous silicon nitridation process is performed on the substrate 302 in the chamber 100 to treat the first amorphous silicon layer 312 and convert it to a first silicon nitride layer 314. The nitridation process may include performing a thermal nitridation process or a plasma-based nitridation process. Silicon nitridation performed using a plasma process treats the amorphous silicon layer to form a conformal layer of silicon nitride having a thickness of about 5 Å to about 60 Å.

[0040]

[0045] The plasma-based nitridation process involves flowing process gases, including, but not limited to, N, NH, hydrazine (N, H), H, noble gases (He, Ar, Ne, Kr, Xe), or combinations thereof, from the gas distribution assembly 120 to generate a plasma. The plasma can be generated in the plasma region between the substrate and the electrostatic chuck 150 using process gases introduced from one or both of a first RF power source 180 and a second RF power source 182 to apply a first RF bias to the electrostatic chuck. Typically, the RF power can be from about 1 kW to about 10 kW, although other power levels are contemplated.

[0041]

[0046] When the plasma is ignited, radical nitrogen containing species formed from the nitrogen-containing process gas react with the substrate 302. Such radical nitrogen containing species can include N and / or NH, e.g., N * and / or NH *During the nitridation process, the radical nitrogen containing species saturates on the surface of the amorphous silicon layer 312 due to a high flux of the species, such that diffusion of the reactive species becomes the dominant factor. As shown in FIG. 3C , the diffusion and reaction of the radical nitrogen containing species converts amorphous silicon atoms in the amorphous silicon layer 312 to SiN, thereby converting the first amorphous silicon layer 312 into a first silicon nitride layer 314.

[0042]

[0047] In step 206, the process chamber 100 for the nitridation process may be operated at a temperature of about 100° C. to about 1200° C., e.g., about 150° C. to about 650° C.; and / or a pressure of about 0.025 Torr (25 milliTorr (mTorr)) to about 5 Torr, e.g., about 0.050 Torr (50 mTorr) to about 2 Torr. However, other temperatures and pressures are contemplated. The RF power may be controlled between about 25 Watts and about 2000 Watts, e.g., between about 100 Watts and about 800 Watts, e.g., about 400 Watts. A plasma-forming gas, e.g., N2 gas, may be supplied at a rate between about 1000 sccm and about 5000 sccm, e.g., about 2000 sccm. In another embodiment, NH3 plasma-forming gas may be supplied at a rate between about 500 sccm and about 2000 sccm, e.g., about 1000 sccm.

[0043]

[0048] Step 208 selectively inhibits silicon nucleation at portions of the substrate surface 304 and sidewalls 308, 310 near the opening of the trench 305, but does not selectively inhibit nucleation inside the trench 305 at the bottom 306 and portions of the sidewalls 308, 310 near the bottom 306. In one embodiment, selective inhibition of portions of a feature on the substrate 304 can include exposing the feature to active species that passivate the feature surface. In the present disclosure, portions of the first silicon nitride layer 314 are passivated by exposing them to an oxygen-based plasma, where oxygen atoms from the plasma replace nitrogen atoms in the silicon nitride film, thereby oxidizing the silicon nitride (SiN) and forming silicon oxide (SiO).

[0044]

[0049] In step 208, selective inhibition is performed by selectively oxidizing the aforementioned portions of the substrate surface 304 and trench 305. As shown in FIG. 3D , portions of the first silicon nitride layer 314 along the substrate surface 304 adjacent the opening of trench 305 and portions of the sidewalls 308, 310 near the opening of trench 305 are selectively oxidized and converted from SiN to SiO to form a silicon oxide layer 316. The oxidation of SiN in the first silicon nitride layer 314 selectively inhibits silicon nucleation for purposes of this disclosure due to the delayed incubation of amorphous silicon deposition observed on silicon oxide surfaces during thermal CVD processes. FIG. 4 illustrates the delayed deposition of amorphous silicon on silicon oxide surfaces compared to non-oxidized silicon surfaces, such as SiN layer surfaces. This delayed incubation on the silicon oxide surface can then be utilized in a next step to selectively deposit amorphous silicon on the uninhibited portions of trench 305 .

[0045]

[0050] Exemplary plasma-forming gases that may be flowed into the processing space 126 of the chamber 100 for the oxidation plasma treatment process of step 208 include oxygen-containing gases, such as oxygen (O) and nitrous oxide (NO). In some embodiments, tailoring the suppressed profile at the substrate 302 (e.g., selective oxidation of portions of the substrate surface 304 and sidewalls 308, 310 near the opening of the trench 305) may include appropriately adjusting and selecting one or more of the substrate bias power, plasma power, process pressure, gas type, exposure time, and other process parameters, such as the spacing between the substrate support assembly 146 and the gas distribution assembly 120. When properly adjusted, oxygen radicals from the ignited plasma may contact and react with only portions of the SiN layer deposited on the substrate surface 304 and sidewalls 308, 310 near the opening of the trench 305, thereby selectively oxidizing and converting only those portions of the first silicon nitride layer 314 to silicon oxide.

[0046]

[0051] In one embodiment, the process pressure is controlled between about 0.1 Torr and about 100 Torr (e.g., between about 0.1 Torr and about 80 Torr, between about 1 Torr and about 20 Torr, or between about 7 Torr and about 30 Torr). In one implementation, the process temperature is between about 100 degrees Celsius and about 900 degrees Celsius (e.g., between about 125 degrees Celsius and about 350 degrees Celsius, e.g., between about 200 degrees Celsius and about 300 degrees Celsius, e.g., between about 164 degrees Celsius and about 340 degrees Celsius). The RF power can be controlled between about 25 watts and about 2000 watts, e.g., between about 100 watts and about 800 watts, e.g., about 400 watts. A plasma-forming gas, e.g., O2 gas, can be supplied at between about 5 sccm and 200 sccm.

[0047]

[0052] Once portions of the first silicon nitride layer 314 along the substrate surface 304 adjacent the opening of the trench 305 and portions of the sidewalls 308, 310 near the opening of the trench 305 have been selectively inhibited by selective oxidation, a thermal CVD process is then performed in step 210 to selectively deposit a second amorphous silicon layer 318 on the remaining uninhibited / unoxidized portions 314 of the first silicon nitride layer according to an inhibited profile. The selective deposition according to an inhibited profile is selective in the sense that the thermal CVD process of step 410 is performed only for a period (or a shorter period) during which amorphous silicon grows first and preferentially only on the unoxidized silicon surfaces. Thus, in one embodiment, the thermal CVD process is performed for about 1 to 4 minutes, e.g., about 2 to 3 minutes. As shown in FIG. 3E, the selective deposition of amorphous silicon forms a second amorphous silicon layer 318 only on the uninhibited portions of the first silicon nitride layer 314 in the trench 305.

[0048]

[0053] In step 212, as shown in FIG. 3F, an amorphous silicon nitridation process similar to the nitridation process performed in step 206 is performed in process chamber 100 to treat second amorphous silicon layer 318 and convert second amorphous silicon layer 318 into second silicon nitride layer 320 formed in trench 305.

[0049]

[0054] The selective oxidation, selective deposition, and nitridation processes in steps 208, 210, and 212 can be repeated sequentially to fill trench 305. In some embodiments, the number of cycles can depend on the size and depth of the feature to be filled. After second silicon nitride layer 320 is formed in trench 305, the selective plasma oxidation process is also repeated to reinforce the silicon oxide layer 316's silicon nucleation suppression. FIG. 3G shows a third amorphous silicon layer 322 selectively deposited on second silicon nitride layer 320 and subsequently converted to third silicon nitride layer 324 shown in FIG. 3H. FIG. 31 shows a silicon nitride gapfill 326 formed in trench 305 after steps 208, 210, and 212 have been repeated a sufficient number of cycles to completely fill trench 305 with a silicon nitride layer.

[0050]

[0055] FIG. 5 is a flow diagram of one embodiment of a method 500 for forming a silicon nitride gap fill in a gap feature, according to some embodiments of the present disclosure.

[0051]

[0056] The method 500 begins in step 502 by positioning a substrate having gap features within the interior processing volume 126 of the process chamber 100 for processing. In one embodiment, the substrate is transferred into the process chamber 100 and onto the substrate support assembly 146 by any suitable means, for example, by a substrate transfer port (not shown).

[0052]

[0057] In step 504, a deposition process is performed in the process chamber 100 to deposit a first conformal amorphous silicon layer over the substrate and the gap features.

[0053]

[0058] In step 506, a nitridation process is performed to convert the first conformal amorphous silicon layer into a first silicon nitride layer. After the nitridation process, the first silicon nitride layer is disposed directly on the substrate and the gap features.

[0054]

[0059] In step 508, a selective inhibition process is performed according to an inhibition profile to selectively inhibit silicon nucleation on the first silicon nitride layer disposed on portions of the substrate and gap feature. In one embodiment, the inhibited profile of the substrate and gap feature includes the substrate surface above the field of the opening of the gap feature and the top of the sidewall within the gap feature near the opening. Selective inhibition, which may also be referred to as preferential inhibition, preferential passivation, selective passivation, differential inhibition, or differential passivation, involves inhibiting subsequent silicon nucleation in portions of the substrate and gap feature while not inhibiting (or inhibiting nucleation to a lesser extent) nucleation in remaining portions of the substrate and gap feature.

[0055]

[0060] Selective suppression can include selectively exposing portions of the substrate and gap features to activated species of a plasma according to a suppression profile. In one embodiment, the substrate and gap features are selectively suppressed by selectively exposing them to a plasma generated from a molecular oxygen-containing gas in a process chamber. The desired suppression profile can be created by appropriately selecting one or more of the suppression chemistry, substrate bias power, plasma power, process pressure, exposure time, and other processing parameters, such as the spacing between the substrate and the showerhead of the process chamber.

[0056]

[0061] Once the selective inhibition process has been performed, method 400 can proceed to step 510, which includes selectively depositing a second amorphous silicon layer with an inhibited profile. Step 508 can include one or more CVD and / or atomic layer deposition (ALD) processes, including thermal and plasma CVD and / or ALD processes. The deposition is selective in the sense that during the deposition process, amorphous silicon grows preferentially on the less inhibited and uninhibited portions of the substrate surface and gap features. The deposition process may be performed for a limited time during which the inhibition of silicon nucleation is effective. In one embodiment, step 510 includes selectively depositing amorphous silicon at the bottom or within the gap features.

[0057]

[0062] In step 512, an amorphous silicon nitridation process similar to the nitridation process performed in step 406 is performed in process chamber 100 to treat the second amorphous silicon layer and convert it into a second silicon nitride layer. In one embodiment, the second silicon nitride layer formed in step 512 is disposed on top of the first silicon nitride layer in the gap feature.

[0058]

[0063] The selective inhibition, selective deposition, and nitridation processes in steps 508, 510, and 512 may be repeated sequentially until the gap feature is completely filled with silicon nitride.

[0059]

[0064] Using the aspects described herein, it has been found that, in some embodiments, features on a substrate, such as trenches, can be seamlessly filled from the bottom up with a layer of SiN by using the cyclic amorphous silicon deposition, nitridation, and selective oxidation processes disclosed herein to form a SiN gapfill. In one embodiment, the cyclic deposition, nitridation, and oxidation processes disclosed herein are performed in situ in the same process chamber 100, which may eliminate the need for substrate transfer and the use of expensive cluster systems. Furthermore, because the deposition process utilized herein only requires the deposition of amorphous silicon, the present disclosure enables the formation of a seamless, complete SiN gapfill using inexpensive silicon-precursor gases, such as silane and disilane, compared to other deposition methods that may require expensive, specialized precursors.

[0060]

[0065] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A method for forming a silicon nitride structure, comprising: Positioning a substrate having at least one feature thereon in a process chamber; depositing a first silicon layer over the substrate and the at least one feature; nitriding the first silicon layer to form a first silicon nitride layer on the substrate and the at least one feature; selectively inhibiting silicon nucleation on portions of the first silicon nitride layer to form an inhibited profile; selectively depositing a second silicon layer on the first silicon nitride layer according to the constrained profile; and nitriding the second silicon layer to form a second silicon nitride layer directly on the first silicon nitride layer. A method comprising:

2. the at least one feature extends a depth from a substrate surface to a bottom surface and has a width defined by a first sidewall and a second sidewall, and the method comprises: Sequentially repeating the selective inhibition process, the selective deposition process, and the nitridation process to fill the at least one feature with silicon nitride to form a silicon nitride gapfill. The method of claim 1 further comprising:

3. The method of claim 2 , wherein the at least one feature is substantially seam-free within the silicon nitride gap fill.

4. 10. The method of claim 1, wherein depositing the first silicon layer and selectively depositing the second silicon layer comprises performing a thermal CVD process or a thermal ALD process.

5. 2. The method of claim 1, wherein selectively inhibiting silicon nucleation on a portion of the first silicon nitride layer comprises selectively oxidizing the portion of the first silicon nitride layer to a silicon oxide layer.

6. 5. The method of claim 4, wherein depositing the first silicon layer and selectively depositing the second silicon layer comprises flowing a raw material-containing precursor gas into an interior processing space of a process chamber, the raw material-containing precursor gas being selected from the group consisting of silane, disilane, tetrasilane and other higher silanes, dichlorosilane, trichlorosilane, and silicon tetrachloride, and thermally decomposing the precursor gas within the interior processing space.

7. The method of claim 1 , wherein nitriding the first silicon layer and the second silicon layer comprises performing a plasma nitridation process in the process chamber.

8. 2. The method of claim 1, wherein selectively depositing a second silicon layer comprises performing a thermal CVD process in the process chamber for a period of time that is shorter than a SiO incubation delay period, the SiO incubation delay period comprising the period of time required for amorphous silicon to first be deposited on a silicon oxide surface in a thermal CVD process.

9. 10. The method of claim 1, wherein selectively depositing a second silicon layer comprises performing a thermal ALD process in the process chamber for a period of time that is shorter than a SiO incubation delay period, the SiO incubation delay period comprising the period of time required for amorphous silicon to first be deposited on a silicon oxide surface in a thermal ALD process.

10. 2. The method of claim 1 , wherein the inhibited profile comprises inhibited silicon nucleation on one or more portions of the first silicon nitride layer disposed on the substrate surface and on a top of a first sidewall and a second sidewall near an opening of the at least one feature in the substrate surface.

11. The method of claim 1 , wherein the first silicon layer comprises an amorphous silicon layer.

12. 1. A method for forming a silicon nitride gap fill, comprising: Positioning a substrate having at least one feature thereon in a process chamber, the at least one feature extending a depth from a surface of the substrate to a bottom surface and having a width defined by a first sidewall and a second sidewall; depositing a first amorphous silicon layer over the substrate and the at least one feature; nitriding the first amorphous silicon layer to form a first silicon nitride layer over the substrate and the at least one feature; selectively oxidizing one or more portions of the first silicon nitride layer disposed on the substrate surface and on tops of the first sidewall and the second sidewall near an opening of the at least one feature in the substrate surface to form a silicon oxide layer on one or more portions of the substrate and inhibit silicon nucleation on the oxidized portions of the first silicon nitride layer; selectively depositing a second silicon layer on the remaining unoxidized portions of the first silicon nitride layer on the substrate; and nitriding the second silicon layer to form a second silicon nitride layer disposed directly on the remaining unoxidized portion of the first silicon nitride layer. A method comprising:

13. 13. The method of claim 12, further comprising sequentially repeating the selective oxidation process, the selective deposition process, and the nitridation process to fill the at least one feature with silicon nitride to form a silicon nitride gap fill, wherein the at least one feature is substantially seam-free within the silicon nitride gap fill.

14. 13. The method of claim 12, wherein depositing the first amorphous silicon layer and selectively depositing the second silicon layer comprises performing a thermal CVD process or a thermal ALD process.

15. 13. The method of claim 12, wherein depositing the first amorphous silicon layer and selectively depositing the second silicon layer comprises flowing a raw material-containing precursor gas into an interior processing space of a process chamber, the raw material-containing precursor gas being selected from the group consisting of silane and disilane, and thermally decomposing the precursor gas within the interior processing space.

16. 13. The method of claim 12, wherein nitriding the first silicon layer and the second silicon layer comprises performing a plasma nitridation process in the process chamber.

17. 13. The method of claim 12, wherein selectively depositing the second silicon layer comprises performing a CVD or ALD process for a period of time that is shorter than a SiO incubation delay period, the SiO incubation delay period comprising the period of time it takes for amorphous silicon to first be deposited on the silicon oxide surface in a CVD or ALD process, respectively.

18. 1. A method for forming a silicon nitride gap fill, comprising: Positioning a substrate having at least one feature thereon in a process chamber, the at least one feature extending a depth from a surface of the substrate to a bottom surface and having a width defined by a first sidewall and a second sidewall; performing a deposition process to deposit a first amorphous silicon layer over the substrate and the at least one feature; performing a plasma nitridation process on the substrate to convert the first amorphous silicon layer into a first silicon nitride layer; performing a plasma oxidation process to selectively oxidize one or more portions of the first silicon nitride layer over one or more portions of the substrate and the at least one feature; performing a deposition process to selectively deposit a second amorphous silicon layer on the remaining unoxidized portions of the first silicon nitride layer on the substrate; performing the plasma nitridation process on the substrate to convert the second amorphous silicon layer into a second silicon nitride layer disposed directly on the remaining unoxidized portion of the first silicon nitride layer; and sequentially repeating the selective plasma oxidation process, the selective deposition process, and the plasma nitridation process to fill the at least one feature with silicon nitride to form the silicon nitride gapfill. A method comprising:

19. The method of claim 18 , wherein the at least one feature is substantially seam-free within the silicon nitride gap fill.

20. 20. The method of claim 18, wherein performing the deposition process to selectively deposit the second amorphous silicon layer comprises performing a CVD process or an ALD process for a period of time that is shorter than a SiO incubation delay period, the SiO incubation delay period comprising the period of time it takes for amorphous silicon to first be deposited on a silicon oxide surface in a CVD process or an ALD process, respectively.

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