Back contacts for stacked field-effect transistors.

Abstract

Disclosed are embodiments of a semiconductor device and a method for fabricating the same. The device includes a first gate stack disposed above a bottom FET, the top FET being in electrical contact with a top source / drain epitaxial (S / D epi) and a back-end-of-line (BEOL) interconnect. The device further includes a bottom FET. The bottom FET is in electrical contact with the bottom S / D epi. Further, a shallow backside contact is in electrical contact with the bottom S / D epi. The device further includes a deep via in electrical contact with the BEOL interconnect and the shallow backside contact. The deep via and shallow backside contact provide a conductive path between the BEOL interconnect and the bottom S / D epi.

Description

[Technical Field]

[0001] The present disclosure relates to backside contacts, and more particularly to backside contacts for stacked field effect transistor (FET) semiconductor devices. [Background technology]

[0002] Semiconductor device(s) may be used in computer processors, computer memories, and the like. These devices include transistors, such as field-effect transistors (FETs), which enable the processing and data storage of computer processors and memories by controlling the flow of current from source to drain. FETs use an electric field to control the flow of current. Some semiconductor devices are stacked FETs, i.e., they include two layers, each with metal wiring and contacts to the front and back of the device.

[0003] The term front side refers to the back end of line (BEOL) interconnects, which include signal routing for a semiconductor device. The signal routing may include logic circuitry for the device. With respect to the back side, the term specifically refers to the backside interconnects, which may include routing for power supplies (i.e., Vss / Vdd) to the device.

[0004] Semiconductor devices are fabricated on wafers. Therefore, when discussing the fabrication of wafers having semiconductor devices, it can be useful to describe the location of elements on the wafer using reference points. More specifically, backside and frontside provide reference points for describing the relative locations of particular elements on the wafer. For example, the backside is "below" the frontside. Additionally, the wafer includes a middle-of-line (MOL) having wiring and contacts. In these descriptions, the BEOL interconnects (frontside) are above the top layer of FETs, which are above the MOL, which are above the bottom layer of FETs, which are above the backside interconnects. However, references to relative locations herein (e.g., top, bottom, below, left, and the like) are merely examples and are not limiting with respect to any particular arrangement described.

[0005] As mentioned above, FETs can be stacked on top and bottom layers. Therefore, the top layer of the stacked FET is located between the bottom source / drain (S / D) of the BEOL and the bottom layer FET. Therefore, the top layer FET blocks a potential path for wiring between the bottom S / D and the BEOL. Furthermore, using backside contacts for wiring can potentially short to the Vss / Vdd on the backside. Therefore, it can be difficult to route wiring between the bottom S / D and the BEOL signal wiring. Summary of the Invention

[0006] An embodiment of a semiconductor device is disclosed. The device comprises a first gate stack disposed above a bottom FET, the top FET being in electrical contact with a top source / drain epitaxial (S / D epi) and a back-end-of-line (BEOL) interconnect. The device further comprises a bottom FET. The bottom FET is in electrical contact with the bottom S / D epi. Further, a shallow backside contact is in electrical contact with the bottom S / D epi. Further, the device comprises a deep via in electrical contact with the BEOL interconnect and the shallow backside contact. The deep via and shallow backside contact provide a conductive path between the BEOL interconnect and the bottom S / D epi.

[0007] Disclosed is an embodiment of a method for fabricating a semiconductor device. The method includes forming a first back contact placeholder by forming a first recess under a region for a first bottom source / drain epitaxial (S / D epi) of a first gate stack having a first top S / D epi disposed above a first bottom S / D epi. The method also includes depositing a sacrificial dielectric material within the first recess. The method further includes forming a first gate cut between the first gate stack and a second gate stack. The method further includes filling the first gate cut with a bi-layer dielectric fill. The method further includes forming a first deep via through an inner dielectric of the bi-layer dielectric fill, the first deep via contacting the back contact placeholder. The method also includes removing the first back contact placeholder. The method further includes creating a first deep backside contact by filling an area previously occupied by the removed backside contact placeholder with a conductive metal that is in electrical contact with the first deep via and the first bottom S / D epi, forming a shallow backside contact by recessing the first deep backside contact, and forming a back end of line (BEOL) interconnect in electrical contact with the first deep via, wherein the shallow backside contact does not short to a backside power rail (BSPR).

[0008] Further aspects of the present disclosure are directed to computer program products with functionality similar to that discussed above with respect to the computer-implemented methods. This Summary is not intended to illustrate every implementation and / or every aspect of every embodiment of the present disclosure. [Brief explanation of the drawings]

[0009] The drawings included in this application are incorporated into and form a part of this specification. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of particular embodiments and are not intended to limit the disclosure.

[0010] [Figure 1] FIG. 1 is a block diagram of an exemplary computing environment in accordance with some embodiments of the present disclosure.

[0011] [Figure 2A] 1 is a top view of an exemplary semiconductor device according to some embodiments of the present disclosure.

[0012] [Figure 2B] 1 is a vertical cross-sectional view of an exemplary semiconductor device according to some embodiments of the present disclosure.

[0013] [Figure 3] 3A and 3B are process flow diagrams of exemplary methods for manufacturing semiconductor devices according to some embodiments of the present disclosure.

[0014] [Figure 4] FIG. 1 is a block diagram of an overhead view of an exemplary semiconductor device during fabrication in accordance with some embodiments of the present disclosure.

[0015] [Figure 5-1] Figure 5A is an exemplary manufacturing state of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure; Figure 5B is an exemplary manufacturing state of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure; Figure 5C is an exemplary manufacturing state of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure; and Figure 5D is an exemplary manufacturing state of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure.

[0016] [Figure 5-2] FIG. 5E is a block diagram of an overhead view of an exemplary semiconductor device during fabrication in accordance with some embodiments of the present disclosure.

[0017] [Figure 5-3] FIG. 5F is an exemplary manufacturing state of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure.

[0018] [Figure 5-4] FIG. 5G is a block diagram of an overhead view of an exemplary semiconductor device during fabrication in accordance with some embodiments of the present disclosure.

[0019] [Figure 5-5] FIG. 5H is an exemplary manufacturing state of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure.

[0020] [Figure 5-6] FIG. 5I is a block diagram of an overhead view of an exemplary semiconductor device during fabrication in accordance with some embodiments of the present disclosure.

[0021] [Figure 5-7] FIG. 5J is an exemplary manufacturing state of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure.

[0022] [Figure 5-8]FIG. 5K is a block diagram of an overhead view of an exemplary semiconductor device during fabrication in accordance with some embodiments of the present disclosure.

[0023] [Figure 5-9] FIG. 5L is an exemplary manufacturing state of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure.

[0024] [Figure 5-10] FIG. 5M is a block diagram of an overhead view of an exemplary semiconductor device in fabrication, according to some embodiments of the present disclosure.

[0025] [Figure 5-11] FIG. 5N is an exemplary manufacturing state of an exemplary semiconductor device during manufacture according to some embodiments of the present disclosure. FIG. 5O is an exemplary manufacturing state of an exemplary semiconductor device during manufacture according to some embodiments of the present disclosure. FIG. 5P is an exemplary manufacturing state of an exemplary semiconductor device during manufacture according to some embodiments of the present disclosure. FIG. 5Q is an exemplary manufacturing state of an exemplary semiconductor device during manufacture according to some embodiments of the present disclosure. FIG. 5R is an exemplary manufacturing state of an exemplary semiconductor device during manufacture according to some embodiments of the present disclosure. FIG. 5S is an exemplary manufacturing state of an exemplary semiconductor device during manufacture according to some embodiments of the present disclosure.

[0026] [Figure 5-12] FIG. 5T is a block diagram of an overhead view of an exemplary semiconductor device in fabrication according to some embodiments of the present disclosure.

[0027] [Figure 5-13] 5U, 5V, and 5W are exemplary manufacturing states of an exemplary semiconductor device during manufacture according to some embodiments of the present disclosure.

[0028] While the present disclosure is susceptible to various modifications and alternative forms, specific aspects of the disclosure have been shown by way of example in the drawings and are described in detail below. It should be understood, however, that the intention is not to limit the disclosure to the described embodiments. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0029] As mentioned above, the use of Buried Power Rails (BPR) and Backside Power Distribution Network (BSPDN) for backside interconnects can reduce routing congestion for stacked FET devices, but routing between the bottom source / drain of stacked FETs and signal routing in the BEOL can be challenging.

[0030] Accordingly, some embodiments of the present disclosure can fabricate stacked FET semiconductor devices with interconnects between the bottom S / D epitaxial (epis) and back-end line (BEOL) signal interconnects. Such embodiments can include a gate cut region filled with a bilayer dielectric and located between the top and bottom stacked FET cells. Furthermore, such embodiments can include at least one deep via formed through the internal dielectric fill. This deep via connects to a shallow backside contact that connects to the bottom S / D. Furthermore, the shallow backside contact's reduced depth can prevent shorts to the backside power rail. Furthermore, such embodiments can include a backside contact with a greater height than a shallow backside contact that connects the bottom S / D epi to the backside power rail. Furthermore, such embodiments can include a deep via that connects the top S / D epi to the backside power rail. Thus, such embodiments can provide stacked FET semiconductor devices with interconnects between the bottom S / D epi and backside line, and between the top S / D epi and backside line.

[0031] 1 is a block diagram of an exemplary computing environment 100 according to some embodiments of the present disclosure. Various aspects of the present disclosure are described through text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. For any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, two operations shown in successive flowchart blocks may be performed in the reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time, again depending on the technology involved.

[0032] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media") collectively included in a set of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as punch cards or pits / lands formed on a major surface of a disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, should not be construed as storage of transient signals per se in the form of radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media.As will be appreciated by those skilled in the art, data typically moves at some infrequent time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but this does not make the storage device considered transient, as data is not transient while it is stored.

[0033] Computing environment 100 includes an example environment for executing at least a portion of the computer code required to perform the methodology of the present invention, such as a semiconductor device manufacturing manager 150. Additionally, computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, computer 101 includes a processor set 110 (including processing circuitry 120 and cache 121), a communications fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and semiconductor device manufacturing manager 150, as identified above), a peripheral device set 114 (including a user interface (UI) device set 123, a storage device 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. Remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140, a cloud orchestration module 141, a set of host physical machines 142, a set of virtual machines 143, and a set of containers 144.

[0034] Computer 101 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 130. As is well understood in the art of computer technology, and in accordance with such technology, execution of a computer-implemented method may be distributed among multiple computers and / or multiple locations. While, in this description of computing environment 100, to keep the description as concise as possible, the detailed discussion focuses on a single computer, and in particular computer 101. Computer 101 may be located in a cloud, even if not depicted in the cloud in FIG. 1 . However, it is not required that computer 101 be in a cloud, except where expressly indicated at all.

[0035] Processor set 110 includes one or more computer processors of any type now known or later developed. Processing circuitry 120 may be distributed across multiple packages, e.g., multiple integrated circuit chips coupled together. Processing circuitry 120 may be implemented with multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores running on processor set 110. Cache memory is typically divided into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all of the cache for a processor set may be located "off-chip." In some computing environments, processor set 110 may be designed to operate with qubits and perform quantum computing.

[0036] Computer-readable program instructions are typically loaded onto computer 101 to cause processor set 110 of computer 101 to execute a series of operational steps, thereby implementing a computer-implemented method; therefore, the instructions so executed instantiate the method specified in the flowcharts and / or descriptions of the computer-implemented method contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media described below. The program instructions and associated data are accessed by processor set 110 to control and direct the execution of the methods of the present invention. In computing environment 100, at least a portion of the instructions for implementing the methods of the present invention may be stored in semiconductor device manufacturing manager 150 in persistent storage 113.

[0037] Communications fabric 111 is the signal-conducting pathway that allows various components of computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as those that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways may be used, such as fiber optic and / or wireless communication pathways.

[0038] Volatile memory 112 may be any type of volatile memory now known or later developed. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory 112 is characterized by random access, although this is not required unless expressly indicated. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 101.

[0039] Persistent storage 113 may be any form of non-volatile storage for a computer, now known or later developed. The term non-volatile storage means that stored data is maintained regardless of whether power is supplied to computer 101 and / or to persistent storage 113 directly. Persistent storage 113 may be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, data to be erased, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems employing a kernel. The code contained in block 150 typically includes at least a portion of the computer code involved in performing the methods of the present invention.

[0040] The peripheral device set 114 includes a set of computer 101 peripheral devices. Data communication connections between the peripheral devices and other components of the computer 101 may be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cable (such as a universal serial bus (USB)-type cable), insertion-type connections (e.g., a secure digital (SD) card), connections made over a local area communication network, and even connections made over a wide area network such as the Internet. In various embodiments, the UI device set 123 may include components such as a display screen, speakers, a microphone, wearable devices (such as goggles and smartwatches), a keyboard, a mouse, a printer, a touchpad, a game controller, and a haptic device. The storage device 124 may be an external storage device such as an external hard drive or an insertable storage device such as an SD card. The storage device 124 may be persistent and / or volatile. In some embodiments, the storage device 124 may take the form of a quantum computing storage device that stores data in the form of qubits. In embodiments where computer 101 needs to have large capacity storage (e.g., computer 101 stores and manages a large database locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. IoT sensor set 125 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector.

[0041] Network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers over WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi® signal transceiver, software for packetizing and / or de-packetizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages multiple different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention can typically be downloaded to computer 101 from an external computer or external storage device via a network adapter card or network interface included in network module 115.

[0042] WAN 102 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances by any now known or later developed technology for communicating computer data. In some embodiments, WAN 102 may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0043] End-user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise that operates computer 101) and may take any of the forms discussed above in connection with computer 101. EUD 103 typically receives useful and useful data from the operation of computer 101. For example, in a hypothetical case in which computer 101 is designed to provide advice to the end user, this advice would typically be communicated from network module 115 of computer 101 over WAN 102 to EUD 103. In this manner, EUD 103 can display or otherwise present this advice to the end user. In some embodiments, EUD 103 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0044] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide advice based on historical data, this historical data may be provided to computer 101 from remote database 130 of remote server 104.

[0045] A public cloud 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer functionality, particularly data storage (cloud storage) and computing power, without direct, active management by users. Cloud computing typically leverages resource sharing to achieve consistency and economies of scale. Direct, active management of the computing resources of the public cloud 105 is performed by computer hardware and / or software in a cloud orchestration module 141. The computing resources provided by the public cloud 105 are typically realized by virtual computing environments running on various computers comprising a host physical machine set 142, which is the entire set of physical computers included in and / or available to the public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines in a virtual machine set 143 and / or containers in a container set 144. It is understood that these VCEs may be stored as images and may be transferred between various physical machine hosts either as images or after instantiation of the VCEs. Cloud orchestration module 141 manages the transfer and storage of images, deploys newly instantiated VCEs, and manages active instances of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that allows public cloud 105 to interact over WAN 102.

[0046] Some further explanation of virtualized computing environments (VCEs) is now provided. A VCE can be stored as an "image." From this image, new, active instances of the VCE can be instantiated. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of an operating system in which the kernel allows the existence of multiple isolated user space instances called containers. These isolated user space instances typically behave as actual computers from the perspective of the programs running within them. A computer program running on a typical operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and the devices assigned to the container; this feature is known as containerization.

[0047] A private cloud 106 is similar to a public cloud 105, except that the computing resources are available only for use by a single enterprise. While the private cloud 106 is shown as interacting with the WAN 102, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. Each of the multiple clouds remains a separate, isolated entity, but is joined together in a larger hybrid cloud architecture by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both the public cloud 105 and the private cloud 106 are part of a larger hybrid cloud.

[0048] 2A is a top view 250 of an exemplary semiconductor device 200 according to some embodiments of the present disclosure. The overhead view 250A includes four device regions 252-1, 252-2, 252-3, and 252-4 (collectively referred to as device regions 252) and three gate regions 254-1, 254-2, and 254-3 (collectively referred to as gate regions 254). The device regions 252 represent the location of the channel and S / D epi of the exemplary semiconductor device 200. The gate regions 254 include areas above the intersecting device regions 252 with stacked FETs. Additionally, the overhead view 250A includes X, Y1, and Y2 cross-sections that correspond to cross-sectional views (described below) of the exemplary semiconductor device 200.

[0049] 2B is a vertical cross-sectional view of an exemplary semiconductor device 200 according to some embodiments of the present disclosure. As shown, the X cross section corresponds to an X view representing a cross section of device region 252-1 across gate regions 254-1, 254-2, and 254-3. Additionally, a Y view represents a cross section of gate region 254-1 across device regions 252-1 and 252-2, and a Y view represents a cross section of the intervening space between gate regions 254-2 and 254-3 (i.e., a cross section along device regions 252-1, 252-2, 252-3, and 252-4).

[0050] Additionally, the perspectives share similar features across perspectives. For example, the X, Y1, and Y2 perspectives include a carrier wafer 202, a BEOL 204, and an ILD 206 on the front side, and a backside ILD layer 216, a BSPR 222, and a BSPDN 224 on the back side. The carrier wafer 202 may represent layers of a silicon (Si) wafer. Furthermore, the BEOL 204 may be composed of multiple layers of metal lines (including signal wiring and power rails) and vias (e.g., copper (Cu)-based interconnects). Regarding the backside, the backside ILD layer 216 may be a material such as SiO2, SiOC, SiN, low-k oxide, etc. The backside ILD layer 216 separates backside contacts from each other and separates the device layers from the BSPR 222, which includes source and drain power rails on the backside. The backside ILD layer 216 is a backside interlayer dielectric (ILD) deposited from the backside of the wafer. Thus, the BSPR 222 and the BSPDN 224, when connected to a power source, can provide power to the exemplary semiconductor device 200. The BSPDN 224 includes insulators (e.g., backside ILD) and backside interconnects (e.g., backside metal wires and backside metal vias).

[0051] The X-view represents device region 252-1 across three gate regions 254, and therefore includes three stacks of stacked FETs 212 (e.g., gate stacks), two stacks of S / D epi 214 between these three gate stacks, contacts, and vias. From top to bottom, the gate stacks include a top FET 212-T and a bottom FET 212-B (collectively referred to as stacked FETs 212). The ILD 206 can be a dielectric material such as SiO, SiN, SiBCN, SiOCN, SiOC, SiC, and the like. With respect to the gate stacks, the top FET and bottom FET are isolated from each other by a middle dielectric isolation (MDI) layer 212-0M. Similarly, the bottom FET 212-B is isolated from the backside ILD layer 216 by a bottom dielectric isolation (BDI) layer 212-0B.

[0052] Furthermore, stacked FET 212 may represent a transistor having spacer 212-1, nanosheet channel 212-2, inner spacer 212-3, high-k metal gate (HK / MG) 212-4, MDI layer 212-0M, and BDI layer 212-0B. Spacer 212-1 may include a layer of dielectric material deposited and etched back to provide spacing between HK / MG 212-4 and contact 208-A. Furthermore, nanosheet channel 212-2 may include a nanosheet of semiconducting material that may be conductive in the transistor's "on" state and highly resistive in the transistor's "off" state. The conductivity of nanosheet channel 212-2 may be controlled by HK / MG 212-4. Furthermore, inner spacer 212-3 may represent a dielectric material that provides spacing between HK / MG 212-4 and S / D epi 214. Additionally, HK / MG212-4 may include transistor gate electrodes and gate dielectrics of high-k materials (e.g., k=7 or greater), which may vary based on the type of device being built (e.g., N-type or P-type FET).

[0053] Additionally, the X-view includes two stacks of S / D epi 214 (top S / D epi 214-T and bottom S / D epi 214-B). S / D epi 214 can be a heavily doped epitaxial layer, such as boron-doped SiGe for a p-type field effect transistor (PFET) or phosphorus-doped Si for an n-type FET (NFET). Additionally, the S / D epi stack includes, from top to bottom, contact 208-A, top S / D epi 214-T, ILD 206 (which separates the top and bottom S / D epi from each other), and bottom S / D epi 214-B. Furthermore, the S / D epi stack is different below bottom S / D epi 214-B. More specifically, the left S / D epi stack (between gate regions 254-1 and 254-2) also includes a shallow backside contact 208-S that is part of an interconnect (not shown) between the bottom S / D epi 214-B and the BEOL 204. According to some embodiments of the present disclosure, the shallow backside contact 208-S allows the example semiconductor device 200 to connect to this interconnect without risking shorting to the BSPR 222. In contrast, in the right S / D epi stack (between gate regions 254-2 and 254-3), the bottom S / D epi 214-B is connected to the BSPR 222 by a deep backside contact 208-D.

[0054] As previously mentioned, the Y1 view represents a cross section of gate region 254-1 across device regions 252-1 and 252-2. Therefore, the Y1 view represents four FETs (i.e., two gate stacks), contacts, and vias in and between these device regions. The Y1 view structure includes (from top to bottom) contact 208-B, HK / MG 212-4, nanosheet channel 212-2, MDI 212-0M at the bottom of top FET 212-T, and BDI layer 212-0B at the bottom of bottom FET 212-B. Additionally, the Y1 view structure includes STI layer 218. Each of the gate stacks is located above and isolated from BSPR 222-VSS.

[0055] Between the gate stacks, the Y1 view includes backside ILD layers 216 on either side of the deep via 210. The deep via 210 provides a conductive path (shown in view Y2) between the top S / D epi 214-T and the BSPR 222-VDD. Additionally, the backside ILD layer 216 separates the deep via 210 from the gate stacks.

[0056] As previously mentioned, the Y2 view represents a cross section of the exemplary semiconductor device 200 in the device regions 252-1, 252-2, 252-3, and 252-4 within the intervening spaces between the gate regions 254-2 and 254-3. More specifically, the Y2 view includes the S / D epi 214, contacts, and vias between the gates (i.e., stacked FETs) of these gate regions. Thus, the Y2 view represents a cross S / D epi view of the four S / D epi stacks (i.e., top and bottom S / D epi), contacts, and vias located between the 16 stacked FETs 212 (eight stacks, four along each of the gate regions 254-2 and 254-3). The S / D epi stacks in the Y2 view are similar to the S / D epi stacks in the X and Y1 views. From left to right, the S / D epi stack represents the S / D epi for device regions 252-1, 252-2, 252-3, and 252-4 and includes deep backside contact 208-D, shallow backside contact 208-S, deep backside contact 208-D, and deep frontside contact 208-DF. Deep frontside contact 208-DF shorts bottom S / D epi 214-B and top S / D epi 214-T together.

[0057] Additionally, between the S / D epi stacks of device regions 252-1 and 252-2, in the Y2 view, are pillars of first and second dielectric materials 217-1 and 217-2, an STI layer 218, and a backside ILD layer 216. Additionally, between the S / D epi stacks of device regions 252-2 and 252-3, in the Y2 view, are deep vias 210 that contact the BEOL 204, and shallow backside contacts 208-S. Additionally, on either side of deep via 210, backside ILD layers 216 separate deep via 210 from adjacent S / D epi 214. Backside ILD layer 216 also contacts STI layer 218. In this manner, exemplary semiconductor device 200 provides a conductive path between the bottom S / D epi for the bottom FET in a stacked FET device and signal wiring in BEOL 204.

[0058] Additionally, between the S / D epi stacks of device regions 252-3 and 252-4, in the Y2 view, is a deep via 210 that contacts contact 208-A on the top of the S / D epi stack, and BSPR 222-VDD. Additionally, on either side of deep via 210, backside ILD layer 216 separates deep via 210 from the adjacent S / D epi stack. In this manner, deep via 210 provides a conductive path from top S / D epi 214T to BSPR 222-VDD.

[0059] FIG. 3 (which includes FIGS. 3A and 3B) is a process flowchart of a method 300 for manufacturing a semiconductor device according to some embodiments of the present disclosure. In some embodiments, an example semiconductor device manufacturing manager, such as the semiconductor device manufacturing manager 150 described with reference to FIG. 1, can perform the method 300. In this method, the semiconductor device manufacturing manager 150 can manufacture a semiconductor device, such as the semiconductor device 200 described with reference to FIG. 2. For clarity, the method 300 is described with reference to FIGS. 4 and 5A-5W, which provide perspectives of an example semiconductor device manufactured after each operation of the method 300. Furthermore, the perspectives depicted in FIGS. 4 and 5A-5W are merely examples of perspectives that the method 300 may generate. However, in some implementations of the method 300, other perspectives may be generated.

[0060] In operation 302, the semiconductor device fabrication manager 150 can instruct the fabrication tool to form a dummy gate. Forming the dummy gate can include depositing a sacrificial layer to serve as a placeholder for the gate. More specifically, the semiconductor device fabrication manager 150 can instruct the fabrication tool to form a patterned nanosheet stack above an insulating layer. Patterning the nanosheet can include forming the patterned nanosheet stack above an underlying layer. More specifically, the fabrication tool can deposit alternating nanosheet layers of sacrificial nanosheet layers and nanosheet channel layers. The sacrificial nanosheet layers can be composed of silicon germanium (e.g., SiGe). Furthermore, the channel layer can be composed of Si. Furthermore, forming the dummy gate can include depositing material that forms a dummy gate and a gate hard mask above the patterned nanosheet stack. For clarity, operation 302 is described with reference to FIGS. 4 and 5A.

[0061] FIG. 4 is a block diagram of an overhead view 450 of an exemplary semiconductor device 400 during fabrication, in accordance with some embodiments of the present disclosure. In the overhead view 450, the exemplary semiconductor device 400 includes device regions 452-1, 452-2, 452-3, and 452-4 (collectively referred to as device regions 452) and gate regions 454-1, 454-2, and 454-3 (collectively referred to as gate regions 454). The device regions 452 represent the location of channel and S / D epi to be fabricated. Similarly, the gate regions 454 indicate the location of gates to be fabricated, specifically, the location of the intersecting device and gate regions 454. The overhead view 450 is similar to the overhead view 250A described with respect to FIG. 2A. Accordingly, the overhead view 450 includes X, Y1, and Y2 cross-sectional lines that correspond to the cross-sectional views described below with respect to FIGS. 5A-5D.

[0062] As described below, FIGS. 5A-5W include an exemplary semiconductor device during fabrication. In particular, these figures include several elements, each labeled for descriptive purposes. However, due to the large number of elements, including a reference number for every element would clutter the figures and potentially lead to confusion. Therefore, the following steps are taken to limit the reuse of reference numbers within the figures. For example, these figures include multiple views of the same device. Therefore, these views share some of the same elements. Therefore, to limit the reference numbers, reference numbers are placed only on the left-most view of an element. Therefore, similar elements (without reference numbers) are indicated by the same vertical position (as shown) and the same hash pattern (or lack thereof). Furthermore, as elements are added to a figure, they are labeled with a reference number. However, subsequent figures may retain elements but not include a reference number. For example, an element introduced and therefore labeled in FIG. 5A may not be labeled in FIG. 5B. While these steps help reduce clutter in the figures, some exceptions to the labeling above are made for clarity.

[0063] FIG. 5A illustrates an exemplary manufacturing state 500A of an exemplary semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. The exemplary manufacturing state 500A may represent the state of the semiconductor device after operation 302. The exemplary manufacturing state 500A includes X, Y1, and Y2 perspectives corresponding to the X, Y1, and Y2 cross-sectional lines described with reference to FIG. 4. Similar to the exemplary semiconductor device 200 described with reference to FIG. 2B, the views of the exemplary manufacturing state 500A share similar features throughout the figures. For example, the X, Y1, and Y2 perspectives all include a substrate 402-S (e.g., silicon (Si)), an etch-stop layer 404, a silicon layer 402-1, and a patterned nanosheet stack 406. Additionally, the nanosheet stack 406 includes sacrificial layers 406-1 and 406-2, which may be composed of SiGe60 and SiGe30, respectively. Additionally, the nanosheet stack 406 includes a nanosheet channel 406-3, which may be composed of a semiconductor material such as Si.

[0064] Additionally, both the X and Y1 views include a dummy gate 407-DG and a gate hard mask 407-HM. The dummy gate may serve as a placeholder for an actual gate fabricated at a different manufacturing stage. The gate hard mask 407-HM may be a cap to facilitate patterning of the nanosheet stack. The dummy gate 407-DG in the X view may represent the location of gate regions 454-1, 454-2, and 454-3 (from left to right as shown) discussed with respect to FIG. 4.

[0065] Additionally, the Y1 view includes two nanosheet stacks 406 representing device regions 452-1 and 452-2 along cross-section line Y1. Additionally, the Y1 view includes an STI layer 408 between and in the trenches on either side of the two nanosheet stacks 406. The STI layer 408 can be similar to the STI layer 218 described with respect to FIG.

[0066] Additionally, the Y2 view includes four nanosheet stacks 406 representing device regions 452-1, 452-2, 452-3, and 452-4 along cross-sectional line Y2. Like the Y1 view, the Y2 view includes the STI layers 408 between and on either side of the nanosheet stacks 406. In this manner, the exemplary fabrication state 500A can represent the state of a fabricated semiconductor device after operation 302 is performed.

[0067] 3A, in operation 304, the semiconductor device fabrication manager 150 can instruct the fabrication tool to perform sacrificial layer removal, spacer, BDI, MDI, and inner spacer formation. The fabrication tool removes the sacrificial layer 406-1, which may be composed of a SiGe material such as SiGe60. Removing the SiGe60 layer can include etching the sacrificial layer 406-1 selective to the Si nanosheet channel 406-3 and other surrounding materials.

[0068] Furthermore, forming the spacers can include conformal dielectric deposition and anisotropic reactive-ion etching (RIE) to remove the spacer material from horizontal surfaces. The spacers can be a dielectric material (e.g., SiN, SiBCN, SiOCN, SiOC, and the like). Furthermore, forming the BDI includes depositing a dielectric material in the area previously occupied by the sacrificial layer removed from the bottom of the nanosheet stack 406. Similarly, forming the MDI includes depositing a dielectric material in the area previously occupied by the sacrificial layer removed from the middle of the nanosheet stack 406.

[0069] Further, forming the interior spacer may include performing nanosheet recessing, SiGe indentation, and interior spacer formation. More specifically, performing nanosheet recessing may include etching back the nanosheet stack (e.g., sacrificial layer 406-2 and nanosheet channel 406-3). Furthermore, SiGe indentation may include a mechanical process to remove a portion of sacrificial layer 406-2 and provide sufficient space for depositing material to form interior spacer 412-2. Furthermore, forming the interior spacer may include depositing a dielectric material in the space created by SiGe indentation. For clarity, operation 304 is described with reference to FIG. 5B.

[0070] 5B illustrates an exemplary manufacturing state 500B of the exemplary semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500A, the X-view of the exemplary manufacturing state 500B includes two trenches between the dummy gates 407-DG, thus forming three nanosheet stacks 406. Additionally, the X-view includes the BDI layer 406-0B and the MDI layer 406-0M in the area previously occupied by the removed sacrificial layer 406-1. Additionally, the X-view includes spacers 412-1 on either side of the dummy gate 407-DG and the gate hard mask 407-HM. Similar to the X-view, the Y1-view includes the BDI layer 406-0B and the MDI layer 406-0M in the area previously occupied by the removed sacrificial layer 406-1. In this manner, the exemplary manufacturing state 500B can represent the state of a semiconductor device fabricated after performing operation 304.

[0071] 3A, in operation 306, the semiconductor device manufacturing manager 150 can instruct the manufacturing tool to perform placeholder patterning. Performing the placeholder patterning can include depositing a mask material (such as an organic planarization layer (OPL)) followed by conventional lithographic patterning. Further, the placeholder patterning includes creating trenches through the OPL to the silicon layer 402-1 and the STI layer 408. For clarity, operation 306 is described with reference to FIG. 5C.

[0072] 5C is an example manufacturing state 500C of example semiconductor device 400 during manufacturing, according to some embodiments of the present disclosure. Compared to example manufacturing state 500B, the X-view of example manufacturing state 500C further includes trench 414 and OPL 416. As previously discussed, trench passes through OPL 416 to silicon layer 402-1. In this manner, example manufacturing state 500C may represent the state of a semiconductor device being manufactured after operation 306 is performed.

[0073] 3A , in operation 308, the semiconductor device fabrication manager 150 can instruct the fabrication tool to form a placeholder, perform S / D epi growth, form an ILD layer, remove the dummy gate and sacrificial layer, and form a replacement HK / MG. Forming the placeholder includes depositing a sacrificial material in the trench 414 and recessing it flush with the BDI layer 406-0B, or forming the sacrificial placeholder 418 through a bottom-up deposition process, such as selective epitaxy growth. Furthermore, performing S / D epi growth includes growing semiconductor S / D epitaxy from exposed semiconductor surfaces (e.g., nanosheet channel 406-3). Furthermore, forming the ILD layer includes performing interlayer dielectric (ILD) deposition on the STI layer 408 and the grown S / D epi. Further, forming the ILD layer includes performing chemical mechanical planarization (CMP), which removes material (e.g., gate hard mask 407-HM, material of ILD layer 422) and forms a flat surface. In dummy gate removal, the fabrication tool may selectively remove dummy gate 407-DG relative to surrounding material (e.g., ILD). Further, removing sacrificial layer 406-2 includes SiGe release. In the case of SiGe release, the fabrication tool may etch sacrificial layer 406-2 (e.g., SiGe 30) selectively relative to Si and other surrounding materials in nanosheet channel 406-3. Further, forming the replacement gate includes depositing a high-k metal gate material in the space created by removing dummy gate 407-DG and sacrificial layer 406-2. For clarity, operation 308 is described with reference to FIG. 5D .

[0074] 5D illustrates an exemplary manufacturing stage 500D of the exemplary semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500C, the X and Y1 views of the exemplary manufacturing stage 500D no longer include the dummy gate 407-DG, the gate hard mask 407-HM, and the sacrificial layer 406-2. Furthermore, compared to the exemplary manufacturing stage 500C, the X view includes three gate stacks and two intervening S / D epi stacks. The gate stack includes the bottom FET 406-B, which includes (from bottom to top) the BDI layer 406-0B, the internal spacer 412-2, and alternating layers of HK / MG 424 and nanosheet channel 406-3. The top FET 406-T includes the MDI layer 406-0M, the internal spacer 412-2, and alternating layers of HK / MG 424 and nanosheet channel 406-3. Additionally, the S / D epi stack includes (from bottom to top): sacrificial placeholder 418, bottom S / D epi 420-B, ILD layer 422, top S / D epi 420-T, and ILD layer 422. In contrast to the three gate stacks in the X view, the Y1 view includes two gate stacks. These gate stacks include elements of top FET 406-T and bottom FET 406-B. The Y2 view includes four S / D epi stacks, similar to the S / D epi stacks described with respect to the X view. However, the second S / D epi stack from the left includes a placeholder that extends beyond the right edge of the overlaid S / D epi. In this way, the sacrificial placeholder 418 allows for the creation of a via that reaches the contact that would be created in place of the sacrificial placeholder 418. Furthermore, the rightmost S / D epi stack does not include a sacrificial placeholder 418. In this manner, FIG. 5D may represent the state of the fabricated semiconductor device after act 308.

[0075] 3A , in operation 310, the semiconductor device fabrication manager 150 can direct the fabrication tool to perform ILD deposition and gate cut patterning. Performing ILD deposition includes depositing ILD material on the semiconductor device being fabricated. Additionally, performing gate cut patterning includes performing an overfill of sacrificial material on the deposited ILD and removing the sacrificial material and the deposited ILD to create a gate cut down to the STI layer 408 and between the device regions 452. For clarity, operation 310 is further described with respect to FIGS. 5E and 5F .

[0076] 5E is a block diagram of an overhead view 450E of the exemplary semiconductor device 400 during fabrication, in accordance with some embodiments of the present disclosure. The overhead view 450E is similar to the overhead view 450 and further includes gate cuts 456-1, 456-2, 456-3 (collectively referred to as gate cuts 456) between the device regions 454.

[0077] 5F is a block diagram of an example manufacturing state 500F of the example semiconductor device 400 during manufacturing, according to some embodiments of the present disclosure. Compared to example manufacturing state 500D, the X, Y1, and Y2 views of example manufacturing state 500F further include additional ILD and OPL 426 within ILD layer 422. Additionally, Y1 view further includes gate cut 456-1. Similarly, Y2 view further includes gate cuts 456-1, 456-2, and 456-3. In this manner, FIG. 5F can represent the state of the semiconductor device being manufactured after operation 310.

[0078] Referring again to FIG. 3A , in operation 312, the semiconductor device manufacturing manager 150 can instruct the manufacturing tool to perform a bi-layer gate cut fill. Performing the bi-layer gate cut fill includes removing the OPL 426. Furthermore, performing the bi-layer gate cut fill includes lining the gate cut 456 with a first dielectric material and filling the lined gate cut with a second dielectric material different from the first dielectric material. For example, the first dielectric material can be silicon nitride (SiN) and the second dielectric material can be silicon oxide (SiO ). For clarity, operation 312 is further described with reference to FIGS. 5G and 5H.

[0079] 5G is a block diagram of an overhead view 450G of the exemplary semiconductor device 400 in fabrication, according to some embodiments of the present disclosure. The overhead view 450G is similar to the overhead view 450E, in that the gate cut 456 further includes a first dielectric material 430 and a second dielectric material 432.

[0080] 5H is a block diagram of an example manufacturing state 500H of the example semiconductor device 400 during manufacturing, according to some embodiments of the present disclosure. Compared to the example manufacturing state 500F, the X, Y1, and Y2 views of the example manufacturing state 500H no longer include the OPL 426. Additionally, the Y1 and Y2 views include the first dielectric material 430 lining the gate cut 456 and the second dielectric filling the gate cut 456. In this manner, FIG. 5H can represent the semiconductor device as manufactured after operation 312.

[0081] 3A, in operation 314, the semiconductor device fabrication manager 150 can direct the fabrication tool to perform self-aligned deep via patterning. Performing self-aligned deep via patterning includes performing a sacrificial material overfill and creating a deep trench through the OPL 426, the second dielectric material 432, and the STI layer 408 to either reach the silicon layer 402-1 or expose the sacrificial placeholder 418. For clarity, operation 314 is further described with respect to FIGS. 5I and 5J.

[0082] 5I is a block diagram of an overhead view 450I of the exemplary semiconductor device 400 in fabrication, according to some embodiments of the present disclosure. The overhead view 450I is similar to the overhead view 450G and further includes deep trenches 458-1, 458-2, 458-3, 458-4 (collectively referred to as deep trenches 458).

[0083] 5J is a block diagram of an exemplary manufacturing state 500J of the exemplary semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500H, the X, Y1, and Y2 views of the exemplary manufacturing state 500J include the OPL 426 on top of the ILD layer 422. Additionally, the Y1 view includes a deep trench 458-1 located between two gate stacks. Additionally, the Y2 view of the exemplary manufacturing state 500G includes a deep trench 458-3 located between the two gate stacks (exposing the sacrificial placeholder 418) and a deep trench 458-4 located between the S / D epi stacks (reaching down to the silicon layer 402-1). In this manner, FIG. 5J can represent a semiconductor device fabricated after operation 314.

[0084] 3A , in operation 316, the semiconductor device fabrication manager 150 can direct the fabrication tool to perform contact patterning. Performing contact patterning includes removing OPL 426 and material from ILD layer 422 to expose top S / D epi 420-T, HK / MG 424, and bottom S / D epi 420-B in device region 452-3 and create openings for deep vias. For clarity, operation 316 is further described with respect to FIGS. 5K and 5L.

[0085] 5K is a block diagram of an overhead view 500K of the exemplary semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. The overhead view 450K is similar to the overhead view 450I and further includes front contact openings 434-OA, 434-OB (also individually referred to as S / D epi openings 434-OA and gate opening 434-OB).

[0086] 5L is a block diagram of an example manufacturing state 500L of the example semiconductor device 400 during manufacturing, according to some embodiments of the present disclosure. Compared to the example manufacturing state 500J, the X, Y1, and Y2 views of the example manufacturing state 500L no longer include the OPL 426. Additionally, the X view includes an S / D contact opening 434-OA to the top S / D epi 420-T. The Y1 view also includes a gate opening 434-OB to the HK / MG 424 of the top FET 406-T. Additionally, the Y2 view includes three S / D openings 434-OA to the top of each top S / D epi 420-T and a fourth S / D opening 434-OA to both sides of the top S / D epi 420-T and bottom S / D epi 420-B of the device region 452-4. The Y2 view also includes three deep via openings 428-DO: one located near the center of the Y2 view, a second located near the center of the Y2 view exposing the sacrificial placeholder 418, and a third located to the right of the second deep via in the Y2 view. In this manner, Figure 5L may represent the fabricated semiconductor device after operation 316.

[0087] Referring again to Figure 3A, operation 316 indicates flow to placeholder A. Placeholder A does not represent a method operation, but rather serves to connect the operation described in Figure 3A with other operations of method 300, which are described in more detail with respect to Figure 3B.

[0088] 3B is a process flowchart of operations 318 through 334 of method 300 according to some embodiments of the present disclosure. For clarity, these operations are described with respect to FIGS. 5M through 5W.

[0089] The process flowchart of Figure 3B shows the flow from placeholder A to operation 318. As previously mentioned, placeholder A does not represent an operation of method 300, but rather serves to connect operations 302-316 described in Figure 3A with operations 318-334 described below.

[0090] In operation 318, the semiconductor device manufacturing manager 150 can instruct the manufacturing tools to perform middle-of-line (MOL) metallization, form the BEOL, and perform carrier wafer bonding. Performing the MOL metallization can include filling the front contact openings 434-OA, 434-OB with a conductive metal to create the front contacts. Furthermore, performing the formation of the BEOL interconnects can include fabricating elements of the BEOL interconnects 436, such as multiple layers of Cu-based metal lines and vias. Furthermore, the carrier wafer bonding can include bonding the carrier wafer 402-2 to the BEOL interconnects 436. For clarity, operation 318 is further described with reference to FIGS. 5M and 5N.

[0091] 5M is a block diagram of an overhead view 450M of an exemplary semiconductor device 400 during fabrication in accordance with some embodiments of the present disclosure. The overhead view 450M is similar to the overhead view 450K and further includes front contacts 434-A and 434-B instead of front contact openings 434-OA and 434-OB. For clarity, not all front contacts are labeled. Rather, boxes depicting front contacts 434-A and 434-B also represent similar contacts within similarly sized boxes. Here, the front contacts 434-A and 434-B are referred to as S / D contacts 434-A and gate contacts 434-B, respectively.

[0092] 5N is a block diagram of an example manufacturing state 500N of the example semiconductor device 400 during manufacturing, according to some embodiments of the present disclosure. Compared to example manufacturing state 500L, the X, Y1, and Y2 views of example manufacturing state 500N further include carrier wafer 402-2 and BEOL interconnect 436. Additionally, the X view includes S / D contacts 434-A on the top S / D epi 420-T. The Y1 view further includes gate contacts 434-B to HK / MG 424. Additionally, the Y1 view includes deep vias 440-D to silicon layer 402-1. The Y2 view further includes three S / D contacts 434-A to the top of each top S / D epi 420-T and a fourth S / D contact 434-A to both sides of the top S / D epi 420-T and bottom S / D epi 420-B. Additionally, the Y2 view includes two deep vias 440-D that are between device regions 452-2, 452-3 and extend down to sacrificial placeholder 418. The second deep via 440-D extends down to silicon layer 402-1. In this manner, Figure 5N may represent the fabricated semiconductor device after operation 318.

[0093] Referring again to FIG. 3A , in operation 320, the semiconductor device fabrication manager 150 can instruct the fabrication tool to perform wafer flip and substrate removal. Performing wafer flip may include reversing the vertical orientation of the semiconductor device under fabrication. Thus, wafer flipping can expose the substrate 402-S for removal. Performing substrate removal includes an etching process that removes substrate material from the exposed surface down to the etch stop layer 404. For clarity, operation 320 is further described with respect to FIG. 5O.

[0094] 5O is a block diagram of an example manufacturing state 500O of the example semiconductor device 400 during manufacturing, according to some embodiments of the present disclosure. Compared to example manufacturing state 500N, the X, Y1, and Y2 views of example manufacturing state 500O no longer include substrate 402-S. In this manner, FIG. 5O may represent the semiconductor device being manufactured after operation 320.

[0095] 3A, in operation 322, the semiconductor device fabrication manager 150 can direct the fabrication tool to remove the etch stop layer 404 and the remaining silicon layer 402-1. Removal of the etch stop layer 404 and the silicon layer 402-1 exposes the underlying sacrificial placeholder, BDI layer 406-0B, STI layer 408, and deep via 440-D. For clarity, operation 322 is further described with respect to FIG. 5P.

[0096] FIG. 5P is a block diagram of an exemplary manufacturing state 500P of the exemplary semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500O, the X, Y1, and Y2 views of the exemplary manufacturing state 500P no longer include the silicon layer 402-1 and the etch stop layer 404. In the X1 view, removing these layers exposes the sacrificial placeholder 418 below the bottom S / D epi 420-B. In the Y1 view, removing these layers exposes the STI layer 408, the BDI layer 406-0B, and the deep via 440-D. In the Y2 view, removing these layers exposes the three sacrificial placeholders 418, the rightmost deep via 440-D, and the rightmost BDI layer 406-0B. In this manner, FIG. 5P may represent the semiconductor device being fabricated after operation 322.

[0097] 3A , in operation 324, the semiconductor device manufacturing manager 150 can instruct the manufacturing tool to perform backside ILD deposition and CMP. Performing backside ILD deposition includes depositing ILD material on surfaces exposed by removing the silicon and etch stop layers. Performing CMP includes creating a planar surface on the deposited ILD. For clarity, operation 324 is further described with respect to FIG. 5Q.

[0098] 5Q is a block diagram of an example manufacturing state 500Q of the example semiconductor device 400 during manufacturing, according to some embodiments of the present disclosure. Compared to example manufacturing state 500P, the X, Y1, and Y2 views of example manufacturing state 500Q further include ILD layer 438. In this manner, FIG. 5Q can represent the semiconductor device being manufactured after operation 324.

[0099] 3A, in operation 326, the semiconductor device fabrication manager 150 can instruct the fabrication tool to remove the sacrificial placeholders 418. Removing the sacrificial placeholders 418 can include a selective dry etching or wet etching process. For clarity, operation 326 is further described with respect to FIG. 5R.

[0100] 5R is a block diagram of an example manufacturing state 500R of the example semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. Compared to the example manufacturing state 500Q, the X, Y1, and Y2 views no longer include the sacrificial placeholder 418. The remaining areas are left with backside contact openings 442-O. In this manner, FIG. 5R may represent the semiconductor device as fabricated after operation 326.

[0101] 3A , in operation 328, the semiconductor device manufacturing manager 150 can instruct a manufacturing tool to perform backside contact metallization. Backside contact metallization can include depositing a conductive metal material in the backside contact openings 442-O. In this manner, some embodiments of the present disclosure can provide backside contact wiring, i.e., one of the bottom S / D epi 420-B and deep via 440-D, described in further detail below, for backside interconnect. For clarity, operation 328 is further described with respect to FIG. 5S.

[0102] 5S is a block diagram of an example manufacturing state 500S of the example semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. Compared to the example manufacturing state 500R, the X and Y2 views of the example manufacturing state 500S include a deep backside contact (BSCA) 442-D in place of the removed sacrificial placeholder 418. Furthermore, in the X and Y2 views, the deep backside contact 442-D extends to the bottom S / D epi 420-B. However, the Y1 view remains unchanged. In this manner, FIG. 5S can represent a semiconductor device fabricated after operation 328.

[0103] Referring again to FIG. 3A , in operation 330, the semiconductor device manufacturing manager 150 can direct the manufacturing tool to perform selective backside contact recession. The selective backside contact recession includes performing an overfill of sacrificial material to form the OPL 426 and removing a portion of the OPL 426. Additionally, the selective backside contact recession includes removing metal to reduce the thickness of predetermined backside contacts 442-D. In this manner, the selective backside contact recession can be useful for forming shallow backside contacts, such as the shallow backside contacts 208-S described with respect to FIG. 2 . For clarity, operation 330 is further described with respect to FIGS. 5T and 5U.

[0104] 5T is a block diagram of an overhead view 450T of an exemplary semiconductor device 400 during fabrication, according to some embodiments of the present disclosure. The overhead view 450T is similar to the overhead view 450M and further includes a deep backside contact 442-D and a shallow backside contact 442-S (collectively referred to as backside contacts 442). For clarity, not all backside contacts are labeled. Rather, a box depicting a backside contact 442 also represents a similar backside contact within a similarly sized box.

[0105] FIG. 5U is a block diagram of an example manufacturing stage 500U of a semiconductor device according to some embodiments of the present disclosure. Compared to example manufacturing stage 500S, the X, Y1, and Y2 views of example manufacturing stage 500U all include OPL 426 missing a portion below shallow backside contact 442-S. Thus, view X further includes shallow backside contact 442-S below bottom S / D epi 420-B located between gate regions 454-1 and 454-2. In contrast, view Y1 does not include any other changes. However, view Y2 further includes shallow backside contact 442-S for bottom S / D epi 420-B in device region 452-2. In this manner, FIG. 5U can represent a semiconductor device fabricated after operation 330.

[0106] 3A, in operation 332, the semiconductor device manufacturing manager 150 can instruct the manufacturing tool to perform backside ILD and CMP refill. Refilling the backside ILD and CMP includes removing the remaining OPL 426, depositing an ILD layer, and performing CMP on the deposited ILD layer. For clarity, operation 332 is further described with respect to FIG. 5V.

[0107] 5V is a block diagram of an example manufacturing state 500V of a semiconductor device according to some embodiments of the present disclosure. Compared to example manufacturing state 500U, the X, Y1, and Y2 views of example manufacturing state 500V further include ILD layer 438. In this manner, FIG. 5V can represent a semiconductor device fabricated after operation 332.

[0108] In operation 334, the semiconductor device manufacturing manager 150 can direct the manufacturing tools to form the backside power rail and the BSPDN. Forming the backside power rail can include fabricating the power rail in the ILD layer 438. Additionally, forming the BSPDN includes fabricating elements of the backside interconnect, such as metal lines and ILD material. For clarity, operation 334 is further described with respect to FIG. 5W.

[0109] FIG. 5W is a block diagram of an exemplary manufacturing state 500W of a semiconductor device according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500V, the X, Y1, and Y2 views of the exemplary manufacturing state 500W further include a BSPDN layer 446. Additionally, the X view includes a BSPR 444-VSS contacting the bottom S / D epi 420-B located between gate regions 454-2 and 454-3. Additionally, the Y1 view includes three BSPRs 444 (two BSPRs 444-VSS and one BSPR 444-VDD). The BSPR 444-VDD contacts the deep via 440-D between the gate stacks. Additionally, the Y2 view includes seven BSPRs 444 alternating between BSPRs 444-VSS and 444-VDD. BSPR 444-VSS of device regions 452-1, 452-3 contacts corresponding deep backside contact 442-D. Additionally, BSPR 444-VDD of device region 452-3 contacts deep via 440-D, and frontside contact 434-A contacts top S / D epi 420-T. In this manner, FIG. 5W may represent the fabricated semiconductor device after operation 334.

[0110] For purposes of this specification, certain aspects, advantages, and novel features of embodiments of the present disclosure are described herein. The disclosed processes and systems should not be construed as limiting in any way. Instead, the present disclosure is directed to all novel and non-obvious features and aspects of the various disclosed embodiments, alone and in various combinations and subcombinations with one another. The processes and systems are not limited to any particular aspect or feature or combination thereof, nor do the disclosed embodiments require that any one or more particular advantages be present or problems be solved.

[0111] Although some operations of the disclosed embodiments are described in a particular sequential order for convenience of presentation, it should be understood that this description style encompasses reordering unless a specific order is required by specific language set forth below. For example, operations described sequentially may in some cases be reordered or performed simultaneously. Moreover, for simplicity, the accompanying drawings may not show the various ways in which the disclosed processes may be used in combination with other processes. Additionally, the description may use terms such as "provide" or "achieve" to describe the disclosed processes. These terms are high-level abstractions of actual operations that are performed. The actual operations corresponding to these terms may vary depending on the particular implementation and are readily discernible by those skilled in the art.

[0112] As used in this application and the claims, the singular forms "a," "an," and "the" include the plural forms unless the context clearly dictates otherwise. Additionally, the word "includes" means "comprises."

[0113] The descriptions of various embodiments of the present disclosure are presented for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to explain the principles, practical applications, or technical improvements of the embodiments beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0114] To demonstrate some aspects of the present disclosure, a list of non-limiting examples is presented below.

[0115] Example 1 is a semiconductor device comprising: a first stacked FET disposed above a bottom FET, the first FET being in electrical contact with a top source / drain epitaxial (S / D epi) and a back end of line (BEOL) interconnect; and a bottom FET, where the bottom FET is in electrical contact with the bottom S / D epi; a shallow backside contact in electrical contact with the bottom S / D epi; and a first deep via in electrical contact with the BEOL interconnect and the shallow backside contact, where the first deep via and the shallow backside contact provide a conductive path between the BEOL interconnect and the bottom S / D epi.

[0116] Example 2 includes the device of example 1, including or excluding optional features. In this example, the device includes a second deep via in electrical contact with the top source / drain contacts and a backside power rail (BSPR). Optionally, the device includes a front side contact between the first top FET and the BEOL interconnect.

[0117] Example 3 includes the device of any one of Examples 1-2, including or excluding optional features. In this example, a shallow backside contact depth prevents shorts to a backside power rail (BSPR). Optionally, the device includes a third deep via in electrical contact with the BEOL interconnect and the BSPR, where the third deep via is separated from the first gate and the second gate by a first dielectric element. Optionally, the device includes a deep backside contact, where the deep backside contact is in electrical contact with the second bottom FET and the BSPR. Optionally, the device includes a gate cut region disposed between the first gate and the third gate, where the gate cut region is filled with a bilayer dielectric.

[0118] Example 4 is a method for fabricating a semiconductor device, the method including: forming a first recess beneath an area for a first bottom source / drain epitaxial (S / D epi), where a first top S / D epi is disposed above the first bottom S / D epi, and depositing a sacrificial dielectric material within the first recess to form a first backside contact placeholder; forming a first gate cut between a first gate and a second gate surrounding the first bottom S / D epi and the first top S / D epi; filling the first gate cut with a bilayer dielectric fill; and forming a first deep via through an inner dielectric of the bilayer dielectric fill, where the first deep via is for forming a first backside contact placeholder. forming a shallow backside contact by removing a first backside contact placeholder, the first backside contact placeholder electrically contacting the first deep via and the first bottom S / D epi; filling an area previously occupied by the removed first backside contact placeholder with a conductive metal that is in electrical contact with the first deep via and the first bottom S / D epi; and recessing the first deep backside contact; and forming a back-end-of-line (BEOL) interconnect that is in electrical contact with the first deep via, wherein the shallow backside contact depth prevents shorts to a backside power rail (BSPR).

[0119] Example 5 includes the method of example 4, including or excluding optional features. In this example, the dual-layer dielectric fill has a first dielectric and a second dielectric, the first dielectric being different from the second dielectric, and the second dielectric including an inner dielectric.

[0120] Example 6 includes the method of any one of examples 4-5, including or excluding optional features. In this example, forming the first deep via includes removing an inner dielectric of the bi-layer dielectric fill material to expose a back contact placeholder.

[0121] Example 7 includes the method of any one of Examples 4-6, including or excluding optional features. In this example, the method includes forming a second gate cut between the second gate and a third gate, where the second gate cut exposes a shallow trench isolation (STI) layer disposed between the second gate and the third gate, filling the second gate cut with a bilayer dielectric fill, forming a second deep via through an inner dielectric of the bilayer dielectric fill, where the second deep via contacts a silicon layer disposed below the STI layer, performing contact patterning to expose a second top S / D epi of the second gate, forming a front contact in electrical contact with the second top S / D epi and the second deep via, where the formed BEOL interconnect is in electrical contact with the front contact, and forming a BSPR, where the BSPR is in electrical contact with the second deep via. Optionally, the method comprises forming a third gate cut between the first gate and the fourth gate, where the third gate cut exposes the STI layer between the first gate and the fourth gate, and filling the third gate cut with a bi-layer dielectric fill. Optionally, the method comprises forming a fourth gate cut between the fourth gate and the fifth gate, where the fourth gate cut exposes the STI layer between the fourth gate and the fifth gate, filling the fourth gate cut with a bi-layer dielectric fill, and forming a third deep via through an inner dielectric of the bi-layer dielectric fill, where the third deep via contacts a silicon layer disposed below the STI layer between the fourth gate and the fifth gate, and the third deep via is in electrical contact with the formed BEOL interconnect and the formed BSPR.Optionally, the method comprises forming a second recess below an area for a second bottom S / D epi of the second gate, where the second bottom S / D epi is disposed below the second top S / D epi, and depositing a sacrificial dielectric material in the second recess to form a second backside contact placeholder; removing the second backside contact placeholder; and forming a second deep backside contact by filling the area previously occupied by the removed second backside contact placeholder with a conductive metal, whereby the conductive metal is in electrical contact with the second bottom S / D epi, where the formed BSPR is in electrical contact with the second deep backside contact.

[0122] Example 8 is a computer program product including program instructions stored on a computer-readable storage medium, the computer-readable medium including steps of forming a first recess beneath an area for a first bottom source / drain epitaxial (S / D epi), the first top S / D epi being disposed above the first bottom S / D epi, and forming a first backside contact placeholder by depositing a sacrificial dielectric material in the first recess, forming a first gate cut between a first gate and a second gate surrounding the first bottom S / D epi and the first top S / D epi, filling the first gate cut with a bilayer dielectric fill material, forming a first deep via through an inner dielectric of the bilayer dielectric fill material, the first deep via electrically contacting the backside contact placeholder, and forming a first gate cut between a first gate and a second gate surrounding the first bottom S / D epi and the first top S / D epi. forming a back end of line (BEOL) interconnect in electrical contact with the first deep via; forming the first back end contact placeholder by filling an area previously occupied by the removed first back end contact placeholder with a conductive metal that is in electrical contact with the first deep via and the first bottom S / D epi to create a first deep back end contact; recessing the first deep back end contact to form a shallow back end contact; and forming a back end of line (BEOL) interconnect in electrical contact with the first deep via, wherein the shallow back end contact depth prevents shorts to a back end power rail (BSPR).

[0123] Example 9 includes the computer-readable medium of example 8, including or excluding optional features. In this example, the dual-layer dielectric fill material has a first dielectric and a second dielectric, the first dielectric being different from the second dielectric, and the second dielectric comprising an inner dielectric.

[0124] Example 10 includes the computer-readable medium of any one of Examples 8-9, including or excluding optional features. In this example, forming the first deep via includes removing an inner dielectric of the dual-layer dielectric fill material to expose a back contact placeholder.

[0125] Example 11 includes the computer-readable medium of any one of Examples 8 to 10, including or excluding optional features. In this example, the computer-readable medium includes the steps of forming a second gate cut between the second gate and a third gate, the second gate cut exposing a shallow trench isolation (STI) layer disposed between the second gate and the third gate, filling the second gate cut with a bilayer dielectric fill material, forming a second deep via through an inner dielectric of the bilayer dielectric fill material, the second deep via contacting a silicon layer disposed below the STI layer, performing contact patterning to expose a second top S / D epi of the second gate, forming a front contact electrically contacting the second top S / D epi and the second deep via, the formed BEOL interconnect electrically contacting the front contact, and forming a BSPR, the BSPR electrically contacting the second deep via. Optionally, the computer-readable medium comprises the steps of: forming a third gate cut between the first gate and a fourth gate, where the third gate cut exposes the STI layer between the first gate and the fourth gate; filling the third gate cut with a bi-layer dielectric fill material. Optionally, the computer-readable medium comprises the steps of: forming a fourth gate cut between the fourth gate and a fifth gate, where the fourth gate cut exposes the STI layer between the fourth gate and the fifth gate; filling the fourth gate cut with a bi-layer dielectric fill material; and forming a third deep via through an inner dielectric of the bi-layer dielectric fill material, where the third deep via contacts a silicon layer disposed below the STI layer between the fourth gate and the fifth gate, and where the third deep via is in electrical contact with the formed BEOL interconnect and the formed BSPR.

Claims

1. A semiconductor device comprising: a top FET disposed above the bottom FET and in electrical contact with the top source / drain epitaxial (S / D epi) and back-end-of-line (BEOL) interconnect; and the bottom FET, the bottom FET being in electrical contact with the bottom S / D epi; a first stacked FET having a shallow backside contact in electrical contact with the bottom S / D epi; and a first deep via in electrical contact with the BEOL interconnect and the shallow backside contact, the first deep via and the shallow backside contact providing a conductive path between the BEOL interconnect and the bottom S / D epi; A semiconductor device comprising:

2. 10. The semiconductor device of claim 1, further comprising a second deep via in electrical contact with the top source / drain contact and a backside power rail (BSPR).

3. The semiconductor device of claim 2 , further comprising a front contact between the first top FET and the BEOL interconnect.

4. 10. The semiconductor device of claim 1, wherein the shallow backside contact depth prevents shorts to a backside power rail (BSPR).

5. 5. The semiconductor device of claim 4, further comprising a deep backside contact, the deep backside contact electrically contacting the second bottom FET and the BSPR.

6. 6. The semiconductor device of claim 5, further comprising a gate cut region disposed between the first gate and the third gate, the gate cut region being filled with a dual-layer dielectric.

7. 7. The semiconductor device of claim 6, further comprising a deep front contact shorting the second bottom S / D epi and the second top S / D epi.

8. 1. A method for manufacturing a semiconductor device, comprising: forming a first recess below an area for a first bottom source / drain epitaxial (S / D epi), wherein a first top S / D epi is disposed above the first bottom S / D epi; and depositing a sacrificial dielectric material within the first recess; forming a first back contact placeholder by forming a first gate cut between a first gate and a second gate surrounding the first bottom S / D epi and the first top S / D epi; filling the first gate cut with a dual-layer dielectric fill material; forming a first deep via through an inner dielectric of the dual-layer dielectric fill, the first deep via making electrical contact with the first backside contact placeholder; removing the first back contact placeholder; creating a first deep backside contact by filling the area previously occupied by the removed first backside contact placeholder with a conductive metal in electrical contact with the first deep via and the first bottom S / D epi; and Recessing the first deep back contact forming a shallow back contact by forming a back end of line (BEOL) interconnect in electrical contact with the first deep via, wherein the shallow backside contact depth prevents shorting to a backside power rail (BSPR); 1. A method for manufacturing a semiconductor device, comprising:

9. 9. The method of claim 8, wherein the dual-layer dielectric fill comprises a first dielectric and a second dielectric, the first dielectric being different from the second dielectric, and the second dielectric comprising the inner dielectric.

10. 9. The method of claim 8, wherein forming the first deep via comprises removing the inner dielectric of the dual-layer dielectric fill to expose the back contact placeholder.

11. forming a second gate cut between the second gate and a third gate, the second gate cut exposing a shallow trench isolation (STI) layer disposed between the second gate and the third gate; filling the second gate cut with the dual-layer dielectric fill material; forming a second deep via through the inner dielectric of the dual-layer dielectric fill, the second deep via contacting a silicon layer disposed below the STI layer; performing contact patterning to expose a second top S / D epi of the second gate; forming a front contact in electrical contact with the second top S / D epi and the second deep via, wherein the formed BEOL interconnect is in electrical contact with the front contact; and forming the BSPR, the BSPR being in electrical contact with the second deep via. The method of claim 8 further comprising:

12. forming a third gate cut between the first gate and the fourth gate, the third gate cut exposing an STI layer between the first gate and the fourth gate; and filling the third gate cut with the dual-layer dielectric fill material. The method of claim 11 further comprising:

13. forming a fourth gate cut between the fourth gate and the fifth gate, the fourth gate cut exposing an STI layer between the fourth gate and the fifth gate; filling the fourth gate cut with the dual-layer dielectric fill material; and forming a third deep via through the inner dielectric of the dual-layer dielectric fill, the third deep via contacting the silicon layer disposed below the STI layer between the fourth gate and the fifth gate, the third deep via electrically contacting the formed BEOL interconnect and the formed BSPR. The method of claim 12 further comprising:

14. forming a second recess under an area for a second bottom S / D epi of the second gate, the second bottom S / D epi being disposed below the second top S / D epi; and depositing the sacrificial dielectric material in the second recess. forming a second back contact placeholder by removing the second back contact placeholder; forming a second deep back contact by filling the area previously occupied by the removed second back contact placeholder with the conductive metal, the conductive metal electrically contacting the second bottom S / D epi and the formed BSPR electrically contacting the second deep back contact. The method of claim 13 further comprising:

15. 1. A computer program product comprising program instructions stored on a computer-readable storage medium, the program instructions being executable by a processor to cause the processor to perform a method on a wafer, the method comprising: forming a first recess below an area for a first bottom source / drain epitaxial (S / D epi), wherein a first top S / D epi is disposed above the first bottom S / D epi; and depositing a sacrificial dielectric material within the first recess; forming a first back contact placeholder by forming a first gate cut between a first gate and a second gate surrounding the first bottom S / D epi and the first top S / D epi; filling the first gate cut with a dual-layer dielectric fill material; forming a first deep via through an inner dielectric of the dual-layer dielectric fill, the first deep via making electrical contact with the first backside contact placeholder; removing the first back contact placeholder; creating a first deep backside contact by filling the area previously occupied by the removed first backside contact placeholder with a conductive metal in electrical contact with the first deep via and the first bottom S / D epi; and Recessing the first deep back contact forming a shallow back contact by forming a back end of line (BEOL) interconnect in electrical contact with the first deep via, wherein the shallow backside contact depth prevents shorting to a backside power rail (BSPR); 1. A computer program product comprising:

16. 16. The computer program product of claim 15, wherein the dual-layer dielectric fill comprises a first dielectric and a second dielectric, the first dielectric being different from the second dielectric, and the second dielectric comprising the inner dielectric.

17. 16. The computer program product of claim 15, wherein forming the first deep via comprises removing the inner dielectric of the dual-layer dielectric fill to expose the back contact placeholder.

18. The method comprises: forming a second gate cut between the second gate and a third gate, the second gate cut exposing a shallow trench isolation (STI) layer disposed between the second gate and the third gate; filling the second gate cut with the dual-layer dielectric fill material; forming a second deep via through the inner dielectric of the dual-layer dielectric fill, the second deep via contacting a silicon layer disposed below the STI layer; performing contact patterning to expose a second top S / D epi of the second gate; forming a front contact in electrical contact with the second top S / D epi and the second deep via, wherein the formed BEOL interconnect is in electrical contact with the front contact; and forming the BSPR, the BSPR being in electrical contact with the second deep via.

16. The computer program product of claim 15, further comprising:

19. The method comprises: forming a third gate cut between the first gate and the fourth gate, the third gate cut exposing an STI layer between the first gate and the fourth gate; and filling the third gate cut with the dual-layer dielectric fill material.

20. The computer program product of claim 18, further comprising:

20. The method comprises: forming a fourth gate cut between the fourth gate and the fifth gate, the fourth gate cut exposing an STI layer between the fourth gate and the fifth gate; filling the fourth gate cut with the dual-layer dielectric fill material; and forming a third deep via through the inner dielectric of the dual-layer dielectric fill, the third deep via contacting the silicon layer disposed below the STI layer between the fourth gate and the fifth gate, the third deep via electrically contacting the formed BEOL interconnect and the formed BSPR.

20. The computer program product of claim 19, further comprising:

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