Power devices and driver circuits with mixed materials

Abstract

A power integrated circuit, the power integrated circuit comprising: a gallium nitride (GaN) chip having a heterojunction structure, the GaN chip having at least one GaN layer and at least one aluminum gallium nitride (AlGaN) layer, the GaN chip having at least one main power device having a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG) formed at an interface between the AlGaN layer and the GaN layer and formed between the source terminal and the drain terminal, the gate terminal being configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal; and a driver having at least one low-side component and at least one high-side component, the low-side component being configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal. a low-side component having a terminal connected to a low DC voltage rail and at least one other terminal connected to a gate terminal of the main power device, and a high-side component having at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device, wherein at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during turn-off of the main power device and is monolithically integrated within the GaN chip, and at least one high-side component of the driver is configured to charge an input capacitance of the main power device and is formed in a semiconductor region including a material other than GaN.

Description

[Technical Field]

[0001] Field of Disclosure This disclosure relates to power semiconductor devices and driver circuits. In particular, but not exclusively, this disclosure relates to the use of heterostructure AlGaN / GaN high electron mobility transistors and silicon companion chips. [Background technology]

[0002] Background of the Disclosure Gallium nitride (GaN) is a wide bandgap material suitable for power and RF semiconductor devices. GaN technology enables the design of transistors with high electron mobility and high saturation velocity, both of which are generally useful features in the fields of power and radio frequency (RF) electronics. The use of GaN material has additional advantages in power devices. For example, the wide bandgap (E g =3.39 eV) is the high critical electric field (E c =3.3 MV / cm), which may enable the design of devices with shorter drift regions (and therefore lower on-state resistance) compared to silicon-based devices with the same breakdown voltage.

[0003] The use of aluminum gallium nitride (AlGaN) / GaN heterostructures also allows the formation of a two-dimensional electron gas (2DEG) at the heterointerface, where carriers can move with very high carrier mobility values ​​(e.g., μ = 2000 cm 2 In addition, the piezoelectric polarization charges present in the AlGaN / GaN heterostructure create a high electron density (e.g., 1e 13 cm -2) These properties enable the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. Much research has focused on developing power devices using AlGaN / GaN heterostructures, resulting in several technologies that realize normally-on (Schottky gate-based technology) and normally-off (insulated gate and p-GaN gate technologies) HEMT devices. It will be understood that normally-off devices are sometimes referred to as enhancement-mode devices, while normally-on devices are sometimes referred to as depletion-mode devices.

[0004] A gate driver is an interface circuit between a power device and a controller. It takes a low-power input from a controller integrated circuit (IC), for example in the form of pulse-width modulation (PWM), and outputs the appropriate signal to charge or discharge the gate of the power device to turn the power device on or turn the power device off. Generally, the gate of a power device cannot be directly driven by a PWM signal from the controller due to its low current capability. Therefore, the gate driver must be able to provide the appropriate current to charge the input capacitance of the power device to turn the device on and to discharge this capacitance to turn the device off.

[0005] A totem-pole driver (e.g., as shown schematically in FIG. 1 ) incorporates silicon features pnp and npn complementary transistors. The npn transistor (as the high-side component) has its collector connected to a high-voltage DC rail, and the pnp transistor (as the low-side component) has its collector connected to a low-voltage DC rail. As used herein, the terms “high-side” and “low-side” generally refer to different portions of the driver circuit. The high-side is the part of the circuit connected to the high-potential DC rail and is responsible for driving the power device during turn-on. The low-side is the part of the circuit connected to ground (or a DC rail of lower potential) and is responsible for driving the power device during turn-off. The emitters of the two transistors may be connected together and through a resistor to the gate of the power device. This configuration also provides good clamping of the gate to a voltage equal to VDD + VBE, where VBE is the base-emitter voltage of the npn transistor. This is a beneficial feature, especially for some GaN power devices with sensitive gates (limited voltages that can be applied to the gate). An additional gate resistor is often introduced to adjust the dV / dt gradient during turn-on and turn-off. Alternatively, the emitters of the two transistors can be connected to the gates through different resistor paths, allowing the dV / dt gradient to be adjusted independently during turn-on and turn-off. Ideally, npn and pnp transistors operate in saturation, resulting in a very low voltage drop between their collector and emitter terminals. However, bipolar transistors often require a relatively high base current to operate in saturation (to minimize the voltage drop between their collector and emitter terminals), and pnp transistors tend to be particularly slow, limited by their relatively high saturation voltage drop for a given chip area. A bypass capacitor between VDD and ground is also provided. This capacitor is charged to VDD and supplies the gate current when the power device turns on.

[0006] An alternative solution is to use two NPN transistors, where the pnp transistor mentioned above is replaced by an npn transistor with an additional inverter attached to its base.

[0007] A two-stage CMOS inverter configuration is also known in the prior art, where the second inverter stage is made from several parallel inverter chips (FIG. 2).

[0008] The second inverter stage (202, 203, 204) (with its output connected to the gates of the power devices) can be replaced with a single inverter of larger area (higher current) that can have a current equivalent to the parallel configuration. This second stage can include an n-channel MOSFET device on the low side that provides the turn-off discharge path for the input capacitance of the power devices, and a p-channel MOSFET device that provides the turn-on charge path for the input capacitance of the power devices. It is desirable to have as low an on-state resistance as possible for both the n-channel MOSFET and the p-channel MOSFET to speed up gate turn-on and turn-off charging and discharging.

[0009] Configurations involving monolithic integration of drivers and power devices are attractive because they reduce component count and parasitics (inductance, capacitance, and resistance) between the driver and power device. This is particularly desirable when operating power integrated circuits at high frequencies. Given their low inherent parasitic capacitance, GaN power devices can actually operate at higher frequencies than equivalent silicon devices, making a monolithically integrated solution desirable. Furthermore, this integrated solution can also help reduce the effects of dV / dt and dI / dt by reducing parasitics (such as parasitic inductance) between the power device and driver.

[0010] However, integrating a complete driver in GaN also has some drawbacks: there are no npn or pnp transistors available in GaN technology, and the development of p-channel unipolar transistors is at a very early stage. Such p-channels operating in a two-dimensional hole gas (2DHG) have poor performance due to very low hole mobility.

[0011] Moreover, since GaN does not have a CMOS architecture (no p-channel devices), the power consumption of monolithically integrated drivers in GaN (especially in standby state) cannot be neglected. Moreover, integrating the complete driver and power devices in the same chip may cause some undesired thermal coupling between the two, further degrading the driver performance.

[0012] In view of the above problems, an improved architecture is desirable.

[0013] The following documents are considered to be known in the art: [1] F. Udrea et al., “The smart ICeGaN TM platform with sensing and protection functions for both enhanced ease of use and gate reliability,”2022 IEEE 34 th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2022, pp. 41-44, doi: 10.1109 / ISPSD49238.2022.9813659; [2] L. Efthymiou, M. Arnold, G. Longobardi and F. Udrea, “A novel depletion mode p-GaN island HEMT and its use in a monolithically integrated start-up circuit,” ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC), 2022, pp. 396-399, doi: 10.1109 / ESSDERC55479.2022.9947100; [3] U.S. Patent No. 11,081,578; [4] U.S. Patent No. 11,404,565. Summary of the Invention [Problem to be solved by the invention]

[0014] overview Generally, it is an object of the present invention to provide an improved architecture between power devices and drivers to address the above problems. [Means for solving the problem]

[0015] According to a first aspect of the present invention, there is provided a power integrated circuit, the power integrated circuit comprising a gallium nitride (GaN) chip with a heterojunction structure, the gallium nitride (GaN) chip with the heterojunction structure comprising at least one GaN layer and at least one aluminum gallium nitride (AlGaN) layer, wherein the GaN chip comprises at least one main power device, the main power device comprising a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG), the two-dimensional electron gas (2DEG) being formed at an interface between the AlGaN layer and the GaN layer and between the source terminal and the drain terminal, the gate terminal being configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal. The driver includes at least one low-side component and at least one high-side component, the low-side component having a terminal connected to a low DC voltage rail and at least one other terminal connected to a gate terminal of the main power device, and the high-side component having at least one terminal connected to a high DC voltage rail and at least one other terminal connected to a gate of the main power device. At least one low-side component of the driver is configured to discharge the input capacitance of the main power device during turn-off of the main power device and is monolithically integrated within the GaN chip, and at least one high-side component of the driver is configured to charge the input capacitance of the main power device and is formed in a semiconductor region including a material other than GaN.

[0016] Optionally, at least one other terminal of the high-side component connected to the gate of the main power device is directly connected to the gate of the main power device.

[0017] Optionally, at least one other terminal of the high-side component of the driver connected to the gate of the main power device is indirectly connected to the gate of the main power device via a diode and / or a resistor.

[0018] Preferably, the main power device and / or the low side component of the driver is a high electron mobility transistor (HEMT), the main power device having a higher power output and a higher blocking voltage than the low side component of the driver.

[0019] Optionally, the main power device and / or the low-side component of the driver comprises a plurality of 2DEG channels arranged in parallel between the source and drain terminals of the main power device.

[0020] Optionally, the low-side component of the driver comprises one of a HEMT, a MOSFET, or a MISFET operating as a Miller clamp having a drain terminal connected to a gate terminal of the main power device and a source connected to a source of the main power device, said low-side component being located near or within the structure of the main power device. Preferably, the low-side component of the driver is a HEMT, and can use similar layers as the main power device for ease of manufacturing.

[0021] Optionally, at least the low-side component of the driver comprises a normally-on or a normally-off transistor, or a parallel combination of normally-on and normally-off transistors.

[0022] Optionally, the low-side component is configured to provide an increased resistance when the low-side component is in an off-state and to provide a decreased resistance when the low-side component is in an on-state.

[0023] Optionally, the low-side component of the driver includes said HEMT, the HEMT comprising a plurality of p+ GaN islands displaced in a dimension perpendicular to current flow, with all p+ islands connected to a gate terminal. By p+ GaN here is meant a layer of gallium nitride highly doped with an acceptor-type dopant (such as magnesium), e.g., at least 1e19 cm -3 would be considered an appropriately high level of doping.

[0024] Optionally, the GaN chip comprises one or more further 2DEG low power transistors connected to the main power device or low side components of the driver.

[0025] Optionally, at least one high-side component is configured as a hole conducting component.

[0026] Optionally, the at least one high-side component is provided in a first semiconductor material and the at least one low-side component is provided in a second semiconductor material, the first semiconductor material and the second semiconductor material being different semiconductor materials.

[0027] Optionally, at least one high-side component and at least one low-side component operate as CMOS cells.

[0028] Optionally, a further low-side component of the driver is arranged in parallel with the at least one low-side component of the driver and is provided in a semiconductor region comprising a material other than GaN (first semiconductor).

[0029] Optionally, the further low-side component comprises an n-channel MOSFET, an n-channel JFET or a PNP bipolar transistor, or an NPN transistor with an additional inverter driving its base.

[0030] According to a further embodiment of the present disclosure, a power integrated circuit (power IC) is provided, the power integrated circuit comprising a gallium nitride chip (GaN chip) based on a heterojunction structure including at least one gallium nitride (GaN) layer and at least one aluminum gallium nitride (AlGaN) layer. The GaN chip includes at least one main power device having a source terminal, a drain terminal, and a gate terminal, and a two-dimensional electron gas (2DEG) formed at the interface between the AlGaN layer and the GaN layer, and the GaN chip is disposed between the source terminal and the drain terminal, and at least a portion of the 2DEG layer is modulated by a charge applied to the gate terminal. A driver is also provided, the driver including at least one low-side component and at least one high-side component, the low-side component having one terminal connected to a low DC voltage rail (e.g., ground) and at least one other terminal connected to the gate of the main power device, and the high-side component having at least one terminal connected to a high DC voltage (e.g., VDD) and at least one other terminal connected directly to the gate of the main power device or indirectly to the gate terminal of the main power device via a diode and / or a resistor. At least one low-side component of the driver, responsible for discharging the input capacitance of the main power device during turn-off of the main power device, is monolithically integrated within the GaN chip, and at least one high-side component of the driver, responsible for charging the input capacitance of the main power device, is integrated in a different semiconductor region based on a different material other than GaN.

[0031] The main power device may be a HEMT (High Electron Mobility Transistor) and may feature a two-dimensional gas (2DEG) at the heterojunction interface between an AlGaN layer and a GaN layer, disposed between the source and drain terminals. This may be a normally-off or normally-on device. It may feature a p-type GaN gate (made of magnesium, for example) to modulate the 2DEG channel in the region between the source and drain terminals. An ohmic or Schottky metal may be disposed on top of the p-type gate to form the gate terminal. Alternatively, it may feature an insulated gate or a Schottky gate. The main power device may incorporate several fingers or cells to scale up current capability.

[0032] The main power device may feature multiple 2DEG channels formed between subsequent layers of GaN and AlGaN. The multiple 2DEG layers serve to reduce the on-state resistance between the source and drain terminals when the device is in the on-state. The multi-channel HEMT may feature a tri-gate or FinFET structure to control the channels, or may be based on a CASCODE configuration.

[0033] At least one low-side component of the driver may be a HEMT device featuring a 2DEG and operating similarly to a Miller clamp. Its drain terminal may be connected to the gate terminal of the GaN power device, and its source may be connected to the source of the main power device. The at least one low-side component (Miller clamp) may be integrated within the GaN chip and located alongside, next to, or even within the main power device (Figure 4). The at least one low-side component (low-side HEMT) has a lower on-state current and lower blocking voltage capability than the power device. As used herein, the term blocking voltage is the voltage that can be applied across the drain-source terminals of a component before it begins to conduct due to a breakdown mechanism or a significant increase in leakage current. This is also called the breakdown voltage or avalanche voltage. This is the maximum voltage that can be applied across a component, beyond which it begins to conduct and allow current to flow, even when the device is biased in its off-state operating mode. In some cases, breakdown voltage may refer to the voltage that causes the device to fail open (i.e., the device can no longer pass current when subsequently biased in its on-state operating mode).

[0034] Alternatively, at least one low-side component of the driver can be an n-channel MOSFET or MISFET using a classical insulated gate and surface channel, monolithically integrated on the GaN chip.

[0035] The driver's low-side component can be a normally-off or normally-on device, or a parallel combination between a normally-on device and a normally-off device. The driver's low-side component can be a low-side HEMT, fabricated in the same process steps and using similar layers as the main power device, and therefore does not add any complexity to the process flow. The low-side HEMT can be a lower-voltage and lower-power device than the main GaN power device. Its size can be significantly smaller than that of the main power device. The low-side HEMT (the driver's low-side component) can be self-isolated from the main power device. Alternatively, the main power device and the low-side HEMT can be located in two different locations in the active area with isolation provided between them.

[0036] If the main power device is formed using multiple 2DEG channels, it is preferable to use multiple channels for the low-side component (low-side HEMT) with a gate architecture similar to that of the main power device. Alternatively, the low-side component of the gate driver (Miller clamp) can feature a single 2DEG channel, while the power devices can feature multiple 2DEG channels.

[0037] The low-side HEMT device may be based on or incorporate a p+ island design as described in U.S. Pat. Nos. 11,081,578, 11,404,565, and F. Udrea et al. [1] and L. Efthymiou et al. [2].

[0038] The driver may incorporate other components and logic blocks. For example, the driver may incorporate a first inverter stage in series with a second inverter stage, the second inverter stage comprising the at least one low-side component and the at least one high-side component. The first inverter stage may be driven by a PWM signal from a controller, and the second inverter stage may have one or more outputs directly or indirectly connected to the gate terminal of the main power device (via resistors and / or diodes). The driver may also incorporate one or more bypass capacitors, diodes (such as Schottky or Zener) for clamping and protection, or multiple DC rails for biasing.

[0039] An additional low-side component of the first inverter stage may also be monolithically integrated within the GaN chip in the form of an additional low-power HEMT (FIG. 5). The drain and source of the additional low-power HEMT may be connected to the gate and source, respectively, of at least one low-side component of the second stage of the driver. The additional low-power HEMT may have lower power and possibly lower blocking voltage capability than the low-power components of the driver. The additional low-power HEMT may be part of the first inverter stage of the driver and connected to the PWM signal.

[0040] The first inverter stage may also incorporate an additional high-side p-channel device (using hole conduction), which may have a lower power than the high-side p-channel device of the second inverter stage.

[0041] Alternatively, further low-side components of the first inverter stage may be integrated in a different semiconductor region based on a different material other than GaN.

[0042] Furthermore, any logic or low-power components (part of the driver or controller or sensing and protection circuitry) or components formed with n-channel (i.e., characterized by electronic conduction) or playing the role of low-side devices can be monolithically integrated within the GaN chip in the form of low-power HEMTs, taking advantage of the high performance of HEMTs, including the high electron mobility, low on-state resistance, and low parasitic capacitance of the 2DEG channel. Alternatively, for matching purposes, or due to the need for local integration of CMOS circuits, or due to the need for the use of bipolar transistors as low-power n-channel components, the low-side components, except for at least one low-side component of the drive (Miller clamp), can be integrated within a different semiconductor region based on a different material other than GaN.

[0043] Furthermore, at least one high-side component and any other components featuring p-channel devices (using hole conduction rather than electron conduction) or any components featuring npn or pnp transistors can be incorporated into different semiconductor regions based on different materials other than GaN.

[0044] Figure 6 shows an NPN transistor (integrated in a different semiconductor region based on a different material than GaN) that is monolithically integrated with the main power device and features a low-power HEMT on the low side of the driver, while the NPN transistor is on the high side of the driver, monolithically integrated with the main power device. In this figure, the first stage of the inverter is shown implemented on a silicon chip, showing an n-channel MOSFET and a p-channel MOSFET in a CMOS configuration.

[0045] Optionally, an additional low-side component (of the second stage) can be configured in parallel with at least one low-side component (Miller clamp) and located in the different semiconductor region based on a different material other than GaN. This component can be, for example, an n-channel MOSFET, an n-channel JFET, or a PNP transistor (FIG. 7a), or an NPN transistor with an additional inverter located at its base (FIG. 7b). The role of this additional low-side component of the driver is to assist in discharging the input capacitance during turn-off and thus provide a parallel path for transient current flow from the main power device during turn-off. For example, if a PNP transistor is added, a parallel combination between a different semiconductor region of the PNP transistor based on a different material other than GaN and the low-side component of the driver (Miller clamp) integrated into the GaN chip can be more stable at high temperatures. On the other hand, bipolar devices fabricated with GaN, such as HEMTs, are known to have a significant increase in on-state resistance at high temperatures due to a decrease in channel mobility (2DEG mobility) at high temperatures. On the other hand, the base-emitter junction voltage decreases at high temperatures, and carrier injection increases at high temperatures. As a result, a parallel combination of a low-side GaN HEMT and a low-side PNP transistor made of a different semiconductor material can provide more stable operation over temperature. The same argument applies if an NPN transistor with an additional inverter in the base is used instead of a PNP transistor. The use of additional low-side components in the driver can be advantageous to more efficiently absorb higher dV / dt currents and therefore increase dV / dt immunity.

[0046] The different semiconductor regions based on different materials other than GaN can be part of a silicon companion chip. The silicon chip can optionally (and preferably) be located near the GaN chip, preferably in the same package or module. Both the silicon chip and the GaN chip can have a lateral configuration, thus allowing for a simple die for die bonding. Thus, the two chips (GaN and Si) can be integrated in the same package or module in a hybrid mode.

[0047] The advantage of having a silicon companion chip is that at least one high-side component of the driver can be made with a p-channel MOSFET or an npn bipolar transistor, which can be fabricated with good performance in mature silicon processes (e.g., 0.35um, 0.18, or 0.13um nodes). Such transistors (i.e., p-channel or bipolar) do not exist or have very poor performance when fabricated in gallium nitride. The silicon companion chip can be fabricated, for example, in a CMOS process, a bipolar process, a CMOS-bipolar probe, a bipolar-CMOS-DMOS (BCD) process, or a high-voltage CMOS process.

[0048] Furthermore, p-channel high-side components in silicon (e.g., MOSFETs) can be combined with n-channel low-side components in GaN (e.g., HEMTs) to form efficient CMOS-type cells that allow low power consumption (virtually zero in steady state and relatively small in transient conditions) and optimized area consumption.

[0049] Furthermore, the n-channel low-side component (HEMT) in GaN can be placed very close to the main power device, thereby reducing undesired parasitics (especially inductance) between its drain terminal and the gate of the main power device. This can help tolerate higher dV / dt and dI / dt signals during switching. The high mobility of HEMT (>1600 cm 2 Considering the low-side component's V(Vs) and its low parasitic capacitance, such a device could potentially have higher performance or occupy a smaller area than an equivalent n-channel transistor integrated in silicon. As already mentioned, its location in close proximity to the power device is very important because it serves to quickly discharge the input capacitance during turn-off and minimizes gate signal oscillations. As used herein, the terms proximate or very close mean "close." In this context, it means that the low-side component can be positioned either very close to the main power device or within the structure of the main power device.

[0050] The low-side component (HEMT) in GaN can be turned on in high resistance mode (ohmic range) during the on-state or active reverse conduction of the main power device, and can be fully turned on in low resistance mode (ohmic range) during the turn-off or off-state or reverse conduction of the main power device.

[0051] The different semiconductor regions based on different materials other than GaN can be part of a substrate physically below (or adjacent to and below) the GaN and AlGaN layers (Figure 8). This allows for a high level of integration and a very compact solution. Access to the substrate can be achieved by etching through the GaN layer located on top. Transistors in the substrate can be fabricated by etching through the GaN layer and using typical techniques such as implantation, oxidation, or deposition of oxide layers to form the transistors.

[0052] The substrate can be made of silicon or silicon carbide. Silicon carbide is more expensive than silicon, but offers a higher breakdown field and better matching with the overlying GaN / AlGaN layer. Furthermore, the presence of SiC may allow for the growth of thinner layers of GaN on the SiC substrate. Nevertheless, the channel mobility of p-channel transistors made of silicon is higher than that of equivalent p-channel transistors made of silicon carbide.

[0053] In a further embodiment of the present disclosure (FIG. 9), a power integrated circuit includes a half-bridge circuit including a low-side main power device within a GaN chip and a high-side main power device disposed within the GaN chip or an additional GaN chip. A driver is provided including a first pair and a second pair, each pair including at least one low-side component and at least one high-side component, the first pair configured to charge and discharge the input capacitance of the low-side main power device during turn-on and turn-off of the low-side main power device, and the second pair configured to charge and discharge the input capacitance of the high-side main power device during turn-on and turn-off of the low-side main power device. The driver further includes a level shifter that shifts the low-voltage control of the first pair to the high-voltage control of the second pair.

[0054] Each of the at least one low-side component of the driver is in the GaN chip or in a further GaN chip. Finally, each of the at least one high-side component of the driver is integrated in a different semiconductor region based on a different material other than GaN.

[0055] As already mentioned above, different semiconductor regions based on different materials other than GaN may be part of a silicon companion chip or may be part of a silicon or silicon carbide substrate.

[0056] The level shifter may also be part of a silicon companion chip (or part of a silicon or silicon carbide substrate), or its elements may be located on the silicon chip and other elements may be located on the GaN chip or further GaN chips.

[0057] An isolation region made of optical, capacitive, and inductive (magnetic) elements can be provided between the logic signal (PWM) from the controller and the input driver. For example, an optocoupler featuring an LED and a photodiode can be used for isolation.

[0058] A half-bridge including two main power devices can be integrated onto a single GaN chip. This would be preferable to reduce the number of components and reduce complexity or cost. However, integrating the low-side high-voltage device with the high-side high-voltage device poses significant challenges in terms of voltage crosstalk and isolation. For this reason, the two main power devices may be located in separate chips, each with a different substrate.

[0059] Each of the main power devices may feature a low-side driver component based on a 2DEG and operating similarly to a Miller clamp. The high-side driver component (e.g., a p-channel MOSFET or bipolar transistor) may be located in a different semiconductor region based on a different material other than GaN. The high-side components may have different DC rail voltages (level-shifted relative to each other).

[0060] In a further embodiment of the present disclosure (FIG. 11), a power integrated circuit is provided comprising: a plurality of GaN chips, each featuring a main power device and a driver low-side component (Miller clamp); all main power devices connected in parallel to provide higher output current and / or lower on-state resistance; and a single silicon companion chip featuring at least one driver high-side component, the at least one driver high-side component connected directly (or indirectly via a resistor and / or diode) to all drain terminals of the driver low-side components and further connected to the gate terminal of the main power devices.

[0061] In this embodiment, instead of having one silicon companion chip for each GaN chip, a single companion chip is provided for multiple GaN chips arranged in parallel, which is advantageous as it reduces the BOM and provides a more efficient solution from an assembly and cost standpoint.

[0062] The silicon companion chip described above may additionally incorporate any of the following circuit blocks: - Level shifter (to shift the signal for high-side power devices) - Logic circuits (inverters, gates) - PWM controller - Voltage regulator (adaptable to a wide range of rail voltages) - Start circuit (to provide DC voltage from the high voltage rail) - Bandgap reference (to provide a temperature stable reference voltage) - Current sense or current amplifier or transconductance circuit (to provide current sensing or facilitate current sensing or to amplify the signal from a current sensing device) - Temperature sensing (e.g. using the VPTAT circuit) - Overcurrent and overheat protection circuit - Memory storage (e.g. for calibration) - Undervoltage lockout circuit - Slew rate control circuit - ESD protection devices

[0063] The GaN chips described above can additionally incorporate a current sensing device or a high voltage current sensing switch that is used to facilitate current sensing.

[0064] In this disclosure, unless explicitly stated, a heterojunction transistor may be any known transistor based on a heterojunction, such as a p-gate HEMT transistor, or an insulated gate transistor such as a Schottky gate transistor or a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor). A diode may be a Schottky diode, a Zener diode, or a pn diode, or a diode made of a transistor by connecting the gate terminal to any of the other terminals. A GaN chip may be a heterojunction chip or may incorporate a heterojunction power device, which may be referred to as a heterojunction smart power device, a heterojunction smart chip, a heterojunction power integrated circuit, or a heterojunction integrated circuit.

[0065] The power IC can incorporate a GaN chip or multiple GaN chips and a silicon companion chip in a single package or a single module.

[0066] BRIEF DESCRIPTION OF THE DRAWINGS These and other aspects are now described. [Brief explanation of the drawings]

[0067] [Figure 1] 1 shows an exemplary schematic diagram of a known totem pole driver; [Figure 2] 1 shows an exemplary schematic diagram of a known two-stage CMOS inverter type driver; [Figure 3]1 exemplarily shows a schematic diagram of a gate driver and a main power device according to the present disclosure; [Figure 4] 4 shows, by way of example, a schematic cross-sectional view of an example of a GaN-integrated component such as that shown in FIG. 3. [Figure 5] 10A and 10B are schematic diagrams of additional examples of gate drivers and main power devices according to the present disclosure, where the gate driver is partially integrated in silicon and partially integrated in GaN; [Figure 6] 10A and 10B are schematic diagrams of additional examples of gate drivers and main power devices according to the present disclosure, where the gate driver is partially integrated in silicon and partially integrated in GaN; [Figure 7a] 10A and 10B are schematic diagrams of additional examples of gate drivers and main power devices according to the present disclosure, where the gate driver is partially integrated in silicon and partially integrated in GaN; [Figure 7b] 10A and 10B are schematic diagrams of additional examples of gate drivers and main power devices according to the present disclosure, where the gate driver is partially integrated in silicon and partially integrated in GaN; [Figure 8] 1 illustrates, by way of example, a schematic cross-sectional view of an example of a component integrated with GaN and silicon on the same wafer according to the present disclosure. [Figure 9] FIG. 10 exemplarily shows a schematic diagram of an additional example of the present disclosure in which a combination of gate drivers and main power transistors may be used in a half-bridge configuration. [Figure 10] FIG. 4 illustrates an exemplary block diagram of a companion silicon chip with the GaN chip of FIG. 3 in accordance with the present disclosure. [Figure 11] 1 illustrates an exemplary configuration of multiple GaN chips of the present disclosure connected in parallel with one silicon companion chip. DETAILED DESCRIPTION OF THE INVENTION

[0068] Detailed Description FIG. 1 shows a schematic diagram of a totem-pole driver in the prior art. The illustrated totem-pole driver comprises pnp and npn complementary transistors. The npn transistor Q1 (as a high-side component) has its collector connected to a high DC rail VDD, and the pnp transistor Q2 (as a low-side component) has its collector connected to a low-voltage DC rail. In the example shown in FIG. 1, the collector of the pnp transistor is connected to the source terminal of a power device Q3. The emitters of the two transistors may be connected together and, optionally, to the gate of the power device via a resistor (not shown here).

[0069] FIG. 2 shows a schematic diagram of a two-stage CMOS inverter driver known in the prior art. The driver comprises a CMOS inverter as the first stage. In the illustrated example, the second inverter stage comprises three parallel inverters. Fewer or more inverters may be used in parallel. The output of the second stage is optionally connected to the gate of a power device via a resistor (not shown here).

[0070] FIG. 3 shows a schematic diagram of the gate driver and main power device, where the gate driver is partially integrated in silicon and partially integrated in GaN. The main power device Q4 in this embodiment is integrated in GaN. In the example shown in FIG. 3, the part of the gate driver integrated in silicon is a CMOS inverter INV1 and a high-side device Q6, which is a p-channel MOSFET. The part of the gate driver integrated in GaN is a low-side device Q5, which in this example is a GaN HEMT.

[0071] FIG. 4 shows a schematic cross-sectional view of an example of a GaN-based component as shown in FIG. 3. The cross-sectional view shows the substrate and epitaxial stack including a silicon substrate 404, a transition layer 403, a GaN layer 402, and an AlGaN layer 401. Two devices are built on this material: a main power HEMT 40 and a gate driver low-side device 41. Both devices are three-terminal devices with drain, source, and gate contacts. Both devices shown have p-GaN gates. The main power HEMT 40 can be a higher voltage rated device than the gate driver low-side device 41, as indicated by the longer drift region (i.e., the separation from the drain contact to the gate contact) of the main power HEMT. As shown in FIG. 3, the electrical connection between the gate driver device and the main power HEMT can be made using track metal.

[0072] 5 shows a schematic diagram of an additional example of a gate driver and main power device in which the gate driver is partially integrated in silicon and partially integrated in GaN. In this example, as in the previous example, the main power HEMT Q9 and at least one gate driver low-side device Q10 are integrated in GaN. However, in this example, an additional low-side device Q11 is integrated in GaN, and the additional low-side device may be a GaN HEMT. All gate driver high-side devices (Q7 and Q8) in the example shown in FIG. 5 are integrated in silicon and may be p-channel MOSFETs.

[0073] FIG. 6 shows a schematic diagram of an additional example of a gate driver and main power device, where the gate driver is partially integrated in silicon and partially integrated in GaN. The main power device Q15 in this embodiment is integrated in GaN. In the example shown in FIG. 6, the part of the gate driver integrated in silicon is a CMOS inverter (Q13, Q14) and a high-side device Q12, which is an npn transistor. In this example, the npn transistor is driven by the gate driver's input signal. The gate driver's input signal may be a signal from a controller, such as a PWM signal or another pulse signal. The part of the gate driver integrated in GaN is the low-side device Q16, which in this example is a GaN HEMT. The gate signal for the low-side device GaN HEMT is the output of the CMOS inverter.

[0074] FIG. 7a shows a schematic diagram of an additional example of a gate driver and main power device Q15, where the gate driver is partially integrated in silicon and partially integrated in GaN. In this example, the gate driver in silicon includes a totem-pole driver (Q19, Q20A) as shown in FIG. 1 and further includes a CMOS inverter (Q17, Q18). The totem-pole driver (Q19, Q20A) output is connected to the gate of power device Q15, optionally via a resistor (not shown here). The output of the Si CMOS inverter (Q17, Q18) is used to drive the low-side GaN device Q16. In this example, the low-side of the totem-pole driver is configured in parallel with at least one low-side GaN component Q16. Its role is to assist in discharging the input capacitance during turn-off, thus providing a parallel path for transient current flow during turn-off leaving the main power device Q15. This is achieved while maintaining the advantage that the n-channel low-side component Q16 in GaN (HEMT) is placed very close to (i.e., on-chip) the main power device Q15, thus reducing undesirable parasitics (especially inductance) between its drain terminal and the gate of the main power device.

[0075] Figure 7b shows a schematic diagram of an additional example of a gate driver and main power device Q15, where the gate driver is partially implemented in silicon and partially implemented in GaN. Figure 7b is similar to the example shown in Figure 7a, but in this example, PNP transistor Q20A has been replaced with inverter INV2 and NPN transistor Q20B.

[0076] FIG. 8 shows a schematic cross-section of an example of a component built on GaN and silicon (i.e., monolithically integrated, whereby both the driver and GaN device are in thermal equilibrium) on the same wafer. The cross-section shows the substrate and epitaxial stack, including a silicon substrate 404, a transition layer 403, a GaN layer 402, and an AlGaN layer 401. Two devices are built on this material: a main power HEMT 40 and a gate driver low-side 41. Both devices are three-terminal devices with drain, source, and gate contacts. Both devices shown have p-GaN gates. The cross-section additionally includes a driver high-side component 42 built on the silicon substrate 404 by using conventional techniques to access the substrate. In this example, the high-side component comprises a p-channel MOS transistor.

[0077] FIG. 9 shows a schematic diagram of an additional example in which the gate driver and main power transistor combination shown in the previous example can be used in a half-bridge configuration. The gate driver has two pairs of devices associated with it. Each pair includes a low-side device and a high-side device. There are two pairs because there are two power devices in the half-bridge configuration. The main power device Q24 may be used as the half-bridge low-side device, and the main power device Q23 may be used as the half-bridge high-side device. The gate driver for the half-bridge low-side device may receive a PWM signal (or another pulse signal) from the low-side controller. The PWM signal may be inverted as shown. The gate driver for the half-bridge low-side device in the example shown in FIG. 9 includes a first pair of devices Q22 and Q26. The gate driver for the high-side device may also receive a signal from the low-side controller, but the signal must be level-shifted using a level shifter. The gate driver for the half-bridge high-side device in the example shown in FIG. 9 includes a second pair of devices Q21 and Q25.

[0078] The level shifter may also be part of a silicon companion chip as shown in FIG. 9, or some elements of it may be located on the silicon chip and other elements on the GaN chip (not shown here).

[0079] Figure 10 shows an example block diagram of a companion silicon chip with the GaN chip of Figure 3. In addition to the high-side components 1001 of the gate driver, the silicon companion chip can be utilized to include a selection of control and protection circuits to benefit in terms of speed, power dissipation, design flexibility, yield, etc., due to the maturity of silicon technology compared to GaN technology, particularly with regard to the availability of p-channel devices. The control and protection circuits include, but are not limited to, current sensing circuits, bandgap references, overcurrent protection, undervoltage lockout (UVLO), slew rate control, overtemperature detection and protection, voltage regulators, level shifters, ESD protection, logic circuits, start-up circuits, and / or any other control and protection circuits.

[0080] FIG. 11 shows another embodiment of the present invention in which multiple GaN chips (GaN chip 1, GaN chip 2, .... GaN chip N) are connected in parallel with one silicon companion chip. Each GaN chip includes the main power device and associated low-side components of the driver, while the high-side components of the driver are located within the silicon chip. In addition, the silicon chip includes a selection of control and protection circuitry similar to FIG. 10.

[0081] Those skilled in the art will understand that in the preceding description and the appended claims, positional terms such as "top," "above," "overlapping," "below," "lateral," and the like are made with reference to conceptual views of the device, such as those showing standard cross-sectional perspectives and those shown in the accompanying drawings. These terms are used for ease of reference but are not intended to be terms of limiting nature. Thus, these terms should be understood to refer to the device when oriented as shown in the accompanying drawings.

[0082] While the present disclosure has been described in terms of the above preferred embodiments, it should be understood that these embodiments are merely examples and that the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and alternatives in light of this disclosure that are believed to fall within the scope of the appended claims. Each feature disclosed or illustrated herein may be incorporated into the present disclosure, whether alone or in any suitable combination with any other feature disclosed or illustrated herein.

[0083] Many other effective alternatives will occur to those skilled in the art, and it will be understood that the present disclosure is not limited to the described embodiments, but encompasses all modifications that fall within the spirit and scope of the present disclosure.

[0084] For example, the term low power as used herein may refer to a typical output power of a controller that is insufficient by itself to drive a gate, and conversely, high power is a typical output power of a driver that is sufficient to drive a gate.

Claims

1. 1. A power integrated circuit comprising: a gallium nitride (GaN) chip with a heterojunction structure, the GaN chip comprising at least one GaN layer and at least one aluminum gallium nitride (AlGaN) layer, the GaN chip comprising at least one main power device comprising a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG) formed at an interface between the AlGaN layer and the GaN layer and between the source terminal and the drain terminal, the gate terminal being configured to modulate at least a portion of the 2DEG when an electric charge is applied to the gate terminal; and a driver comprising at least one low-side component and at least one high-side component, the low-side component having a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device, and the high-side component having at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device; the at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during a turn-off of the main power device, and is monolithically integrated within the GaN chip; A power integrated circuit, wherein the at least one high-side component of the driver is configured to charge the input capacitance of the main power device and is formed in a semiconductor region comprising a material other than GaN.

2. 2. The power integrated circuit of claim 1, wherein the at least one other terminal of the high-side component connected to the gate of the main power device is indirectly connected to the gate of the main power device via a diode and / or a resistor.

3. 3. A power integrated circuit according to claim 1 or 2, wherein the main power device and / or the low-side component of the driver are high electron mobility transistors (HEMT), the main power device having a higher power output and a higher blocking voltage than the low-side component of the driver.

4. 4. The power integrated circuit according to claim 1, wherein the main power device and / or the low-side component of the driver comprises a plurality of 2DEG channels arranged in parallel between the source and drain terminals of the main power device.

5. the low-side component of the driver comprises one of a HEMT, a MOSFET, or a MISFET operating as a Miller clamp having a drain terminal connected to the gate terminal of the main power device and a source connected to the source of the main power device; The power integrated circuit according to any one of claims 1 to 4, wherein the low-side component can be located in the vicinity of the main power device or within the structure of the main power device.

6. 6. A power integrated circuit according to any one of claims 1 to 5, wherein the at least low-side component of the driver comprises a normally-on or a normally-off transistor, or a parallel combination of normally-on and normally-off transistors.

7. 5. The power integrated circuit of claim 4, wherein the low-side component of the driver is configured to provide an increased resistance when the low-side component of the driver is in an off-state and a decreased resistance when the low-side component of the driver is in an on-state.

8. 6. The power integrated circuit of claim 5, wherein the low-side component of the driver comprises the HEMT, the HEMT comprising a plurality of p+ GaN islands displaced in a direction perpendicular to current flow between the source and drain terminals of the HEMT, all of the plurality of p+ GaN islands connected to the gate terminal of the HEMT.

9. A power integrated circuit according to any one of claims 1 to 8, wherein the GaN chip comprises one or more further 2DEG low power transistors connected to the main power device or the low side component of the driver.

10. 10. A power integrated circuit according to any one of claims 1 to 9, wherein the at least one high-side component of the driver is configured as a hole conducting component and / or is a p-channel MOSFET and / or is a bipolar NPN transistor.

11. 11. The power integrated circuit of claim 1, wherein the at least one high-side component of the driver is provided in a first semiconductor material and the at least one low-side component of the driver is provided in a second semiconductor material, the first and second semiconductor materials being different semiconductor materials.

12. 12. The power integrated circuit of claim 11, wherein the at least one high-side component of the driver and the at least one low-side component of the driver operate as CMOS cells.

13. 13. The power integrated circuit according to claim 1, wherein a further low-side component of the driver is arranged in parallel with the at least one low-side component of the driver and is provided in the semiconductor region comprising a material other than GaN.

14. 14. The power integrated circuit of claim 13, wherein the further low-side component of the driver comprises an n-channel MOSFET, an n-channel JFET, a PNP bipolar transistor, or an NPN transistor with an additional inverter disposed on its base terminal.

15. 1. A power integrated circuit comprising: at least one heterojunction gallium nitride (GaN) chip, comprising at least one GaN layer and at least one aluminum gallium nitride (AlGaN) layer, the GaN chip comprising at least one main power device comprising a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG) formed at an interface between the AlGaN layer and the GaN layer and between the source terminal and the drain terminal, the gate terminal configured to modulate at least a portion of the 2DEG when an electric charge is applied to the gate terminal; a half-bridge circuit comprising a low-side main power device formed in the at least one GaN chip and a high-side main power device formed in the at least one GaN chip or in a further GaN chip; and a driver including a first pair and a second pair, each pair comprising at least one low-side component and at least one high-side component, the first pair configured to charge and discharge the input capacitance of the low-side main power device during the turn-on and turn-off of the low-side main power device, and the second pair configured to charge and discharge the input capacitance of the high-side main power device during the turn-on and turn-off of the low-side main power device; the driver further comprising a level shifter configured to shift a low voltage control of the first pair to a high voltage control of the second pair; each of the at least one low-side component of the driver is formed in the GaN chip or in the further GaN chip; A power integrated circuit wherein each of the at least one high side component of the driver is formed in a semiconductor region comprising a material other than GaN.

16. 1. A power integrated circuit comprising: a plurality of heterojunction gallium nitride (GaN) chips, each comprising at least one GaN layer and at least one aluminum gallium nitride (AlGaN) layer, each of the GaN chips comprising at least one main power device comprising a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG) formed at an interface between the AlGaN layer and the GaN layer and between the source terminal and the drain terminal, the gate terminal configured to modulate at least a portion of the 2DEG when an electric charge is applied to the gate terminal; each of the GaN chips comprises a low-side component of a driver; a plurality of gallium nitride (GaN) chips having a heterojunction structure, the main power devices of the plurality of GaN chips being connected in parallel; and a single silicon companion chip comprising at least one high-side component of the driver, the at least one high-side component of the driver being connected to the drain terminal of the low-side component of the main power device of the plurality of GaN chips and further connected to the gate terminal of the main power device of the plurality of GaN chips; 1. A power integrated circuit comprising:

17. 17. The power integrated circuit of claim 16, wherein the semiconductor region including a material other than GaN comprises a silicon companion chip configured for one of CMOS operation, high voltage CMOS operation, bipolar CMOS operation, bipolar CMOS operation, DMOS (BCD) operation.

18. the single silicon companion chip comprising: Level shifter, logic circuits, voltage regulator, Start circuit, bandgap reference, a current sense, current amplifier, or transconductance circuit; temperature sensing, Overcurrent and overheat protection circuit, memory storage, Undervoltage lockout circuit, slew rate control circuit, Electrostatic discharge (ESD) protection devices, and PWM controller 18. A power integrated circuit according to claim 16 or 17, comprising one or more of:

19. A power integrated circuit according to any preceding claim, wherein the GaN chip comprises one or more current sensing devices or high voltage current sensing switches configured for current sensing.

20. 20. The power integrated circuit of any one of claims 1 to 14 or 19, wherein the semiconductor region comprising a material other than GaN is formed on a semiconductor substrate and is positioned below or adjacent to a heterojunction interface of the GaN chip, the substrate comprising a silicon or silicon carbide material.

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