Method and system for software-based prefetching for low buffer depth sequential read traffic

Abstract

A system and associated method includes a storage circuit and a control circuit that receives at least one instruction of a stream of instructions for the storage device while executing a storage device driver. The control circuit determines that a hardware buffer of the storage device stores fewer than two instructions. In response to the determination that the hardware buffer of the storage device stores fewer than two instructions, the control circuit accesses data associated with an address in the memory of the storage device, where the address is predicted based on an analysis of the stream of instructions, and stores the data in a buffer of a plurality of buffers. The control circuit executes the instructions of the stream of instructions using at least the data stored in the buffer.

Description

[Technical Field]

[0001] The present disclosure relates to a host device system and related methods for software-based prefetching for low hardware buffer depths in a storage device, where the host device is executing a storage device driver. Specifically, the present disclosure relates to analyzing received read instructions by host software to predict a stream of spatially sequential read instructions and prefetch data from memory based on the prediction to improve latency of the stream of instructions. Summary of the Invention

[0002] According to the present disclosure, systems and methods for software-based prefetching are provided that operate on a host device. Specifically, the host device is communicatively coupled to a storage circuit, such as a solid-state drive (SSD) with a low instruction hardware buffer depth, and the host device is executing a storage device driver. In some embodiments, the storage circuit (e.g., SSD device) may be located within the host device or may be connected to the host via a suitable cable. For example, a storage host device may include a storage circuit (e.g., SSD device), control circuitry, and additional memory (e.g., RAM that is faster than the SSD memory). In some embodiments, the storage circuit may be an SSD or other suitable storage non-volatile memory drive that includes a hardware buffer.

[0003] In one approach, current techniques are implemented when the hardware buffer has fewer than two outstanding hardware instructions (e.g., just one hardware instruction). Software-based prefetching may be implemented at least in part on the control circuitry using software, hardware, or a combination thereof. In some embodiments, when the hardware buffer of the storage circuitry has a low buffer depth (e.g., one outstanding hardware instruction stored in the hardware buffer), without software-based prefetching, the control circuitry must access data for input hardware instructions directly from the storage device without the benefit of pipelining or prefetching, which may result in greater latency. To address this issue, prefetching may be initiated by software at the host level (e.g., by a storage device driver) when the number of outstanding hardware instructions in the hardware buffer is low. According to this approach, the storage device driver stores data in a buffer provided on a memory device (e.g., RAM memory) with a shorter access time, thereby reducing the latency of memory accesses and reducing the overall latency of storage accesses.

[0004] In some embodiments, software-based (e.g., driver-based) prefetching can be used to improve instruction processing efficiency at low hardware buffer depths in any suitable host device having control circuitry coupled to a hardware buffer and running a device driver. In some embodiments, the device can be, for example, any suitable host device running a memory device driver.

[0005] In some embodiments, a host device is provided having a control circuit and a storage circuit communicatively coupled to each other. In some embodiments, the control circuit includes a processor, a software instruction buffer, and a storage device driver having a plurality of buffers. In some embodiments, the control circuit is configured to progressively receive a stream of read instructions to be executed by the control circuit (e.g., while executing the storage device driver). The control circuit is further configured to determine, while executing the storage device driver, that a hardware buffer of the storage circuit currently stores fewer than two hardware instructions (i.e., exactly one hardware instruction). In some embodiments, when the control circuit determines that the hardware buffer currently stores fewer than two hardware instructions (i.e., exactly one hardware instruction), the control circuit predicts an address of a future read instruction based on a received read instruction of the stream of instructions. The control circuit then accesses data associated with the predicted address in a memory of the storage circuit and stores the data in a software buffer. In some embodiments, when the control circuit receives the predicted software read instruction, the control circuit accomplishes this by at least prefetching data stored in the software buffer. In some embodiments, the received stream of instructions can be received from an operating system of the host, from another application running on the host, or from a device other than the host device. [Brief explanation of the drawings]

[0006] The following description includes discussion of figures with illustrations provided as examples of implementations of embodiments of the present invention. The figures should be understood by way of example and not by way of limitation. As used herein, reference to one or more "embodiments" should be understood as describing particular features, structures, and / or characteristics included in at least one implementation. Thus, phrases such as "in one embodiment" or "in an alternate embodiment" appearing herein are intended to describe various embodiments and implementations, and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0007] [Figure 1] 1 shows a system diagram of a host device system having storage circuitry, control circuitry, and a storage device driver, according to some embodiments of the present disclosure;

[0008] [Figure 2] 1 shows an illustration of an operating system handling multiple applications while executing a storage device driver, according to some embodiments of the present disclosure;

[0009] [Figure 3] 1 illustrates a diagram of a buffer of a storage device driver in which a stream of instructions is detected to prefetch data for a predicted stream of instructions when the hardware buffer has a small number of hardware instructions, according to some embodiments of the present disclosure;

[0010] [Figure 4] 1 shows an illustrative diagram of a storage device driver at three different times (time t1, time t2, and time t3) according to some embodiments of the present disclosure;

[0011] [Figure 5]1 shows an illustration of two timelines of instruction execution with prefetching disabled and prefetching enabled, according to some embodiments of the present disclosure;

[0012] [Figure 6] 1 shows a flowchart illustrating a process for accessing data associated with an address in a memory of a host device and executing instructions of a stream of instructions using at least prefetched data stored in a buffer, according to some embodiments of the present disclosure;

[0013] [Figure 7] 1 shows a flowchart illustrating a process for marking and reclaiming identified stale buffers according to some embodiments of the present disclosure;

[0014] [Figure 8] 1 shows a flowchart illustrating a process for determining a buffer to be reused from a plurality of buffers when each buffer of the plurality of buffers is already allocated for data associated with a determined stream of instructions, according to some embodiments of the present disclosure;

[0015] [Figure 9] 1 shows a flowchart illustrating a process for addressing input instructions with software-based prefetching, according to some embodiments of the present disclosure; and

[0016] [Figure 10] 1 shows a flowchart illustrating a process for performing a single multi-plane read operation using snap reads triggered by a sequential read command, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0017] According to the present disclosure, a host device system and method are provided for software-based (e.g., storage device driver-based) prefetching of low hardware buffer depths in a storage circuit to improve the quality of operation of the host system (e.g., improve latency when the hardware buffer has a small number of outstanding hardware instructions). In some embodiments, the hardware buffer (e.g., of the storage circuit) may be an instruction stack or instruction queue for the storage circuit. In some embodiments, the hardware buffer and the storage circuit may be located outside the host device (e.g., connected via a suitable cable). The host device may have control circuitry that executes a storage device driver to control the storage device. The storage device driver may provide multiple buffers (e.g., using RAM in the host device). In some embodiments, the control circuitry of the host device may include a processing unit (e.g., a processor) that can operate on instructions in an instruction stream (e.g., an instruction sequential stream), where the control circuitry receives the instruction stream (e.g., when executing the storage device driver). In some embodiments, the spatially sequential stream of read instructions includes instructions stored at sequential memory addresses. In some embodiments, executing instructions may be divided into four timing category stages, including software sending / completing instructions, hardware processing instructions, software idling while hardware processes instructions, and software copying prefetched buffers.

[0018] In some embodiments, operations are performed sequentially with respect to clock cycles for each instruction in the stream of instructions. In a single processor example, hardware processing of a second instruction may not necessarily begin before hardware processing of a first instruction is completed. By analyzing a specific number of instructions in the stream of instructions and predicting which prefetched data will be accessed based on the identified stream of instructions, latency of data access by the host device is improved. In some embodiments, while executing the storage device driver, the storage control circuit analyzes a portion or a specific number of input instructions to predict the stream of instructions associated with prefetched data stored in multiple buffers. Software-based prefetching for the host device driver may enable improved latency of the host device when driving instructions or requests.

[0019] In one approach, when the hardware buffer has a small number of hardware instructions (e.g., less than two or only one hardware instruction), there may be additional latency between each instruction request received by the control circuitry due to the instructions being driven and underutilizing the storage device's pipeline.

[0020] To solve this problem, operation of the host device may cause software (e.g., a storage device driver) to predict and prefetch data associated with at least one instruction so that the storage device driver does not need to idle between receipt of each instruction. Thus, the storage device driver predicts a stream of instructions and prefetches data associated with the predicted stream of instructions before any further requests are received. In this manner, host device latency is reduced in situations where the number of instructions in the hardware buffer is less than two hardware instructions (i.e., or just one instruction).

[0021] In some embodiments, the processor of the control circuitry may be a highly parallel processor that can quickly handle a high instruction bandwidth (e.g., by starting simultaneous processing of a new instruction before the previous instruction has completed).

[0022] In some embodiments, the systems and methods of the present disclosure may refer to a host device communicatively coupled to an SSD storage system, where the host device is running a storage device driver that has multiple buffers for a network protocol interface, such as non-volatile memory express (NVMe) buffers.

[0023] An SSD is a data storage device that uses integrated circuit assemblies as memory to persistently store data. SSDs have no moving mechanical components, which distinguishes them from conventional electromechanical magnetic disks, such as hard disk drives (HDDs) or floppy disks, which contain rotating disks and movable read / write heads. Compared to electromechanical disks, SSDs are typically more resistant to physical shock, operate quieter, and have shorter access times and lower latency.

[0024] Many types of SSDs use NAND-based flash memory, which retains data without power and includes some type of non-volatile storage technology. SSD Quality of Service (QoS) can refer to predictably low latency and consistently high input / output operations per second (IOPS) while processing read / write input / output (I / O) workloads. This means that latency or I / O command completion times must be within a specific range without unexpected outliers. Throughput or I / O speeds may also need to be tightly controlled without causing sudden drops in performance levels.

[0025] The subject matter of the present disclosure may be better understood with reference to FIGS.

[0026] 1 shows an illustration of a host device system 100 having a storage circuit 104, a control circuit 106, and a storage device driver 118 according to some embodiments of the present disclosure. In some embodiments, the host device system 100 may include a host device 102 including the control circuit 106 and the storage circuit 104. In some embodiments, the control circuit 106 may include a processor 120, a software instruction buffer (e.g., reserved in memory 124), and a storage device driver 118 having multiple buffers 116 (e.g., reserved in memory 124). In some embodiments, the multiple buffers 116 and the software instruction buffer may use memory 124 other than the storage circuit 104 (e.g., memory 124 may be a RAM memory with lower access latency than the storage circuit 104).

[0027] In some embodiments, each buffer 114 is configured to store data associated with an instruction of the determined instruction stream (e.g., data prefetched from a predicted address of the instruction stream in storage circuit 104) to manage instruction stream detection for software-based prefetching. In some embodiments, while executing storage device driver 118, control circuit 106 uses software instruction buffer 122 as a temporary software buffer to store received software instructions while analyzing and predicting the instruction stream. In some embodiments, storage circuit 104 includes hardware buffer 112 configured to store hardware instructions. Host device 102 may also include memory 124, such as volatile memory such as RAM memory (e.g., dynamic random access memory (DRAM)), having a fast access time compared to the access time of storage circuit 104 (e.g., SSD). It should be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, host device system 100 may include a hard disk drive (HDD) device in addition to or instead of storage circuit 104.

[0028] In some embodiments, the host device system 100 may receive the stream of instructions 110 from a source located external to the host device 102 or located internal to the host device 102 (e.g., from an application). In some embodiments, the control circuitry 106 may identify the stream of instructions 110 when it receives a read request for a number (e.g., 5, 10, or any other suitable number) of sequential addresses in the storage circuitry 104.

[0029] In some embodiments, memory 124 includes any one or more of: Phase Change Memory (PCM), PCM and switch (PCMS), Ferroelectric Random Access Memory (FeRAM) or Ferroelectric Transistor Random Access Memory (FeTRAM), non-volatile memory such as Magnetoresistive Random Access Memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, memory 124 includes any one of non-volatile memory, volatile memory, or any combination thereof. In some embodiments, control circuitry 106 is communicatively coupled to hardware buffer 112 of storage circuitry 104 to receive information of unprocessed hardware instructions stored in hardware buffer 112. Additionally, control circuitry 106 is communicatively coupled to memory 124. In some embodiments, a data bus interface is used to carry instructions (e.g., instructions 108) or addresses or data associated with instructions. A data bus between memory 124 and control circuitry 106 provides a network bus for reading or writing data through memory 124. Processor 120 of control circuitry 106 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. Processor 120 may include any suitable software, hardware, or both for controlling storage device driver 118, instruction stream prediction, and prefetching of data associated with the predicted instruction stream. Memory 124 may include hardware elements for non-transitory storage of commands or instructions.

[0030] In some embodiments, memory 124 is a multi-plane or three-dimensional (3D) memory array. In some embodiments, memory 124 includes floating gate NAND gates. Control circuitry 106 may receive a sequential read command that triggers a read operation. The read operation may be a snap read operation used to access 4K, 8K, or 16K of data from memory 124. In some embodiments, a snap read operation may be used to access data of any other suitable size from memory 124. In some embodiments, a sequential read command may trigger a read that accesses multiple planes of memory 124. Control circuitry 106 may trigger a multi-plane read by using an independent multi-plane read operation (IMPRO) that accesses portions of at least two different planes of memory 124. To improve the efficiency of IMPRO, control circuitry 106 may be configured to perform IMPRO using snap reads, which allows control circuitry 106 to perform a multi-plane snap read and access at least two planes of memory 124.

[0031] While executing storage device driver 118, control circuitry 106 is configured to receive instructions 108 in stream of instructions 110 and determine how many outstanding hardware instructions are stored within hardware buffer 112. While executing storage device driver 118, when control circuitry 106 determines that the depth of hardware buffer 112 is low (e.g., a hardware buffer depth of just one hardware instruction), control circuitry 106 may prefetch data associated with an address in memory 124, where the address is predicted based on stream of read instructions 110. In some embodiments, while executing storage device driver 118, control circuitry 106 stores the prefetched data for stream of instructions 110 in buffer 114 of multiple buffers 116. When control circuitry 106 receives instruction 108 as part of stream of instructions 110, if the instruction matches the predicted prefetched data, the instruction 108 is fulfilled by storage device driver 118 directly from buffer 114 without needing to further access storage circuitry 104.

[0032] Storage circuit 104 (e.g., an SSD device) may include one or more packages of non-volatile memory dies, where each die includes storage cells. In some embodiments, the storage cells are organized into pages, and the pages are organized into blocks. Each storage cell can store one or more bits of information.

[0033] Although host device system 100 represents one embodiment in which host device 102 is configured with software-based prefetching capabilities while executing storage device driver 118 according to the present disclosure, it should be understood that any other suitable device may have software-based prefetching in a similar manner.

[0034] For clarity and brevity, and not by way of limitation, the present disclosure is provided in the context of software-based prefetching for low hardware buffer depths, providing the features and functionality disclosed herein. Software-based prefetching can be configured by any suitable software, hardware, or both to implement such features and functionality. Software-based prefetching can be implemented, for example, at least in part, in host device system 100 (e.g., as part of host device 102 or any other suitable device that may benefit from improved efficiency with low hardware buffer depth) while executing storage device driver 118. For example, for host device 102 communicatively coupled to a solid-state storage device (i.e., storage circuitry 104), software-based prefetching can be implemented in control circuitry 106 while executing storage device driver 118. In some embodiments, software-based prefetching can be implemented, at least in part, as part of an operating system for the host device system into which storage device driver 118 is integrated.

[0035] FIG. 2 illustrates an illustration of an operating system 202 serving multiple applications (e.g., a first application 210, a second application 212, and a third application 214) while executing a storage device driver 204, according to some embodiments of the present disclosure. While three applications (210, 212, and 214) are shown in FIG. 2, in some embodiments, any suitable number of applications may be included. In some embodiments, the operating system 202 is loaded onto the control circuitry 106 of the host device 102 (see FIG. 1). In some embodiments, the storage device driver 204 includes multiple buffers 206, where each buffer 208 is configured to store data associated with a stream of instructions determined for software-based prefetching. In some embodiments, each buffer 208 may store prefetched data for a stream from an application 210-214 in a memory faster than the storage circuitry 216 (e.g., in memory 124 of FIG. 1). In some embodiments, storage device driver 204, multiple buffers 206, buffer 208, and storage circuit 216 correspond to storage device driver 118, multiple buffers 116, buffer 114, and storage circuit 104, respectively, in Figure 1. Storage device driver 204 may be communicatively coupled to storage circuit 216.

[0036] In some embodiments, storage device driver 204 receives streams of instructions from multiple applications, such as a first stream of read instructions from first application 210, a second stream of read instructions from second application 212, and a third stream of read instructions from third application 214. Storage device driver 204 may also receive stream of instructions 110 from operating system 202 or from outside operating system 202, as shown in system 100 of Figure 1. In some embodiments, storage device driver 204 may receive more than three different streams of read instructions from more than three applications.

[0037] In some embodiments, each buffer 208 of the plurality of buffers 206 may store data associated with a stream of instructions prefetched from the storage circuitry 216. In some embodiments, while executing the storage device driver 204, the control circuitry 106 may track whether a buffer 208 storing data associated with a partial stream of instructions or a complete stream of instructions stores valid data by configuring a bitmap of valid bits. In some embodiments, each buffer 208 of the plurality of buffers 206 may correspond to a bit in the bitmap, where the bitmap includes a flag bit for each buffer 208 of the plurality of buffers 206. When each buffer 208 of the plurality of buffers 206 stores data associated with a partial stream of instructions or a complete stream of instructions, the valid bits may be useful in determining which buffers 208 to clear or overwrite.

[0038] 3 illustrates a diagram of buffer 208 of storage device driver 204 where stream of instructions 302 is detected to prefetch data at predicted addresses of the stream of instructions (e.g., 306, 308, 310, 312, 314, 316, 318, 320) when the hardware buffer has a small number of hardware instructions, according to some embodiments of the present disclosure. In some embodiments, storage device driver 204 and buffer 208 correspond to storage device driver 118 and buffer 114 of FIG. 1, respectively.

[0039] Storage device driver 204 includes buffers 208 that store data associated with a stream of instructions (e.g., 306, 308, 310, 312, 314, 316, 318, and 320). As shown, control circuitry 106 progressively receives input instructions 302 (e.g., a read instruction at address 1001, a read instruction at address 1002, a read instruction at address 1003, a read instruction at address 1004, and a read instruction at address 1005). In some embodiments, while executing storage device driver 204, control circuitry 106 analyzes a certain number of input instructions 302 and predicts the stream of instructions. In some embodiments of the present disclosure, the number of input instructions and the number of buffers are not limited to the number of input instructions 302 and the number of buffers 208 shown in FIG. 3 , respectively. For example, while executing storage device driver 204, control circuitry 106 predicts a stream of instructions because a particular number (e.g., 5 or 10) of requests to read data from five addresses (e.g., addresses 1001-1005) have been received by storage device driver 204. In some embodiments, while executing storage device driver 204, control circuitry 106 prefetches data associated with addresses in the predicted stream of instructions. While executing storage device driver 204, control circuitry 106 does not prefetch any data until it detects a spatially sequential stream of read instructions (e.g., addresses 1001-1005). For example, control circuitry 106 may predict the addresses of the stream of instructions after receiving a read instruction at address 1001 sequentially through a read instruction at address 1005 (thus, control circuitry 106 may predict that the stream will have future read requests for addresses following address 100, i.e., addresses 1006, 1007, 1008, etc.). Thus, while executing storage device driver 204, control circuitry 106 prefetches data 304 associated with future instructions at predicted addresses in the stream of instructions (e.g., 308, 310, 312, 314, 316, 318, and 320).As shown, data prefetched from predicted addresses 1006-1013 is stored in buffer 208 before stream of instructions 302 requests the data from the predicted addresses. By using software-based prefetching, data associated with the predicted addresses in the stream of instructions can be more easily accessed while stored in buffer 208 with less access latency than if it were stored in host memory 124.

[0040] FIG. 4 shows illustrations 400, 401, and 402 of storage device driver 204 at three different times (time t1, time t2, and time t3) according to some embodiments of the present disclosure. For example, the buffer at time t1 may be the same as buffer 208 in FIG. 3. As shown at time t1, the buffer stores data prefetched from spatially sequential addresses 1006-1037 (e.g., 406, 408, 410, 412, 414, 416, and 418). In one example, when the prefetched data from address 1037 is stored in the last entry in buffer 418, the buffer has no more space to store the prefetched data, and prefetching may be temporarily suspended or continue prefetching data into another available buffer. In the illustrated example, the prediction was accurate, and a stream of sequential read instructions 404 began requesting data from address 1006 through address 1037. Because the data was prefetched, storage device driver 204 could place the data from the buffer. When data from address 1037 is requested, while executing storage device driver 204, the control circuitry provides the stored prefetched data from buffer entry 418 and determines that the most recently prefetched data in the buffer was already requested by stream of sequential read instructions 404. Thus, the buffer may be reused for further prefetching of data at predicted sequential addresses in stream of read instructions 404 (e.g., a read instruction at address 1038, a read instruction at address 1039, a read instruction at address 1040, etc.). In some embodiments of the present disclosure, the number of input instructions is not limited to the number of input instructions in stream of sequential read instructions 404 shown in FIG. 4 .

[0041] At time t2, the control circuitry marks the buffer entries as stale and available for reuse. Thus, the buffer entries in the buffer are available to store data associated with a newly identified stream of instructions or to continue prefetching the currently identified stream of sequential read instructions. At time t3, while executing the storage device driver, the control circuitry resumes prefetching predicted instructions for stream of sequential read instructions 404 (e.g., by prefetching data from addresses 1038-1069 into the previously stale buffer). In some embodiments, buffer entries (e.g., 420, 422, 424, 426, 428, 430, and 432) are no longer marked as stale by setting the corresponding valid bits in the valid bitmap to indicate valid data. In another example, the buffer is available for use for a newly predicted stream of instructions. For example, if another stream of instructions requires reading from addresses 2500-2505, the buffer may prefetch data from addresses 2506-2537 for quick data access when processing the instructions.

[0042] In some embodiments, the bitmap of valid bits indicates whether each buffer of the plurality of buffers may be either a valid buffer or a stale buffer. At time t2, the symbol "*" in the buffer entry for buffer 204 indicates the corresponding valid bit for buffer 208 in the bitmap of the plurality of buffers. These valid bits may be useful when determining which buffer memory to clear or overwrite when each buffer of the plurality of buffers stores data associated with a partial stream of instructions or data associated with a complete stream of instructions. Thus, at time t2, buffer 208 is marked as a stale buffer and can be reused by the control circuitry to store data associated with a newly identified stream of instructions.

[0043] 5 shows an illustration of two timelines of executing instructions (e.g., 501, 502, 503, 504, 511, 512, 513, and 514) with prefetching disabled 500 and prefetching enabled 510, according to some embodiments of the present disclosure. To illustrate the comparison between the two timelines 500 and 510, four instructions are shown in each timeline, where each instruction is a sequential read instruction. Additionally, each timeline has a corresponding instruction on the opposite timeline. For example, assume that instruction 501 is the exact same instruction as instruction 511, only with a different implementation for instruction processing.

[0044] In some embodiments, executing instructions may be divided into four timing category stages, including software sending / completing instructions, hardware processing instructions, software idling while hardware processes instructions, and software copying prefetched buffers. However, in general, operations must be performed sequentially with respect to clock cycles for each instruction in the stream of instructions. In the single processor example, hardware processing of second instruction 502 cannot necessarily begin before hardware processing of first instruction 501 is complete.

[0045] In some embodiments of the present disclosure, the no-prefetch timeline 500 shows a cyclical pattern of instruction processing with consistent idle times during which the storage device software waits for instruction processing in hardware to complete. However, once a stream of instructions is predicted by the control circuitry, while the storage device driver is executing (see prefetch timeline), the control circuitry can prefetch data associated with the predicted stream of instructions for the second instruction 512 before the second instruction is received and sent for processing. As expected, the latency of each first instruction 501 and 511 in the two timelines is the same. Because the latency associated with accessing a buffer of multiple buffers is much less than accessing host memory (e.g., RAM memory), the latency of subsequent instructions is reduced. By prefetching data at predicted sequential addresses into the buffers, the control circuitry can quickly access the data when it is requested. The latency of subsequent instructions (e.g., 512, 513, and 514) on the prefetch timeline 510 is reduced, but the latency of the first instruction remains the same as when the control circuit has not yet prefetched any data for the first instruction 511 and is using the first instruction 511 to determine the predicted stream of instructions.

[0046] 6 shows a flowchart illustrating a process 600 for accessing data associated with an address in a memory of a storage device and executing instructions of a stream of instructions using at least the data stored in a buffer, according to some embodiments of the present disclosure. In some embodiments, the referenced control circuitry, storage device driver, instructions of the stream of instructions, storage device, hardware buffer, memory, and buffer may be implemented as control circuitry 106, storage device driver 118, instructions 108 of the stream of instructions 110, storage device 102, hardware buffer 112, memory 124, and buffer 114, respectively. In some embodiments, process 600 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0047] In step 602, while executing the storage device driver, the control circuitry receives at least one instruction from a stream of instructions for the storage device. In some embodiments of the present disclosure, the stream of instructions may be an external source outside the storage device. In some embodiments, the stream of instructions may be an internal source within the operating system (e.g., operating system 202), such as an application with many outstanding instructions to be executed. In some embodiments, while executing the storage device driver, the control circuitry may receive multiple streams of instructions from a source located inside or outside the storage device. In some embodiments, the stream of instructions is a stream of sequential instructions, where at least one instruction is a sequential read instruction. After receiving the stream of instructions, while executing the storage device driver, the control circuitry then determines in step 604 that a hardware buffer of the storage circuitry (e.g., storage circuit 104) stores fewer than two outstanding hardware instructions.

[0048] In step 604, while executing the storage device driver, the control circuitry determines whether the hardware buffer of the storage device currently stores fewer than two instructions. In some examples, when the depth of outstanding hardware instructions in the hardware buffer is low (e.g., just one hardware instruction is stored in the hardware buffer), the time to access data associated with an outstanding instruction stored in a buffer of multiple buffers may be less than the latency of receiving a subsequent instruction in the stream of instructions. In examples without prefetching, the storage device driver and control circuitry experience a high latency to access data associated with an outstanding instruction from memory. In some embodiments, this increase in latency adversely affects the efficiency of the host device's processing power.

[0049] In step 606, while executing the storage device driver, the control circuitry determines the next step in process 600 based on whether the hardware buffer in 604 currently stores fewer than two hardware instructions. If the hardware buffer stores two or more hardware instructions, while executing the storage device driver, the control circuitry executes the outstanding hardware instructions in the hardware buffer without any instruction stream prediction or software-based prefetching while continuing to receive the stream of instructions in 602. In some embodiments, while executing the storage device driver, if the hardware buffer currently stores only one hardware instruction or does not currently hold any instructions, the control circuitry performs stream prediction in 608 by accessing data associated with an address in the memory of the storage device.

[0050] At step 608, while executing the storage device driver, the control circuitry accesses data associated with an address in the memory of the storage device, where the address is predicted based on analysis of the received stream of instructions. In some embodiments, the control circuitry determines the predicted stream of instructions by analyzing a certain number of the received stream of instructions, rather than just based on unprocessed hardware instructions in a hardware buffer. In such embodiments, the control circuitry may determine a buffer of a plurality of buffers, where a corresponding stream of instructions associated with data stored in the buffer matches the predicted stream of instructions. Once the control circuitry determines the buffer, while executing the storage device driver, the control circuitry stores the data in the buffer at 610.

[0051] At step 610, while executing the storage device driver, the control circuitry stores data in a buffer. In some embodiments, the buffer is an available buffer of a plurality of buffers. In some embodiments, the determined buffer may contain data associated with an incomplete stream of instructions, such that any data associated with a newly detected instruction of the sequential instruction stream may be stored in the determined buffer. In such embodiments, the determined buffer may be capable of storing additional data associated with instructions until the stream of instructions ends or the buffer reaches its full memory capacity. In some embodiments, while executing the storage device driver, the control circuitry may maintain data associated with a corresponding stream of instructions associated with each buffer of the plurality of buffers until every buffer has data associated with at least a partial stream of instructions stored for software-based prefetching. In some embodiments of the present disclosure, while executing the storage device driver, the control circuitry may mark buffers as stale or available for reuse to store data associated with a newly identified stream of instructions. According to the present disclosure, data associated with at least one instruction of the predicted stream of instructions stored in the determined buffer is executed by the control circuitry at 612 while executing the storage device driver.

[0052] In step 612, while executing the storage device driver, the control circuitry executes the instructions of the stream of instructions using at least the data stored in the determined buffer. In some embodiments, while executing the storage device driver, the control circuitry can prefetch data to more efficiently execute the stream of instructions rather than waiting longer access times for data associated with each sequential instruction stored in memory. In some embodiments, the stream of instructions is a stream of sequential read instructions.

[0053] 7 shows a flowchart illustrating a process 700 for marking and reclaiming identified stale buffers according to some embodiments of the present disclosure. In some embodiments, the referenced control circuitry, storage device driver, instructions of the instruction stream, storage device, and buffer of the plurality of buffers may be implemented as control circuitry 106, storage device driver 118, instructions 108 of the instruction stream 110, storage device 102, and buffer 114 of the plurality of buffers 116, respectively. In some embodiments, process 700 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0054] In step 702, while executing the storage device driver, the control circuitry configures a plurality of buffers, where each buffer of the plurality of buffers may be assigned data associated with an instruction of a corresponding one of the plurality of streams of instructions received by the driver for the storage device. In some embodiments, the plurality of buffers are configured to be contained within the storage device driver. Each buffer is configured such that, while executing the storage device driver, if the control circuitry detects a further instruction in the received instructions that matches the stream of instructions of the buffer, the data associated with the further instruction may be added to the end of the buffer. Additionally, in some embodiments, each buffer of the plurality of buffers may store data associated with the instruction or an address indicating the data associated with the instruction. In some embodiments, each buffer of the plurality of buffers may correspond to a bitmap, where the bitmap includes a flag bit for each buffer of the plurality of buffers. In some embodiments, the corresponding bitmap is used to track whether a buffer storing data associated with a partial stream of instructions or data associated with a complete stream of instructions is still valid. When each buffer of the plurality of buffers stores data associated with a partial stream of instructions or data associated with a complete stream of instructions, the valid bit may be useful in determining which buffer memory to clear or overwrite. In some embodiments, the valid bitmap uses a single bit for each corresponding data structure (e.g., each buffer), where in some implementations a valid bit value of 1 means that the buffer should not be cleared and a valid bit value of 0 indicates that the stream of instructions for that buffer may no longer need to be detected.

[0055] At step 704, while executing the storage device driver, the control circuitry identifies a stream of instructions by detecting a certain number of sequential read instructions. In some embodiments, while executing the storage device driver, the control circuitry determines a predicted stream of instructions by analyzing a certain number of received stream of instructions. In such embodiments, while executing the storage device driver, the control circuitry may determine a buffer of the plurality of buffers, where a corresponding stream of instructions associated with stored data in the buffer matches the predicted stream of instructions based on the analyzed certain number of instructions in the received stream of instructions. While executing the storage device driver, the control circuitry may then determine a buffer of the plurality of buffers as stale, as at step 706.

[0056] In step 706, while executing the storage device driver, the control circuitry identifies a stale buffer among the plurality of buffers. After identifying a buffer for a given predicted stream of instructions and completing software-based prefetching, while executing the storage device driver, the control circuitry may determine a source of the stream of instructions, such as an application that is not executing, and thus at least one buffer among the plurality of buffers that stored data associated with the stream of instructions for the source. Once the control circuitry identifies a stale buffer, while executing the storage device driver, the control circuitry then marks the identified stale buffer in step 708.

[0057] In step 708, while executing the storage device driver, the control circuitry marks the identified buffer for reuse. In some embodiments of the present disclosure, while executing the storage device driver, the control circuitry marks the identified buffer as stale, for example, by toggling a corresponding valid bit in a valid bitmap to indicate that the data in the identified buffer is no longer valid for use. According to the present disclosure, the marked buffer may be reused by data associated with a newly identified stream of instructions by the control circuitry.

[0058] 8 shows a flowchart illustrating a process 800 for determining a buffer of a plurality of buffers to reuse when each buffer of the plurality of buffers is already allocated for data associated with the determined stream of instructions, according to some embodiments of the present disclosure. In some embodiments, the referenced control circuitry, storage device driver, instructions of the stream of instructions, storage device, and buffer of the plurality of buffers may be implemented as control circuitry 106, storage device driver 118, instructions 108 of the stream of instructions 110, storage device 102, and buffer 114 of the plurality of buffers 116, respectively. In some embodiments, process 800 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0059] In step 802, while executing the storage device driver, the control circuitry identifies a new stream. In some embodiments, while executing the storage device driver, the control circuitry may detect a new stream of instructions that does not match any of the streams of instructions associated with stored data in multiple buffers. Therefore, data associated with the newly identified stream of instructions is stored in a buffer to help reduce latency for subsequent streams of instructions. In some embodiments, while executing the storage device driver, the control circuitry then determines, in 804, whether all buffers are already allocated for valid data associated with the stream of instructions.

[0060] In step 804, while executing the storage device driver, the control circuitry determines whether all buffers of the plurality of buffers have already been allocated for data associated with the corresponding stream of instructions. In some embodiments, while executing the storage device driver, the control circuitry can determine whether each valid bit of a valid bitmap associated with the plurality of buffers is set valid. While executing the storage device driver, the control circuitry then determines 806 the next step in process 800 based on whether all buffers of the plurality of buffers have already been allocated for valid data associated with the stream of instructions.

[0061] In step 806, while executing the storage device driver, the control circuitry determines the next step in process 800 based on whether all buffers of the plurality of buffers are already allocated for data associated with the corresponding stream of instructions. In some embodiments, if the control circuitry determines that all buffers of the plurality of buffers are already allocated for valid data associated with the stream of instructions, while executing the storage device driver, the control circuitry determines a buffer of the plurality of buffers to reuse at 808. However, if, while executing the storage device driver, the control circuitry determines that there is either an unallocated buffer or an aged buffer available, the control circuitry allocates one of the unallocated buffers or an aged buffer for data associated with a new stream of instructions at 810.

[0062] In step 808, while executing the storage device driver, the control circuitry determines a buffer to reuse from the plurality of buffers. In some embodiments, when each buffer of the plurality of buffers is determined to store valid data associated with the stream of instructions, the control circuitry may need to determine which buffer was the least recently used buffer for accessing data associated with the stream of instructions predicted by the control circuitry, the least recently used buffer, or a buffer storing data at an address close to the predicted address of the new stream of instructions. The least recently used buffer is the buffer that has been accessed the longest by the control circuitry, and in some examples, may indicate that while executing the storage device driver, the control circuitry is unlikely to receive a stream of instructions matching the corresponding stream of instructions associated with the stored data of the least recently used buffer. In other implementations of the present disclosure, while executing the storage device driver, the control circuitry may determine a buffer to reuse based on which buffer is least recently used. In such implementations, while executing the storage device driver, the control circuitry may maintain a counter for each buffer, where the counter increments each time the control circuitry accesses data associated with the corresponding buffer while executing the storage device driver. Thus, the control circuitry can determine the least recently used buffer indicated by the buffer with the smallest corresponding counter value. In some embodiments, while executing the storage device driver, the control circuitry can use a combination of least recently used and least recently used to determine the buffer to reuse. In some embodiments, the buffer storing data at an address near the predicted address of the new stream of instructions can be the buffer that prefetched a first portion of the predicted address of the stream of instructions, while data at a second portion of the predicted address is also prefetched.In some embodiments, if no other buffers are available, the control circuit reuses the buffer that stored the prefetched data for the first portion of the predicted address to store the prefetched data for the second portion of the predicted address. Once the buffer is determined, the determined data stored on the buffer is cleared to store data associated with the newly identified stream of instructions.

[0063] In step 810, while executing the storage device driver, the control circuitry allocates one of the plurality of unallocated or stale buffers for data associated with the new instruction stream. When, while executing the storage device driver, the control circuitry determines that at least one of the unallocated or stale buffers exists, while executing the storage device driver, the control circuitry may store the data associated with the newly identified buffer in the unallocated buffer or clear the stale buffer so that the data associated with the newly identified buffer can be stored. However, for example, if there is one unallocated buffer and one stale buffer available, while executing the storage device driver, the control circuitry may determine to store the data associated with the newly identified instruction stream in the unallocated buffer because it requires fewer steps to store the data associated with the new instruction stream.

[0064] 9 shows a flowchart illustrating a process 900 for handling input instructions with software-based prefetching according to some embodiments of the present disclosure. In some embodiments, the referenced control circuit, storage device driver, instruction of the instruction stream, hardware buffer, and buffer of the plurality of buffers may be implemented as control circuit 106, storage device driver 118, instruction 108 of the instruction stream 110, hardware buffer 112, and buffer 114 of the plurality of buffers 116, respectively. In some embodiments, process 900 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0065] In step 902, while executing the storage device driver, the control circuitry identifies an input instruction. In some embodiments, the input instruction may be one instruction of a stream of instructions detected by the control circuitry while executing the storage device driver. In some embodiments, while executing the storage device driver, the control circuitry then determines the next step of process 900 at 904 based on whether the hardware buffer stores less than two hardware instructions (i.e., or exactly one instruction).

[0066] At step 904, while executing the storage device driver, the control circuitry determines whether the hardware buffer stores fewer than two hardware instructions. In some embodiments, while executing the storage device driver, if the control circuitry determines that the hardware buffer stores at least two hardware instructions, the control circuitry then processes the input instruction without software-based prefetching at 908. In other embodiments, while executing the storage device driver, when the control circuitry determines that the hardware buffer stores fewer than two hardware instructions, the control circuitry then determines at 906 the next step in process 900 based on whether the instruction is an appropriately sized read instruction.

[0067] At step 906, while executing the storage device driver, the control circuitry determines the next step for process 900 based on whether the instruction is a read instruction of an appropriate size (e.g., 4 KB, 8 KB, . . . , 128 KB). In some embodiments, while executing the storage device driver, if the control circuitry determines that the instruction is neither a read instruction nor of an appropriate size, the control circuitry then processes the incoming instruction without software-based prefetching at 908. In other embodiments, while executing the storage device driver, when the control circuitry determines that the instruction is a read instruction of an appropriate size, the control circuitry then determines the next step for process 900 by determining at 910 whether an identified buffer of the plurality of buffers exists that stores data associated with a matching stream of instructions.

[0068] In step 908, while executing the storage device driver, the control circuitry accommodates incoming instructions without software-based prefetching. In some embodiments, hardware buffers with a depth greater than two hardware instructions may not take advantage of software-based prefetching. Also, prefetching data associated with a stream of instructions that includes a write instruction does not guarantee accurate prefetched data because the write instruction may modify data that has already been prefetched.

[0069] At step 910, while executing the storage device driver, the control circuitry determines the next step for process 900 by determining whether there is an identified buffer of the plurality of buffers storing data associated with the matching stream of instructions. In some embodiments, while executing the storage device driver, if the control circuitry determines there is an identified buffer storing data associated with the matching stream of instructions, the control circuitry then processes at least the instructions using the data stored in the identified buffer at 912. In other embodiments, while executing the storage device driver, when the control circuitry determines there is no identified buffer storing data associated with the matching stream of instructions, the control circuitry then determines the next step for process 900 by determining at 914 whether sequential instruction detection is in progress.

[0070] In step 912, while executing the storage device driver, the control circuit processes at least the input instructions using the data stored on the identified buffer. In some embodiments, the data associated with the identified buffer is an instruction stream that matches the input stream of instructions.

[0071] At step 914, while executing the storage device driver, the control circuitry determines the next step for process 900 by determining whether sequential instruction detection is in progress. In some embodiments, while executing the storage device driver, the control circuitry is configured to monitor the stream of instructions for a certain number of sequential instructions before determining which buffers to prefetch data from. If, while executing the storage device driver, the control circuitry determines that sequential detection is in progress, the control circuitry processes the input instruction as part of the sequential detection at 916. In some embodiments, while executing the storage device driver, when the control circuitry determines that sequential detection is not in progress, the control circuitry then determines the next step for process 900 by determining at 918 whether there are any available or reusable / stale buffers among the plurality of buffers.

[0072] In step 916, while executing the storage device driver, the control circuit processes the input instructions as part of sequential detection. In some embodiments, the instructions are processed and used by the control circuit while executing the storage device driver to determine a predicted stream of instructions for software-based prefetching.

[0073] In step 918, while executing the storage device driver, the control circuitry determines the next step for process 900 by determining whether an available or reusable / stale buffer exists among the plurality of buffers. In some embodiments, a buffer of the plurality of buffers is empty or may not currently store any data associated with the stream of instructions. In some embodiments, a corresponding valid bit in the valid bitmap may indicate that a buffer of the plurality of buffers is stale. The data stored in the stale buffer may be cleared or deleted and used for other data associated with a new stream of instructions. In some embodiments, while executing the storage device driver, the control circuitry determines whether an available or reusable / stale buffer exists among the plurality of buffers, and the control circuitry initializes the available or reusable / stale buffer at 920 to store the data associated with the stream of instructions. In some embodiments, while executing the storage device driver, when the control circuitry determines whether an available or reusable / stale buffer exists among the plurality of buffers, the control circuitry then services the input instructions without software-based prefetching at 908.

[0074] While executing the storage device driver, the control circuitry initializes an available or reusable / stale buffer to store data associated with the stream of instructions, in step 920. In some embodiments, to initialize the stale buffer, the control circuitry deletes or clears the stored stale data or overwrites the stale data with new data associated with the stream of instructions.

[0075] 10 shows a flowchart illustrating a process 1000 for performing a single multi-plane read operation using snap reads triggered by a sequential read command, according to some embodiments of the present disclosure. In some embodiments, the referenced control circuitry and memory may be implemented as control circuitry 106 and memory 124. Performing process 1000 may improve the efficiency of accessing memory 124. In some embodiments, process 1000 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0076] In step 1002, the control circuit 106 receives a read command. In some embodiments, the read command can be from an external source outside the device.

[0077] In step 1004, the control circuit 106 determines whether the read command is a sequential read command. If the read command is a sequential read command, the control circuit 106 then determines whether the control circuit 106 can request a cache read in step 1006. If the read command is not a sequential read command, the control circuit 106 issues an independent multi-plane read operation (IMPRO) to the memory 124 using a snap read.

[0078] In step 1006, the control circuit 106 determines whether the control circuit 106 can request a cache read. In some embodiments, there may be no cache available to the control circuit 106. If there is no cache available and readable by the control circuit 106, the control circuit 106 issues an IMPRO to the memory 124 using a snap read in step 1010. If the control circuit 106 can access the cache, the control circuit 106 issues a multi-plane sequential read to the memory in step 1008.

[0079] At step 1008, control circuitry 106 issues a multi-plane sequential read to memory 124. In some embodiments, the multi-plane sequential read is an independent multi-plane read operation (IMPRO) that accesses portions of at least two different planes of memory 124. Once the IMPRO is complete and control circuitry 106 has accessed the requested data, control circuitry 106 responds to the received read command at 1012.

[0080] At step 1010, the control circuit 106 issues an IMPRO to the memory 124 using a snap read. The control circuit 106 is configured to perform the IMPRO using a snap read, which allows the control circuit 106 to perform a multi-plane snap read and access at least two planes of the memory 124. A snap read is used to access 4K, 8K, or 16K of data from the memory 124. In some embodiments, a snap read can be used to access any other suitable size of data from the memory 124. Once the IMPRO using a snap read is complete and the control circuit 106 has accessed the requested data, the control circuit 106 responds to the received read command at 1012.

[0081] In step 1012, control circuitry 106 generates a response to the received read command with the accessed data from step 1008 or step 1010. The destination of the response is the same as the source of the received read command.

[0082] The terms "an embodiment," "embodiment," "embodiments," "the embodiment," "the embodiment," "the embodiment," "one or more embodiments," "some embodiments," and "one embodiment" mean "one or more (but not all) embodiments," unless expressly specified otherwise.

[0083] The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

[0084] An enumerated list of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

[0085] The terms "a," "an," and "the" mean "one or more," unless expressly specified otherwise.

[0086] Devices that are in communication with each other need not be in continuous communication with each other unless explicitly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

[0087] A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary, various optional components are described to illustrate a wide variety of possible embodiments. Furthermore, while process steps, method steps, algorithms, or the like may be described in a sequential order, such processes, methods, and algorithms may be configured to function in alternative orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. Steps of processes described herein may be performed in any order that is practical. Furthermore, some steps may be performed simultaneously.

[0088] Where a single device or article is described herein, it will be readily apparent that more than one device / article (whether they cooperate or not) may be used in place of the single device / article. Similarly, where more than one device or article (whether they cooperate or not) is described herein, it will be readily apparent that a single device / article may be used in place of the more than one device or article, or that a different number of devices / articles may be used in place of the number of devices or programs shown. The functionality and / or features of a device may alternatively be embodied by one or more other devices not explicitly described as having such functionality / features. Thus, other embodiments need not include the device itself.

[0089] At least some operations may be depicted in figures that show some events occurring in a certain order. In alternative embodiments, some operations may be performed in a different order, modified, or removed. Furthermore, steps may be added to the logic above and still be compatible with the described embodiment. Furthermore, operations described herein may occur sequentially, or some operations may be processed in parallel. Still further, operations may be performed by a single processing unit or by distributed processing units.

[0090] The foregoing description of various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.

Claims

1. receiving, by the control circuitry while executing the storage device driver, at least one instruction of the stream of instructions for the storage device; determining, by the control circuitry while executing the storage device driver, that a hardware buffer of the storage device stores less than two instructions; In response to determining that the hardware buffer of the storage device stores less than two instructions, accessing data associated with an address in the memory of the storage device, where the address is predicted based on an analysis of the stream of instructions; and storing the data in a buffer; and executing instructions of said stream of instructions using at least said data stored in said buffer; A method for providing the above.

2. receiving a sequential read command to read data from the memory of the storage device, wherein: the memory of the storage device comprises at least one floating gate NAND-based memory device; the at least one floating gate NAND-based memory device comprises at least two planes; and performing a read operation based on the sequential read command without referencing a data cache, wherein the read operation comprises a snap read across the at least two planes; The method of claim 1 further comprising:

3. The method of claim 1 or 2, wherein the hardware buffer of the storage device stores exactly one instruction.

4. executing, by the control circuitry, the instructions of the stream of instructions while executing the storage device driver, scheduling a prefetch command into the hardware buffer of the storage device; The method of claim 1 or 2, further comprising:

5. identifying, by the control circuitry while executing the storage device driver, the stream of instructions by detecting a particular number of sequential read instructions; The method of claim 1 or 2, further comprising:

6. configuring, by the control circuitry while executing the storage device driver, a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding stream of instructions from a plurality of streams of instructions received by the driver for the storage device; identifying a stale buffer among the plurality of buffers; and marking the identified stale streams for reuse. The method of claim 5 further comprising:

7. identifying new streams; determining that all buffers of the plurality of buffers have already been allocated for a stream of instructions; and in response to the steps of identifying a new stream and determining that all buffers of the plurality of buffers are already allocated to a stream of instructions, determining a buffer to be reused from the plurality of buffers; The method of claim 6 further comprising:

8. The step of determining which buffers of the plurality of buffers to reuse comprises: determining that a buffer among the plurality of buffers that has not been used for the longest time is to be reused; 8. The method of claim 7, comprising:

9. The step of determining which buffers of the plurality of buffers to reuse comprises: determining a buffer of said plurality of buffers associated with a data address that is closest to a current data address of said at least one instruction of said stream of instructions; 8. The method of claim 7, comprising:

10. configuring, by the control circuitry, a plurality of buffers while executing the storage device driver; identifying a new stream; and allocating one of the unallocated buffers of the plurality of buffers to the new stream. The method of claim 1 or 2, further comprising:

11. configuring, by the control circuitry while executing the storage device driver, a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding stream of instructions from a plurality of streams of instructions received by the storage device driver; receiving a first read command as part of the stream of commands for the storage device; identifying a buffer from the plurality of buffers associated with the stream of instructions; and accessing data associated with the address in the memory of the storage device; and storing the data in the identified buffer of a plurality of buffers. The method of claim 1 or 2, further comprising:

12. determining that the identified buffer is full; In response to determining that the identified buffer is full, stopping prefetching for said stream of instructions; receiving an instruction that hits a last storage location of the identified buffer as part of the stream of instructions to the storage device; in response to receiving an instruction that hits the last storage location of the identified buffer as part of the stream of instructions for the storage device; resuming prefetching of further data into the identified buffer. The method of claim 11 further comprising:

13. scheduling, by the control circuitry while executing the storage device driver, a further access of second data from a second address of the storage device predicted by analyzing the at least one instruction of the stream of instructions. The method of claim 11 further comprising:

14. receiving, by the storage device driver, a second read command as part of the stream of commands for the storage device; and fulfilling the second read instruction by returning the accessed value stored in the identified buffer of the plurality of buffers. The method of claim 13 further comprising:

15. storage circuitry; and While running the storage device driver for the storage device, receiving at least one instruction from a stream of instructions for the storage device; determining that a hardware buffer of the storage device stores less than two instructions; In response to the determination that the hardware buffer of the storage device stores less than two instructions, accessing data associated with an address in a memory of the storage device, wherein the address is predicted based on an analysis of the stream of instructions; storing the data in a buffer of a plurality of buffers; a control circuit that executes instructions of the stream of instructions using at least the data stored in the buffer; A system comprising:

16. The control circuit further comprises: receiving a sequential read command to read data from the memory of the storage device, wherein: the memory of the storage device comprises at least one floating gate NAND-based memory device; the at least one floating gate NAND-based memory device comprising at least two planes; performing a read operation based on the sequential read command without referencing a data cache, wherein the read operation comprises a snap read across the at least two planes; The system of claim 15.

17. 17. The system of claim 15 or 16, wherein the hardware buffer of the storage device stores exactly one instruction.

18. To execute the instructions of the stream of instructions, the control circuitry further comprises: scheduling a prefetch command into the hardware buffer of the storage device; 17. A system according to claim 15 or 16.

19. The control circuit further comprises: identifying a stream of instructions by detecting a specified number of sequential read instructions; 17. A system according to claim 15 or 16.

20. The control circuit further comprises: configuring a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding stream of instructions from a plurality of streams of instructions received by a driver of the storage device; identifying a stale buffer among the plurality of buffers; marking the identified stale stream for reuse; 20. The system of claim 19.

21. The control circuit further comprises: Identify new streams; determining that all buffers of the plurality of buffers are already allocated for the stream of instructions; in response to determining that the identified new stream and all buffers of the plurality of buffers are already allocated to a stream of instructions; determining a buffer to be reused from the plurality of buffers; 21. The system of claim 20.

22. To determine the buffer of the plurality of buffers, the control circuitry: determining that the least recently used buffer of the plurality of buffers is to be reused; 22. The system of claim 21.

23. 23. The system of claim 22, wherein the least recently used buffer of the plurality of buffers is a buffer that stores the oldest data accessed by the storage device driver.

24. The control circuit includes: receiving at least one instruction of a stream of instructions for a storage device; determining that a hardware buffer of the storage device stores less than two instructions; In response to the determination that the hardware buffer of the storage device stores less than two instructions, accessing data associated with an address in the memory of the storage device, wherein the address is predicted based on an analysis of the stream of instructions; storing said data in a buffer of a plurality of buffers; and executing instructions of said stream of instructions using at least said data stored in said buffer; while executing instructions of a storage device driver for said storage device.

25. The control circuit receiving a sequential read command to read data from the memory of the storage device, wherein: the memory of the storage device comprises at least one floating gate NAND-based memory device; the at least one floating gate NAND-based memory device comprises at least two planes; and performing a read operation based on the sequential read command without referencing a data cache, wherein the read operation comprises a snap read across the at least two planes; 25. The computer program of claim 24, further comprising:

26. 26. A computer program product as claimed in claim 24 or 25, wherein the hardware buffer of the storage device stores exactly one instruction.

27. Executing the instructions of the stream of instructions comprises: scheduling a prefetch command into the hardware buffer of the storage device; 26. A computer program according to claim 24 or 25, further comprising:

28. The control circuit identifying a stream of sequential read instructions by detecting a specified number of said instructions; 26. A computer program according to claim 24 or 25, further comprising the steps of:

29. The control circuit configuring a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding stream of instructions from a plurality of streams of instructions received by a driver of the storage device; identifying a stale buffer among the plurality of buffers; and marking the identified stale stream for reuse.

29. The computer program of claim 28, further comprising:

30. The control circuit A procedure for identifying new streams; determining that all buffers of said plurality of buffers have already been allocated for a stream of instructions; in response to determining that the identified new stream and all buffers of the plurality of buffers are already allocated to a stream of instructions; determining which of said plurality of buffers will be reused; 30. The computer program of claim 29, further comprising:

31. The step of determining the buffer from the plurality of buffers includes: determining that a buffer among said plurality of buffers that has not been used for the longest time is to be reused; 31. The computer program of claim 30, comprising:

32. 32. The computer program product of claim 31, wherein the least recently used buffer of the plurality of buffers is a buffer that stores the oldest data accessed by the storage device driver.

33. The step of determining the buffer from the plurality of buffers includes: determining a buffer of said plurality of buffers associated with a data address that is closest to a current data address of said one instruction of said stream of instructions; 31. The computer program of claim 30, comprising:

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