Test method and test apparatus for chips, host computer, chip, and device

Abstract

A test method and test apparatus for a chip, a host computer, a chip, and a device, the method includes the steps of obtaining a test circuit constructed in accordance with requirements of a hot swap test stand, the test circuit including at least one battery module and at least one chip, connecting the at least one chip to the at least one battery module, and testing the functionality of the at least one chip.

Description

[Technical Field]

[0001] The present application relates to the technical field of battery management, and in particular to a test method and test apparatus for chips, host computers, chips, and devices. [Background technology]

[0002] Energy conservation and emission reduction are key to the sustainable development of the automotive industry, and electric vehicles have become an important part of this due to their energy-saving and environmentally friendly advantages, and battery technology has become a key element in the development of electric vehicles.

[0003] In the field of battery management, it is often necessary to sample batteries using various chips to collect various battery states. However, chips used in the field of battery management are often hot-plugged or hot-plugged, which places stricter demands on the chip's voltage resistance performance. Therefore, a technical means for effectively testing chips is desired. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art, and to this end, one of the objectives of the present application is to provide a chip test method and test apparatus, a host computer, a chip, and a device for effectively testing the performance of the chip.

[0005] An embodiment of a first aspect of the present application provides a testing method for chips, including: determining a configuration mode of a test circuit, wherein the test circuit has at least one chip and at least one battery module, and the at least one chip is connectable to the at least one battery module according to the configuration mode; connecting the at least one chip to the at least one battery module based on at least one operating status corresponding to the configuration mode; determining whether an operation termination condition is met; and testing performance of the at least one chip in response to determining that the operation termination condition is met.

[0006] In the technical solutions of the embodiments of the present application, the technical solution of a standard hot swap test device is put forward, thereby standardizing the hot swap test, reducing the test differences between different chip manufacturers in practical applications, and realizing standardized and normalized chip testing.

[0007] In some embodiments, the test circuit further includes a switch matrix interposed between the at least one chip and the at least one battery module and capable of connecting the at least one chip to the at least one battery module according to the configuration mode, and the step of connecting the at least one chip to the at least one battery module includes the step of performing a closing operation to close at least two switches of the switch matrix.

[0008] According to this embodiment, chip testing can be flexibly performed using a switch matrix, complex manual insertion and removal processes can be avoided, required scenarios and operating conditions can be flexibly simulated, and the test for the hot insertion and removal function of the AFE can be performed accurately, quickly, and more closely to actual application conditions.

[0009] In some embodiments, the at least one chip includes a first chip, the at least one battery module includes a first battery module, and the hot swap test stand is required to include a first configuration mode, where the first configuration mode indicates that the first chip is connected to a corresponding switch of a switch matrix, and is configured such that when the corresponding switch is turned on, the sampling channel lines of the first chip are each connectable to a corresponding sampling lead line of the first battery module.

[0010] According to this embodiment, a test based on a normalized use scenario can be realized, and in particular, by making the circuit configuration mode of the test closer to the use scenario of the chip, it is possible to simulate a general use scenario of the chip, thereby obtaining a highly reliable test result.

[0011] In some embodiments, in response to determining that the test circuit is configured according to the first configuration mode, performing the closing operation includes closing a pair of switches corresponding to a pair of sampling channel lines if none of the switches corresponding to the remaining sampling channel lines, except for a pair of sampling channel lines associated with a maximum battery potential difference in the first chip, are closed.

[0012] This embodiment allows further testing of operating conditions that may occur in the simulated use scenario. In particular, by matching the test operating conditions with the circuit configuration mode, i.e., simulating common operating conditions corresponding to the chip's current use scenario, it is possible to obtain reliable and trustworthy test results. In this embodiment, the switches of the pair of sampling channel lines associated with the maximum battery potential difference are first closed to generate the maximum voltage difference across the chip. Therefore, this embodiment further contributes to testing the chip's functionality by simulating the worst-case operating conditions, and the chip obtained through this test can demonstrate sufficient reliability even under extreme operating conditions.

[0013] In some embodiments, in response to determining that the test circuit is configured according to the first configuration mode, performing the closing operation further includes randomly closing switches corresponding to the remaining sampling channel lines in the first chip after a pair of switches corresponding to a pair of sampling channel lines are closed.

[0014] According to this embodiment, it is possible to further test possible operating conditions for the simulated use scenario, and by simulating common operating conditions corresponding to the use scenario of the chip, it is possible to obtain reliable and trustworthy test results. Specifically, by simulating the worst-case operating condition in which both ends are closed first, and then randomly closing the remaining switches, it is possible to cover not only the poor operating condition but also other common insertion and removal operating conditions. Furthermore, by using random closing logic, it is possible to make the simulation results more reliable and comprehensive.

[0015] In some embodiments, in response to determining that the test circuitry is configured according to the first configuration mode, performing the closing operation includes randomly closing switches corresponding to sampling channel lines of a first chip.

[0016] According to this embodiment, by randomly closing the switches corresponding to all sampling channel lines for the simulated usage scenario, it is possible to simulate more general insertion and removal operation situations, making the simulation results more reliable and comprehensive, thereby obtaining a chip with high functional reliability and reducing the number of failures that may occur during use of the chip.

[0017] In some embodiments, the at least one chip includes a first chip, and the at least one battery module includes at least two battery modules connected in series, and the hot swap test stand is required to include a second configuration mode, wherein the first chip is connected to a corresponding switch of a switch matrix, and when the corresponding switch is turned on, the sampling channel lines of the first chip are respectively configured to be connectable to corresponding sampling lead lines of the at least two battery modules.

[0018] Such an embodiment enables testing based on normalized usage scenarios, covering scenarios where the number of sampling channel lines of the first chip is greater than the number of sampling lead lines of a single battery module, or other scenarios where one chip can be used to sample two or more batteries, thereby enabling credible and reliable simulation and testing in such common usage scenarios.

[0019] In some embodiments, in response to determining that the test circuit is in the second configuration mode, performing the closing operation includes, if none of the switches corresponding to the sampling leads of the positive battery module among the at least two battery modules are closed, closing the switches corresponding to the sampling leads of the remaining battery modules among the at least two battery modules excluding the positive battery module, and closing the switch corresponding to the sampling lead associated with the highest battery potential of the positive battery module after a first time lag has elapsed since the switches corresponding to the sampling leads of the remaining battery modules are closed.

[0020] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario, and to simulate relatively poor operating conditions in the scenario where one chip is connected to two or more battery modules, thereby improving the reliability of the chip obtained by this testing method.

[0021] In some embodiments, the step of performing the closing operation further includes, after the switch corresponding to the sampling lead associated with the highest battery potential is closed, randomly closing the switches corresponding to the remaining sampling leads of the positive battery modules, excluding the sampling lead associated with the highest battery potential.

[0022] According to this embodiment, it is possible to further test possible operating conditions for the simulated use scenario, and by using randomly closing logic, it is possible to make the simulation results more reliable and comprehensive. Specifically, for the first simulated operating condition for the second example scenario, it is possible to further simulate the risks to sampling channel lines other than the sampling channel line receiving the largest voltage difference, thereby enabling risk testing and evaluation of each sampling channel line and corresponding circuit part of the chip, and thereby obtaining more reliable test results.

[0023] In some embodiments, performing a closing operation in response to determining that the test circuit is in the second configuration mode includes, if none of the switches corresponding to the sampling leads of the negative battery module among the at least two battery modules are closed, closing switches corresponding to the sampling leads of the remaining battery modules among the at least two battery modules excluding the negative battery module, and closing a switch corresponding to the sampling lead of the negative battery module associated with the lowest battery potential after a second time lag has elapsed since the switches corresponding to the sampling leads of the remaining battery modules are closed.

[0024] According to this embodiment, a second scenario in which one chip is connected to two or more battery modules can be simulated, which is a relatively poorer operating condition.

[0025] In some embodiments, the step of performing the closing operation further includes the step of randomly closing switches corresponding to the remaining sampling leads of the negative battery modules, excluding the sampling lead associated with the lowest battery potential, after the switch corresponding to the sampling lead associated with the lowest battery potential is closed.

[0026] According to this embodiment, it is possible to further test possible operating conditions for the simulated use scenario, and by using random closing logic, it is possible to make the simulation results more reliable and comprehensive. Specifically, for the second simulated operating condition for the second example scenario, it is possible to further simulate the risks to sampling channel lines other than the sampling channel line receiving the maximum voltage difference, thereby obtaining more reliable test results.

[0027] In some embodiments, the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and the step of obtaining a test circuit constructed in accordance with requirements of a hot swap test stand includes a step of determining that the test circuit is constructed in accordance with the third configuration mode, the third configuration mode indicating that the first chip and the second chip are connected to corresponding switches in a switch matrix, such that when the corresponding switches are turned on, the first chip and the second chip are configured to be connectable to corresponding sampling leads of the first battery module.

[0028] Such an embodiment covers situations where the number of sampling channel lines on the first chip is less than the number of sampling lead lines on a single battery module, and other situations where two or more chips are available for sampling a single battery, thereby enabling credible and reliable simulation and testing in such common usage scenarios.

[0029] In some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip are connectable to adjacent first sampling lead lines and second sampling lead lines of the first battery module, and the third sampling channel line of the first chip and the fourth sampling channel line of the second chip are connectable to third sampling lead lines and fourth sampling lead lines of the first battery module associated with a maximum battery potential difference, and in response to determining that the test circuit is configured according to the third configuration mode, performing a closing operation includes: closing switches corresponding to the first sampling channel line and the second sampling channel line when none of the switches corresponding to the remaining sampling channel lines of the first chip and the second chip other than the first sampling channel line and the second sampling channel line are closed; and closing the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line after a third time lag has elapsed since the switches corresponding to the first sampling channel line and the second sampling channel line were closed.

[0030] According to this embodiment, by simulating adverse conditions, the test effect and the reliability of the chip obtained through the test can be improved, and the chip obtained through such a test can exhibit sufficient reliability even under extreme operating conditions.

[0031] In some embodiments, the step of performing the closing operation further includes the step of randomly closing switches corresponding to the remaining sampling channel lines of the first chip and the second chip, excluding the first sampling channel line, the second sampling channel line, the third sampling channel line, and the fourth sampling channel line, after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed.

[0032] According to this embodiment, it is possible to further test possible operating conditions for the simulated use scenario. By using random closing logic, it is possible to make the simulation results more reliable and comprehensive. In other words, for the first simulated operating situation for the third example scenario, it is possible to further simulate the risks to sampling channel lines other than the sampling channel line receiving the largest voltage difference, thereby comprehensively testing the chip's tolerance.

[0033] In some embodiments, in response to determining that the test circuit is configured according to the third configuration mode, performing a closing operation includes randomly closing switches corresponding to sampling channel lines of the first chip and the second chip.

[0034] According to this embodiment, in addition to the worst-case operating condition provided, other more common operating conditions that are actually used in testing can be simulated. According to this embodiment, other common insertion and removal operating conditions can be covered. Furthermore, by using random closing logic, the simulation results can be made more credible, thereby obtaining comprehensive and reliable test results.

[0035] In some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip are connectable to adjacent first sampling lead lines and second sampling lead lines of the first battery module, and the third sampling channel line of the first chip and the fourth sampling channel line of the second chip are connectable to third sampling lead lines and fourth sampling lead lines of the first battery module associated with the maximum battery potential difference, and the third configuration mode further indicates that the first sampling channel line and the second sampling channel line are electrically connected.

[0036] According to this embodiment, by further considering an example scenario in which the chip is short-circuited in advance, it is possible to more comprehensively cover the scenarios that the chip may encounter, thereby obtaining a more reliable test result.

[0037] In some embodiments, in response to determining that the test circuit is configured according to the third configuration mode, performing a closing operation includes closing a switch corresponding to the sampling channel line of the second chip if none of the switches corresponding to the sampling channel line of the first chip are closed, and closing a switch corresponding to the third sampling channel line a third time lag after the switch corresponding to the sampling channel line of the second chip is closed.

[0038] According to this embodiment, highly reliable test results can be obtained by simulating the poor operating conditions that can be endured during hot swapping in the case of chip shorts.

[0039] In some embodiments, the step of performing the closing operation further includes the step of randomly closing switches corresponding to the remaining sampling channel lines of the first chip except for the third sampling channel line after the switch corresponding to the third sampling channel line is closed.

[0040] According to such an embodiment, other common insertion / removal operating conditions and each sampling channel line can be covered, thereby enabling risk testing and evaluation of each sampling channel line and corresponding circuit part of the chip, and obtaining more reliable test results.

[0041] In some embodiments, the operation termination condition includes at least one of: the number of times a close operation has been performed for at least one chip has reached a first threshold; and the number of times a close operation has been performed based on a particular placement mode has reached a second threshold for the particular placement mode.

[0042] Such an embodiment allows for more standardized testing of chips by limiting the termination conditions.

[0043] In some embodiments, the testing method further includes repeating the steps of performing a power-off operation on the at least one chip, discharging a capacitor in the at least one chip, and performing a closing operation to close at least two switches of the switch matrix in response to determining that an operation termination condition is not satisfied, and testing the functionality of the at least one chip, wherein the operation termination condition includes at least one of: the number of times the closing operation is performed on the at least one chip reaches a first threshold; and the number of times each operating condition of the at least one operating condition is performed reaches a second threshold for the operating condition.

[0044] According to this embodiment, the influence of the charge on the capacitor can be reduced, and a more reliable test effect can be obtained.

[0045] In some embodiments, the testing method further includes, in response to determining that the step of connecting the at least one chip to the at least one battery module is performed for the first time, adjusting a voltage of a single cell of a battery in the at least one battery module to a predetermined value before testing the function of the at least one chip. According to such embodiments, stability of the test can be ensured.

[0046] In some embodiments ,before The step of testing the functionality of the at least one chip includes the step of performing a range of power supply voltage tests on the at least one chip. nothing.

[0047] An embodiment of a second aspect of the present application provides a test device for chips, comprising at least one battery module, a switch matrix, and a host computer capable of controlling the operation of at least one switch in the switch matrix, wherein the switch matrix is ​​arranged to connect at least one chip to at least one battery module, and the host computer is arranged to execute a method according to an embodiment of the present application.

[0048] In some embodiments, the test apparatus further comprises at least one discharge unit, which, when turned on, can discharge a corresponding capacitor of the at least one chip.

[0049] According to this embodiment, the influence of the charge on the capacitor can be reduced, and a more reliable test effect can be obtained.

[0050] An embodiment of a third aspect of the present application provides a host computer capable of controlling the operation of at least one switch in a switch matrix arranged to connect at least one chip to at least one battery module, the host computer being configured to execute a method according to an embodiment of the present application.

[0051] An embodiment of the fourth aspect of the present application provides a chip for a battery, which is tested by a method according to an embodiment of the present application.

[0052] An embodiment of a fifth aspect of the present application provides an electronic device comprising at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores commands executable by the at least one processor, and execution of the commands by the at least one processor enables the at least one processor to perform a method of an embodiment of the present application.

[0053] An embodiment of a sixth aspect of the present application provides a non-transitory computer-readable storage medium having stored thereon computer instructions for causing a computer to perform a method according to an embodiment of the present application.

[0054] The above description is merely a brief description of the technical solution of the present application. In order to make the technical solution of the present application clearer and to make the above and other objectives, features and advantages of the present application more comprehensible, so that the present application can be implemented based on the contents of the specification, the following provides specific embodiments of the present application. [Brief explanation of the drawings]

[0055] In the drawings, unless otherwise limited, the same reference numerals throughout the several views indicate the same or similar parts or elements. The drawings are not necessarily drawn to scale. It should be noted that the drawings illustrate only some embodiments disclosed by the present application and should not be considered as limitations on the scope of the present application.

[0056] [Figure 1] 1 is a structural schematic diagram of a vehicle according to some embodiments of the present application; [Figure 2] 1 is an exploded structural schematic diagram of a battery according to some embodiments of the present application; [Figure 3] 1 is an exploded structural schematic diagram of a battery cell according to some embodiments of the present application; [Figure 4] 1 is a schematic flow chart of a test method for a chip in some embodiments of the present application; [Figure 5] FIG. 2 is a schematic diagram of a test circuit according to some embodiments of the present application. [Figure 6] FIG. 2 is a schematic diagram of a test circuit according to some other embodiments of the present application. [Figure 7] FIG. 10 is a schematic diagram of a test circuit according to some further embodiments of the present application. [Figure 8] FIG. 10 is a schematic diagram of a test circuit according to still further some embodiments of the present application. [Figure 9] FIG. 1 is a schematic diagram of a test apparatus according to some embodiments of the present application. [Figure 10]FIG. 2 is a schematic diagram of a computing device according to some embodiments of the present application. [Figure 11] FIG. 2 is a schematic diagram of a test circuit according to some other embodiments of the present application. [Figure 12] FIG. 10 is a schematic diagram of a test circuit according to some further embodiments of the present application. [Figure 13] FIG. 10 is a schematic diagram of a test circuit according to still further some embodiments of the present application. [Figure 14] FIG. 10 is a schematic diagram of a test circuit according to still further some embodiments of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0057] The following detailed description will be given of the embodiments of the technical solution of the present application with reference to the drawings. The following embodiments are merely for the purpose of more clearly illustrating the technical solution of the present application, and are therefore merely illustrative and do not limit the scope of protection of the present application.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this application pertains. The terms used herein are merely for the purpose of describing specific examples and are not intended to limit this application. The terms "comprises," "having," and any variations thereof in the specification, claims, and description of the drawings of this application are intended to mean a non-exclusive inclusion.

[0059] In the description of the embodiments of the present application, technical terms such as "first," "second," etc. are used merely to distinguish between different objects and should not be understood as expressing or implying relative importance, the number of technical features indicated, or a particular order or hierarchical relationship. In different embodiments of the present application, the objects described as "first," "second," etc. should not be considered to be the same object. For example, a "first chip" described in one embodiment of the present application may be a "second chip" in another embodiment, and a "first battery module" described in one embodiment of the present application may be a "second battery module" or a "third battery module" in another embodiment. In the description of the embodiments of the present application, "plurality" means two or more, unless otherwise specifically limited.

[0060] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described with reference to an embodiment may be included in at least one embodiment of the present application. The use of this term in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that contradicts other embodiments. Those skilled in the art will recognize that the embodiments described herein may be combined with other embodiments.

[0061] In the description of the embodiments of the present application, the term "and / or" is used simply to explain the relation between related objects and indicates three possible relationships. For example, A and / or B indicates three relationships: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in this specification, the symbol " / " generally indicates that the related objects before and after it are in an "or" relationship.

[0062] In describing the examples of the present application, the term "plurality" means two or more (including two); similarly, "multiple sets" means two or more (including two sets); and "multiple sheets" means two or more (including two).

[0063] In describing the embodiments of the present application, directions or positional relationships indicated by technical terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," etc. are directions or positional relationships based on the drawings and are intended merely for the convenience of describing the embodiments of the present application, and do not indicate or suggest that the devices or elements described therein have a specific orientation or should be configured or operated in a specific direction. Therefore, they should not be understood as limitations on the embodiments of the present application.

[0064] In describing the embodiments of the present application, unless otherwise clearly specified or limited, the technical terms "attached," "connected," "coupled," "fixed," etc. should be understood in a broad sense. For example, they may refer to a fixed connection, a detachable connection, or an integral connection. They may also refer to a mechanical connection or an electrical connection. They may also refer to a direct connection, an indirect connection via an intermediate medium, internal communication between two elements, or interaction between two elements. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application depending on the specific circumstances. <Summary of the invention>

[0065] Currently, in view of the trend of market development, the applications of power batteries are becoming increasingly widespread. Power batteries are not only used in energy storage power systems such as hydroelectric, thermal, wind and solar power plants, but also widely used in electric transportation such as electric bicycles, electric motorcycles and electric cars, as well as in multiple fields such as military equipment and aerospace. With the continuous expansion of the application fields of power batteries, the demand in the market is also constantly increasing.

[0066] In the field of battery management, various chips, such as analog front-end chips, are required for battery management and sampling. For example, the chip collects information such as battery cell voltage, temperature, etc., and supports battery balancing function. Therefore, stable functioning of the chip is very important.

[0067] However, the applicant has noticed that chips used in the field of battery management are often hot-plugged, especially since the chip itself needs to be connected to the battery and there is a voltage difference between different pins of the battery as a power source, thus putting the functionality of the chip into a more severe test.

[0068] The applicant further found that in the current field of battery management systems, there is no effective method for performing hot swap testing on sampling analog front-end chips. The lack of an effective testing method may cause failures during terminal application. The applicant also found that existing non-comprehensive testing methods often simulate operating conditions by manually pushing and unplugging, which requires a large amount of human intervention and is poor in flexibility and comprehensiveness.

[0069] Therefore, the applicant has conducted research and developed a test method that can realize flexible chip testing and can be applied to various hot swapping operating situations in various application scenarios.

[0070] Based on the above considerations, a test method for a chip is provided, in order to fully verify the hot swap performance of the chip at the chip design stage, including the steps of: determining a configuration mode of a test circuit, wherein the test circuit includes at least one chip, at least one battery module, and a switch matrix, the switch matrix being interposed between the at least one chip and the at least one battery module, and the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode; performing a closing operation to close at least two switches of the switch matrix based on the configuration mode; determining whether an operation termination condition is met; and testing the performance of the at least one chip according to determining that the operation termination condition is met.

[0071] This test method allows a standard hot swap test to be obtained, and the hot swap performance of the chip can be fully verified before the chip is put into practical use (for example, at the chip design stage), thereby reducing chip abnormalities during application and reducing terminal application losses. <Introduction to application scenarios>

[0072] In the embodiments of the present application, battery cells using chips include, but are not limited to, electric devices such as vehicles, ships, and aircraft. Electric devices using batteries as power sources include, but are not limited to, mobile phones, tablets, laptops, electric toys, power tools, electric motorcycles, electric cars, ships, and aircraft. Electric toys may include, for example, game consoles, electric car toys, electric boat toys, electric airplane toys, and other stationary or mobile electric toys. Aircraft may include airplanes, rockets, space shuttles, spaceships, and the like.

[0073] In the following embodiment, for convenience of explanation, a case where the electric device of one embodiment of the present application is a vehicle 1000 will be described as an example.

[0074] Referring to FIG. 1, FIG. 1 is a structural schematic diagram of a vehicle 1000 provided in some embodiments of the present application. The vehicle 1000 may be a fuel vehicle, a natural gas vehicle, or a new energy vehicle. The new energy vehicle may be a battery vehicle, a hybrid vehicle, a range extender vehicle, etc. A battery 100 is provided inside the vehicle 1000, and may be provided at the bottom, front, or rear of the vehicle 1000. The battery 100 can be used to power the vehicle 1000. For example, the battery 100 may be an operating power source for the vehicle 1000. The vehicle 1000 may further include a controller 200 and a motor 300. The controller 200 controls the battery 100 to supply power to the motor 300 according to an operating electricity usage request, for example, when the vehicle 1000 starts, navigates, and runs.

[0075] In some embodiments of the present application, the battery 100 may be used not only as an operating power source for the vehicle 1000, but also as a driving power source for the vehicle 1000 to provide driving force for the vehicle 1000, replacing at least a portion of fuel oil or natural gas.

[0076] Referring to FIG. 2, FIG. 2 is an exploded view of a battery 100 provided in some embodiments of the present application. The battery 100 includes a box 10 and battery cells 20 housed inside the box 10. The box 10 provides a storage space for the battery cells 20 and may have various structures. In some embodiments, the box 10 may include a first portion 11 and a second portion 12. When the first portion 11 and the second portion 12 are stacked together, the first portion 11 and the second portion 12 define a storage space for accommodating the battery cells 20. The second portion 12 may have a hollow structure with one end open. The first portion 11 may have a plate-like structure. The first portion 11 covers the open side of the second portion 12, thereby defining the storage space between the first portion 11 and the second portion 12. The first portion 11 and the second portion 12 may also have a hollow structure with one end open. The open side of the second portion 12 is covered by the open side of the first portion 11. Of course, the box 10 formed by the first portion 11 and the second portion 12 may have various shapes, such as a cylindrical shape, a rectangular parallelepiped shape, etc.

[0077] The battery 100 may include a plurality of battery cells 20. The plurality of battery cells 20 may be connected in series, parallel, or a mixed connection. A mixed connection refers to a combination of the plurality of battery cells 20 connected in both series and parallel. The plurality of battery cells 20 may be directly connected in series, parallel, or a mixed connection, and then the entire combination of the plurality of battery cells 20 may be housed in the box 10. Of course, the battery 100 may also include a plurality of battery cells 20 first connected in series, parallel, or a mixed connection to form a battery module, and then the plurality of battery modules may be further integrated in series, parallel, or a mixed connection and housed in the box 10. The battery 100 may further include other structures. For example, the battery 100 may further include current collecting members for electrical connection between the plurality of battery cells 20.

[0078] Each battery cell 20 may be a secondary battery or a primary battery. It may also be, but is not limited to, a lithium-sulfur battery, a sodium-ion battery, or a magnesium-ion battery. The battery cells 20 may be cylindrical, flat, rectangular, or have other shapes.

[0079] Please refer to Figure 3, which is an exploded structural schematic diagram of a battery cell 20 provided in some embodiments of the present application. The battery cell 20 is the smallest unit constituting a battery. As shown in Figure 3, the battery cell 20 includes an end cover 21, a case 22, a cell assembly 23, and other functional components.

[0080] The end cover 21 is a component that covers the opening of the case 22 to isolate the internal environment of the battery cell 20 from the external environment. The shape of the end cover 21 may be, but is not limited to, a shape that matches the shape of the case 22. In some embodiments, the end cover 21 may be manufactured from a material (e.g., aluminum alloy) that has a certain degree of hardness and strength. In this way, the end cover 21 is less likely to deform when pressed or hit, and the battery cell 20 has higher structural strength and improved safety functions. The end cover 21 may be provided with a functional component, such as an electrode terminal 21a. The electrode terminal 21a may be electrically connected to the cell assembly 23 for inputting and outputting electrical energy to and from the battery cell 20. In some embodiments, the end cover 21 may further be provided with a pressure release mechanism that releases internal pressure when the internal pressure or temperature of the battery cell 20 reaches a threshold. The end cover 21 may also be made of various materials, such as copper, iron, aluminum, stainless steel, aluminum alloy, or plastic, but is not particularly limited thereto in the embodiments of the present application. In some embodiments, an insulating member may be further provided inside the end cover 21. The insulating member isolates the electrical connection members inside the case 22 from the end cover 21, thereby reducing the risk of short circuits. Illustratively, the insulating member may be made of plastic, rubber, or the like.

[0081] The case 22 is a component that, together with the end cover 21, forms an internal environment of the battery cell 20. The internal environment formed by them can accommodate the cell assembly 23, an electrolyte, and other components. The case 22 and the end cover 21 may be separate components. The internal environment of the battery cell 20 may be formed by providing an opening in the case 22 and covering the opening with the end cover 21. The end cover 21 and the case 22 may be integrated, but are not limited to this. Specifically, before accommodating other components, a common connection surface may be formed between the end cover 21 and the case 22, and the end cover 21 may cover the case 22 when sealing the interior of the case 22. The case 22 may have various shapes and sizes, such as a rectangular parallelepiped, a cylindrical shape, or a hexagonal prism. Specifically, the shape of the case 22 may be determined based on the specific shape and size of the cell assembly 23. The case 22 may be made of various materials such as copper, iron, aluminum, stainless steel, aluminum alloy, plastic, etc., but is not particularly limited to these in the embodiments of the present application.

[0082] The cell assembly 23 is a component that performs the electrochemical reaction in the battery cell 100. The case 22 may contain one or more cell assemblies 23 inside. The cell assembly 23 is primarily formed by winding or stacking positive and negative electrode sheets, with a separator typically provided between the positive and negative electrode sheets. The portions of the positive and negative electrode sheets that contain active material form the main body of the cell assembly, while the portions of the positive and negative electrode sheets that do not contain active material form tabs 23a, respectively. The positive and negative electrode tabs may both be located at one end of the main body, or may be located at both ends of the main body. During the charge and discharge process of the battery, the positive and negative electrode active materials react with the electrolyte, causing the tabs 23a to connect to the electrode terminals and form a current circuit.

[0083] Hereinafter, a test method 400 for a chip according to an embodiment of the present application will be described with reference to Fig. 4. As shown in Fig. 4, the method 400 may include:

[0084] In step S401, a configuration mode of a test circuit is determined, where the test circuit has at least one chip and at least one battery module, and the at least one chip is connectable to the at least one battery module according to the configuration mode.

[0085] In step S402, the at least one chip is connected to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0086] It should also be understood that the placement mode may indicate a simulated test scenario. For example, a particular placement mode of a circuit may be realized by constructing a test bench or by other methods. As an example, the placement mode may be selected from a group of predetermined test modes. As another example, the placement mode may be selected according to actual conditions, such as the number of sampling channel lines of a chip, the number of cells of a battery module, the characteristics of a particular application scenario in which the chip is implemented, etc.

[0087] In the embodiment of this application, a technical means of a standard hot swap test device is proposed to standardize hot swap testing, which in practical application can reduce the test differences between different chip manufacturers and realize standardized and normalized chip testing.

[0088] In particular, in the embodiments of the present application, the live insertion and removal function of the chip can be fully verified before the chip is put into practical use (e.g., at the chip design stage), thereby reducing chip abnormalities during application and reducing application losses of the terminal.

[0089] The embodiments of the present application are applicable to the field of battery management systems, and are particularly suitable for hot swap testing of analog front-end (AFE) chips, such as AFE chips for sampling and managing batteries in new energy vehicles. Therefore, the methods of the embodiments of the present application can accelerate the practical application and application of terminal design, and further contribute to the healthy development of the new energy vehicle industry.

[0090] In some embodiments, the method further includes testing the performance of the at least one chip. In some embodiments, the method further includes determining whether an end-of-operation condition is met before testing the performance of the at least one chip, and testing the performance of the at least one chip in response to determining that an end-of-operation condition is met.

[0091] It should be understood that in some exemplary embodiments, electrical data for test verification can be acquired at the end of an operating state and at the end of switch connection. In some additional or optional embodiments, electrical data for test verification can also be acquired during switch connection for each operating state.

[0092] In this exemplary embodiment, the method may further include steps S403 to S404. In step S403, it is determined whether an operation termination condition is met.

[0093] In step S404, in response to determining that the operation termination condition is met, the performance of the at least one chip is tested.

[0094] The operation end condition is satisfied when the simulation of the chip's operating conditions (e.g., voltage boost or power-on) has been completed and the chip's performance can be tested. As a specific, non-limiting example of the operation end condition, the "operation end condition" may be considered to be satisfied when the closing operation is completed, i.e., when at least two switches that need to be closed according to the current configuration mode have been closed (or after a predetermined time lag has elapsed since they were already closed). Other non-limiting examples of the operation end condition are described in more detail below.

[0095] The process of testing the performance of the at least one chip may include testing various chip functions and performance checks that would be understood by one skilled in the art, such as one or more tests conducted under specific conditions of temperature, pressure, etc.

[0096] In some embodiments, a method may include obtaining a test circuit including at least one battery module and at least one chip, the test circuit being constructed in accordance with requirements of a hot-swap test stand; connecting the at least one chip to the at least one battery module; and testing functionality of the at least one chip. The test circuit constructed in accordance with requirements of a hot-swap test stand may be a test circuit constructed based on a desired circuit design that can simulate one or more desired scenarios or operating conditions. While the test circuit constructed in accordance with requirements of a hot-swap test stand may connect the at least one battery module and the at least one chip, it should be understood that in the step of obtaining the test circuit, the battery module and chip may be in an unconnected state, such as a state where they have never been connected, a state where they were connected but have now been disconnected, or a state where they were connected but have now been disconnected and are fully discharged.

[0097] It should be understood that the chip here may be an Analog Front End (AFE) chip, which can process an analog signal provided from a signal source into a digital signal, and includes modules such as an ADC, a multiplexer, and a state machine. More specifically, the chip here may be an analog front end chip for an electric vehicle.

[0098] At least one chip may be combined as a cell monitor unit (CMU), which may be a circuit module obtained by designing and producing an analog front-end chip according to a typical recommended circuit design.

[0099] Hot Plug refers to active insertion and removal, that is, inserting and removing a module into and from a system without shutting down the power supply to the system.

[0100] In some embodiments, the test circuit further includes a switch matrix interposed between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode, and the step of energizing the at least one chip includes the step of performing a closing operation to close at least two switches of the switch matrix based on at least one operating status corresponding to the test circuit.

[0101] It should be understood that a statement that the switch matrix is ​​capable of "connecting" the at least one chip to at least one battery module according to at least one operating state (or, as described below, a configuration mode) corresponding to a test circuit does not require that the corresponding switch of the switch matrix be already closed or that the chip be already electrically connected to the corresponding battery module when determining the configuration mode of the test circuit. Conversely, a statement that the switch matrix is ​​capable of connecting the at least one chip to the at least one battery module according to the configuration mode may mean that a first end of a corresponding switch of the switch matrix is ​​connected to a corresponding connection point (e.g., a corresponding sampling channel line) of the at least one chip and a second end of the corresponding switch is connected to a corresponding connection point (e.g., a corresponding sampling lead line) of the at least one battery module of the at least one chip, such that when the corresponding switch is turned on, the chip and the battery module are connected according to the desired configuration mode. Closing at least two switches of the switch matrix electrically connects the chip and the battery module, forming a closed circuit between the chip and the battery module, thereby simulating the insertion and removal of a chip while it is powered on.

[0102] It should also be understood that although a switch matrix is ​​described herein, the present disclosure is not limited thereto, and that other technical means capable of connecting a chip to a battery module, as understood by those skilled in the art, may be used to implement the hot swap testing of the present disclosure.

[0103] In the embodiment of the present application, the switch can be closed according to the configuration mode of the test circuit and the corresponding operating status, so that a standardized chip testing method can be realized.

[0104] In the examples of the present application, test By introducing a switch matrix into the circuit, the complicated manual insertion and removal process can be avoided, and the required scenarios and operating conditions can be flexibly simulated, making the test of the AFE's hot-swap function accurate, fast, and closer to the actual application situation.

[0105] In some embodiments, performing a closing operation to close at least two switches of the switch matrix includes closing switches of the switch matrix based on at least one of a first strategy that preferentially closes two switches that form a current-carrying circuit with a maximum potential difference and a second strategy that preferentially closes switches that enable a closed circuit to be formed between the at least one battery module.

[0106] In some embodiments, the at least one chip may include a first chip. The at least one battery module may include a first battery module. In such embodiments, determining a configuration mode of the test circuit may include determining that the test circuit is in a first configuration mode. The first configuration mode indicates that the first chip is configured to be connected to a corresponding switch in the switch matrix such that, when the corresponding switch is turned on, sampling channel lines of the first chip are each connectable to a corresponding sampling lead line of the first battery module.

[0107] It should be understood that the placement mode may indicate a simulated test scenario. For example, a particular placement mode of a circuit may be realized by constructing a test bench or by other methods. As an example, the placement mode may be selected from a group of predetermined test modes. As another example, the placement mode may be selected according to actual conditions, such as the number of sampling channel lines of a chip, the number of cells of a battery module, the characteristics of a particular application scenario in which the chip is implemented, etc.

[0108] In this example, the first configuration mode can simulate a typical usage scenario in which one chip is fully connected to one battery module. For convenience of explanation, this scenario is referred to as the first example scenario. For example, the number of sampling channel lines of the first chip may be the same as the number of sampling lead lines of the first battery module. Figure 5 shows an example diagram of one test circuit in the first configuration mode of the first example scenario. As shown in FIG. 5, in the test circuit 500, the first chip 530 is connected to the corresponding switches 520-1, 520-2, 520-3...520-N of the switch matrix 520, so that when the corresponding switches 520-1, 520-2, 520-3...520-N are turned on, the sampling channel lines 530-1, 530-2, 530-3...530-N of the first chip 530 can be connected to the corresponding sampling lead lines 510-1, 510-2, 510-3...510-N of the first battery module 510, respectively.

[0109] 5 shows a one-to-one correspondence between the sampling channel lines of the first chip and the sampling lead lines of the first battery module, it should be understood that this is not limited thereto. As another non-limiting example, in such an embodiment, the number of sampling channels of the first chip may be less than the number of sampling lead lines of the battery module. For example, only some of the sampling lead lines of the battery module may be sampled.

[0110] It should also be understood that although FIG. 5 shows N switches for connecting N sampling channel lines to N sampling lead lines, the number N is not limited and may be 2 or greater so long as a voltage difference is formed on the chip when the corresponding switch is in communication.

[0111] According to this embodiment, a test based on a normalized use scenario can be realized, and in particular, by making the circuit configuration mode of the test closer to the use scenario of the chip, it is possible to simulate a general use scenario of the chip, thereby obtaining a highly reliable test result.

[0112] In some embodiments, in response to determining that the test circuit is in a first configuration mode, performing the closing operation includes closing a pair of switches corresponding to a pair of sampling channel lines, except for a pair of sampling channel lines associated with a maximum battery potential difference in the first chip, if none of the switches corresponding to the remaining pair of sampling channel lines are closed.

[0113] This provides a first configuration mode, i.e., a poor operating condition in which the chip experiences the maximum possible voltage difference for a first exemplary scenario desired to be simulated. For ease of explanation, this will be referred to herein as a first simulated operating condition for the first exemplary scenario. It should be understood that the battery voltage difference "associated" with a pair of sampling channel lines is the voltage difference across a pair of sampling leads connected to the pair of sampling channel lines when the corresponding switches are closed. It should also be understood that the pair of sampling channel lines associated with the maximum battery voltage difference means that the battery voltage difference associated with this pair of sampling channel lines is the largest of all the battery voltage difference values ​​that all of the sampling channel lines of the first chip can be associated with. Continuing to refer to FIG. 5, as a specific example, in an embodiment where the number of sampling channel lines of the first chip and the number of sampling lead lines of the first battery are the same and correspond one-to-one, the pair of sampling channel lines associated with the maximum battery potential difference are the two sampling channel lines connected to the sampling lead line 510-1 closest to the positive electrode side of the first battery and the sampling lead line 510-N closest to the negative electrode side, respectively, i.e., 530-1 and 530-N shown in FIG. 5. In this example, switches 520-1 and 520-N may be closed first before the remaining switches are closed.

[0114] It should be understood that throughout this specification, descriptions of the order in which a particular two switches are closed relative to the order in which the remaining switches are closed, such as "closing the pair of switches when none of the remaining switches are closed," "closing the two switches when none of the remaining switches are closed," "closing the two switches preferentially," or "closing the pair of switches preferentially," are not intended to limit the order in which the "pair of switches" or "two switches" are closed, unless otherwise stated. On the contrary, such descriptions may include, but are not limited to, cases in which the two switches are closed simultaneously, one of the two switches is closed immediately after the other is closed, one of the two switches is closed first and then the other is closed after a predetermined or random time lag has elapsed, etc., as long as the timing at which the two switches are closed satisfies a specific relationship with the timing at which the "remaining switches" are closed (e.g., closed before the "remaining switches").

[0115] Furthermore, it should be understood that when none of the switches corresponding to the remaining sampling channel lines are closed, closing the pair of switches may mean closing the pair of switches before or with priority over the remaining switches. It should be understood that such a description does not require that all switches other than the pair of switches be closed in a subsequent closing operation, but rather that the pair of switches be closed first. As a specific and non-limiting example, after the pair of switches corresponding to the maximum potential difference is closed, the current closing operation may be considered to have already ended.

[0116] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated use scenario. In particular, by matching the test operating conditions with the circuit configuration mode, i.e., simulating the general operating conditions that correspond to the current use scenario of the chip, it is possible to obtain reliable and trustworthy test results.

[0117] According to this embodiment, the maximum voltage difference can be generated across the chip by first closing the switches of the pair of sampling channel lines associated with the maximum battery potential difference. Therefore, according to this embodiment, it is advantageous for testing the performance of the chip by simulating the worst-case operating conditions, and the chip obtained through such testing can demonstrate sufficient reliability even under extreme operating conditions.

[0118] In some embodiments, in response to determining that the test circuit is in a first configuration mode, performing the closing operation further includes randomly closing switches corresponding to the remaining sampling channel lines in the first chip after the pair of switches corresponding to the pair of sampling channel lines are closed.

[0119] Thus, in the first simulated operating condition for the first example scenario, switches other than the sampling channel line receiving the maximum voltage difference can be further closed to simulate the first example scenario. It should be understood that the term "randomly closing" used throughout this specification may include any one of the following: the order in which the switches are closed is random, the time lag between two switches being closed one after the other is random, or any other closing parameter that would be understood by a person skilled in the art is random. As a specific, non-limiting example, the closing order may include any one or more of forward order, reverse order, group random (e.g., two groups, three groups, four groups), and random number random.

[0120] Continuing to refer to FIG. 5, as a specific, non-limiting example, switches 520-1 and 520-N may be closed, followed by switches 520-2, 520-3, etc., randomly closing.

[0121] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated use scenario, and by simulating common operating conditions corresponding to the use scenario of the chip, it is possible to obtain reliable and trustworthy test results.

[0122] Specifically, by simulating the worst-case operating condition where both ends are closed first, and then randomly closing the remaining switches, it is possible to cover not only the worst-case operating condition but also other common insertion and removal operating conditions. Furthermore, by using random closing logic, the simulation results can be made more reliable and comprehensive.

[0123] In some embodiments, in response to determining that the test circuit is in a first configuration mode, performing the closing operation may include randomly closing switches corresponding to sampling channel lines of the first chip.

[0124] This allows the first example scenario to simulate not only the worst-case operating condition provided, but also other more common operating conditions that are practiced in testing, which for convenience of explanation will be referred to as the second simulated operating condition for the first example scenario.

[0125] 5, as a specific, non-limiting example, switches 520-1 to 520-N may be randomly closed in response to the second simulated operating condition, or at least two of switches 520-1 to 520-N may be randomly closed.

[0126] It should be understood that the closing operation according to this embodiment may be combined with closing operations according to other embodiments of the present application. For example, in a first deployment mode, a closing operation may be performed one or more times to close both switches for a first simulated operating condition, and then, for the same chip, a closing operation may be performed one or more times to randomly close all switches for a second simulated operating condition. Or vice versa. The switches may be disconnected after each closing operation. In some embodiments, the chip may also be discharged. Such exemplary embodiments are further described below.

[0127] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated use scenario, and in particular, by simulating the general operating conditions corresponding to the use scenario of the chip, it is possible to obtain reliable and trustworthy test results.

[0128] In particular, by randomly closing the switches corresponding to all sampling channel lines, it is possible to simulate more common insertion and removal operation situations, making the simulation results more reliable and comprehensive, thereby obtaining a chip with high performance and reliability and reducing the number of failures that may occur during chip use.

[0129] In some embodiments, the at least one chip may include a first chip, and the at least one battery module may include at least two battery modules connected in series, and determining a configuration mode of the test circuit may include determining that the test circuit is in a second configuration mode, wherein the second configuration mode may indicate that the first chip is configured to be connected to a corresponding switch of the switch matrix such that, when the corresponding switch is turned on, sampling channel lines of the first chip are connectable to corresponding sampling lead lines of the at least two battery modules, respectively.

[0130] In this example, the second configuration mode can simulate a typical usage scenario in which one chip is connected to two or more battery modules. For convenience of explanation, this will be referred to as the second example scenario. It should be understood that the series-connected at least two battery modules may include a configuration in which the negative electrode of a first battery module is connected to the positive electrode of a second battery module, the negative electrode of the second battery module is connected to the positive electrode of a third battery module, etc. The fact that the sampling channel lines of the first chip are connectable to corresponding sampling lead lines of the at least two battery modules may mean that the number of sampling channel lines of the first chip is greater than the number of sampling lead lines of a single battery module among the at least two battery modules. For example, the number of sampling channel lines of the first chip may be equal to the sum of the number of sampling lead lines of the at least two battery modules.

[0131] 6 shows an example of a second configuration mode for a second example scenario. As shown in FIG. 6, in the test circuit 600, a first chip 630 is connected to corresponding switches 620-1, ... 620-n, 620-(n+1), ... 620-N of the switch matrix 620 such that, when the corresponding switches 620-1, ... 620-n, 620-(n+1), ... 620-N are turned on, the sampling channel lines 630-1, ... 630-n of the first chip 630 are respectively connectable to corresponding sampling lead lines 610-1, ... 610-n of the first battery module 611 of the two series-connected battery modules 611, 612, and the sampling channel lines 630-(n+1), ... 630-N of the first chip 630 are respectively connectable to corresponding sampling lead lines 610-(n+1) ... 610-N of the second battery module 612.

[0132] It should be understood that while FIG. 6 illustrates the at least one battery module including two battery modules connected in series, it may include more battery modules. Also, while FIG. 6 illustrates a one-to-one correspondence between the sampling channel lines of the first chip and the sampling lead lines of the two battery modules, it should be understood that the present application is not limited thereto. As another non-limiting example, in such an embodiment, the number of sampling channels of the first chip may be less than the total number of sampling lead lines of the battery modules. For example, only some of the sampling lead lines of the battery modules may be sampled.

[0133] It should also be understood that, although Figure 6 illustrates the first chip including N sampling channel lines that can be respectively connected to the n sampling leads 610-1...610-n of the first battery module 611 and the (Nn) sampling leads of the second battery module 612, this number is not limiting. In one example, the first battery module 611 and the second battery module 612 may have the same number of sampling leads, e.g., N = 2n. In other examples, the first battery module 611 and the second battery module 612 (and, in some other embodiments, other battery modules connected in series) may have different numbers of sampling leads.

[0134] According to this embodiment, a test based on a normalized use scenario can be realized, and in particular, by making the circuit configuration mode of the test closer to the use scenario of the chip, it is possible to simulate a general use scenario of the chip, thereby obtaining a highly reliable test result.

[0135] Specifically, this embodiment covers the scenario where the number of sampling channel lines of the first chip is greater than the number of sampling lead lines of a single battery module, or other scenarios where one chip can be used to sample two or more batteries, thereby realizing credible and reliable simulation and testing of such common usage scenarios. It should be understood that for this second example scenario, the maximum voltage that the chip can receive may be greater than the voltage of a single battery module, so it is very advantageous to cover such scenarios in testing.

[0136] In some examples, in response to determining that the test circuit is in the second configuration mode, performing the closing operation may include, if none of the switches corresponding to sampling leads of a positive battery module among the at least two battery modules are closed, closing switches corresponding to sampling leads of the remaining battery modules among the at least two battery modules excluding the positive battery module, and closing a switch corresponding to a sampling lead associated with a highest battery potential of the positive battery module after a first time lag has elapsed since the switches corresponding to the sampling leads of the remaining battery modules are closed.

[0137] According to this embodiment, the following operating situation can be provided for the second configuration mode, i.e., the second exemplary scenario to be simulated: Since the negative battery module has already been installed, the sampling channel line corresponding to the positive battery module may already be at a corresponding negative voltage potential. In this case, when the positive battery module is installed, the chip may instantly experience a very large voltage difference. For convenience of explanation, this will be referred to as the first simulated operating situation for the second exemplary scenario.

[0138] As will be understood by those skilled in the art, the positive battery module may be the battery module closest to the positive electrode among at least two battery modules connected in series, i.e., the battery module with the highest battery potential. For example, continuing to refer to the example of FIG. 6, the positive battery module may be the first battery module 611, and the "remaining battery module" may be the second battery module 612. The sampling lead associated with the highest battery potential may be sampling lead 610-1, and the corresponding switch may be switch 620-1. In other words, before closing switches 620-1, ..., 620-n, switches 620-(n+1), ..., 620-N may be closed, and after a predetermined first time lag, the farthest switch 620-1 may be closed. The first time lag may be any time lag selectable by those skilled in the art as needed. For example, a longer first time lag may be selected so that the sampling channel lines 630-1 to 630-n that are not connected to the corresponding sampling lead lines are set to a relatively low voltage, a shorter first time lag may be selected so as to improve test efficiency, or a suitable intermediate value between the two may be selected. Alternatively, the first time lag may be selected randomly.

[0139] In some embodiments, the step of closing the switches corresponding to the sampling leads of the remaining battery modules of the at least two battery modules may further include preferentially closing the switches corresponding to a pair of sampling leads associated with a maximum battery potential difference among the sampling leads of the remaining battery modules, thereby locally simulating a relatively poor operating condition, or may further include randomly closing the switches corresponding to the sampling leads of the remaining battery modules.

[0140] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated use scenario. In particular, by matching the test operating conditions with the circuit configuration mode, i.e., simulating the general operating conditions that correspond to the current use scenario of the chip, it is possible to obtain reliable and trustworthy test results.

[0141] Specifically, this embodiment can simulate relatively poor operating conditions when one chip is connected to two or more battery modules, and can improve the reliability of the chip obtained by this testing method.

[0142] In some examples, the step of performing the closing operation may further include, after the switch corresponding to the sampling lead associated with the highest battery potential is closed, randomly closing switches corresponding to the remaining sampling leads of the positive battery modules excluding the sampling lead associated with the highest battery potential.

[0143] Continuing with the example of FIG. 6, after the farthest switch 620-1 is closed, a power-on test may be performed on the corresponding sampling channel line by closing the second switch (not shown) through the nth switch (620-n) etc. using a random strategy.

[0144] According to this embodiment, it is possible to further test possible operating conditions for the simulated use scenario, and by using randomly closing logic, it is possible to make the simulation results more reliable and comprehensive. Specifically, for the first simulated operating condition for the second example scenario, it is possible to further simulate the risks to sampling channel lines other than the sampling channel line receiving the largest voltage difference, thereby enabling risk testing and evaluation of each sampling channel line and corresponding circuit part of the chip, and thereby obtaining more reliable test results.

[0145] In some embodiments, in response to determining that the test circuit is in the second configuration mode, performing the closing operation may include, if none of the switches corresponding to the sampling leads of a negative battery module among the at least two battery modules are closed, closing switches corresponding to the sampling leads of the remaining battery modules among the at least two battery modules excluding the negative battery module, and closing a switch corresponding to the sampling lead of the negative battery module associated with a lowest battery potential after a second time lag has elapsed since the switches corresponding to the sampling leads of the remaining battery modules are closed.

[0146] The second example scenario provides a symmetrical operating situation corresponding to the first operating situation. That is, since the positive battery module has already been installed, the sampling channel line corresponding to the negative battery module may already be at the corresponding positive voltage potential. In this case, when the negative battery module is installed, the chip may be instantaneously subjected to a very large voltage difference. For convenience of explanation, this will be referred to as the second simulated operating situation for the second example scenario.

[0147] Similarly, as will be understood by those skilled in the art, the negative battery module may be the battery module closest to the negative terminal among the at least two battery modules connected in series, i.e., the battery module with the lowest battery potential. For example, continuing to refer to the example of FIG. 6, the negative battery module may be the second battery module 612, and the "remaining battery modules" may be the first battery module 611. In other words, before closing switches 620-(n+1), ..., 620-N, switches 620-1, ..., 620-n may be closed, and after a predetermined second time lag, the farthest switch 620-N may be closed. The second time lag may be similar to the first time lag, e.g., may be the same or similar value as the first time lag, or may be a value selected by a strategy similar to the first time lag, which will not be repeated here.

[0148] In some embodiments, closing the switches corresponding to the sampling leads of the remaining battery modules excluding the negative battery module among the at least two battery modules may include preferentially closing the switches corresponding to a pair of sampling leads associated with a maximum battery potential difference among the sampling leads of the remaining battery modules to locally simulate a relatively poor operating condition, or may include randomly closing the switches corresponding to the sampling leads of the remaining battery modules.

[0149] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated use scenario. In particular, by matching the test operating conditions with the circuit configuration mode, i.e., simulating the general operating conditions that correspond to the current use scenario of the chip, it is possible to obtain reliable and trustworthy test results.

[0150] Specifically, this embodiment can simulate a second scenario in which one chip is connected to two or more battery modules, which is a relatively poorer operating condition.

[0151] It should be understood that, for the second scenario, in some embodiments, the second operating conditions here can be combined with the first operating conditions (e.g., performing each test once or multiple times) to more comprehensively cover the various application scenarios to which the chip may be subjected, making the tests more regular, comprehensive, and reliable.

[0152] In some examples, the step of performing the closing operation may further include, after the switch corresponding to the sampling lead associated with the lowest battery potential is closed, randomly closing switches corresponding to the remaining sampling leads of the negative battery module excluding the sampling lead associated with the lowest battery potential.

[0153] Continuing with the example of FIG. 6, for example, after the farthest switch 620-N is closed, a power-on test may be performed on the corresponding sampling channel line by closing the (n+1)th switch to the (N-1)th switch (not shown) etc. using a random strategy.

[0154] According to this embodiment, it is possible to further test possible operating conditions for the simulated use scenario, and by using random closing logic, it is possible to make the simulation results more reliable and comprehensive. Specifically, for the second simulated operating condition for the second example scenario, it is possible to further simulate the risks to sampling channel lines other than the sampling channel line receiving the maximum voltage difference, thereby obtaining more reliable test results.

[0155] In some embodiments, the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a third configuration mode, the third configuration mode indicating that the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix such that when the corresponding switches are turned on, the first chip and the second chip are connectable to corresponding sampling leads of the first battery module.

[0156] In this example, the third configuration mode can simulate a scenario in which two chips are connected to one battery module. Here, for convenience of explanation, this will be referred to as the third example scenario. For example, the number of sampling leads of the first battery module may be equal to the sum of the number of sampling channel lines of the first chip and the second chip. Or, in the third example scenario, the number of sampling leads of the first battery module may be equal to the sum of the number of sampling channel lines of the first chip and the second chip. but Number of sampling channel lines on the first chip More thanSince only one chip may be required to sample the first battery module, more than one chip is required to sample the first battery module, but it is not required that the number of sampling lead lines of the first battery module exactly match the number of sampling channel lines of the first chip and the second chip.

[0157] 7 shows an example of a third configuration mode for a third example scenario. As shown in FIG. 7, in the test circuit 700, a first chip 731 is configured to be connected to corresponding switches 720-1, ..., 720-n of the switch matrix 720, and a second chip 732 is connected to corresponding switches 720-(n+1), ..., 720-N of the switch matrix 720, such that when the corresponding switches 720-1, ..., 720-n, 720-(n+1), ..., 720-N are turned on, the sampling channel lines 730-1, ..., 730-N of the first chip 731 and the second chip 732 can be connected to corresponding sampling lead lines 710-1, ..., 710-n, 710-(n+1), ..., 710-N of the battery module 710, respectively.

[0158] It should be understood that while FIG. 7 illustrates a first chip 731 and a second chip 732, the present application is not limited thereto. For example, there may be three or more chips sampling the same battery module. Also, while FIG. 7 illustrates a one-to-one correspondence between the sampling channel lines of the first chip 731 and the second chip 732 and the sampling lead lines of the battery module 710, it should be understood that the present application is not limited thereto. For example, only some of the sampling lead lines of the battery module may be sampled. It should be understood that the first chip 731 and the second chip 732 may have the same number of sampling channel lines, e.g., N=2n, or the first chip 731 and the second chip 732 may have different numbers of sampling lead lines, but the present application is not limited thereto.

[0159] According to this embodiment, a test based on a normalized use scenario can be realized, and in particular, by making the circuit configuration mode of the test closer to the use scenario of the chip, it is possible to simulate a general use scenario of the chip, thereby obtaining a highly reliable test result.

[0160] Specifically, such an embodiment covers situations where the number of sampling channel lines of the first chip is less than the number of sampling lead lines of a single battery module, and other situations where two or more chips are available for sampling a single battery, thereby enabling credible and reliable simulation and testing in such common usage scenarios.

[0161] In some embodiments, a first sampling channel line of the first chip and a second sampling channel line of the second chip may be connectable to adjacent first and second sampling lead lines of the first battery module, and a third sampling channel line of the first chip and a fourth sampling channel line of the second chip may be connectable to third and fourth sampling lead lines of the first battery module associated with a maximum battery potential difference, and performing the closing operation in response to determining that the test circuit is in a third configuration mode may include: closing switches corresponding to the first and second sampling channel lines when none of switches corresponding to the remaining sampling channel lines of the first and second chips other than the first and second sampling channel lines are closed; and closing the switches corresponding to the third and fourth sampling channel lines after a third time lag has elapsed since the switches corresponding to the first and second sampling channel lines were closed.

[0162] According to this embodiment, a third configuration mode, i.e., an operating condition in which switches corresponding to adjacent sampling channel lines of two chips are closed first for a third example scenario to be simulated, is provided, which for convenience of explanation will be referred to herein as a first simulated operating condition for the third example scenario.

[0163] 7, in this exemplary case, the adjacent first and second sampling leads of the first battery module are sampling leads 710-n and 710-(n+1), the corresponding first sampling channel line of the first chip is sampling channel line 730-n, and the corresponding second sampling channel line of the second chip is sampling channel line 730-(n+1). The third and fourth sampling leads associated with the maximum battery potential difference are sampling leads 710-1 and 710-N, respectively, so the third sampling channel line of the first chip may be sampling channel line 730-1, and the fourth sampling channel line of the second chip may be sampling channel line 730-N.

[0164] As shown in FIG. 7, it should be understood that in the third exemplary scenario, the assumed first simulated operating situation is the worst-case operating situation, because in such a scenario, the two adjacent sampling channel lines 730-n and 730-(n+1) of the two chips are respectively connected to adjacent sampling lead lines of the battery module by corresponding switches, and at this time, the two chips can be approximately regarded as one large chip in the circuit, so that when the switches 720-1 and 720-N corresponding to the two sampling channel lines 730-1, 730-N at the farthest ends of the chip are turned on, the chip will receive the voltage of the entire battery module 710.

[0165] It should also be understood that, as explained above, the term “closing the switches corresponding to the first sampling channel line and the second sampling channel line” as used herein may include, but is not limited to, logic such as closing switches 720-n and 720-(n+1) simultaneously or approximately simultaneously within a tolerance, closing one of switches 720-n and 720-(n+1) immediately after closing the other switch, or closing one of switches 720-n and 720-(n+1) first and then closing the other switch after a predetermined or random time lag, as long as it ensures that the two switches corresponding to the first sampling channel line and the second sampling channel line are already closed and electrically connectable before the other switch is closed.

[0166] Similarly, it should be understood that "closing the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line" may include, but is not limited to, logic such as closing switches 720-1 and 720-N simultaneously or approximately simultaneously within a tolerance, closing one of switches 720-1 and 720-N immediately after closing the other switch, or closing one of switches 720-1 and 720-N first and then closing the other switch after a predetermined or random time lag has elapsed.

[0167] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated use scenario. In particular, by matching the test operating conditions with the circuit configuration mode, i.e., simulating the general operating conditions that correspond to the current use scenario of the chip, it is possible to obtain reliable and trustworthy test results.

[0168] Specifically, this embodiment can simulate adverse conditions to improve the test effect and the reliability of the chip obtained through the test, and the chip obtained through such a test can exhibit sufficient reliability even under extreme operating conditions.

[0169] In some embodiments, the step of performing the closing operation may further include the step of randomly closing switches corresponding to the remaining sampling channel lines of the first chip and the second chip, excluding the first sampling channel line, the second sampling channel line, the third sampling channel line, and the fourth sampling channel line, after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed.

[0170] Continuing with reference to the example of FIG. 7, for example, adjacent switches 720-n and 720-(n+1) may be closed first, followed by the farthest switches 720-1 and 720-N, and then the remaining switches (not shown) may be closed in a random strategy to perform a power-on test on the corresponding sampling channel line.

[0171] According to this embodiment, it is possible to further test possible operating conditions for the simulated use scenario. By using random closing logic, it is possible to make the simulation results more reliable and comprehensive. In other words, for the first simulated operating situation for the third example scenario, it is possible to further simulate the risks to sampling channel lines other than the sampling channel line receiving the largest voltage difference, thereby comprehensively testing the chip's tolerance.

[0172] In some embodiments, in response to determining that the test circuit is in a third configuration mode, performing the closing operation may include randomly closing switches corresponding to sampling channel lines of the first chip and the second chip.

[0173] 7, for convenience of explanation, this operating situation will be referred to as the second simulated operating situation for the third example scenario. In the second simulated operating situation for the third example scenario, any two or more of switches 720-1, ... 720-n, 720-(n+1), ... 720-N may be closed, and the closing operations may be performed in a random order and / or the time lag between two switches being closed sequentially may be random.

[0174] This allows for the third example scenario to simulate not only the worst-case operating condition provided, but also other common operating conditions that are actually used in testing. This embodiment allows for other common insertion and removal operating conditions to be covered. Furthermore, the use of random closing logic makes the simulation results more credible, resulting in comprehensive and reliable test results.

[0175] In some embodiments, a first sampling channel line of the first chip and a second sampling channel line of the second chip may be connectable to adjacent first sampling lead lines and second sampling lead lines of the first battery module, and a third sampling channel line of the first chip and a fourth sampling channel line of the second chip may be connectable to third sampling lead lines and fourth sampling lead lines of the first battery module associated with a maximum battery potential difference, and the third configuration mode may further indicate that the first sampling channel line and the second sampling channel line are electrically connected.

[0176] In this example, two more chips are short-circuited compared to the third example scenario. For convenience of explanation, this scenario may be referred to as the fourth example scenario. In practical applications, the fourth example scenario may cover the case where two or more chips are short-circuited or connected in series in advance when the number of sampling channel lines of a single chip is less than the number of sampling lead lines of a single battery waiting to be sampled.

[0177] Referring to Figure 8 as an example, similar to Figure 7, in the test circuit 800 of Figure 8, a first chip 831 is arranged to be connected to corresponding switches 820-1, ..., 820-n of the switch matrix 820, and a second chip 832 is arranged to be connected to corresponding switches 820-(n+1), ..., 820-N of the switch matrix 820, such that when the corresponding switches 820-1, ..., 820-n, 820-(n+1), ..., 820-N are turned on, the sampling channel lines 830-1, ..., 830-N of the first chip 831 and the second chip 832 can be connected to corresponding sampling lead lines 810-1, ..., 810-n, 810-(n+1), ..., 810-N of the battery module 810, respectively. It should also be understood that the number of channels, the number of chips, etc. in the figure are merely examples, and the present application is not limited thereto.

[0178] As shown in FIG. 8, the first chip 831 and the second chip 832 are electrically connected by a short-circuit wire 8301 .

[0179] According to this embodiment, a test based on a normalized use scenario can be realized, and in particular, by making the circuit configuration mode of the test closer to the use scenario of the chip, it is possible to simulate a general use scenario of the chip, thereby obtaining a highly reliable test result.

[0180] Specifically, this embodiment, based on the third scenario, further considers a fourth example scenario in which the chip is pre-short-circuited, thereby more comprehensively covering the scenarios that the chip may encounter and obtaining reliable test results.

[0181] In some embodiments, in response to determining that the test circuit is in a third configuration mode, performing the closing operation may include closing a switch corresponding to a sampling channel line of the second chip if none of the switches corresponding to the sampling channel line of the first chip are closed, and closing a switch corresponding to the third sampling channel line a third time lag after the switch corresponding to the sampling channel line of the second chip is closed.

[0182] Continuing to refer to FIG. 8 as an example, in this exemplary case, the adjacent first and second sampling leads of the first battery module are sampling leads 810-n and 810-(n+1), the corresponding first sampling channel line of the first chip is sampling channel line 830-n, and the corresponding second sampling channel line of the second chip is sampling channel line 830-(n+1). Since the third and fourth sampling leads associated with the maximum battery potential difference are sampling leads 810-1 and 810-N, respectively, the third sampling channel line of the first chip may be sampling channel line 830-1, and the fourth sampling channel line of the second chip may be sampling channel line 830-N. In other words, switches 820-(n+1) to 820-N may be closed first, and then switch 820-1 may be closed after a third time lag. For convenience of explanation, this operating situation may be referred to as a first operating situation for the fourth exemplary scenario.

[0183] In some embodiments, in response to determining that the test circuit is in a third configuration mode, performing the closing operation may include: closing a switch corresponding to the sampling channel line of the first chip when none of the switches corresponding to the sampling channel line of the second chip are closed; and closing a switch corresponding to the fourth sampling channel line after a fourth time lag has elapsed since the switch corresponding to the sampling channel line of the first chip is closed. It should be understood that this operating situation is symmetrical to the first operating situation and may be referred to as a second operating situation for convenience of distinction.

[0184] It should be understood that the third and / or fourth time lags may be similar to the first and second time lags, e.g., may be the same or similar value as the first or second time lag, or may be selected by a strategy similar to the first or second time lag, which will not be repeated here.

[0185] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated use scenario. In particular, by matching the test operating conditions with the circuit configuration mode, i.e., simulating the general operating conditions that correspond to the current use scenario of the chip, it is possible to obtain reliable and trustworthy test results.

[0186] Specifically, this embodiment closes one chip first, and then closes the switch furthest from another chip, thereby simulating the poor operating conditions that can be endured during hot swapping in the case of a chip short circuit, thereby obtaining reliable test results.

[0187] In some embodiments, the step of performing the closing operation may further include the step of randomly closing switches corresponding to the remaining sampling channel lines of the first chip except for the third sampling channel line after the switch corresponding to the third sampling channel line is closed.

[0188] Continuing to refer to FIG. 8 as an example, in the first operating condition for the fourth example scene, after switch 820-1 is closed, the switches (e.g., 820-n) corresponding to the remaining sampling channel lines (e.g., 830-n) of the first chip 831 may be randomly closed.

[0189] It should be understood that the above Symmetry The operating state, i.e., the second operating state for the fourth example scenario, may also have subsequent random operations, for example, after a fourth time lag has elapsed since the switch corresponding to the sampling channel line of the first chip is closed, and after the switch corresponding to the fourth sampling channel line is closed, the switches corresponding to the remaining sampling channel lines of the second chip may be randomly closed.

[0190] According to this embodiment, it is possible to further test possible operating conditions for the simulated use scenario, and by using random closing logic, it is possible to make the simulation results more reliable and comprehensive. Specifically, for the fourth example scenario, other common insertion and removal operating conditions and each sampling channel line can be covered, so that risk testing and evaluation of each sampling channel line and corresponding circuit part of the chip can be performed, and more reliable test results can be obtained.

[0191] In some embodiments, the operation termination condition may include at least one of: the number of times a close operation is performed on the at least one chip reaches a first threshold; and the number of times a close operation is performed based on a particular placement mode reaches a second threshold for the particular placement mode.

[0192] According to this embodiment, when the test count is met, it is determined that the operation termination condition is met, and a chip performance test, for example, a 5-point test, can be performed. It should be understood that the first threshold and the second threshold may be 1, that is, it can also cover a situation where the test is performed only once.

[0193] In some embodiments, the operation termination condition may include that a closing operation has already been performed in one or more specific operating conditions for a specific configuration mode. As a specific and non-limiting example, the operation termination condition may include that a first predetermined number of closing operations have already been performed for a first operating condition for a first configuration mode (first example scenario), a second predetermined number of closing operations have already been performed for a second operating condition, etc. As a more specific and non-limiting example, the number of hot swaps in each operating condition may be specified as 30 or more, although the present application is not limited thereto.

[0194] This allows for more standardized testing of the chips by limiting the termination conditions.

[0195] Specifically, if the first or second threshold value in the operation termination condition is set to a value greater than 1, the reliability can be tested by increasing the number of repeated tests under the same operating conditions. Also, for example, if the same first or second threshold value is specified for different chip manufacturers or test locations, the chip tests will be more regular and standardized, reducing the variance in test results, and the resulting chips will be more stable and standardized.

[0196] In some embodiments, the testing method may further include, in response to determining that an operation termination condition is not satisfied, repeating the steps of performing a power-off operation on the at least one chip, discharging a capacitor in the at least one chip, performing a close operation to close at least two switches of the switch matrix, and testing functionality of the at least one chip, wherein the operation termination condition includes at least one of: a first threshold value for the number of close operations performed on the at least one chip; and a second threshold value for the number of times each operating condition of the at least one operating condition is performed.

[0197] According to such an embodiment, if the termination condition is not met (e.g., not enough times or not tested in a particular configuration mode), the switch is disconnected, the configuration mode is determined, and the test is repeated, thereby further normalizing and automating the test method, avoiding manual insertion and removal, and improving test efficiency.

[0198] According to such an embodiment, when the test count is met, it is determined that the operation termination condition is met, and chip functionality tests can be performed, such as, but not limited to, various sample functionality tests described below. It should be understood that the first threshold and the second threshold can be 1, i.e., can cover the scenario of only one test.

[0199] In some embodiments, the operation termination condition may include that a closing operation has already been performed in one or more specific operating conditions for a specific configuration mode. As a specific, non-limiting example, the operation termination condition may include that, for a first configuration mode (first example scenario), a first predetermined number of closing operations have already been performed for a first operating condition, a second predetermined number of closing operations have already been performed for a second operating condition, etc. As a more specific, non-limiting example, the number of hot swaps in each operating condition may be specified as 30 or more, although the present application is not limited thereto.

[0200] This allows for more standardized testing of the chips by limiting the termination conditions.

[0201] Specifically, if the first or second threshold value in the operation termination condition is set to a value greater than 1, the reliability can be tested by increasing the number of repeated tests under the same operating conditions. Also, for example, if the same first or second threshold value is specified for different chip manufacturers or test locations, the chip tests will be more regular and standardized, reducing the variance in test results, and the resulting chips will be more stable and standardized.

[0202] Furthermore, according to this embodiment, by performing a discharge operation before each closing operation, the operation is repeated under the condition that the capacitor is uncharged, reducing the influence of the previous operation on the capacitor and making the test operating conditions worse. This type of test results in more reliable chip function. Specifically, without the discharge unit, the AFE chip would be locally charged after the first hot swap (closing operation), weakening the stress of subsequent hot swaps. On the other hand, adding the discharge unit makes each hot swap more realistic, resulting in more reliable test results and more favorable for repeating tests to improve reliability.

[0203] It should be understood that the discharge operation may be achieved by grounding or other operation understood by those skilled in the art. For example, the discharge process may be considered complete after a predetermined time has elapsed since the discharge circuit was turned on. Such a time may be determined by those skilled in the art based on experience, experimentation, or other criteria, and may be constant in a hot swap test or may be varied depending on other environmental conditions, circuit conditions, or sample conditions. The discharge operation may be a discharge operation to a test stand.

[0204] According to one or more embodiments of the present application, various possible hot swapping scenarios and operating conditions in actual applications can be simulated, which has a wide range of applications and high standardizability and consistency.

[0205] In some embodiments, the testing method may further include, in response to determining that the step of energizing the at least one chip is performed for the first time for the at least one chip, adjusting the voltage of a single cell of a battery in the at least one battery module to a predetermined value before testing the functionality of the at least one chip.

[0206] According to this embodiment, the stability of the test can be ensured. As a non-limiting example, the predetermined value of the voltage of a single cell may be 4.25V. For example, the predetermined value of the voltage of a single cell may be approximately the same as the cell voltage used in the corresponding scene or operating condition, or may be higher than the cell voltage used in the corresponding scene or operating condition to obtain reliable test results. Other examples will be described in detail below with reference to specific embodiments.

[0207] In some embodiments, testing the performance of the at least one chip includes performing a range of power supply voltage tests on the at least one chip.

[0208] The power supply voltage range test may be a five-point test, i.e., testing the chip five times under five predetermined combinations of environmental temperature, voltage, etc. The power supply voltage range test may also be any other test, detection, inspection, or verification performed on the voltage performance of a chip that is understood by those skilled in the art.

[0209] Additionally or alternatively, testing the functionality of the at least one chip may further include performing at least one of the following tests on the at least one chip: a power supply current range test, a cell voltage sampling accuracy test, a cell temperature sampling accuracy test, and a leakage current diagnostic threshold test. It should also be understood that these tests may be tests, detections, inspections, or verifications of corresponding chip performance as understood by those skilled in the art.

[0210] Below are some non-limiting examples of chip tests that will not be repeated here.

[0211] According to this embodiment, the performance of the chip can be ensured and the test effect can be made more reliable.

[0212] According to one or more aspects of the present application, there is further disclosed a test apparatus for chips, comprising: a switch matrix; and a control device capable of controlling the operation of at least one switch of the switch matrix to perform a current-carrying operation for at least one chip according to a configuration mode, wherein the control device is configured to connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0213] According to some demonstrative embodiments, the test apparatus may further include at least one battery module, and performing a power-on operation on the at least one chip according to the configuration mode includes connecting the at least one chip to the at least one battery module.

[0214] According to some demonstrative embodiments, connecting the at least one chip to the at least one battery module includes performing a closing operation to close at least two switches of the switch matrix.

[0215] According to some demonstrative embodiments, performing a closing operation to close at least two switches of the switch matrix includes closing the switches of the switch matrix based on at least one of a first strategy that preferentially closes two switches that form a current-carrying circuit with a maximum potential difference and a second strategy that preferentially closes switches that enable a closed circuit to be formed between the at least one battery module.

[0216] According to some example embodiments, the test device includes an interface for connecting to the at least one chip, for example, an interface for connecting a chip under test, such as an AFE or a CSC.

[0217] According to some exemplary embodiments, the control device includes a host computer.

[0218] According to one or more aspects of the present application, there is further disclosed a test apparatus for chips, comprising at least one battery module, a switch matrix, and a host computer capable of controlling the operation of at least one switch in the switch matrix capable of connecting at least one chip to the at least one battery module, the host computer being configured to perform a method described in one or more embodiments of the present application.

[0219] 9 , a test apparatus 900 may include at least one battery module 910, a switch matrix 920, and a host computer 940. At least one chip 930 may be connected to corresponding switches 920-1, 920-2, 920-3, ... 920-N of the switch matrix 920, and arranged such that, when the corresponding switches 920-1, 920-2, 920-3, ... 920-N are turned on, the sampling channel lines 930-1, 930-2, 930-3, ... 930-N of the at least one chip 930 are connectable to corresponding sampling lead lines 910-1, 910-2, 910-3, ... 910-N of the at least one battery module 910, respectively.

[0220] As will be understood by those skilled in the art, when a host computer is capable of controlling the operation of at least one switch in a switch matrix, the host computer is operably connected to the switch matrix by electrical connection, signal connection, or other means, thereby being able to control the opening and closing of one or more switches in the switch matrix.

[0221] In some embodiments, the test apparatus may further comprise at least one discharge unit, which, when turned on, can discharge a corresponding capacitor of the at least one chip.

[0222] 9, the test apparatus 900 may further include a discharge unit 950. Specifically, the discharge unit 950 may include a ground switch and a resistor. Alternatively, the discharge unit may adopt other circuit designs capable of discharging a capacitor, but the present application is not limited thereto.

[0223] According to this embodiment, the chip can be discharged by providing a ground switch, which allows the closing operation to be performed in a discharged state of the capacitor, thereby reducing the influence of possible capacitor current flow on the chip and realizing more reliable testing.

[0224] According to one or more aspects of the present application, there is further disclosed a host computer capable of controlling the operation of at least one switch in a switch matrix arranged to connect at least one chip to at least one battery module, the host computer being configured to perform a method described in one or more embodiments of the present application.

[0225] According to one or more aspects of the present application, there is further disclosed a chip for a battery, which is tested by a method described in one or more examples of the present application.

[0226] According to one or more aspects of the present application, there is further disclosed an electronic device including at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores commands executable by the at least one processor, and the commands, when executed by the at least one processor, enable the at least one processor to perform a method according to one or more embodiments of the present application.

[0227] According to one or more aspects of the present application, there is further disclosed a non-transitory computer-readable storage medium having stored thereon computer instructions for causing a computer to perform a method according to one or more examples of the present application.

[0228] Illustrative examples of a computer device, a non-transitory computer-readable storage medium and a computer program product according to the present application are described below with reference to FIG.

[0229] 10 illustrates an exemplary configuration of a computing device 1000 capable of implementing the methods described herein. The computing device 1000 may be a variety of different types of devices, such as, for example, a server of a service supplier, a device associated with a client (e.g., a client device), a system-on-a-chip, and / or any other suitable computing device or system. Examples of computing devices 1000 include, but are not limited to, desktop computers, server computers, laptops, netbook computers, mobile devices (e.g., tablet PCs, cellular or other wireless telephones (e.g., smartphones), notebook computers, mobile stations), wearable devices (e.g., eyeglasses, watches), or other display devices, automotive computers, etc. Accordingly, computing devices 1000 may range from full-resource devices (e.g., personal computers) with large amounts of memory and processing resources to low-resource devices with limited memory and / or processing resources.

[0230] The computing device 1000 may include, for example, at least one processor 1002, memory 1004, communication interface(s) 1006, a display device 1008, other input / output (I / O) devices 1010, and one or more mass memory devices 1012, all of which may communicate with each other via a system bus 1014 or other suitable connections.

[0231] The processor 1002 may be a single processing unit or multiple processing units. Every processing unit may include single or multiple computing units or multiple cores. The processor 1002 may be embodied as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that controls signals based on operational commands. The processor 1002 may be configured to retrieve and execute computer-readable instructions stored in the memory 1004, mass memory device 1012, or other computer-readable medium, such as program code for an operating system 1016, program code for applications 1018, program code for other programs 1020, etc., among other capabilities.

[0232] The memory 1004 and the mass memory device 1012 are examples of computer-readable storage media for storing instructions that, when executed by the processor 1002, perform the various functions described above. By way of example, the memory 1004 may typically include both volatile and non-volatile memory (e.g., RAM, ROM, etc.). The mass memory device 1012 may also typically include hard disk drives, solid-state drives, removable media (including external and removable drives), memory cards, flash memory, soft disks, optical disks (e.g., CDs, DVDs), memory arrays, network-attached memory, storage area networks, etc. The memory 1004 and the mass memory device 1012 may be collectively referred to herein as memory or computer-readable storage media, and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code. The computer program code may be executed by the processor 1002 as a specific device configured to perform the operations and functions described in the examples herein.

[0233] A number of program modules may be stored on the mass memory device 1012. These programs, including an operating system 1016, one or more applications 1018, other programs 1020, and program data 1022, may be loaded and executed by the memory 1004. Examples of such applications or program modules may include, for example, computer program logic (e.g., computer program code or commands) for implementing the methodologies of one or more embodiments of the present application.

[0234] 10 as being stored in memory 1004 of computing device 1000, modules 1016, 1018, 1020, and 1022, or portions thereof, may be embodied by any computer-readable medium accessible by computing device 1000. As used herein, "computer-readable medium" includes at least two types of computer-readable media: computer storage media and communication media.

[0235] Computer storage media include volatile and nonvolatile, removable and non-removable media implemented by any method or technology for storage of information, such as computer-readable commands, data structures, program modules, or other data, including, but not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVDs) or other optical storage devices, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic memory devices, or any other non-transmission medium for storing information for access by a computing device.

[0236] In contrast, communication media may tangibly embody computer-readable commands, data structures, program modules or other data in a modulated data signal, such as a carrier wave or other transport mechanism. Computer storage media, as defined herein, does not include communication media.

[0237] Computing device 1000 may further include one or more communication interfaces 1006 for exchanging data with other devices, such as over a network, a direct connection, etc., as described above. Such communication interfaces may include any type of network interface (e.g., a network interface card (NIC)), wired or wireless (e.g., IEEE 802.10 Wireless LAN (WLAN) )stomach interface, Wi-MAX interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth TM The communication interface 1006 may be one or more of a wireless interface, a near field communication (NFC) interface, etc. The communication interface 1006 can facilitate communication over a variety of networks and protocols, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. Additionally, the communication interface 1006 can provide communication with external storage devices (not shown), for example, in a memory array, network-attached memory, storage area network, etc.

[0238] In some examples, a display device 1008, such as a monitor, may be included for displaying information and images to a user. Other I / O devices 1010 may be devices that receive various inputs from a user and provide various outputs to a user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, etc.

[0239] Next, non-limiting examples of the present application will be described with reference to FIGS.

[0240] As shown in FIG. 11, an exemplary test circuit 1100 may include at least one battery module 1110, a switch matrix 1120, at least one chip 1130, and a host computer 1140.

[0241] 11 shows two analog front-end (AFE) chips 1131 and 1132. The two AFE chips may be designed to form a cell monitor circuit (CMC) or a cell monitor unit (CMU) based on a typical recommended circuit. In some embodiments, a CMC needs to have at least two AFE chips.

[0242] The at least one battery module 1110 may include battery modules 1111 and 1112. The number of cells in the battery module may be changed during actual application. Real cells or cell simulators may be used.

[0243] The switch matrix 1120 may include switches for opening and closing modules and discharge circuits for discharging CMCs. Closing the switch corresponds to inserting a connector, and disconnecting the switch corresponds to removing the connector. By opening and closing switches (relays, semiconductor switches, etc.), the opening and closing of connector insertion and removal in actual applications can be simulated, providing greater flexibility. By linking the switch matrix with a host computer, various insertion and removal sequences can be flexibly simulated.

[0244] The host computer 1140 can control the disconnection logic and closing timing of the switch matrix to simulate hot swapping operation situations with different access orders. The host computer 1140 can also be used to receive and read information from the CMC and verify the normality of circuit function after hot swapping of the CMC. The host computer 1140 can execute the methods described in one or more embodiments of the present application. It should be understood that the present application is not limited thereto. The methods described in one or more embodiments of the present application can be realized by other devices, apparatuses, units, code logic, etc.

[0245] 11 , an example test circuit layout for the first example scenario is shown. As a specific, non-limiting example, the number of cells in the first battery 1111 and the number of sampling channels in the first chip 1131 are the same, the sampling lead wires of the first battery 1111 are all concentrated at the F1 connector, and the sampling channel wires of the first chip 1131 are all concentrated at the J1 connector. As a more specific, non-limiting example, the number of cells in the first battery 1111 and the number of sampling channels in the first chip 1131 may be the same, i.e., 16.

[0246] For such a circuit arrangement, as an example of a first operating condition for the first example scenario described in this specification, the worst operating condition for the first chip 1131 may be when both ends of the switches K1 and Km are closed first.

[0247] In some embodiments, FIG. 11 further illustrates a second chip 1132, which may be arranged similarly to the first chip 1131. It should be understood that while the two chips 1131 and 1132 are shown arranged to be connectable to the two corresponding batteries 1111 and 1112, respectively, the present application is not limited thereto. For example, the test circuit may include only one chip and one battery module. Alternatively, the test circuit may include more chips and more battery modules. In this example, the worst-case operating condition for the second chip 1132 in the first example operating condition for the first example scenario is when both switches Km+1 and K2m are closed first.

[0248] For example, the host computer 1140 (or other possible unit, device, etc.) may be configured to close the switches on both ends by performing a closing operation on the first chip and the second chip independently or simultaneously, or the host computer 1140 may be configured to test two or more chips in sequence by performing a closing operation on the first chip and the second chip, respectively, but the present application is not limited thereto.

[0249] For the first chip 1131, the switches K1 and Km on both ends may be closed first, followed by closing the other pins in a random order and / or after a random time lag. Similarly, in some embodiments, for the second chip 1132, the switches Km+1 and K2m on both ends may be closed first, followed by closing the other pins in a random order and / or after a random time lag.

[0250] As another example, as a second operating situation for the first example scene, the switches K1 to Km and the switches Km+1 to K2m may be closed randomly, for example with a random time lag or a random closing order, in order to simulate a situation that is closest to reality.

[0251] According to one or more embodiments of the present application, in some embodiments, a discharge unit 1150 may be provided. For example, after each power-off of a hot swap simulation, all discharge switches in the discharge unit 1150 are closed to discharge the circuit, thereby restoring the initial state and ensuring the consistency of the initial state for each hot swap.

[0252] Next, referring to FIG. 12, an example of a test circuit configuration for the second example scenario will be described. As shown in FIG. 12, the test circuit 1200 may include at least one battery module 1210, a switch matrix 1220, at least one chip 1230, and an upper computer 1240. More specifically, the at least one battery module 1210 includes battery modules 1211 and 1212, and at least one chip includes an AFE chip 1231. The total number of cells in the battery modules 1211 and 1212 is equal to the number of sampling channels in the AFE chip 1231. The battery modules 1211 and 1212 have separate sampling leads F1 and F2, and all of the sampling channel lines of the AFE chip 1231 are concentrated at J1. More specifically, the number of cells in the battery module 1211 may be 8, the number of cells in the battery module 1212 may be 8, or M1 + M2 = 16, and the number of sampling channels in the AFE chip 1231 may be 16. Some embodiments may further include a second AFE chip, which may be arranged similarly to the first AFE chip (not shown).

[0253] As a first simulated operating situation for the second example scenario, the switches K1 to Km of the AFE chip 1231 may be closed first, and then Km+1 to K2m may be closed after a predetermined time lag. In the process of closing the switches Km+1 to K2m, K2m may be closed preferentially, and then Km+1 to K2m-1 may be closed randomly.

[0254] As a second simulated operating situation for the second example scene, the switches Km+1 to K2m of the AFE chip 1231 may be closed first, and then K1 to Km may be closed after a predetermined time lag. In the process of closing the switches K1 to Km, K1 may be closed preferentially, and then K2 to Km may be closed randomly.

[0255] According to one or more embodiments of the present application, in some embodiments, a discharge unit 1250 may be provided. For example, after each power-off of a hot swap simulation, all discharge switches in the discharge unit 1250 are closed to discharge the circuit, thereby restoring the initial state and ensuring the consistency of the initial state for each hot swap.

[0256] Next, an example of a test circuit arrangement for the third example scenario will be described with reference to Fig. 13. As shown in Fig. 13, the test circuit 1300 may include at least one battery module 1310, a switch matrix 1320, at least one chip 1330, and a host computer 1340. More specifically, the at least one battery module 1310 includes a battery module 1311, and the at least one chip includes an AFE chip 1331 and an AFE chip 1332, where the number of cells in the battery module 1311 is equal to the total number of sampling channels in the AFE chip 1331 and the AFE chip 1332.

[0257] The battery module 1311 may be pulled out from one single connector F1. Alternatively, the battery module 1311 may be divided into two connectors F1 and F2 (not shown). All sampling channel lines of the AFE chip 1331 and the AFE chip 1332 are concentrated at J1. As a more specific example, the number of cells M1 of the battery module 1311 is set to 32, and the number of sampling channels of the AFE chip 1331 and the AFE chip 1332 is similarly set to 16+16.

[0258] As a first simulated operating situation for the third example scene, the switches Km and Km+1 may be closed preferentially, K1 and K2m may be closed after a time lag, and the remaining switches may be closed randomly.

[0259] As a second simulated operating situation for the third example scene, all of the switches K1 to K2m may be closed with a random time lag.

[0260] According to one or more embodiments of the present application, the discharge unit 1350 may be exemplarily configured to, for example, close all discharge switches in the discharge unit 1350 to discharge the circuit after each hot swap simulation power cut, thereby restoring the initial state and ensuring the consistency of the initial state for each hot swap.

[0261] Next, a test circuit layout example for the fourth example scenario will be described with reference to Figure 14. The fourth example scenario is based on the third example scenario, and has a short circuit between two AFE chips. contact It may also be a scene in which the above has been added.

[0262] 14, the test circuit 1400 may include at least one battery module 1410, a switch matrix 1420, at least one chip 1430, and a host computer 1440. More specifically, the at least one battery module 1410 includes a battery module 1411, and the at least one chip includes an AFE chip 1431 and an AFE chip 1432, where the number of cells in the battery module 1411 matches the total number of sampling channels in the AFE chip 1431 and the AFE chip 1432. The AFE chip 1431 and the AFE chip 1432 can be short-circuited by a short-circuit line 14301.

[0263] The battery module 1411 may be pulled out from one single connector F1. Alternatively, the battery module 1411 may be divided into two connectors F1 and F2 (not shown). All sampling channel lines of the AFE chip 1431 and the AFE chip 1432 are concentrated at J1. As a more specific example, the number of cells M1 of the battery module 1411 is set to 32, and the number of sampling channels of the AFE chip 1431 and the AFE chip 1432 is similarly set to 16+16.

[0264] It should be understood that in this example, switches Km and Km+1 may correspond to the first and second sampling leads, respectively, and switches K1 and K2m may correspond to the third and fourth sampling channel lines.

[0265] As a first simulated operating situation for the fourth example scene, the switches Km+1 to K2m may be closed preferentially, then the switch K1 may be closed after a time lag, and finally the switches K2 to Km may be closed randomly.

[0266] As a second simulated operating situation for the fourth example scene, the switches K1 to Km may be closed preferentially, then the switch K2m may be closed after a time lag, and finally the switches Km+1 to K2m-1 may be closed randomly.

[0267] According to one or more embodiments of the present application, for example, a discharge unit 1450 may be provided. For example, after each hot swap simulation power cut, all discharge switches in the discharge unit 1450 are closed to discharge the circuit, thereby restoring the initial state and ensuring the consistency of the initial state for each hot swap.

[0268] According to one or more embodiments of the present application, the sample state may be defined, for example, as follows: --Sample count: 6 from 3 different batches --Sample string number placement: chip sampling channel must be fully populated --Number of hot plugging / unplugging times under each operating condition: 30 times or more --Cell voltage: 4.25V or higher --Sample condition: No abnormalities after 5-point function verification

[0269] As a specific, non-limiting example, the test may include the following steps a to g. a) For the test sample, complete the construction of a simulation test stand according to the requirements of the live insertion / removal test stand. b) Applying electricity to the test sample, adjusting the voltage of a single cell to a predetermined value, and inspecting whether the function of the test sample meets the specified requirements. c) Turn off the power to the test sample and discharge any residual charge from the sample. d) Simulate the hot swapping scenario and the corresponding operating conditions, connect the corresponding cell channels in sequence, and after the channel connections are all completed, check whether the sample functions normally. e) Steps c to d are repeated until the required number of hot swap tests in the operating state is met. f) Repeat steps c to e until the test requirements for the remaining hot swapping operating conditions are met. g) Illustratively, steps b to f may be further repeated until the test requirements of the hot swap operation conditions of the remaining samples are met.

[0270] It should be understood that the above "scenes" and "operating situations" may correspond to various "example scenes" and "simulated operating situations" described in this application.

[0271] The test sample parameters are shown below. The number of samples may be 6 or some other number. The number of sample strings S may be selected according to the specific requirements of the hot swap test stand, the typical circuit layout, the battery module, the number of cells in each battery module, the layout requirements of the CMU, etc. --Sample condition: The functional condition after testing meets the required level of requirements. The voltage value of a single cell is, for example, 4.25V. This value may be determined through negotiation between the manufacturer and the consumer. For example, if there is variation in the voltage value of a single cell, the manufacturer may require that the content of the difference be explained in the test report. --The number of hot swaps is 30 or more.

[0272] It should be understood that throughout this text, unless otherwise stated or clearly indicated in context, terms such as test sample, chip, device under test, test sample, test chip, etc. may be used interchangeably to refer to a chip that is to undergo, is undergoing, or has undergone hot-swap testing. Additionally, terms such as test, testing, verification, functional testing, etc. may be used interchangeably to refer to performance verification or functional testing of a chip or test sample. The present disclosure is not limited in this respect.

[0273] For illustrative purposes, examples of environmental conditions and power supply voltages are given below.

[0274] Exemplary environmental conditions may include: --Room temperature: 23℃±5℃ --Relative humidity: 20%RH~80%RH Atmospheric pressure: 86kPa to 106kPa --Altitude: 1000m or less. For example, if it exceeds 1000m, the results shall be corrected according to the relevant provisions of GB / T 18488.1-2015.

[0275] Exemplary supply voltage conditions may include: --Single cell voltage: 3.65V. --Total power supply voltage: (3.65*L)V

[0276] Here, L is the number of cells in the battery module, and may be, for example, 8, 12, 16, 18, etc. It may be changed according to the specific requirements of the hot swap test stand, the typical circuit layout, the battery module, the number of cells in each battery module, the CMU layout requirements, etc.

[0277] Below are given specific, non-limiting examples of testing methods for some exemplary functional parameters.

[0278] For example, the power supply voltage range test may be performed by a test method including the following steps to verify the power supply voltage range for the AFE chip. a) Place the test sample in the oven and adjust the oven temperature to a predetermined temperature value. b) Applying electricity to the test sample, adjusting the voltage of a single cell to a predetermined value, and inspecting whether the function of the test sample meets the specified requirements. c) Once the temperature of the test sample has stabilized, maintain this condition for the specified operating time. d) During operation, monitor in real time whether the operating status of the test sample meets the specified requirements. --Number of samples: 6 --Operating hours: 24 hours --Table 1 shows the combinations of ambient temperature and power supply voltage.

[0279] [Table 1]

[0280] Here, L is the number of cells, and may be, for example, 8, 12, 16, 18, etc. It may be changed according to the specific requirements of the hot swap test stand, the typical circuit layout, the battery modules, the number of cells in each battery module, the layout requirements of the CMU, etc. The number of cells L can be selected according to the number of samples and the sampling channels of each sample chip, and vice versa.

[0281] It should be understood that the ambient temperatures and power supply voltages shown in Table 1 may be referred to as a five-point test. It should also be understood that the number of temperatures and voltages is merely an example and can be adjusted as needed. In some cases, more combinations of ambient temperatures and power supply voltages may be selected, for example, more than five test points may be performed.

[0282] For example, the chip may be subjected to a range test of power supply current. The AFE chip may be subjected to a range test of power supply current according to the following test method. a) Place the test sample in the oven and adjust the oven temperature to a predetermined temperature value. b) Applying electricity to the test sample, adjusting the voltage of a single cell to a predetermined value, and inspecting whether the function of the test sample meets the specified requirements. c) Once the temperature of the test sample has stabilized, the test sample is turned off. d) Maintain the specified operating time under these conditions. e) During operation, the operating current of the test sample is monitored and recorded in real time. f) Repeat steps a to e to complete the current test in the sleep state and the operating state. --Number of samples: 6 --Working time: 15 min --For combinations of ambient temperature and power supply voltage, see Table 1, for example.

[0283] For example, the chip may be tested for cell voltage sampling accuracy. The AFE chip may be tested for cell voltage sampling accuracy according to the following test method. a) Place the test sample in the oven and adjust the oven temperature to a predetermined temperature value. b) Applying electricity to the test sample, adjusting the voltage of a single cell to a predetermined value, and inspecting whether the function of the test sample meets the specified requirements. c) Once the temperature of the test sample has stabilized, begin taking single cell voltage readings collected from the test sample. d) Compare and record the voltage values ​​collected from the test sample with the values ​​from the sensing device. e) Repeat steps a to d to complete the voltage sampling accuracy test at all set temperatures. --Number of samples: 32 The number of sample placement strings is S. S may be a number selected according to the actual situation and typical operating conditions. --Sample condition: A sample aged for 1000 hours at +125°C. The aging conditions may be those understood by those skilled in the art, for example, aging conditions set according to relevant standards. --Operating time: 1 min --For combinations of ambient temperature and power supply voltage, see Table 2, for example.

[0284] [Table 2]

[0285] For example, the chip may be tested for cell temperature sampling accuracy, and the AFE chip may be verified for cell voltage sampling accuracy according to the following test method. a) Place the test sample in the oven and adjust the oven temperature to a predetermined temperature value. b) Applying electricity to the test sample, adjusting the voltage of a single cell to a predetermined value, and inspecting whether the function of the test sample meets the specified requirements. c) Once the temperature of the test sample has stabilized, begin reading the voltage values ​​of the temperature sampling lines collected from the test sample. d) Compare and record the voltage values ​​collected from the test sample with the values ​​from the sensing device. e) Repeat steps a to d to complete the test of the voltage accuracy of the temperature sampling line at all set temperatures. --Number of samples: 32. The number of sample placement strings is S. S may be a number selected according to the actual situation and typical operating conditions. --Sample condition: A sample aged for 1000 hours at +125°C. The aging conditions may be those understood by those skilled in the art, for example, aging conditions set according to relevant standards. --Working time: 1min. --For combinations of ambient temperature and power supply voltage, see Table 3, for example.

[0286] [Table 3]

[0287] Illustratively, the chip may be tested for a diagnostic threshold of leakage current. The AFE chip may be tested for a diagnostic threshold of leakage current according to the following test method. a) For the test sample, complete the construction of a simulated test stand according to the test requirements of the leakage current diagnostic threshold. b) Applying electricity to the test sample, adjusting the voltage of a single cell to a predetermined value, and inspecting whether the function of the test sample meets the specified requirements. c) A wave generator generates a specific wave interference and applies it to the corresponding diagnostic channel. d) The threshold changes of the diagnostic channel are observed and recorded by the host computer. e) Repeat steps cd to complete the test requests for the remaining channels. --Number of samples: 6. The number of sample placement strings is S. S may be a number selected according to the actual situation and typical operating conditions. --Sample status: The test results for the power supply voltage range verify that the functional status meets the level requirements. --Interference wave parameters: frequency 1kHz~20kHz, width ±300mV. --Interference duration: 5min.

[0288] For example, the levels of functional status are defined as follows: A rank is defined according to the functional status of the device under test (DUT) during and after the electromagnetic interference. --Condition A: During and after the test, all functions and parameters of the DUT meet the requirements of the design specification. -- Condition B: During the test, all functions of the DUT were normal, but one or more parameter indicators exceeded the specifications. After the test, all parameters automatically recovered to the specified requirements. --State C: During the test, one or more functions of the DUT failed to perform normally. After the test, all functions automatically recovered to the specified requirements. -- Condition D: During the test, one or more functions of the DUT failed to perform normally. After the test, it could not automatically recover to the specified requirements, and the DUT needed to be easily operated or re-functioned. -- Condition E: During the test, one or more functions of the DUT failed to perform normally. After the test, it could not automatically recover to the specified requirements, and the DUT needed to be repaired or replaced.

[0289] Illustratively, the functional status A level for the unpowered / off / sleeped test is determined by powering up the device after testing.

[0290] As an example, in this specification, terms such as "meet required level requirements" and "meet level requirements" used in the functional test portion of a chip indicate that the sample matches the level of condition A, but it should be understood that the present disclosure is not limited thereto.

[0291] The present application further provides the following examples.

[0292] Example 1 determining a configuration mode of a test circuit, the test circuit having at least one chip and at least one battery module, the at least one chip being connectable to the at least one battery module according to the configuration mode; and connecting the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0293] Example 2 10. The method of Example 1, further comprising testing the performance of the at least one chip.

[0294] Example 3 determining whether an end-of-operation condition is met before testing the performance of the at least one chip; 3. The method of Example 2, further comprising: testing the performance of the at least one chip in response to determining that an end-of-operation condition has been met.

[0295] Example 4 the test circuit further includes a switch matrix interposed between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode; 4. The method of any one of Examples 1 to 3, wherein connecting the at least one chip to the at least one battery module includes performing a closing operation to close at least two switches of the switch matrix.

[0296] Example 5 The method of Example 4, wherein the step of performing a closing operation to close at least two switches of the switch matrix includes a step of closing the switches of the switch matrix based on at least one of a first strategy of preferentially closing two switches that form a current-carrying circuit with a maximum potential difference and a second strategy of preferentially closing switches that enable a closed circuit to be formed between the at least one battery module.

[0297] Example 6 The method of Example 4, wherein the at least one chip includes a first chip, the at least one battery module includes a first battery module, and the step of determining a configuration mode of the test circuit includes determining that the test circuit is in a first configuration mode, the first configuration mode indicating that the first chip is configured to be connected to a corresponding switch of the switch matrix such that, when the corresponding switch is turned on, the sampling channel lines of the first chip are each connectable to a corresponding sampling lead line of the first battery module.

[0298] Example 7 performing the closing operation in response to determining that the test circuit is in a first configuration mode; The method of Example 6 includes a step of closing a pair of switches corresponding to the remaining pair of sampling channel lines, except for the pair of sampling channel lines associated with the maximum battery potential difference in the first chip, when none of the switches corresponding to the remaining pair of sampling channel lines are closed.

[0299] Example 8 performing the closing operation in response to determining that the test circuit is in a first configuration mode; The method of Example 7 further includes, after the pair of switches corresponding to the pair of sampling channel lines are closed, randomly closing switches corresponding to the remaining sampling channel lines in the first chip.

[0300] Example 9 9. The method of any one of Examples 6 to 8, wherein, in response to determining that the test circuit is in a first configuration mode, performing the closing operation includes randomly closing switches corresponding to sampling channel lines of the first chip.

[0301] Example 10 The method of Example 4, wherein the at least one chip includes a first chip, the at least one battery module includes at least two battery modules connected in series, and the step of determining the configuration mode of the test circuit includes the step of determining that the test circuit is in a second configuration mode, the second configuration mode indicating that the first chip is configured to be connected to a corresponding switch of the switch matrix such that, when the corresponding switch is turned on, the sampling channel lines of the first chip are each connectable to corresponding sampling lead lines of the at least two battery modules.

[0302] Example 11 performing the closing operation in response to determining that the test circuit is in the second configuration mode, If none of the switches corresponding to the sampling lead wires of the positive-side battery module among the at least two battery modules is closed, closing the switches corresponding to the sampling lead wires of the remaining battery modules among the at least two battery modules excluding the positive-side battery module; and closing the switch corresponding to the sampling lead associated with the highest battery potential of the positive battery module a first time lag after the switches corresponding to the sampling leads of the remaining battery modules are closed.

[0303] Example 12 The step of performing the closing operation includes: The method of Example 11 further includes, after the switch corresponding to the sampling lead wire associated with the highest battery potential is closed, randomly closing the switches corresponding to the remaining sampling leads of the positive battery modules excluding the sampling lead wire associated with the highest battery potential.

[0304] Example 13 performing the closing operation in response to determining that the test circuit is in the second configuration mode, If none of the switches corresponding to the sampling lead wires of the negative battery module among the at least two battery modules is closed, closing the switches corresponding to the sampling lead wires of the remaining battery modules among the at least two battery modules except for the negative battery module; and closing the switch corresponding to the sampling lead of the negative battery module associated with the lowest battery potential a second time lag after the switches corresponding to the sampling leads of the remaining battery modules are closed.

[0305] Example 14 The step of performing the closing operation includes: Example 14. The method of Example 13, further comprising the step of randomly closing switches corresponding to the remaining sampling leads of the negative battery modules, excluding the sampling lead associated with the lowest battery potential, after the switch corresponding to the sampling lead associated with the lowest battery potential is closed.

[0306] Example 15 The method of Example 4, wherein the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and the step of determining the configuration mode of the test circuit includes the step of determining that the test circuit is in a third configuration mode, the third configuration mode indicating that the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix such that when the corresponding switches are turned on, the first chip and the second chip are connectable to corresponding sampling leads of the first battery module.

[0307] Example 16 a first sampling channel line of the first chip and a second sampling channel line of the second chip are connectable to adjacent first sampling lead lines and second sampling lead lines of the first battery module, and a third sampling channel line of the first chip and a fourth sampling channel line of the second chip are connectable to third sampling lead lines and fourth sampling lead lines of the first battery module associated with a maximum battery potential difference; and performing the closing operation in response to determining that the test circuit is in a third configuration mode: When none of the switches corresponding to the remaining sampling channel lines of the first chip and the second chip other than the first sampling channel line and the second sampling channel line are closed, closing the switches corresponding to the first sampling channel line and the second sampling channel line; and closing the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line a third time lag after the switches corresponding to the first sampling channel line and the second sampling channel line are closed.

[0308] Example 17 The step of performing the closing operation includes: The method of Example 16 further includes, after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, randomly closing switches corresponding to the remaining sampling channel lines of the first chip and the second chip, excluding the first sampling channel line, the second sampling channel line, the third sampling channel line, and the fourth sampling channel line.

[0309] Example 18 18. The method of any one of Examples 15 to 17, wherein, in response to determining that the test circuit is in a third configuration mode, performing the closing operation includes randomly closing switches corresponding to sampling channel lines of the first chip and the second chip.

[0310] Example 19 The method of Example 15, wherein the first sampling channel line of the first chip and the second sampling channel line of the second chip are connectable to adjacent first sampling lead lines and second sampling lead lines of the first battery module, and the third sampling channel line of the first chip and the fourth sampling channel line of the second chip are connectable to third sampling lead lines and fourth sampling lead lines of the first battery module associated with a maximum battery potential difference, and the third configuration mode further indicates that the first sampling channel line and the second sampling channel line are electrically connected.

[0311] Example 20 performing the closing operation in response to determining that the test circuit is in a third configuration mode; If none of the switches corresponding to the sampling channel lines of the first chip are closed, closing the switches corresponding to the sampling channel lines of the second chip; and closing a switch corresponding to the third sampling channel line a third time lag after the switch corresponding to the sampling channel line of the second chip is closed.

[0312] Example 21 The step of performing the closing operation includes: The method of Example 20 further includes, after the switch corresponding to the third sampling channel line is closed, randomly closing the switches corresponding to the remaining sampling channel lines of the first chip except for the third sampling channel line.

[0313] Example 22 The test method of any one of Examples 3 to 21, wherein the operation termination condition includes at least one of: the number of times a close operation is performed for the at least one chip reaches a first threshold; and the number of times a close operation is performed based on a specific placement mode reaches a second threshold for the specific placement mode.

[0314] Example 23 turning off the at least two switches; determining a current configuration mode between the first chip and the at least one battery module; performing a close operation again based on the current placement mode; 23. The testing method of any one of Examples 1 to 22, further comprising:

[0315] Example 24 Example 24. The testing method of Example 23, further comprising: performing a discharge operation before performing a close operation again based on the current configuration mode.

[0316] Example 25 In response to a determination that the second operation termination condition is not satisfied, performing a power-off operation on the at least one chip; Discharging a capacitor in the at least one chip; further comprising repeating the steps of performing a closing operation to close at least two switches of the switch matrix and testing the functionality of the at least one chip; The method of any one of Examples 1 to 24, wherein the second operation termination condition includes at least one of: the number of times the closing operation is performed on the at least one tip reaches a first threshold; and the number of times each operating condition among the at least one operating condition is performed reaches a second threshold for that operating condition.

[0317] Example 26 The method of any one of Examples 1 to 25, further comprising, in response to determining that the step of connecting the at least one chip to the at least one battery module is performed for the first time, adjusting the voltage of a single cell of a battery in the at least one battery module to a predetermined value before testing the functionality of the at least one chip.

[0318] Example 27 27. The method of any one of Examples 1 to 26, wherein testing the performance of the at least one chip includes performing a range of power supply voltage tests on the at least one chip.

[0319] Example 28 A switch matrix; a control device capable of controlling the operation of at least one switch of the switch matrix so as to perform a current-carrying operation for at least one chip according to a placement mode; the control device is configured to connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode. Test equipment for chips.

[0320] Example 29 The test apparatus of Example 28 further comprises at least one battery module, and performing a power supply operation on at least one chip according to the configuration mode includes connecting the at least one chip to the at least one battery module.

[0321] Example 30 The test apparatus of Example 29, wherein connecting the at least one chip to the at least one battery module includes performing a closing operation to close at least two switches of the switch matrix.

[0322] Example 31 The test apparatus of Example 30, wherein performing a closing operation to close at least two switches of the switch matrix includes closing the switches of the switch matrix based on at least one of a first strategy that preferentially closes two switches that form a current-carrying circuit with a maximum potential difference, and a second strategy that preferentially closes switches that enable a closed circuit to be formed between the at least one battery module.

[0323] Example 32 32. The test apparatus of any one of Examples 28 to 31, including an interface for connecting to the at least one chip.

[0324] Example 33 32. The test apparatus of any one of Examples 28 to 31, wherein the control device includes a host computer.

[0325] Example 34 32. The test apparatus of any one of Examples 28 to 31, further comprising at least one discharge unit that, when turned on, can discharge a corresponding capacitor of the at least one chip.

[0326] Example 35 A host computer capable of controlling the operation of at least one switch in a switch matrix arranged to connect at least one chip to at least one battery module, the host computer being configured to execute the method described in any one of Examples 1 to 27.

[0327] Example 36 A chip for a battery, tested by the method of any one of Examples 1 to 27.

[0328] Example 37 at least one processor; a memory communicatively connected to the at least one processor; An electronic device, wherein the memory stores instructions executable by the at least one processor, and the execution of the commands by the at least one processor enables the at least one processor to perform the method of any one of Examples 1 to 27.

[0329] Example 38 A non-transitory computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any one of Examples 1 to 27.

[0330] Finally, it should be noted that the above embodiments are intended to illustrate the technical solutions of the present application, rather than to limit the technical solutions of the present application. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art will understand that the technical solutions described in the above embodiments may be modified, or some or all of the technical features may be equivalently substituted. Such modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application, and are all within the scope of the claims and the description of the present application. In particular, as long as there is no structural contradiction, the technical features described in the embodiments may be arbitrarily combined. The present application is not limited to the specific embodiments disclosed in this specification, but includes all technical solutions within the scope of the claims. [Explanation of symbols]

[0331] 1000 vehicles 100 batteries 200 Controller 300 motor 10 boxes 11 Part 1 12 Part 2 20 battery cells 21 End cover 21a Electrode terminal 22 cases 23 Cell Assembly 23a Tab 500 Test Circuit 510 First battery module 520 Switch Matrix 530 First Chip 510-1, 510-2, 510-3...510-N Sampling Lead Wire 520-1, 520-2, 520-3...520-N Switch 530-1, 530-2, 530-3...530-N sampling channel line 600 Test Circuit 611 First battery module 612 Second battery module 620 Switch Matrix 630 First Chip 610-1, 610-n, 610-(n+1)...610-N Sampling lead wire 620-1, 620-n, 620-(n+1)...620-N switches 630-1, 630-n, 630-(n+1)...630-N sampling channel line 700 Test Circuit 710 First Battery Module 720 Switch Matrix 731 First Chip 732 Second Chip 710-1, 710-n, 710-(n+1)...710-N Sampling lead wire 720-1, 720-n, 720-(n+1)...720-N switches 730-1, 730-n, 730-(n+1)...730-N sampling channel line 800 Test Circuit 810 1st battery module 820 Switch Matrix 831 First Chip 832 Second Chip 810-1, 810-n, 810-(n+1)...810-N sampling lead wire 820-1, 820-n, 820-(n+1)...820-N switches 830-1, 830-n, 830-(n+1)...830-N sampling channel lines 900 Test Circuit 910 1st battery module 920 Switch Matrix 930 First Chip 940 Upper Computer 910-1, 910-2, 910-3...910-N Sampling Lead Wire 920-1, 920-2, 920-3...920-N Switch 930-1, 930-2, 930-3...930-N sampling channel line 1000 Electronic Devices 1100 Test Circuit 1110 at least one battery module 1120 Switch Matrix 1130 at least one chip 1140 Upper Computer 1150 Discharge Unit 1131, 1132 chips 1111, 1112 battery modules 1200 Test Circuit 1210 At least one battery module 1220 Switch Matrix 1230 at least one chip 1240 Upper Computer 1250 Discharge Unit 1231 chips 1211, 1212 battery modules 1300 Test Circuit 1210 At least one battery module 1320 Switch Matrix 1330 at least one chip 1340 Upper Computer 1350 Discharge Unit 1331, 1332 chips 1311 Battery Module 1400 Test Circuit 1210 At least one battery module 1420 Switch Matrix 1430 at least one chip 1440 Upper Computer 1450 Discharge Unit 1431, 1432 chips 1411 Battery Module

Claims

1. determining a configuration mode of a test circuit, the test circuit having at least one chip and at least one battery module, the at least one chip being connectable to the at least one battery module according to the configuration mode; connecting the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode; A test method for a chip, including:

2. The method of claim 1 further comprising testing the performance of the at least one chip.

3. determining whether an end-of-operation condition has been met prior to testing the performance of the at least one chip; 3. The method of claim 2, further comprising: in response to determining that an end-of-operation condition has been met, testing the performance of the at least one chip.

4. the test circuit further includes a switch matrix interposed between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode; 4. The method of claim 1, wherein connecting the at least one chip to the at least one battery module comprises performing a closing operation to close at least two switches of the switch matrix.

5. 5. The method of claim 4, wherein performing a closing operation to close at least two switches of the switch matrix includes closing switches of the switch matrix based on at least one of a first strategy of preferentially closing two switches that form a current-carrying circuit with a maximum potential difference and a second strategy of preferentially closing switches that enable a closed circuit to be formed between the at least one battery module.

6. 5. The method of claim 4, wherein the at least one chip includes a first chip, the at least one battery module includes a first battery module, and determining a configuration mode of the test circuit includes determining that the test circuit is in a first configuration mode, the first configuration mode indicating that the first chip is configured to be connected to a corresponding switch of the switch matrix such that, when the corresponding switch is turned on, sampling channel lines of the first chip are connectable to corresponding sampling lead lines of the first battery module.

7. performing the closing operation in response to determining that the test circuit is in a first configuration mode; 7. The method of claim 6, further comprising the step of closing a pair of switches corresponding to a pair of sampling channel lines, except for a pair of sampling channel lines associated with a maximum battery potential difference in the first chip, when none of the switches corresponding to the remaining pair of sampling channel lines are closed.

8. performing the closing operation in response to determining that the test circuit is in a first configuration mode; 8. The method of claim 7, further comprising the step of randomly closing switches corresponding to the remaining sampling channel lines in the first chip after the pair of switches corresponding to the pair of sampling channel lines are closed.

9. 9. The method of claim 6, wherein, in response to determining that the test circuit is in a first placement mode, performing the closing operation comprises randomly closing switches corresponding to sampling channel lines of the first chip.

10. 5. The method of claim 4, wherein the at least one chip includes a first chip, the at least one battery module includes at least two battery modules connected in series, and determining a configuration mode of the test circuit includes determining that the test circuit is in a second configuration mode, the second configuration mode indicating that the first chip is configured to be connected to a corresponding switch of the switch matrix such that, when the corresponding switch is turned on, sampling channel lines of the first chip are connectable to corresponding sampling lead lines of the at least two battery modules, respectively.

11. performing the closing operation in response to determining that the test circuit is in the second configuration mode; If none of the switches corresponding to the sampling lead wires of the positive battery module among the at least two battery modules are closed, closing the switches corresponding to the sampling lead wires of the remaining battery modules among the at least two battery modules excluding the positive battery module; and closing the switch corresponding to the sampling lead associated with the highest battery potential of the positive battery module a first time lag after the switches corresponding to the sampling leads of the remaining battery modules are closed.

12. The step of performing the closing operation includes:

12. The method of claim 11, further comprising the step of randomly closing switches corresponding to the remaining sampling leads of the positive battery modules, excluding the sampling lead associated with the highest battery potential, after the switch corresponding to the sampling lead associated with the highest battery potential is closed.

13. performing the closing operation in response to determining that the test circuit is in the second configuration mode; If none of the switches corresponding to the sampling lead wires of the negative battery module among the at least two battery modules is closed, closing the switches corresponding to the sampling lead wires of the remaining battery modules among the at least two battery modules excluding the negative battery module; and closing the switch corresponding to the sampling lead of the negative battery module associated with the lowest battery potential a second time lag after the switches corresponding to the sampling leads of the remaining battery modules are closed.

14. The step of performing the closing operation includes:

14. The method of claim 13, further comprising the step of randomly closing switches corresponding to the remaining sampling leads of the negative battery modules, excluding the sampling lead associated with the lowest battery potential, after the switch corresponding to the sampling lead associated with the lowest battery potential is closed.

15. 5. The method of claim 4, wherein the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and determining a configuration mode of the test circuit includes determining that the test circuit is in a third configuration mode, the third configuration mode indicating that the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix such that when the corresponding switches are turned on, the first chip and the second chip are connectable to corresponding sampling leads of the first battery module.

16. a first sampling channel line of the first chip and a second sampling channel line of the second chip are connectable to adjacent first sampling lead lines and second sampling lead lines of the first battery module, and a third sampling channel line of the first chip and a fourth sampling channel line of the second chip are connectable to third sampling lead lines and fourth sampling lead lines of the first battery module associated with a maximum battery potential difference; and performing the closing operation in response to determining that the test circuit is in a third configuration mode: If none of the switches corresponding to the remaining sampling channel lines of the first chip and the second chip other than the first sampling channel line and the second sampling channel line are closed, closing the switches corresponding to the first sampling channel line and the second sampling channel line; and closing the switches corresponding to the third sampling channel line and the fourth sampling channel line a third time lag after the switches corresponding to the first sampling channel line and the second sampling channel line are closed.

17. The step of performing the closing operation includes:

17. The method of claim 16, further comprising: after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, randomly closing switches of the first chip and the second chip corresponding to the remaining sampling channel lines excluding the first sampling channel line, the second sampling channel line, the third sampling channel line, and the fourth sampling channel line.

18. 18. The method of claim 15, wherein, in response to determining that the test circuit is in a third configuration mode, performing the closing operation comprises randomly closing switches corresponding to sampling channel lines of the first chip and the second chip.

19. 16. The method of claim 15, wherein a first sampling channel line of the first chip and a second sampling channel line of the second chip are connectable to adjacent first and second sampling lead lines of the first battery module, a third sampling channel line of the first chip and a fourth sampling channel line of the second chip are connectable to third and fourth sampling lead lines of the first battery module associated with a maximum battery potential difference, and the third configuration mode further indicates that the first sampling channel line and the second sampling channel line are electrically connected.

20. performing the closing operation in response to determining that the test circuit is in a third configuration mode; If none of the switches corresponding to the sampling channel lines of the first chip are closed, closing the switches corresponding to the sampling channel lines of the second chip; and closing a switch corresponding to the third sampling channel line a third time lag after a switch corresponding to the sampling channel line of the second chip is closed.

21. The step of performing the closing operation includes:

21. The method of claim 20, further comprising: after the switch corresponding to the third sampling channel line is closed, randomly closing switches corresponding to the remaining sampling channel lines of the first chip except for the third sampling channel line.

22. 22. The test method according to claim 3, wherein the operation termination condition includes at least one of: the number of times a close operation is performed on the at least one chip reaches a first threshold; and the number of times a close operation is performed based on a specific placement mode reaches a second threshold for the specific placement mode.

23. turning off the at least two switches; determining a current configuration mode between the first chip and the at least one battery module; performing a close operation again based on the current placement mode; 23. The testing method of claim 1, further comprising:

24. 24. The testing method of claim 23, further comprising the step of performing a discharge operation before the step of performing a close operation again based on the current deployment mode.

25. In response to a determination that the second operation termination condition is not satisfied, performing a power-off operation on the at least one chip; Discharging a capacitor in the at least one chip; further comprising repeating the steps of performing a closing operation to close at least two switches of the switch matrix and testing the functionality of the at least one chip; 25. The method of claim 1, wherein the second operation termination condition includes at least one of: the number of times a closing operation is performed on the at least one tip reaches a first threshold; and the number of times each operating condition among the at least one operating condition is performed reaches a second threshold for that operating condition.

26. 26. The method of claim 1, further comprising the step of adjusting a voltage of a single cell of a battery in the at least one battery module to a predetermined value before testing the functionality of the at least one chip in response to determining that the step of connecting the at least one chip to the at least one battery module is performed for the first time.

27. 27. The method of claim 1, wherein testing the performance of the at least one chip comprises performing a range of power supply voltage tests on the at least one chip.

28. A switch matrix; a control device capable of controlling the operation of at least one switch of the switch matrix so as to perform a current-carrying operation for at least one chip according to a placement mode; the control device is configured to connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode. Test equipment for chips.

29. 30. The test apparatus of claim 28, further comprising at least one battery module, wherein performing a power-on operation on the at least one chip according to the configuration mode includes connecting the at least one chip to the at least one battery module.

30. 30. The test apparatus of claim 29, wherein connecting the at least one chip to the at least one battery module includes performing a closing operation to close at least two switches of the switch matrix.

31. 31. The test apparatus of claim 30, wherein performing a closing operation to close at least two switches of the switch matrix includes closing the switches of the switch matrix based on at least one of a first strategy of preferentially closing two switches that form a current-carrying circuit with a maximum potential difference and a second strategy of preferentially closing switches that enable a closed circuit to be formed between the at least one battery module.

32. 32. A test apparatus according to any one of claims 28 to 31, comprising an interface for connecting to said at least one chip.

33. 32. The test apparatus of claim 28, wherein the control device includes a host computer.

34. 32. The test apparatus of any one of claims 28 to 31, further comprising at least one discharge unit, which when turned on, is capable of discharging a corresponding capacitor of said at least one chip.

35. A host computer capable of controlling the operation of at least one switch in a switch matrix arranged to connect at least one chip to at least one battery module, the host computer being arranged to perform the method of any one of claims 1 to 27.

36. A chip for a battery tested by the method of any one of claims 1 to 27.

37. at least one processor; a memory communicatively connected to the at least one processor; 28. An electronic device, wherein the memory stores instructions executable by the at least one processor, the commands being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 27.

38. A non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to carry out the method of any one of claims 1 to 27.

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