P-type back contact battery, its preparation method and solar module

Abstract

This document discloses a P-type back-contact battery, a preparation method thereof, and a solar module. The preparation method for the P-type back-contact battery includes preparing a process wafer for the P-type back-contact battery, forming a gettering structure on the first and / or second surface of the P-type back-contact battery, the gettering structure including a second tunneling layer, a second polysilicon layer, and a second phosphosilicate glass layer, respectively, etching the process wafer after the gettering structure is formed to remove the gettering structure and the first phosphosilicate glass layer on the second surface, and forming passivation layers on the first and second surfaces of the process wafer. The technical solution of this application is to form a gettering structure on the first and second surfaces of the P-type back-contact battery process wafer, thereby absorbing impurities on the first and second surfaces of the process wafer, reducing recombination centers formed by impurities, improving carrier mobility, and improving the conversion efficiency of the P-type back-contact battery.

Description

[Technical Field]

[0001] TECHNICAL FIELD The present application relates to the technical field of solar cells, such as P-type back contact cells, their preparation methods and solar modules. [Background technology]

[0002] Currently, as fossil energy is gradually being phased out, solar cells are becoming increasingly popular as a new energy alternative. A solar cell is a device that converts solar light energy into electrical energy. Solar cells use the photovoltaic principle to generate carriers, which are then guided through electrodes to convert solar energy into electrical energy for use.

[0003] The most significant feature of P-type back contact solar cells is that the emitter and metal contact are both on the back surface of the cell, eliminating the shielding effect of metal electrodes on the front surface, resulting in a higher short circuit current (Isc). The back surface can also utilize wide metal gate lines to reduce series resistance (Rs) and increase fill factor (FF). These front-shielded cells not only have higher conversion efficiency, but also a more aesthetically pleasing appearance, making all-back electrode modules easier to install. Back contact cells are currently one of the technological trends driving high-efficiency crystalline silicon cells.

[0004] However, the laser-created window region in the P-type back contact cell has not undergone the annealing process in the PERC (Passivated Emitter Rear Cell) cell, so there are still a large number of recombination centers. Therefore, how to reduce the recombination centers and improve the conversion efficiency of the battery cell is currently an urgent issue to be solved. Summary of the Invention [Problem to be solved by the invention]

[0005] The following is a general summary of the subject matter described in detail herein. This summary does not limit the scope of the claims.

[0006] The present application provides a P-type back contact cell, a preparation method thereof, and a solar module for reducing recombination centers formed by impurities, improving carrier transport efficiency, and further improving the conversion efficiency of the P-type back contact cell. [Means for solving the problem]

[0007] In aspect 1, the present embodiment comprises: A process wafer for a P-type back contact cell is prepared, the process wafer comprising a P-type silicon substrate, the P-type silicon substrate having a first surface and a second surface opposite to each other, the second surface being provided with a first tunneling layer, a first polysilicon layer, and a first phosphosilicate glass layer stacked in sequence, and a groove penetrating the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer; forming a gettering structure including a second tunneling layer, a second polysilicon layer, and a second phosphosilicate glass layer stacked on the first surface side and / or the second surface side; Etching the process wafer after forming the gettering structure to remove the gettering structure and the first phosphosilicate glass layer on the second surface side; forming a passivation layer on each of the first and second surface sides of the process wafer; A method for preparing a P-type back contact battery is provided.

[0008] Preferably, preparing a process wafer for a P-type back contact cell comprises: providing a P-type silicon substrate; forming the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer, which are sequentially stacked on a first surface and a second surface of the P-type silicon substrate; forming an opening in the first phosphosilicate glass layer on the second surface side to expose a portion of the first polysilicon layer on the second surface side; forming an opening in the first phosphosilicate glass layer on the second surface side, and then removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate to expose the first polysilicon layer on the first surface side; Etching the first surface and the second surface side of the P-type silicon substrate, removing the first polysilicon layer and the first tunneling layer located in the opening, forming the groove in the opening, and removing the first tunneling layer and the first polysilicon layer located on the first surface side.

[0009] Preferably, preparing a process wafer for a P-type back contact cell comprises: providing a P-type silicon substrate; forming a first tunneling layer, a first polysilicon layer, and a first phosphosilicate glass layer sequentially stacked on a first surface and a second surface of the P-type silicon substrate, respectively; removing a first phosphosilicate glass layer on a first surface side of the P-type silicon substrate to expose the first polysilicon layer on the first surface side; removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate, and then forming an opening in the first phosphosilicate glass layer on the second surface side to expose a portion of the first polysilicon layer on the second surface side; Etching the first surface and the second surface side of the P-type silicon substrate, removing the first polysilicon layer and the first tunneling layer located in the opening, forming the groove in the opening, and removing the first tunneling layer and the first polysilicon layer located on the first surface side.

[0010] Preferably, etching the first surface and the second surface of the P-type silicon substrate includes: The method includes using an alkaline etching solution to etch the openings on the first surface side and the second surface side of the P-type silicon substrate, removing the first polysilicon layer and the first tunneling layer located in the openings, forming the grooves in the openings, and removing the first tunneling layer and the first polysilicon layer located on the first surface side.

[0011] Preferably, forming an opening in the first phosphosilicate glass layer on the second surface side and exposing a portion of the first polysilicon layer on the second surface side includes: The method includes forming the opening in the first phosphosilicate glass layer on the second surface side of the P-type silicon substrate using a laser.

[0012] Preferably, forming a gettering structure on the first surface side and / or the second surface side is The method includes sequentially preparing the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer on the first surface side and the second surface side by employing any one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and chemical vapor deposition.

[0013] Preferably, the step of etching the process wafer after forming the gettering structure to remove the gettering structure and the first phosphosilicate glass layer on the second surface side includes: Etching the second phosphosilicate glass layer on the second surface side, the second polysilicon layer on the second surface side, and the second tunneling layer on the second surface side to form a groove having a polished surface on the second surface side; Etching the second phosphosilicate glass layer and the second polysilicon layer on the first surface side to remove the second polysilicon layer; Etching the second tunneling layer and the second tunneling layer on the first surface side to remove the first phosphosilicate glass layer and the second tunneling layer on the first surface side.

[0014] Preferably, forming a passivation layer on each of the first surface side and the second surface side of the process wafer includes: Preparing an aluminum oxide layer on a first surface side and a second surface side of the process wafer; and providing a silicon nitride layer on the first and second surface sides of the aluminum oxide layer facing away from the P-type silicon substrate.

[0015] In aspect 2, the present embodiment comprises: Produced by the method for producing a back-contact battery according to embodiment 1. Provides P-type back contact batteries.

[0016] In aspect 3, the present embodiment comprises: comprising the P-type back contact battery of embodiment 2; The Company provides solar modules. [Effects of the Invention]

[0017] In a technical solution according to an embodiment of the present application, gettering structures are formed on the first and second surface sides of a process wafer for a P-type back contact battery to absorb impurities on the first and second surface sides of the process wafer, reduce recombination centers formed by the impurities, improve carrier mobility, and further improve the conversion efficiency of the P-type back contact battery. After the gettering structures have completed absorbing the impurities on the first and second surface sides, the process wafer on which the gettering structures are formed is etched to remove the gettering structures and the first phosphosilicate glass layer on the second surface side. Then, passivation layers are formed on the first and second surface sides of the process wafer, respectively, to protect the P-type back contact battery, prevent external contaminants from entering the P-type back contact battery, and further improve the photoelectric conversion efficiency of the P-type back contact battery.

[0018] Other aspects may be understood upon reading and understanding the drawings and detailed description. [Brief explanation of the drawings]

[0019] The drawings are intended to provide a further understanding of the technical solution of the present invention, constitute a part of the specification, and are used to interpret the technical solution of the present invention together with the examples of the present application, but are not intended to limit the technical solution of the present invention.

[0020] [Figure 1] 1 is a flowchart of a method for preparing a P-type back contact battery according to an embodiment of the present application. [Figure 2] 1 is a structural schematic diagram of the process for preparing a P-type back contact battery according to an embodiment of the present application. FIG. [Figure 3] 1 is a flowchart of a method for preparing a process wafer of a P-type back contact cell according to an embodiment of the present application. [Figure 4] FIG. 2 is a structural schematic diagram of the process of preparing a process wafer of a P-type back contact battery according to an embodiment of the present application. [Figure 5] 1 is a flowchart of another method for preparing a process wafer of a P-type back contact cell according to an embodiment of the present application. [Figure 6] FIG. 2 is a structural schematic diagram of the process of preparing a process wafer of another P-type back contact battery according to an embodiment of the present application. [Figure 7] 2 is a flowchart of another method for preparing a P-type back contact battery according to an embodiment of the present application. [Figure 8] FIG. 2 is a structural schematic diagram of the process for preparing another P-type back contact battery according to an embodiment of the present application. [Figure 9] 1 is a flowchart of a method for preparing a P-type back contact battery according to another embodiment of the present application. [Figure 10] FIG. 2 is a structural schematic diagram of the process for preparing a further P-type back contact battery according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present application will be further described below with reference to the drawings and examples. It is understood that the specific examples described here are merely for the purpose of interpreting the present application and are not intended to limit the present application. For the sake of convenience, the drawings show only parts relevant to the present disclosure, rather than all of the structures.

[0022] The present embodiment provides a method for preparing a P-type back contact battery, which is applied to the preparation of the P-type back contact battery according to the embodiment. FIG. 1 is a flowchart of the method for preparing a P-type back contact battery according to the embodiment. FIG. 2 is a structural schematic diagram of the process for preparing the P-type back contact battery according to the embodiment. As shown in FIG. 1, the method for preparing a P-type back contact battery includes the following steps:

[0023] In S101, a process wafer for a P-type back contact cell is prepared.

[0024] Here, the process wafer includes a P-type silicon substrate, the P-type silicon substrate having opposing first and second surfaces, and on the second surface side, a first tunneling layer, a first polysilicon layer, and a first phosphosilicate glass layer are sequentially stacked, and a groove is provided that penetrates the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer.

[0025] Specifically, the P-type silicon substrate may be a wafer or silicon wafer doped with a trivalent element such as boron or gallium, and the Si semiconductor is a tetravalent element, which forms electron-hole pairs with the trivalent element, and then generates a large amount of holes in the wafer or silicon wafer, forming a P-type silicon substrate.

[0026] 2, the first tunneling layer 21 and the first polysilicon layer 22 on the second surface side can be formed by a low-pressure chemical vapor deposition process. After the first tunneling layer 21 and the first polysilicon layer 22 are formed, the P-type silicon substrate on which the first tunneling layer 21 and the first polysilicon layer 22 are formed is placed in a low-pressure diffusion furnace, and a phosphorus source is deposited on the second surface side to form a first phosphosilicate glass layer 23. Grooves 31 are formed at positions corresponding to the fingers on the second surface side using a process such as laser or etching, and the grooves 31 penetrate the first tunneling layer 21, the first polysilicon layer 22, and the first phosphosilicate glass layer 23.

[0027] The materials and thicknesses of the first tunneling layer 21, first polysilicon layer 22, and first phosphosilicate glass layer 23 can be set according to actual needs and are not specifically limited herein. For example, the material of the first tunneling layer 21 may include, but is not limited to, one or more of materials such as silica, aluminum oxide, titanium oxide, chromium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride. The thickness of the first tunneling layer 21 may be 1.1 nm to 1.8 nm, the thickness of the first polysilicon layer 22 may be 70 nm to 180 nm, and the first phosphosilicate glass (phosphosilicate glass) layer 23 may include elements such as silica and phosphorus oxide, where the deposition concentration of the phosphorus source is 3e. 20 ~4e 22 / cm 3 may be.

[0028] In S102, a gettering structure is formed on the first surface side and / or the second surface side.

[0029] Here, the gettering structure includes a second tunneling layer, a second polysilicon layer, and a second phosphosilicate glass layer, which are stacked one on top of the other.

[0030] It can be understood that forming a gettering structure on the first surface side and / or the second surface side may mean forming a gettering structure only on the first surface side, forming a gettering structure only on the second surface side, or forming a gettering structure on both the first surface side and the second surface side.For ease of explanation, the following description will be given using an example in which a gettering structure is formed on both the first surface side and the second surface side.

[0031] 2, the gettering structure formed on the first surface side includes a second tunneling layer 111, a second polysilicon layer 112, and a second phosphosilicate glass layer 113, which are stacked together, and the gettering structure formed on the second surface side includes a second tunneling layer 221, a second polysilicon layer 222, and a second phosphosilicate glass layer 223, which are stacked together. After the second tunneling layer 111, the second polysilicon layer 112, the second tunneling layer 221, and the second polysilicon layer 222 are respectively formed on the first surface side and the second surface side of the process wafer using a low-pressure chemical vapor deposition preparation method, the process wafer is then placed in a low-pressure diffusion furnace, and phosphorus diffusion of the process wafer is completed in the low-pressure diffusion furnace. During the phosphorus diffusion, the second phosphosilicate glass layer 113 is formed on the first surface side and the second phosphosilicate glass layer 223 is formed on the second surface side.

[0032] In one preferred embodiment, the method for forming the gettering structure on the first surface side and the second surface side may include employing any one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and chemical vapor deposition to sequentially prepare a first tunneling layer, a first polysilicon layer, and a first phosphosilicate glass layer on the first surface side and the second surface side.

[0033] Specifically, metal impurities such as Fe, Na, Cu, and Au, and non-metallic impurities such as O, C, and N may be present on the first and second surface sides of the P-type silicon substrate process wafer. The presence of these impurities introduces deep level defects into the silicon substrate, which trap majority and minority carriers and become carrier recombination centers, reducing the diffusion length of minority carriers and reducing the efficiency of the P-type back contact battery. In this case, by forming gettering structures on the first surface side and the second surface side, the material of the second tunneling layers 111 and 221 in the gettering structures may include, but is not limited to, one of materials such as silica, aluminum oxide, titanium oxide, chromium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride. Gettering is performed on the first surface side and the second surface side by utilizing the difference in material between the first tunneling layers 111 and 221 and the P-type silicon substrate, i.e., the solubility of impurities in the second tunneling layers 111 and 221 is greater than the solubility in the P-type silicon substrate. For example, the material of the second tunneling layers 111 and 221 is aluminum oxide, and the solubility of metal impurities in aluminum oxide is greater than the solubility in the P-type silicon substrate. When the second phosphosilicate glass layers 113 and 223 in the gettering structure are formed, the phosphorus element in the second phosphosilicate glass layers 113 and 223 diffuses into the second polysilicon layers 112 and 222. As the phosphorus concentration in the second polysilicon layers 112 and 222 increases, the ability to accommodate impurities also increases, increasing the solubility of the impurities in the polysilicon layers and further reducing the impurity concentration in the P-type silicon substrate. Thus, by forming the gettering structures on the first and second sides, gettering is achieved on the first and second surface sides of the P-type silicon substrate, reducing the recombination centers formed by impurities, improving carrier mobility, and further improving the conversion efficiency of the P-type back-contact battery.

[0034] The materials of the second tunneling layer, second polysilicon layer, and second phosphosilicate glass layer may be the same or different from those of the first tunneling layer, first polysilicon layer, and first phosphosilicate glass layer. The thicknesses of the second tunneling layer, second polysilicon layer, and second phosphosilicate glass layer can be set according to actual needs and are not specifically limited herein. For example, the thicknesses of the second tunneling layers 111 and 221 may be 1 nm to 1.5 nm, the thicknesses of the second polysilicon layers 112 and 222 may be 60 nm to 120 nm, and the second phosphosilicate glass layers 113 and 223 may contain elements such as silica and phosphorus oxide, where the deposition concentration of the phosphorus source is 1 e 20 ~2e 22 / cm 3 may be.

[0035] In S103, the process wafer after the gettering structure is formed is etched to remove the gettering structure and the first phosphosilicate glass layer on the second surface side.

[0036] Specifically, the process wafer after the gettering structure is formed is placed in a chain etching machine stand, and the process wafer is etched using an alkaline etching solution or an acidic etching solution, etc., to remove the gettering structures on the first surface side and the second surface side, and the first phosphosilicate glass layer on the second surface side.

[0037] In S104, a passivation layer is formed on each of the first and second surfaces of the process wafer.

[0038] Specifically, the passivation layer can cover the first surface side and the second surface side, respectively, and can prevent airborne contaminants from corroding the interior of the P-type back contact cell, protect the P-type back contact cell, and also provide hydrogen passivation, reduce recombination centers at the silicon wafer interface, and improve the photoelectric conversion efficiency of the P-type back contact cell.

[0039] The material and thickness of the passivation layer can be determined according to actual needs, and are not specifically limited herein. For example, the material of the passivation layer may include, but is not limited to, aluminum oxide, silicon carbide, phosphorus oxide, and other passivation materials.

[0040] A P-type back-contact battery is prepared using the above-described method according to the embodiments of the present application, and gettering structures are formed on the first and second surface sides of the process wafer of the P-type back-contact battery, which absorbs impurities on the first and second surface sides of the process wafer, reduces the recombination centers formed by impurities, improves the carrier mobility, and further improves the conversion efficiency of the P-type back-contact battery. After forming gettering structures on the first and second surface sides of a process wafer for a P-type back contact battery, the process wafer after the gettering structures are formed is etched to remove the gettering structures and the first phosphosilicate glass layer on the second surface side, thereby forming a polished surface in the groove on the second surface side. The polished surface can totally reflect light of different wavelengths, and at least a portion of the light that reaches the second surface side through the smooth polished surface is reflected back into the P-type silicon substrate, realizing repeated use of light, increasing the utilization rate of light energy, and further improving the photoelectric conversion efficiency of the back contact. In addition, passivation layers are formed on the first and second surface sides of the process wafer, respectively, to protect the P-type back contact battery and prevent external contaminants from entering the P-type back contact battery, as well as provide hydrogen passivation, reducing recombination centers at the silicon wafer interface, and further improving the photoelectric conversion efficiency of the P-type back contact battery.

[0041] In a preferred embodiment, FIG. 3 is a flowchart of a method for preparing a process wafer for a P-type back contact battery according to an embodiment of the present application, and FIG. 4 is a structural schematic diagram of the process for preparing a process wafer for a P-type back contact battery according to an embodiment of the present application. As shown in FIG. 3 , preparing a process wafer for a P-type back contact battery specifically includes the following steps:

[0042] In S111, a P-type silicon substrate is provided.

[0043] 4, a P-type silicon substrate 4 has opposing first and second surfaces 10 and 20, which are flat so that other structures of all layers can be subsequently formed on the first and second surfaces 10 and 20. Here, the first surface 10 may be the surface of the P-type back contact cell, i.e., the surface that receives the light source, and the second surface 20 may be the back surface of the P-type back contact cell, i.e., the surface that faces away from the light source.

[0044] In S112, a first tunneling layer, a first polysilicon layer, and a first phosphosilicate glass layer are sequentially formed on the first and second surface sides of the P-type silicon substrate, respectively.

[0045] Specifically, referring to FIG. 4, a first tunneling layer 11, a first polysilicon layer 12, and a first phosphosilicate glass layer 13 are sequentially stacked on a first surface side 10 of a P-type silicon substrate 4, and a first tunneling layer 21, a first polysilicon layer 22, and a first phosphosilicate glass layer 23 are sequentially stacked on a second surface side 20. The specific preparation process may be as follows: A low-pressure chemical vapor deposition process is used to form a first tunneling layer 11, a first polysilicon layer 12, a first tunneling layer 21, and a first polysilicon layer 22 on the first surface 10 and the second surface 20 of a P-type silicon substrate 4, respectively. The processed wafer is then placed in a low-pressure diffusion furnace to form first phosphosilicate glass layers 13 and 23 on the first surface 10 and the second surface, respectively, and phosphorus diffusion is completed in the low-pressure diffusion furnace. That is, the phosphorus in the first phosphosilicate glass layers 13 and 23 can diffuse into the first polysilicon layers 12 and 22 to form high and low potentials.

[0046] In S113, an opening is formed in the first phosphosilicate glass layer on the second surface side to expose a portion of the first polysilicon layer on the second surface side.

[0047] 4, the first phosphosilicate glass layer 23 on the second surface 20 side of the P-type silicon substrate 4 includes an opening 30, which can expose the first polysilicon layer 22 on the second surface 20 side. The opening 30 can be obtained by physical polishing, ion beam etching, laser, or other methods, and the embodiments of the present application are not specifically limited thereto.

[0048] In one preferred embodiment, forming an opening in the first phosphosilicate glass layer on the second surface side and exposing a portion of the first polysilicon layer on the second surface side may include using a laser to form an opening in the first phosphosilicate glass layer on the second surface side of the P-type silicon substrate, where the non-contact nature of laser processing minimizes the impact on the material, allows for precise control of the size of the opening, and improves processing efficiency and mass.

[0049] In S114, after forming an opening in the first phosphosilicate glass layer on the second surface side, the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate is removed to expose the first polysilicon layer on the first surface side.

[0050] Specifically, referring to FIG. 4 , after forming the openings in the first phosphosilicate glass layer 23 on the second surface 20 side, the first phosphosilicate glass layer 13 and the first polysilicon layer 12 are made of different materials, and therefore require different removal methods or processes. Therefore, before removing the first polysilicon layer 12, the first phosphosilicate glass layer 13 must be removed first. The removal method may be a method such as laser etching, and the embodiments of the present application are not limited to this. For example, the process wafer may be placed in a chain etching machine and the first phosphosilicate glass layer 13 on the first surface 10 side may be etched using a hydrogen fluoride solution. The etching time depends on the concentration of the hydrogen fluoride solution and the thickness of the first phosphosilicate glass layer, and is not limited here. The concentration of the hydrogen fluoride solution may be 75% to 85%, and the etching time may be 30 to 60 seconds.

[0051] In S115, the first surface and the second surface of the P-type silicon substrate are etched to remove the first polysilicon layer and the first tunneling layer located in the opening, form a groove in the opening, and remove the first tunneling layer and the first polysilicon layer located on the first surface side.

[0052] 4 , after removing the first phosphosilicate glass layer 13 on the first surface 10 side of the P-type silicon substrate 4, the first polysilicon layer 22 and the first tunneling layer 21 located in the opening 30 are removed using a liquid agent or plasma etching method, forming a groove 31 in the opening 30, and the first tunneling layer 11 and the first polysilicon layer 12 located on the first surface 10 side are removed, thereby forming a pyramidal textured surface on the first surface 10 side of the P-type silicon substrate, improving light utilization and the photoelectric conversion efficiency of the P-type back contact cell. At the same time, a pyramidal textured surface is also formed in the groove 31 formed in the opening on the second surface 20 side of the P-type silicon substrate.

[0053] Preferably, the method for etching the first and second surfaces of the P-type silicon substrate includes using an alkaline etchant to etch the openings on the first and second surfaces of the P-type silicon substrate, removing the first polysilicon layer and the first tunneling layer located in the openings, forming grooves in the openings, and removing the first tunneling layer and the first polysilicon layer located on the first surface, where the alkaline etchant may be a sodium hydroxide solution or the like.

[0054] Specifically, referring to FIG. 4, an alkaline etching solution is used to etch the first polysilicon layer 12 and the first tunneling layer 11 on the first surface 10 side, and the first polysilicon layer 22 and the first tunneling layer 21 located in the opening 30 on the second surface 20 side. The etching time is related to the concentration of the alkaline etching solution, the thickness of the first polysilicon layer and the first tunneling layer, and the temperature during etching, and is not specifically limited here. For example, when the alkaline etching solution is a sodium hydroxide solution, the concentration of sodium hydroxide may be 1.3% to 5%, the temperature during etching may be 74°C to 82°C, and the etching time may be 350 seconds to 600 seconds.

[0055] The above-described method for preparing a process wafer for a P-type back contact battery is merely an exemplary method of the present application, and the method for preparing a process wafer for a P-type back contact battery in the embodiments of the present application is not limited thereto. For example, it can be understood that after forming the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer, the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate can be removed, and then an opening can be formed in the first phosphosilicate glass layer on the second surface side.

[0056] Preferably, FIG. 5 is a flowchart of another method for preparing a P-type back contact battery process wafer according to an embodiment of the present application, and FIG. 6 is a structural schematic diagram of another process for preparing a P-type back contact battery process wafer according to an embodiment of the present application. As shown in FIG. 5 , preparing a P-type back contact battery process wafer may further include the following steps:

[0057] In S111', a P-type silicon substrate is provided.

[0058] In S112', a first tunneling layer, a first polysilicon layer, and a first phosphosilicate glass layer are sequentially formed on the first and second surface sides of the P-type silicon substrate, respectively.

[0059] In S113', the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate is removed to expose the first polysilicon layer on the first surface side.

[0060] Specifically, referring to FIG. 6, the first phosphosilicate glass layer 13 and the first polysilicon layer 12 are made of different materials, and therefore the removal methods or processes are also different. Therefore, before removing the first polysilicon layer 12, the first phosphosilicate glass layer 13 must be removed first. The removal method may be a method such as laser etching, and the embodiments of the present application are not specifically limited thereto. For example, the process wafer may be placed on a chain etching machine stand, and the first phosphosilicate glass layer 13 on the first surface 10 side may be etched using a hydrogen fluoride solution. The concentration of the hydrogen fluoride solution may be 75% to 85%, and the etching time may be 30 to 60 seconds.

[0061] In S114', after removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate, an opening is formed in the first phosphosilicate glass layer on the second surface side to expose a portion of the first polysilicon layer on the second surface side.

[0062] Specifically, referring to FIG. 6, the opening 30 can be obtained by methods such as physical polishing, ion beam etching, or laser, and the embodiments of the present application are not specifically limited thereto.

[0063] Preferably, forming an opening in the first phosphosilicate glass layer on the second surface side and exposing a portion of the first polysilicon layer on the second surface side can be achieved by using a laser to form an opening in the first phosphosilicate glass layer on the second surface side of the P-type silicon substrate, where the non-contact nature of laser processing minimizes the impact on the material, allows for precise control of the opening size, and improves processing efficiency and mass.

[0064] In S115', the first surface and the second surface side of the P-type silicon substrate are etched to remove the first polysilicon layer and the first tunneling layer located in the opening, form a groove in the opening, and remove the first tunneling layer and the first polysilicon layer located on the first surface side.

[0065] The technical solution according to the embodiment of the present application comprises sequentially stacking a first tunneling layer, a first polysilicon layer, and a first phosphosilicate glass layer on the first and second surfaces of a P-type silicon substrate, respectively. The first phosphosilicate glass layer on the first surface of the P-type silicon substrate may be removed before forming an opening in the first phosphosilicate glass layer on the second surface. Alternatively, the opening may be formed in the first phosphosilicate glass layer on the second surface and then the first phosphosilicate glass layer on the first surface of the P-type silicon substrate may be removed. The first and second surfaces of the P-type silicon substrate are then etched to remove the first polysilicon layer and first tunneling layer located in the opening, forming a groove in the opening. The first tunneling layer and first polysilicon layer located on the first surface are also removed, forming a pyramidal textured surface on the first surface, thereby enhancing light utilization and improving the photoelectric conversion efficiency of the P-type back contact battery.

[0066] In one preferred embodiment, FIG. 7 is a flowchart of another method for preparing a P-type back contact battery according to an embodiment of the present application, and FIG. 8 is a structural schematic diagram of the process for preparing another P-type back contact battery according to an embodiment of the present application. As shown in FIG. 7 , etching the process wafer after forming the gettering structure and removing the gettering structure and the first phosphosilicate glass layer on the second surface side specifically includes the following steps:

[0067] In S131, the second phosphosilicate glass layer on the second surface side is etched to remove the second phosphosilicate glass layer on the second surface side.

[0068] 8, the second phosphosilicate glass layers 113 and 223 and the second polysilicon layers 112 and 222 are made of different materials, so the second phosphosilicate glass layers 113 and 223 and the second polysilicon layers 112 and 222 cannot be removed simultaneously. First, the process wafer is etched using an acidic etchant to remove the second phosphosilicate glass layer 223 on the second surface side. Here, the acidic etchant may contain a hydrogen fluoride solution, the hydrogen fluoride concentration may be in the range of 75% to 85%, and the reaction time may be 30 to 60 seconds.

[0069] In S132, the second phosphosilicate glass layer and the second polysilicon layer on the first surface side, and the second polysilicon layer and the second tunneling layer on the second surface side are etched to form a groove having a polished surface on the second surface side.

[0070] 8 , after the second phosphosilicate glass layer 223 on the second surface side is removed, the process wafer is etched using an alkaline etchant to remove the second phosphosilicate glass layer 113 and the second polysilicon layer 112 on the first surface side, and the second polysilicon layer 222 and the second tunneling layer 221 on the second surface side, and a polished surface can be formed in the groove on the second surface side. The alkaline etchant may include a sodium hydroxide solution, with a sodium hydroxide concentration ranging from 1.5% to 5%, a reaction time ranging from 200 to 300 seconds, and a reaction temperature ranging from 65°C to 75°C. The polished surface can totally reflect light of different wavelengths, and at least a portion of the light reaching the second surface side through the smooth polished surface is reflected back into the P-type silicon substrate, realizing repeated light utilization, increasing the utilization rate of light energy, and further improving the photoelectric conversion efficiency of the back contact.

[0071] In S133, the first phosphosilicate glass layer and the second tunneling layer on the first surface side are etched to remove the first phosphosilicate glass layer and the second tunneling layer on the first surface side.

[0072] Specifically, referring to FIG. 8, the second tunneling layer 111 and the first phosphosilicate glass layer 23 of the process wafer can be etched using an acidic etchant, where the acidic etchant may include a hydrogen fluoride and hydrogen chloride solution, the hydrogen fluoride concentration range may be 8% to 15%, the hydrogen chloride concentration range may be 4.5% to 10%, and the reaction time may be 150s to 300s.

[0073] In a preferred embodiment, FIG. 9 is a flowchart of a method for preparing a P-type back contact battery according to another embodiment of the present application, and FIG. 10 is a structural schematic diagram of a process for preparing a P-type back contact battery according to another embodiment of the present application. As shown in FIG. 9 , respectively forming passivation layers on the first surface side and the second surface side of the process wafer specifically includes the following steps:

[0074] In S141, an aluminum oxide layer is prepared on the first surface side and the second surface side of the process wafer.

[0075] 10, aluminum oxide layers 15 and 25 may be formed on the first surface 10 and the second surface 20 of the process wafer using an atomic layer deposition apparatus or the like, or aluminum oxide layers 15 and 25 may be formed by other preparation methods, and are not specifically limited herein. The thickness of the aluminum oxide layer can be set according to actual needs, and for example, the thickness of the aluminum oxide layer may be 2 nm to 10 nm.

[0076] In S142, a silicon nitride layer is prepared on the first surface side and the second surface side of the aluminum oxide layer facing away from the P-type silicon substrate.

[0077] 10, after preparing aluminum oxide layer 15 on first surface 10 and second surface 20 of the process wafer, plasma-enhanced chemical vapor deposition may be used to form silicon nitride over the entire surface of the aluminum oxide layer on the first and second surfaces facing away from the P-type silicon substrate, or other methods may be used to form aluminum oxide layers 15 and 25, without any specific limitations. The thickness of the silicon nitride layer may be set according to actual needs, and for example, the thickness of the silicon nitride layer may be 60 nm to 180 nm.

[0078] Based on the same application concept, an embodiment of the present application provides a P-type back contact battery, which is fabricated by the method for fabricating a back contact battery in any of the embodiments of the present application and has the same beneficial effects as the above method. Please refer to the above description, and the description will be omitted here.

[0079] The back contact battery according to the embodiments of the present application can be fabricated using the method for fabricating a back contact battery according to any of the embodiments of the present application. It is understood that in the actual production and application process, specific preparation parameters can be adaptively selected based on the parameters mentioned in the embodiments of the present application. The performance of P-type back contact batteries prepared using different parameters will be compared below.

[0080] In Example 1, a P-type silicon substrate is provided, and a first tunneling layer and a first polysilicon layer are sequentially formed on a first surface and a second surface of the P-type silicon substrate by low-pressure chemical vapor deposition. The thicknesses of the first tunneling layer on the first surface and the second surface are the same, both 1.8 nm, and the thicknesses of the first polysilicon layer on the first surface and the second surface are the same, both 180 nm. After the first tunneling layer and the first polysilicon layer are sequentially formed on the first surface and the second surface of the P-type silicon substrate, the process wafer is placed in a low-pressure diffusion furnace to form a first phosphosilicate glass layer. The deposition concentration of the phosphorus source in the first phosphosilicate glass layer on the first surface and the second surface is the same, both 4e22 / cm 3 The P-type silicon substrate was placed in a chain etching machine, and the first phosphosilicate glass layer on the first surface side was etched using 85% hydrofluoric acid for 60 seconds. After removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate, an opening was formed in the first phosphosilicate glass layer on the second surface side using a laser etching method, with a laser rated power of 40 W and a frequency of 400 KHz, and the opening width was 250 μm. After forming the opening in the first phosphosilicate glass layer on the second surface side, the P-type silicon substrate was placed in a texturing machine, and the first polysilicon layer and the first tunneling layer in the opening were etched using a 5% sodium hydroxide solution for 600 seconds at an etching temperature of 82° C. The polysilicon layer and the first tunneling layer are removed, and grooves of the pyramid texture surface are formed. After the grooves are formed, a second tunneling layer and a second polysilicon layer are sequentially formed on the first and second surface sides of the P-type silicon substrate by low-pressure chemical vapor deposition. The thicknesses of the second tunneling layer on the first surface side and the second surface side are the same, both 1.5 nm, and the thicknesses of the second polysilicon layer on the first surface side and the second surface side are the same, both 120 nm. After the second tunneling layer and the second polysilicon layer are sequentially formed on the first and second surface sides of the P-type silicon substrate, the process wafer is placed in a low-pressure diffusion furnace to form a second phosphosilicate glass layer. The deposition concentration of the phosphorus source in the second phosphosilicate glass layer on the first surface side and the second surface side is the same, both 2e 22 / cm 3After the gettering structure was formed, the process wafer was placed in a chain etching machine, and the second phosphosilicate glass layer on the second surface side was etched using 85% hydrofluoric acid for 60 seconds to remove the second phosphosilicate glass layer on the second surface side. The process wafer from which the second phosphosilicate glass layer had been removed was placed in a polishing machine, and the second phosphosilicate glass layer and second polysilicon layer on the first surface side, and the second polysilicon layer and second tunneling layer on the second surface side were etched using 5% sodium hydroxide solution at an etching temperature of 75°C for 300 seconds, forming a polished surface in the groove on the second surface side, while the first surface side still had a pyramid textured surface structure. The first phosphosilicate glass layer on the second surface side and the second tunneling layer on the first surface side were then etched using a mixed solution of 10% hydrogen chloride solution and 15% hydrogen fluoride solution for 300 seconds. Finally, aluminum oxide and silicon nitride layers were formed on the first and second surfaces using plasma-enhanced chemical vapor deposition (PCVD). The aluminum oxide layer was 10 nm thick, and the silicon nitride layer was 180 nm thick.

[0081] The P-type back contact battery of Example 1 prepared by the above preparation method was tested, and the short circuit current Isc of the P-type back contact battery was 13.643 A, the open circuit voltage Uoc of the P-type back contact battery was 0.7049 V, the fill factor FF of the P-type back contact battery was 81.34, and the photoelectric conversion efficiency of the P-type back contact battery was 23.70.

[0082] In Example 2, a P-type silicon substrate is provided, and a first tunneling layer and a first polysilicon layer are sequentially formed on the first and second surfaces of the P-type silicon substrate by low-pressure chemical vapor deposition. The thicknesses of the first tunneling layer on the first surface and the second surface are the same, both 1.1 nm, and the thicknesses of the first polysilicon layer on the first surface and the second surface are the same, both 70 nm. After the first tunneling layer and the first polysilicon layer are sequentially formed on the first and second surfaces of the P-type silicon substrate, the process wafer is placed in a low-pressure diffusion furnace to form a first phosphosilicate glass layer. The deposition concentration of the phosphorus source in the first phosphosilicate glass layer on the first surface and the second surface is the same, both 3e 21 / cm 3The P-type silicon substrate was placed in a chain etching machine, and the first phosphosilicate glass layer on the first surface side was etched using 75% hydrofluoric acid for 30 seconds. After removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate, an opening was formed in the first phosphosilicate glass layer on the second surface side using a laser etching method, with a laser rated power of 20 W and a frequency of 350 KHz, and the opening width was 150 μm. After forming the opening in the first phosphosilicate glass layer on the second surface side, the P-type silicon substrate was placed in a texturing machine, and the first polysilicon layer in the opening was etched using a 1.3% sodium hydroxide solution for 350 seconds at an etching temperature of 74° C., and the first polysilicon layer and the first tunneling layer in the opening were removed. the second tunneling layer on the first surface side and the second surface side are both the same and have a thickness of 1.0 nm, and the second polysilicon layer on the first surface side and the second surface side are both the same and have a thickness of 60 nm; after the second tunneling layer and the second polysilicon layer are respectively formed on the first surface side and the second surface side of the P-type silicon substrate in a sequential manner by low-pressure chemical vapor deposition, the process wafer is placed in a low-pressure diffusion furnace to form a second phosphosilicate glass layer; and the deposition concentration of the phosphorus source in the second phosphosilicate glass layer on the first surface side and the second surface side is the same and have a thickness of 1 e 20 / cm 3The process wafer after the gettering structure was formed was placed in a chain etching machine table, and the second phosphosilicate glass layer on the second surface side was etched using 75% hydrofluoric acid for 30 seconds to remove the second phosphosilicate glass layer on the second surface side. The process wafer from which the second phosphosilicate glass layer had been removed was placed in a polishing machine table, and the second phosphosilicate glass layer and the second polysilicon layer on the first surface side, and the second polysilicon layer and the second tunneling layer on the second surface side were etched using 1.5% sodium hydroxide solution at an etching temperature of 65°C for 200 seconds, forming a polished surface in the groove on the second surface side, while the first surface side still had a textured surface structure. The first phosphosilicate glass layer on the second surface side and the second tunneling layer on the first surface side were then etched using a mixed solution of 4.5% hydrogen chloride solution and 8% hydrogen fluoride solution for 150 seconds. Finally, aluminum oxide and silicon nitride layers were formed on the first and second surfaces using plasma-enhanced chemical vapor deposition (PCVD). The aluminum oxide layer was 2 nm thick, and the silicon nitride layer was 60 nm thick.

[0083] The P-type back contact battery of Example 2 prepared by the above preparation method was tested and found to have a short circuit current Isc of 13.642 A, an open circuit voltage Uoc of 0.7052 V, a fill factor FF of 81.33, and a photoelectric conversion efficiency of 23.70.

[0084] In Example 3, a P-type silicon substrate is provided, and a first tunneling layer and a first polysilicon layer are sequentially formed on the first and second surfaces of the P-type silicon substrate by low-pressure chemical vapor deposition. The thicknesses of the first tunneling layer on the first surface and the second surface are the same, both 1.5 nm, and the thicknesses of the first polysilicon layer on the first surface and the second surface are the same, both 120 nm. After the first tunneling layer and the first polysilicon layer are sequentially formed on the first and second surfaces of the P-type silicon substrate, the process wafer is placed in a low-pressure diffusion furnace to form a first phosphosilicate glass layer. The deposition concentration of the phosphorus source in the first phosphosilicate glass layer on the first surface and the second surface is the same, both 8 e 21 / cm 3The P-type silicon substrate was placed in a chain etching machine, and the first phosphosilicate glass layer on the first surface side was etched using 80% hydrofluoric acid for 45 seconds. After removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate, an opening was formed in the first phosphosilicate glass layer on the second surface side using a laser etching method, with a laser rated power of 30 W and a frequency of 600 KHz, and the opening width was 200 μm. After forming the opening in the first phosphosilicate glass layer on the second surface side, the P-type silicon substrate was placed in a texturing machine, and the first polysilicon layer and the first tunneling layer in the opening were etched using a 2.6% sodium hydroxide solution for 500 seconds at an etching temperature of 78° C. The P-type silicon substrate is then subjected to a low-pressure chemical vapor deposition process to form a second tunneling layer and a second polysilicon layer on the first and second surfaces of the P-type silicon substrate, the second tunneling layer having the same thickness of 1.2 nm and the second polysilicon layer having the same thickness of 90 nm. After the P-type silicon substrate is formed, the P-type silicon substrate is then subjected to a low-pressure diffusion process to form a second phosphosilicate glass layer. The second phosphosilicate glass layer has the same deposition concentration of a phosphorus source on the first and second surfaces of the P-type silicon substrate, the second phosphosilicate glass layer having the same deposition concentration of a phosphorus source on the first and second surfaces of the P-type silicon substrate, the P-type silicon substrate is then subjected to a low-pressure diffusion process to form a second phosphosilicate glass layer. 21 / cm 3The process wafer after the gettering structure is formed is placed in a chain etching machine table, and the second phosphosilicate glass layer on the second surface side is etched using 80% hydrofluoric acid, the etching time is 45 seconds, and the second phosphosilicate glass layer on the second surface side is removed. The process wafer from which the second phosphosilicate glass layer has been removed is placed in a polishing machine table, and the second phosphosilicate glass layer and the second polysilicon layer on the first surface side, and the second polysilicon layer and the second tunneling layer on the second surface side are etched using 2.5% sodium hydroxide solution, the etching temperature is 70°C, and the etching The etching time was 250 seconds, forming a polished surface in the grooves on the second surface side, while the first surface side still had a pyramidal textured surface structure. The first phosphosilicate glass layer on the second surface side and the second tunneling layer on the first surface side were then etched using a mixed solution of 7% hydrogen chloride solution and 12% hydrogen fluoride solution for an etching time of 200 seconds. Finally, aluminum oxide and silicon nitride layers were formed on the first and second surface sides using plasma-enhanced chemical vapor deposition. The aluminum oxide layer was 6 nm thick, and the silicon nitride layer was 120 nm thick.

[0085] The P-type back contact battery of Example 3 prepared by the above preparation method was tested and found to have a short circuit current Isc of 13.648 A, an open circuit voltage Uoc of 0.7054 V, a fill factor FF of 81.43, and a photoelectric conversion efficiency of 23.75.

[0086] In Comparative Example 1, a P-type silicon substrate is provided, and a first tunneling layer and a first polysilicon layer are sequentially formed on the first and second surfaces of the P-type silicon substrate by low-pressure chemical vapor deposition. The thicknesses of the first tunneling layer on the first surface and the second surface are the same, both 1.8 nm, and the thicknesses of the first polysilicon layer on the first surface and the second surface are the same, both 180 nm. After the first tunneling layer and the first polysilicon layer are sequentially formed on the first and second surfaces of the P-type silicon substrate, the process wafer is placed in a low-pressure diffusion furnace to form a first phosphosilicate glass layer. The deposition concentration of the phosphorus source in the first phosphosilicate glass layer on the first surface and the second surface is the same, both 4 e 22 / cm 3 The P-type silicon substrate was placed in a chain etching machine, and the first phosphosilicate glass layer on the first surface side was etched using 85% hydrofluoric acid for 60 seconds. After removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate, an opening was formed in the first phosphosilicate glass layer on the second surface side using a laser etching method, with a laser rated power of 40 W and a frequency of 400 KHz, and the opening width was 250 μm. After forming the opening in the first phosphosilicate glass layer on the second surface side, the P-type silicon substrate was placed in a texturing machine, and a 5% sodium hydroxide solution was used to texture the opening. The first polysilicon layer and the first tunneling layer on the first surface side were etched for 600 seconds at an etching temperature of 82°C, forming a pyramidal textured surface on the opening and the first surface side. The first phosphosilicate glass layer on the second surface side was etched using a mixed solution of 10% hydrogen chloride solution and 15% hydrogen fluoride solution for 300 seconds. Then, aluminum oxide and silicon nitride layers were formed on the first and second surface sides using plasma-enhanced chemical vapor deposition, with the aluminum oxide layer having a thickness of 10 nm and the silicon nitride layer having a thickness of 180 nm.

[0087] The P-type back contact battery of Comparative Example 1 prepared by the above preparation method was tested, and the short circuit current Isc of the P-type back contact battery was 13.543 A, the open circuit voltage Uoc of the P-type back contact battery was 0.7051 V, the fill factor FF of the P-type back contact battery was 81.30, and the photoelectric conversion efficiency of the P-type back contact battery was 23.52.

[0088] In Comparative Example 2, a P-type silicon substrate is provided, and a first tunneling layer and a first polysilicon layer are sequentially formed on the first and second surfaces of the P-type silicon substrate by low-pressure chemical vapor deposition. The thicknesses of the first tunneling layer on the first surface and the second surface are the same, both 1.1 nm, and the thicknesses of the first polysilicon layer on the first surface and the second surface are the same, both 70 nm. After the first tunneling layer and the first polysilicon layer are sequentially formed on the first and second surfaces of the P-type silicon substrate, the process wafer is placed in a low-pressure diffusion furnace to form a first phosphosilicate glass layer. The deposition concentration of the phosphorus source in the first phosphosilicate glass layer on the first surface and the second surface is the same, both 3e 21 / cm 3The P-type silicon substrate was placed in a chain etching machine, and the first phosphosilicate glass layer on the first surface side was etched using 75% hydrofluoric acid for 30 seconds. After removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate, an opening was formed in the first phosphosilicate glass layer on the second surface side using a laser etching method, with a laser rated power of 20W and a frequency of 350KHz, and the opening width was 150μm. After forming the opening in the first phosphosilicate glass layer on the second surface side, the P-type silicon substrate was placed in a texturing machine, and an opening was formed using a 1.3% sodium hydroxide solution. The first polysilicon layer and the first tunneling layer at the opening and the first polysilicon layer and the first tunneling layer on the first surface side were etched for 350 seconds at an etching temperature of 74°C, forming a pyramidal textured surface at the opening and the first surface side. The first phosphosilicate glass layer on the second surface side was etched using a mixed solution of 4.5% hydrogen chloride solution and 8% hydrogen fluoride solution for an etching time of 150 seconds. Then, aluminum oxide and silicon nitride layers were formed on the first and second surface sides using plasma-enhanced chemical vapor deposition, with the aluminum oxide layer having a thickness of 2 nm and the silicon nitride layer having a thickness of 60 nm.

[0089] The P-type back contact battery of Comparative Example 2 prepared by the above preparation method was tested, and the short circuit current Isc of the P-type back contact battery was 13.544 A, the open circuit voltage Uoc of the P-type back contact battery was 0.7052 V, the fill factor FF of the P-type back contact battery was 81.28, and the photoelectric conversion efficiency of the P-type back contact battery was 23.52.

[0090] Here, the photoelectric conversion efficiency Eta is related to the open circuit voltage Uoc, short circuit current Isc, and fill factor FF. Comparing the P-type back contact batteries of Examples 1 to 3 with the P-type back contact batteries of Comparative Examples 1 and 2, it can be determined that the P-type back contact batteries prepared using the preparation method of the present application have improved photoelectric conversion efficiencies Eta. In other words, the preparation method of the P-type back contact battery of the present application can effectively improve the photoelectric conversion efficiency of the P-type back contact battery.

[0091] Based on the same application concept, the embodiments of the present application further provide a solar module including a P-type back contact cell according to the embodiments of the present application, which can achieve the beneficial effects of the P-type back contact cell according to the embodiments of the present application. For similar points, please refer to the above, and the description will be omitted here.

[0092] It should be noted that the above is merely a preferred embodiment of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application has been described in detail using the above embodiments, the present application is not limited to the above embodiments, and may further include many other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the appended claims.

Claims

1. A process wafer for a P-type back contact cell is prepared, the process wafer comprising a P-type silicon substrate, the P-type silicon substrate having a first surface and a second surface opposite to each other, the second surface being provided with a first tunneling layer, a first polysilicon layer, and a first phosphosilicate glass layer stacked in sequence, and a groove penetrating the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer; forming a gettering structure including a second tunneling layer, a second polysilicon layer, and a second phosphosilicate glass layer stacked on the first surface side and / or the second surface side; Etching the process wafer after forming the gettering structure to remove the gettering structure and the first phosphosilicate glass layer on the second surface side; forming a passivation layer on the first surface side and the second surface side of the process wafer, respectively; Method for fabricating P-type back contact cells.

2. Preparing the process wafer of the P-type back contact cell includes: providing a P-type silicon substrate; forming the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer, which are sequentially stacked on the first surface and the second surface of the P-type silicon substrate; forming an opening in the first phosphosilicate glass layer on the second surface side to expose a portion of the first polysilicon layer on the second surface side; forming an opening in the first phosphosilicate glass layer on the second surface side, and then removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate to expose the first polysilicon layer on the first surface side; Etching the first surface and the second surface of the P-type silicon substrate, removing the first polysilicon layer and the first tunneling layer located in the opening, forming the groove in the opening, and removing the first tunneling layer and the first polysilicon layer located on the first surface side. The method of claim 1 .

3. Preparing the process wafer of the P-type back contact cell includes: providing a P-type silicon substrate; forming the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer sequentially stacked on the first surface and the second surface of the P-type silicon substrate, respectively; removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate to expose the first polysilicon layer on the first surface side; removing the first phosphosilicate glass layer on the first surface side of the P-type silicon substrate, and then forming an opening in the first phosphosilicate glass layer on the second surface side to expose a portion of the first polysilicon layer on the second surface side; Etching the first surface and the second surface of the P-type silicon substrate, removing the first polysilicon layer and the first tunneling layer located in the opening, forming the groove in the opening, and removing the first tunneling layer and the first polysilicon layer located on the first surface side. The method of claim 1 .

4. Etching the first surface and the second surface of the P-type silicon substrate includes: using an alkaline etching solution to sequentially etch the openings on the first surface side and the second surface side of the P-type silicon substrate, to remove the first polysilicon layer and the first tunneling layer located in the openings, to form the grooves in the openings, and to remove the first tunneling layer and the first polysilicon layer located on the first surface side. The method according to claim 2 or 3.

5. forming the opening in the first phosphosilicate glass layer on the second surface side and exposing a portion of the first polysilicon layer on the second surface side, forming the opening in the first phosphosilicate glass layer on the second surface side of the P-type silicon substrate using a laser; The method according to claim 2 or 3.

6. Forming the gettering structure on the first surface side and / or the second surface side includes: and sequentially preparing the first tunneling layer, the first polysilicon layer, and the first phosphosilicate glass layer on the first surface side and the second surface side by employing any one of a high-temperature thermal oxidation method, a nitric acid oxidation method, an ozone oxidation method, and a chemical vapor deposition method. The method of claim 1 .

7. Etching the process wafer after forming the gettering structure to remove the gettering structure and the first phosphosilicate glass layer on the second surface side, Etching the second phosphosilicate glass layer on the second surface side to remove the second phosphosilicate glass layer on the second surface side; Etching the second phosphosilicate glass layer and the second polysilicon layer on the first surface side and the second polysilicon layer and the second tunneling layer on the second surface side to form a groove having a polished surface on the second surface side; Etching the first phosphosilicate glass layer and the second tunneling layer on the first surface side to remove the first phosphosilicate glass layer and the second tunneling layer on the first surface side. The method of claim 1 .

8. forming a passivation layer on the first surface side and the second surface side of the process wafer, respectively, preparing an aluminum oxide layer on the first surface side and the second surface side of the process wafer; and forming a silicon nitride layer on the first surface side and the second surface side of the aluminum oxide layer facing away from the P-type silicon substrate. The method of claim 1 .

9. 9. A back contact battery produced by the method of claim 1. P-type back contact battery.

10. 10. The P-type back contact battery of claim 9, Solar module.

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