Low-temperature single-crystalline 2D material growth using trench patterns

Abstract

A method for growing two-dimensional (2D) material on a substrate is described, the method including: (a) forming a mask layer on the substrate; (b) forming a trench in the mask layer, the trench having sidewalls formed in the mask layer that surround an exposed portion of the substrate; and (c) depositing nuclei of the 2D material on the exposed portion of the substrate and growing the nuclei into a single-domain monolayer of the 2D material, wherein the nuclei deposition and growth are performed at a temperature less than 705°C.

Description

[Technical Field]

[0001] This application relates to the growth of low-temperature single-crystalline 2D materials using trench patterns.

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Application No. 63 / 484,989, filed February 14, 2023, which is incorporated herein by reference in its entirety for all purposes.

[0003] U.S. Provisional Application No. 63 / 374,090, filed August 31, 2022, entitled "Confined Growth of 2D Materials and Their Heterostructures," and Kim et al., 2023, Nature, 614(7946), 81-87, are incorporated herein by reference in their entireties. [Background technology]

[0004] Two-dimensional (2D) transition metal dichalcogenides (TMDs) and their heterostructures are promising platforms for next-generation electronics, spintronics, valleytronics, and optoelectronics. However, integrating semiconductor 2D heterostructures into industrial platforms has been challenging due to scalability limitations. A common method for constructing 2D heterostructures is mechanical exfoliation and stacking of 2D flakes, but this is a trial-and-error-based operation, which imposes severe limitations on the size of structures that can be fabricated. Furthermore, fabricating 2D heterostructures using mechanical exfoliation and stacking requires a long time.

[0005] In recent years, considerable progress has been made in improving the scalability of single-layer (ML) TMDs grown on single-crystal hexagonal substrates, such as sapphire, using epitaxial growth techniques. However, significant challenges remain for the growth of large-scale 2D heterostructures due to the lack of strategies for growing single-domain TMDs layer-by-layer. Furthermore, some current growth methods involve the undesirable step of implanting 2D materials into silicon devices when grown on hexagonal non-silicon substrates. Single-domain TMD arrays can also be grown by laser irradiation of nucleation points. However, laser-induced growth presents challenges because the second heterolayer is likely to nucleate at the edge of the first single-domain patch. To date, no feasible solution exists for achieving single-domain 2D heterostructures at the wafer scale. Summary of the Invention [Problem to be solved by the invention]

[0006] Embodiments of the present invention are improvements over prior art systems and methods. [Means for solving the problem]

[0007] This Summary is intended to introduce in a simplified form some concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope thereof.

[0008] In one embodiment, the present invention provides a method comprising: (a) providing a substrate of a first material, (b) depositing a mask material on the substrate, (c) forming a trench on the mask material, the trench having a trench shape with lateral dimensions l x w, where l and w are each selected to have a maximum dimension of 2 μm, and the trench having an exposed portion of the substrate surrounded by sidewalls formed of the mask material, (d) depositing adatoms of a second material on the exposed portion of the substrate at a low temperature, (e) allowing the adatoms to selectively nucleate at the low temperature into nuclei within the trench, and (f) growing the nuclei within the trench at a low temperature, wherein the lateral dimensions associated with the trench shape and the low temperature limit the growth of the nuclei to a single-domain monolayer of the second material, the low temperature being less than 400°C, and the trench shape and the low temperature limit the growth of the second material as a single crystal within the trench and prevent growth of the second material outside the trench.

[0009] In another embodiment, the present invention provides a method comprising the steps of: (a) providing a substrate of a first material; (b) depositing a first mask material on the substrate; (c) forming a first trench in the first mask material, the first trench having a first trench shape with lateral dimensions l1×w1, where l1 and w1 are each selected to have a maximum dimension of 2 μm, and the first trench having a first exposed portion of the substrate surrounded by sidewalls formed of the first mask material; and (d) forming a first trench at a low temperature on the substrate. (e) allowing the first adatoms to selectively nucleate first nuclei in the first trench at a low temperature; (f) growing the first nuclei in the first trench at a low temperature, wherein the lateral dimensions and low temperature associated with the first trench shape limit the growth of the first nuclei to a first single-domain monolayer of the second material; (g) waiting an incubation period; (h) forming a first source electrode contact on one side of the first trench and a first drain electrode contact on the other side of the first trench; (i) depositing a first dielectric layer on top of the structure formed in steps (a)-(h); (j) forming a gate electrode.(k) depositing a second dielectric layer on top of the structure formed in steps (a)-(j); (l) depositing a second mask material on the second dielectric layer; (m) forming a second trench in the second mask material, the second trench having a second trench shape with lateral dimensions l2 x w2, where l2 and w2 are each selected to have a maximum dimension of 2 μm, and the second trench having sidewalls formed of the second mask material. (n) depositing, at a low temperature, second adatoms of a third material on the second exposed portions of the second mask material; (o) allowing the second adatoms to selectively nucleate into second nuclei in the second trench at a low temperature; (p) growing the second nuclei in the second trench at a low temperature, wherein the lateral dimensions associated with the second trench shape and the low temperature limit the growth of the second nuclei to a second single-domain monolayer of the third material. wherein the first single-domain monolayer and the second single-domain monolayer form a bilayer at a low temperature, the low temperature being less than 400°C, the low temperature and the first trench shape constraining the growth of the second material as a single crystal within the first trench and preventing the growth of the second material outside the first trench, and the low temperature and the second trench shape constraining the growth of the third material as another single crystal within the second trench and preventing the growth of the third material outside the second trench.

[0010] The following detailed description refers to the accompanying drawings that form a part of this application, and in which is shown, by way of illustration, specific implementation examples. Other implementations are possible without departing from the scope of the disclosure.

[0011] The present disclosure, in accordance with one or more various examples, will now be described in detail with reference to the following drawings. The drawings are provided for illustrative purposes only and merely illustrate examples of the present disclosure. These drawings are provided to facilitate the reader's understanding of the present disclosure and should not be construed as limiting the breadth, scope, or applicability of the present disclosure. It should be noted that for clarity and ease of illustration, these drawings are not necessarily drawn to scale. [Brief explanation of the drawings]

[0012] [Figure 1A] A conventional process for growing transition metal dichalcogenides (TMDs) is shown. [Figure 1B] We present a confined growth process of the present invention for selectively synthesizing single-domain ML TMDs that addresses the limitations of conventional TMD growth processes. [Figure 1C] We demonstrate the fabrication of a single-domain MoS2-WSe2 heterostructure by confining and growing a second MoS2 layer on a WSe2ML in each trench within a trench array. [Figure 1D] Calculations of the binding energies of W3O9, Se2, and W3Se6 clusters on c-Al2O3, a-HfO2, and a-SiO2 substrates are presented. [Figure 2A] 1 illustrates one embodiment of the present invention showing a vertical complementary metal oxide semiconductor (CMOS) fabrication process. [Figure 2B] 1 illustrates one embodiment of the present invention showing a vertical complementary metal oxide semiconductor (CMOS) fabrication process. [Figure 3A] 3(A)-3(F): One embodiment of the present invention is shown, illustrating a vertical CMOS process flow for WSe2 stack on MoS2. [Figure 3B] 3(G)-3(I): One embodiment of the present invention is shown, illustrating a vertical CMOS process flow for WSe2 stack on MoS2. [Figure 4A] Low-temperature 2D material growth of MoS2 is shown. [Figure 4B]Low-temperature 2D material growth of MoS2 is shown. [Figure 4C] Low-temperature 2D material growth of MoS2 is shown. [Figure 4D] Low-temperature 2D material growth of MoS2 is shown. [Figure 5] Figure 1 shows an SEM image showing single-crystalline MoS2 grown below 400 °C in SiO2 trenches. [Figure 6A] The bonding characteristics of WSe2 on HfO2 are shown based on DFT calculations. [Figure 6B] The bonding characteristics of WSe2 on HfO2 are shown based on DFT calculations. [Figure 7] Figures 7(A) to 7(D): Low-temperature growth of single-crystal WSe2. DETAILED DESCRIPTION OF THE INVENTION

[0013] While the present invention has been shown and described with respect to preferred embodiments, the present invention can be made in many different configurations. While preferred embodiments of the present invention are shown in the drawings and described in detail herein, it should be understood that the present disclosure is to be considered as an exemplification of the principles of the invention and functional specifications related to its construction, and is not intended to limit the invention to the illustrated embodiments. Those skilled in the art will envision many other possible variations within the scope of the present invention.

[0014] It should be noted that, as used herein, "one embodiment" or "an embodiment" means that the referenced feature is included in at least one embodiment of the present invention. Furthermore, multiple references to "one embodiment" in this specification do not necessarily refer to the same embodiment, but unless otherwise specified and unless readily apparent to one of ordinary skill in the art, these embodiments are not mutually exclusive. Thus, the present invention may include any various combinations and / or integrations of the embodiments described herein.

[0015] Figure 1(A) illustrates a conventional transition metal dichalcogenide (TMD) growth process. First, a first set of TMD adatoms 12 is introduced to the surface of a substrate 10 (top diagram). The TMD adatoms 12 nucleate, forming nuclei 14 on the substrate 10. The orientation of these nuclei 14 is random because the nuclei 14 typically do not align with the substrate 10. The nuclei 14 grow laterally and contact each other (middle diagram), forming grains 16 that fuse together, resulting in a continuous polycrystalline layer due to the random orientation of the nuclei 14. This polycrystalline growth ultimately degrades the intrinsic properties of the TMD. Additionally, additional nuclei 18 may form on some of the grains 16 (bottom diagram). Without control of the additional nuclei, this process repeats, growing a TMD layer of irregular thickness due to the overlapping grains 16, leading to the nucleation of a second set of nuclei 18 on top of the initial layer of grains 16.

[0016] Figure 1(B) shows a confined growth process that addresses these issues by precisely controlling the thickness and crystallinity of the TMD growth. First, c-plane Al2O3, HfO2, or another material with a relatively low Gibbs free energy, such as an amorphous or crystalline metal oxide, is deposited on a Si wafer to form the substrate 100 on which the TMDs are grown. Other suitable substrate materials include graphene, hexagonal boron nitride (hBN), hafnium zirconium oxide (HZO), TiO2, ZnO, Fe2O3, SnO2, NiO, CuO, or TMD-coated materials.

[0017] Next, a thin layer of mask material 110 (e.g., 5 nm, 10 nm, 50 nm, 100 nm, or a few hundred nanometers thick, in some cases up to 250 nm, 500 nm, 750 nm, or 1 μm thick) is coated onto the c-plane Al2O3 or HfO2 surface of the substrate 100. Suitable mask materials are materials with relatively high Gibbs free energy, such as amorphous SiO2 (a-SiO2), a-Si, a-SiN, etc. x , and a-carbon.

[0018] Next, confined growth regions 102, also known as recesses, pockets, trenches, wells, or cavities, each with lateral dimensions ranging from tens of nanometers up to approximately 2 microns, are patterned in a thin layer of a-SiO 110. The patterned a-SiO 110 is also referred to as a mask or mask layer. These pockets 102 can be of any suitable shape (e.g., square, rectangular, triangular, or circular) and can be formed in 1D or 2D arrays (e.g., square, rectangular, or hexagonal arrays). The pockets 102 may extend completely through the a-SiO 110, exposing a portion of the Al 2 O 3 or HfO 2 surface of the substrate 100 surrounded by a-SiO 2 sidewalls 112. The pockets 102 may extend partway (e.g., a few nanometers) into the c-plane Al 2 O 3 or HfO 2 (FIG. 1B, top).

[0019] Once the pockets 102 are formed in the a-SiO2 layer 110, adatoms 120 of the 2D material are introduced into each pocket (see diagram above). As an example, 42 adatoms (W and Se) were found to exist within a 1 nm x 1 nm area. Therefore, within a 2 μm x 2 μm trench, 84,000 adatoms are required for each pocket for a single layer and 168,000 adatoms for a double layer. Suitable 2D materials include semiconductor TMDs, such as WSe2 (this example), MoS2, MoSe2, and WS2. Other suitable 2D materials include, but are not limited to, graphene, carbon nanotubes (CNTs), hBN, metallic TMDs (e.g., VS2, VSe2, CoS2, CoSe2, TiS2, TiSe2), and high-k 2D materials (e.g., Bi2SeO5, Sb2O3).

[0020] The size of each pocket 102 is small enough that only a single nucleation (represented by a single triangle in Figure 1(B)) 122 occurs in each pocket (center). Each nucleation 122 grows on the exposed c-plane Al2O3 or HfO2 at the bottom of the pocket 102 until it reaches the a-SiO2 sidewall 112, filling the entire trench 102 and forming a TMD film 124 (bottom). Each TMD film 124 is both a single domain and a multi-layer structure (bottom, inset).

[0021] Figure 1(C) shows how the adatom introduction, nucleation, and single-crystal growth steps in the process of Figure 1(B) are repeated to obtain a single-domain MoS2 / WSe2 heterostructure or a single-domain homobilayer (BL) of WSe2. (A BL can be thought of as two MLs connected by van der Waals interactions.) Once WSe2 MLs 124 are formed in the pockets 102, MoS2 adatoms 130 are introduced into the cavities 102 above the WSe2 MLs 124 (Figure 1(C), top). These MoS2 adatoms 130 nucleate to form nuclei 132 (middle) and grow (bottom), forming single-crystalline MoS2 MLs 134 on the WSe2 MLs 124 (bottom inset), resulting in a MoS2 / WSe2 heterostructure 140 in each pocket 102. DFT calculations confirm this growth selectivity. Alternatively, WSe adatoms can be deposited on a WSe ML and undergo nucleation and growth to form a single-domain BL of WSe .

[0022] 1(B) and 1(C) is carried out at low temperatures below 705° C., preferably around 400° C. The low temperature and trench geometry confine the growth of the ML within the trench and prevent growth of any material outside the trench.

[0023] Figure 1(D) shows the DFT-calculated binding energies of the WSe precursors WO and Se and the product WSe clusters on c-AlO, a-HfO, and a-SiO. These DFT calculations indicate that the WO cluster (WO, left), Se cluster (Se, center), and WSe cluster (WSe, right) have stronger bonding interactions with c-AlO and a-HfO ​​than with the SiO surface. This indicates that the clusters preferentially bond with the substrate surface at the bottom of the pocket rather than with the a-SiO sidewalls, leading to selective WSe growth within the pocket.

[0024] This selectivity is confirmed by simultaneously growing WSe2 on Al2O3, HfO2, and SiO2 substrates under identical CVD growth conditions. Atomic force microscopy (AFM) images show that WSe2 nucleates only on Al2O3 and HfO2, but not on SiO2, during 20 min of growth. This led to the successful selective confinement of WSe2 growth on the exposed substrate surface of the micropatterned SiO2 trench array.

[0025] The trench size was selected to allow only single-domain ML WSe2 formation and depends on both the WSe2 lateral growth rate and the second nucleation incubation period. The measured WSe2 lateral growth rate and second nucleation incubation period were approximately 0.4 μm / min and 5 min, respectively. This suggests that the width of each trench needs to be approximately 2 μm or less to avoid the nucleation of a second layer of WSe2. The lateral growth rate or incubation period (and therefore the maximum trench width) can be controlled by varying the TMD powder content, gas ratio (Ar / H2), and growth temperature. For example, such control can be influenced by varying the S / Se powder content between 100 mg and 1500 mg, or by varying the MoO3 / WO3 powder content between 10 mg and 100 mg. The gas ratio between argon (Ar) and hydrogen (H) can be adjusted between Ar-100% / H-0% and Ar-0% / H-100%, and the growth temperature can be adjusted between 200°C and 1000°C.

[0026] 2(A)-2(B) illustrate one embodiment of the present invention. In this embodiment, the method includes the following steps: (a) providing a substrate (230) of a first material—step 202; (b) depositing a trench buffer layer (232) (e.g., HfO2, Al2O3, SiN x, h-BN, etc.—step 204, and depositing a first mask material on the substrate (230)—step 206; (c) forming a first trench in the first mask material (e.g., by etching)—step 208, where the first trench has a first trench shape with lateral dimensions l1×w1, where l1 and w1 are each selected to have a maximum dimension of 2 μm, and the first trench has a first exposed portion of the growth buffer layer (232) on a portion of the substrate (230) surrounded by sidewalls formed of the first mask material; (d) depositing, at low temperature, first adatoms of a second material onto a first exposed portion of the growth buffer layer on a portion of the substrate—step 210; (e) allowing the first adatoms to selectively nucleate first nuclei within the first trench at low temperature—step 210; (f) growing the first nuclei within the first trench at low temperature, where the lateral dimensions associated with the first trench shape and the low temperature limit the growth of the first nuclei to a first single-domain monolayer (250) of the second material—step 210; (g) waiting for an incubation period; (h) depositing a first adatom of a second material onto a first exposed portion of the growth buffer layer on a portion of the substrate on one side of the first trench. (i) forming a first source electrode contact (234 or 236) on the first trench and a first drain electrode contact (236 or 234) on the other side of the first trench - step 212; (i) depositing a first dielectric layer (238) on top of the structure formed in steps (a) to (h) - step 214; (j) forming a gate electrode (240) on the first dielectric layer (238) - step 216; (k) depositing a second dielectric layer (242) on top of the structure formed in steps (a) to (j) - step 218; (l) depositing a second mask material (243) on the second dielectric layer (244); (m) forming (e.g., via etching) a second trench in the second mask material (243)—step 222, the second trench having a second trench shape with lateral dimensions l2×w2, where l2 and w2 are each selected to have a maximum dimension of 2 μm, and the second trench having a second exposed portion of the second mask material surrounded by sidewalls formed of the second mask material; (n) depositing, at low temperature, second adatoms of a third material in the second exposed portion of the second mask material—step 224;(o) allowing second adatoms to selectively nucleate into second nuclei within the second trench at low temperature—step 224, where the lateral dimensions and low temperature associated with the second trench geometry limit the growth of the second nuclei to a second single-domain monolayer (252) of a third material; (p) growing second nuclei within the second trench at low temperature—step 224; (q) forming a second source electrode contact (244 or 246) on one side of the second trench and a second drain electrode contact (246 or 244) on the other side of the second trench—step 226; (r) forming an encapsulation layer (248) on top of the structure formed in (a)-(q)—step 228. Here, the first single-domain monolayer (250) and the second single-domain monolayer (252) form a bilayer at a low temperature, the low temperature being less than 705°C, the low temperature and the first trench shape constraining the growth of the second material as a single crystal within the first trench and preventing the growth of the second material outside the first trench, and the low temperature and the second trench shape constraining the growth of the third material as another single crystal within the second trench and preventing the growth of the third material outside the second trench. The height of each trench can be between 5 and 100 nm.

[0027] Figures 3(A)-3(I) illustrate various resulting structures formed as part of the steps of the method of the present invention illustrated in Figure 2(A). In Figure 3(A), a trench buffer layer (132) (e.g., HfO2) is grown on a substrate 130.

[0028] In FIG. 3B, a first mask material, such as, but not limited to, SiO2, is deposited on the substrate 230, and a first trench 254 is formed (e.g., by etching) in the first mask material. The first trench 254 has a first trench shape with lateral dimensions l1×w1, where l1 and w1 are each selected to have a maximum dimension of 2 μm, and the first trench 254 has a first exposed portion of the growth buffer layer over a portion of the substrate bounded by sidewalls formed by the first mask material. The height of the first trench can be between 5 and 100 nm.

[0029] 3(C), first adatoms of a second material are deposited at a low temperature onto a first exposed portion of a growth buffer layer on a portion of a substrate 230. The first adatoms are allowed to selectively nucleate into first nuclei within the first trench at the low temperature. The first nuclei are grown within the first trench at the low temperature, where the lateral dimensions associated with the first trench geometry and the low temperature limit the growth of the first nuclei to a first single-domain monolayer 250 of the second material. A waiting time period or incubation period is then performed.

[0030] In FIG. 3(D), a first source electrode contact (234 or 236) is formed on one side of the first trench, and a first drain electrode contact (236 or 234) is formed on the other side of the first trench.

[0031] In Figure 3(E), a first dielectric layer 238 is deposited over the structure of Figure 3(D), and a gate electrode 240 is formed in the first dielectric layer 238. A second dielectric layer 242 is then deposited over the gate electrode 240.

[0032] 3(F), a second mask material 243 is deposited on the second dielectric layer 242, and a second trench is formed (e.g., by etching) in the second mask material 243. The second trench has a second trench shape with lateral dimensions l2 x w2, where l2 and w2 are each selected to have a maximum dimension of 2 μm, and the second trench has a second exposed portion of the second mask material surrounded by sidewalls formed from the second mask material.

[0033] 3(G), second adatoms of a third material are deposited at a low temperature on the second exposed portions of the second mask material, allowing the second adatoms to selectively nucleate into second nuclei within the second trench at the low temperature, where the lateral dimensions associated with the second trench geometry and the low temperature limit the growth of the second nuclei into a second single-domain monolayer 252 of the third material. The second nuclei are grown at the low temperature within the second trench.

[0034] In FIG. 3(H), a second source electrode contact 244 or 246 is formed on one side of the second trench, and a second drain electrode contact 246 or 244 is formed on the other side of the second trench.

[0035] In FIG. 3(I), an encapsulation layer 248 is formed over the structure of FIG. 3(H).

[0036] The first single-domain monolayer 250 and the second single-domain monolayer 252 form a bilayer at low temperatures.

[0037] The method of Figures 3(A)-3(I) can be performed at low temperatures, i.e., temperatures below 705°C, where the low temperature and first trench shape confine the growth of the second material as a single crystal within the first trench and prevent growth of the second material outside the first trench, and the low temperature and second trench shape confine the growth of the third material as another single crystal within the second trench and prevent growth of the third material outside the second trench.

[0038] In one embodiment, the first material has a first Gibbs free energy and the mask material has a second Gibbs free energy, the second Gibbs free energy being higher than the first Gibbs free energy.

[0039] In one embodiment, the first material includes one of hafnium oxide (HfO), aluminum oxide (AlO), hafnium zirconium oxide (HZO), titanium dioxide (TiO), zinc oxide (ZnO), iron oxide (FeO), tin oxide (SnO), nickel oxide (NiO), or copper oxide (CuO).

[0040] In one embodiment, either the second material or the third material is selected from any of the following, or a combination thereof: graphene, carbon nanotubes (CNTs), hexagonal boron nitride (h-BN), a metallic transition metal dichalcogenide (e.g., vanadium disulfide (VS), vanadium diselenide (VSe), cobalt sulfide (CoS), cobalt selenide (CoSe), titanium disulfide (TiS), or titanium diselenide (TiSe)), a semiconducting transition metal dichalcogenide (e.g., molybdenum disulfide (MoS), molybdenum diselenide (MoSe), tungsten disulfide (WS), or tungsten diselenide (WSe)), or a high-k material (e.g., BiSeO or SbO).

[0041] In one embodiment, the first mask material or the second mask material is selected from any one of the following, or a combination thereof: amorphous silicon dioxide (a-SiO), amorphous silicon (a-Si), amorphous silicon nitride (a-SiN x ), amorphous carbon (a-carbon), hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium zirconium oxide (HfZrO), titanium dioxide (TiO2), zinc oxide (ZnO), iron oxide (Fe2O3), tin oxide (SnO2), nickel oxide (NiO), or copper oxide (CuO).

[0042] In one embodiment, the bilayer is a heterojunction bilayer in which the second material and the third material are different from one another.

[0043] In one embodiment, the bilayer is a homojunction bilayer in which the second and third materials are similar to each other.

[0044] In one embodiment, the low temperature is about 385°C.

[0045] In one embodiment, a method includes forming a semiconductor device (e.g., a valleytronic device, a forked-sheet field effect transistor (FET), or a complementary FET) including a first single-domain monolayer and a second single-domain monolayer.

[0046] In one embodiment, l1=l2 and w1=w2.

[0047] Figures 4(A)-4(B) show photographs and schematic diagrams of HfO deposited on a Si wafer in pockets with lateral dimensions of 1 μm (scale bar: 5 μm). As disclosed herein, single-crystalline MoS was synthesized at low temperature (385 °C) by fabricating SiO trenches on the HfO coated silicon wafer.

[0048] Figures 4(A)-4(D) show the low-temperature growth of single-crystalline MoS2. Figure 4(A) shows a schematic diagram showing that nucleation primarily initiates at the edges of SiO2 trenches on HfO2 substrates, rather than in areas without SiO2 trenches. Figure 4(B) is a microscopic image showing SiO2 trenches formed on HfO2 substrates; the scale bar indicates 5 μm. Figure 4(C) shows Raman spectra taken outside and inside the trenches. The Raman spectra confirm that MoS2 nucleation and formation occur only inside the trenches. Figure 4(D) shows photoluminescence (PL) spectra taken on single-crystalline MoS2 grown at 700°C and 385°C. The PL spectrum of MoS2 grown at 385°C is nearly identical to that of MoS2 grown at 700°C, indicating its single crystal nature.

[0049] Fabrication of such low temperature structures enables the techniques of the present invention to be used in the fabrication of next generation semiconductor devices, such as gate-all-around (GAA), fork-sheet, complementary FETs (CFETs), and multi-bridge channel FETs (MBCFETs).

[0050] Figure 5 shows images demonstrating the confined growth of single-layer (ML) MoS on an HfO layer. As shown in the OM image, MoS did not grow at low temperatures (approximately 400 °C) where no SiO trenches were present (outer pockets), but single-crystalline MoS grew inside the SiO trenches (inner pockets). Raman spectroscopy and photoluminescence (PL) analysis confirmed that MoS grew as single crystals, as shown in Figures 4(C) and 4(D).

[0051] To examine the nucleation dynamics on structured surfaces, density functional theory (DFT) calculations were performed. Figures 6(A) and 6(B) show the bonding characteristics of WSe2 on HfO2 based on DFT calculations. Figure 6(A) shows the calculated bond energy between WSe2 and a-HfO2 or c-HfO2 plotted against the edge length of WSe2. Figure 6(B) is a schematic diagram illustrating two nucleation scenarios: i) basal contact with a-HfO2 plus edge contact with SiO2, and ii) basal contact only with a-HfO2 (see top panel). The graph shows the calculated bond energy versus the edge length of WSe2 under edge and center contact conditions (see top panel). DFT analysis revealed that the amorphous nature of HfO2 at temperatures below 400 °C promotes nucleation at the trench edges. Figure 6(A) shows that the TMD bonds on amorphous a-HfO2 are significantly weaker than on crystalline (c)-HfO2. As a result, nucleation at the edge of SiO2 is further promoted, resulting in a 35% increase in edge bonding energy, as shown in the graph in Figure 6(B).

[0052] Figures 7(A) to 7(C) show the low-temperature growth of single-crystalline WSe. The SEM images show the initial nucleation of single-crystalline WSe within patterned SiO pockets formed on a HfO substrate at T, T, and T, respectively. growth are shown under the conditions of 700°C (Fig. 7(A)), 485°C (Fig. 7(B)), and 385°C (Fig. 7(C)), and T growthIt is emphasized that the initial nucleation probability increases near the pocket edge as the temperature decreases. Figure 7(A) shows experimental results of the nucleation tendency of WSe2 at 700 °C. As shown in Figure 7(B), nucleation shifts dramatically from the center to the edge at 485 °C. Finally, all nuclei form at the edge of the SiO2 trench at 385 °C (Figure 7(C)). Figure 7(D) shows an SEM image of single-crystalline WSe2 grown at 385 °C in a confined state. In Figure 7(D), further growth at such a low temperature results in the formation of limited single-domain TMDs because the trench size is small enough that lateral TMD growth is completed within a very short time frame before secondary nucleation occurs. Notably, TMD quality is maintained even at 385 °C due to its single-crystalline nature, and this temperature is low enough to maintain the performance of modern electronic logic and memory circuits.

[0053] It is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific embodiments described above, which are disclosed by way of example only.

[0054] While various inventive embodiments have been described and illustrated herein, those skilled in the art will readily envision various other means and / or structures for performing the functions and / or obtaining the results and / or obtaining one or more of the advantages described herein, and each such variation and / or modification is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will understand that all parameters, dimensions, materials, and configurations described herein are intended to be exemplary, and that the actual parameters, dimensions, materials, and / or configurations will depend on the application in which the inventive teachings are used. Those skilled in the art will recognize or be able to ascertain, using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. Accordingly, the foregoing embodiments are presented by way of example only, and it should be understood that, within the scope of the appended claims and their equivalents, inventive embodiments may be implemented otherwise than as specifically described and claimed. The inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods is included within the inventive scope of the present disclosure, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent.

[0055] Also, various inventive concepts may be embodied as one or more methods, examples of which are provided. The acts performed as part of a method may be ordered in any suitable manner. Thus, embodiments may be constructed such that the acts are performed in an order different from that shown, and may include performing some acts simultaneously, even though shown as sequential acts in the exemplary embodiments.

[0056] All definitions, as defined and used herein, should be understood to supersede dictionary definitions, definitions incorporated herein by reference, and / or ordinary meanings of the defined terms.

[0057] The indefinite articles "a" and "an," as used herein in the specification and claims, unless clearly indicated to the contrary, should be understood to mean "at least one."

[0058] The term "and / or," as used herein in the specification and claims, should be understood to mean "either or both" of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with "and / or" should be construed in the same manner, i.e., "one or more" of the elements so conjoined. Other elements other than the elements specifically identified by the "and / or" clause may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to "A and / or B," when used in conjunction with open-ended language such as "comprising," may in one embodiment refer to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements), etc.

[0059] As used herein in the specification and claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" shall be construed as inclusive, i.e., the inclusion of at least one of a plurality of elements or a list of elements, but may include more than one, and optionally including additional unlisted items. Only terms clearly indicated to the contrary, such as "only one of" or "exactly one of," or, as used in the claims, "consisting of," shall refer to the inclusion of exactly one element of a plurality of elements or a list of elements. In general, the term "or" as used herein shall only be construed as indicating exclusive alternatives (i.e., "either one of, but not both") when preceded by terms of exclusivity, such as "either," "one of," "only one of," or "exactly one of." "Consisting essentially of," when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0060] As used herein in the specification and claims, the phrase "at least one," in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed in the list of elements, and not excluding any combination of elements in the list of elements. This definition also allows for elements other than those specifically identified in the list of elements to which the phrase "at least one" refers, whether related or unrelated to those specifically identified elements, may optionally be present. Thus, as a non-limiting example, "at least one of A and B" (or, equivalently, "at least one of A or B" or, equivalently, "at least one of A and / or B") can refer in one embodiment to at least one, optionally two or more, As, and no Bs (and optionally including elements other than B); in another embodiment to at least one, optionally two or more, Bs, and no As (and optionally including elements other than A); in yet another embodiment to at least one, optionally two or more, As, and at least one, optionally two or more, Bs (optionally including other elements); etc.

[0061] In the claims and the above specification, all transitional phrases, such as "comprising," "including," "carrying," "having," "containing," "involving," "holding," and "composed of," are understood to be open-ended, i.e., meaning including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively, as set forth in the U.S. Patent Office Manual of Patent Examining Procedures, Section 2111.03.

[0062] [Conclusion] The above embodiments illustrate systems and methods for effectively implementing low-temperature single-crystalline 2D material growth using trench patterns. While various preferred embodiments have been shown and described, it will be understood that no limitation of the invention is intended by such disclosure, but rather, the disclosure is intended to cover all modifications within the spirit and scope of the invention as defined by the appended claims.

Claims

1. 1. A method comprising: (a) providing a substrate of a first material; (b) depositing a mask material onto the substrate; (c) forming a trench in the mask material, the trench having a trench shape with lateral dimensions l x w, where l and w are each selected to have a maximum dimension of 2 μm, and the trench having an exposed portion of the substrate surrounded by sidewalls formed of the mask material; (d) depositing adatoms of a second material on the exposed portion of the substrate at a low temperature; (e) allowing the adatoms to selectively nucleate at the low temperature on nuclei within the trenches; and (f) growing the nuclei in the trenches at the low temperature; Including, wherein the lateral dimensions associated with the trench shape and the low temperature limit the growth of the nuclei to a single domain monolayer of the second material; The low temperature is less than 705°C; the trench shape and the low temperature confine the growth of the second material as a single crystal within the trench and prevent growth of the second material outside the trench; method.

2. The method of claim 1 , wherein the low temperature is less than 400° C.

3. The method of claim 1 , comprising forming a semiconductor device comprising the single-domain monolayer.

4. 4. The method of claim 3, wherein the semiconductor device comprises one of a valleytronics device, a fork-sheet field effect transistor (FET), a complementary FET, a gate-all-around FET (GAAFET), or a multi-bridge channel (MBCFET).

5. The method of claim 1 , wherein a first bond energy between the first material and the second material is greater than a second bond energy between the mask material and the second material.

6. The first material is hafnium oxide (HfO ２ ), aluminum oxide (Al ２ O ３ ), hafnium zirconium oxide (HZO), titanium dioxide (TiO ２ ), zinc oxide (ZnO), iron oxide (Fe ２ O ３ ), tin oxide (SnO ２ ), nickel oxide (NiO), or copper oxide (CuO).

7. 10. The method of claim 1, wherein the second material comprises one of graphene, carbon nanotubes (CNTs), hexagonal boron nitride (h-BN), metallic transition metal dichalcogenides, semiconducting transition metal dichalcogenides, or high dielectric constant materials.

8. The metallic transition metal dichalcogenide is vanadium disulfide (VS ２ ), vanadium diselenide (VSe ２ ), cobalt sulfide (CoS ２ ), cobalt selenide (CoSe ２ ), titanium disulfide (TiS ２ ), or titanium diselenide (TiSe ２ 8. The method of claim 7, wherein the method is one of:

9. The semiconducting transition metal dichalcogenide is molybdenum disulfide (MoS ２ ), molybdenum diselenide (MoSe ２ ), tungsten disulfide (WS ２ ), or tungsten diselenide (WSe ２ 8. The method of claim 7, wherein the method is one of:

10. The high dielectric constant material is Bi ２ SeO ５ or Sb ２ O ３ 8. The method of claim 7, wherein the step of:

11. The mask material is amorphous silicon dioxide (a-SiO ２ ), amorphous silicon (a-Si), amorphous silicon nitride (a-SiN ｘ ), amorphous carbon (a-carbon), hafnium oxide (HfO ２ ), aluminum oxide (Al ２ O ３ ), hafnium zirconium oxide (HfZrO), titanium dioxide (TiO ２ ), zinc oxide (ZnO), iron oxide (Fe ２ O ３ ), tin oxide (SnO ２ ), nickel oxide (NiO), or copper oxide (CuO).

12. 1. A method comprising: (a) providing a substrate of a first material; (b) depositing a first mask material onto the substrate; (c) forming a first trench in the first mask material, the first trench having a lateral dimension of 1. １ ×w １ and a first trench shape of l １ and w １ are each selected to have a maximum dimension of 2 μm, and the first trench has a first exposed portion of the substrate surrounded by sidewalls formed of the first mask material; (d) depositing, at low temperature, first adatoms of a second material onto the first exposed portion of the substrate; (e) allowing the first adatoms to selectively nucleate onto first nuclei within the first trench at the low temperature; (f) growing the first nuclei in the first trench at the low temperature, wherein the lateral dimensions associated with the first trench shape and the low temperature limit the growth of the first nuclei to a first single-domain monolayer of the second material; (g) waiting for an incubation period; (h) forming a first source electrode contact on one side of the first trench and a first drain electrode contact on the other side of the first trench; (i) depositing a first dielectric layer on top of the structure formed in steps (a)-(h); (j) forming a gate electrode in the first dielectric layer; (k) depositing a second dielectric layer on top of the structure formed in steps (a)-(j); (l) depositing a second mask material over the second dielectric layer; (m) forming a second trench in the second mask material, the second trench having a lateral dimension of 1. ２ ×w ２ and a second trench shape of l ２ and w ２ are each selected to have a maximum dimension of 2 μm, and the second trench has a second exposed portion of the second mask material surrounded by sidewalls formed of the second mask material; (n) depositing second adatoms of a third material on the second exposed portions of the second mask material at the low temperature; (o) allowing the second adatoms to selectively nucleate onto second nuclei within the second trench at the low temperature; (p) growing the second nuclei in the second trench at the low temperature, wherein the lateral dimensions associated with the second trench shape and the low temperature limit the growth of the second nuclei to a second single-domain monolayer of the third material; (q) forming a second source electrode contact on one side of the second trench and a second drain electrode contact on the other side of the second trench; (r) forming an encapsulation layer on top of the structure formed in (a) through (q); Including, wherein the first single-domain monolayer and the second single-domain monolayer form a bilayer at the low temperature; The low temperature is less than 400°C; the low temperature and the first trench shape confine the growth of the second material as a single crystal within the first trench and prevent the growth of the second material outside the first trench, and the low temperature and the second trench shape confine the growth of the third material as another single crystal within the second trench and prevent the growth of the third material outside the second trench; method.

13. 13. The method of claim 12, wherein the first material has a first Gibbs free energy and the mask material has a second Gibbs free energy, the second Gibbs free energy being higher than the first Gibbs free energy.

14. The first material is hafnium oxide (HfO ２ ), aluminum oxide (Al ２ O ３ ), hafnium zirconium oxide (HZO), titanium dioxide (TiO ２ ), zinc oxide (ZnO), iron oxide (Fe ２ O ３ ), tin oxide (SnO ２ ), nickel oxide (NiO), or copper oxide (CuO).

15. 13. The method of claim 12, wherein either the second material or the third material is selected from any of graphene, carbon nanotubes (CNTs), hexagonal boron nitride (h-BN), metallic transition metal dichalcogenides, semiconducting transition metal dichalcogenides, or high dielectric constant materials, or combinations thereof.

16. The metallic transition metal dichalcogenide is vanadium disulfide (VS ２ ), vanadium diselenide (VSe ２ ), cobalt sulfide (CoS ２ ), cobalt selenide (CoSe ２ ), titanium disulfide (TiS ２ ), or titanium diselenide (TiSe ２ 16. The method of claim 15, wherein the

17. The semiconducting transition metal dichalcogenide is molybdenum disulfide (MoS ２ ), molybdenum diselenide (MoSe ２ ), tungsten disulfide (WS ２ ), or tungsten diselenide (WSe ２ 16. The method of claim 15, wherein the

18. The high dielectric constant material is Bi ２ SeO ５ or Sb ２ O ３ 16. The method of claim 15, wherein the

19. Either the first mask material or the second mask material is amorphous silicon dioxide (a-SiO ２ ), amorphous silicon (a-Si), amorphous silicon nitride (a-SiN ｘ ), amorphous carbon (a-carbon), hafnium oxide (HfO ２ ), aluminum oxide (Al ２ O ３ ), hafnium zirconium oxide (HfZrO), titanium dioxide (TiO ２ ), zinc oxide (ZnO), iron oxide (Fe ２ O ３ ), tin oxide (SnO ２ 13. The method of claim 12, wherein the oxide is selected from any one of nickel oxide (NiO), nickel oxide (NiO), or copper oxide (CuO), or a combination thereof.

20. 13. The method of claim 12, wherein the bilayer is a heterojunction bilayer in which the second material and the third material are different from one another.

21. 13. The method of claim 12, wherein the bilayer is a homojunction bilayer in which the second material and the third material are similar to each other.

22. The method of claim 12 , comprising forming a semiconductor device comprising the first single-domain monolayer and the second single-domain monolayer.

23. 23. The method of claim 22, wherein the semiconductor device comprises one of a valleytronic device, a fork-sheet field effect transistor (FET), a complementary FET, a gate-all-around FET (GAAFET), or a multi-bridge channel (MBCFET).

24. l １ =l ２ , and w １ =w ２ The method of claim 12, wherein

Images