Enhancement-mode GaN devices with hole-removal electrodes

Abstract

An enhancement-mode gallium nitride (GaN) transistor includes a p-type gate configured to remove holes that accumulate under the gate metal. The gate has two electrodes: a gate electrode and a hole collector electrode. In a preferred embodiment, a negative voltage is applied to the hole collector electrode, attracting holes that accumulate under the gate metal. The attracted holes recombine with electrons supplied by the negative voltage, thereby substantially removing the holes.

Description

[Technical Field]

[0001] The present invention relates to the field of columnar III-nitride transistors, such as gallium nitride (GaN) transistors. [Background technology]

[0002] Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices due to their ability to carry large currents and support high voltages. The development of these devices is generally aimed at high-power / high-frequency applications. Devices fabricated for these types of applications exhibit high electron mobility and are based on a common device structure variously referred to as a heterojunction field-effect transistor (HFET), high-electron mobility transistor (HEMT), or modulation-doped field-effect transistor (MODFET).

[0003] GaN HEMT devices contain nitride semiconductors with at least two nitride layers. The layers have different bandgaps due to the different materials formed on the semiconductor or buffer layer. The different materials in adjacent nitride layers also create polarization, which contributes to a conductive two-dimensional electron gas (2DEG) region near the junction of the two layers, especially in the layer with the narrower bandgap.

[0004] The nitride layer that creates the polarization typically includes an AlGaN barrier layer adjacent to the GaN layer to contain the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate with zero gate bias, nitride devices are essentially normally-on or depletion-mode devices. If the 2DEG region is depleted, or eliminated, under the gate with zero applied gate bias, the device is an enhancement-mode device. Enhancement-mode devices are normally-off and are desirable because of the additional safety they offer and because they are easier to control using simple, low-cost drive circuitry. Enhancement-mode devices require a positive bias applied to the gate to conduct current.

[0005] Figure 1 is a cross-sectional view of an enhancement-mode GaN transistor disclosed and claimed in U.S. Patent No. 8,890,168. The GaN device of Figures 1A and 1B includes a silicon substrate 10, a transition layer 12, an undoped GaN buffer material 13, an undoped AlGaN barrier layer 14, a p-type GaN gate material 15, a gate metal 17, a dielectric material 18, a drain ohmic contact 19, and a source ohmic contact 20.

[0006] Like all enhancement-mode GaN transistors, the GaN device of Figure 1 conducts current from drain 19 to source 20 when the drain is biased positively with respect to the source and a positive voltage is applied to the gate. However, as shown in Figure 1, under high-voltage drain bias, holes generated in the drain region (or other regions of the device where a high electric field exists) drift toward the gate and become trapped or confined within the p-type GaN gate layer. Holes can also be generated in the gate region itself. Over time, these holes accumulate under the gate metal, resulting in a low threshold voltage and high leakage current between the drain and source when the device is off. It would be desirable to provide an enhancement-mode GaN transistor in which these holes that accumulate under the gate metal are eliminated. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent No. 8,890,168 Summary of the Invention

[0008] The present invention advantageously provides an enhancement-mode GaN transistor that includes a feature that attracts holes that accumulate under the gate metal and continuously removes them from the gate region. Holes are removed from the gate region by one of several transport processes, including, but not limited to, (1) recombination of holes with electrons, thereby neutralizing the holes; (2) thermionic emission of holes onto Schottky metal contacts, preferably contacts biased with a negative voltage to enhance emission; and (3) tunneling or injection of holes across ohmic contacts. Using any of the above, holes are removed from the gate region to allow the device to withstand higher voltages.

[0009] The gate is made of p-type GaN material and has two electrodes: a gate electrode and a hole collector electrode. The hole collector electrode may form either a Schottky or an ohmic contact with the underlying p-type GaN material. The hole collector electrode is disposed on top of the p-type GaN gate material and may extend into or through the p-type GaN gate material. The p-type GaN material below the hole collector electrode may be thinner than the p-type GaN material below the gate electrode. In a preferred embodiment of the present invention, a negative voltage is applied to the hole collector electrode such that holes accumulated below the gate are attracted to and recombine with electrons provided by the negative voltage connected to the hole collector electrode, thereby substantially removing the holes accumulated below the gate.

[0010] The negative voltage supplied to the hole collector electrode can be generated by a negative voltage generating circuit implemented in GaN and integrated with an enhancement mode GaN transistor.

[0011] The features, objects, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief explanation of the drawings]

[0012] [Figure 1] 1 shows a cross-sectional view of a prior art enhancement mode GaN transistor. [Figure 2] FIG. 2 is a top view of the prior art GaN device of FIG. [Figure 3] 1 shows a top view of a first embodiment of a GaN device of the present invention. [Figure 4A] 1 shows a cross-sectional view of a first embodiment of the present invention. [Figure 4B] 1 shows a top view of a first embodiment of the present invention. [Figure 5] 3 and 4A / 4B, where the contact metal contacts the p-type GaN gate material on top and on the p-GaN sidewalls. [Figure 6]10 shows an alternative arrangement in which the gate lines form a racetrack surrounding the drain contact. [Figure 7A] 1 shows various possible connections of the hole collector metal to p-type GaN. [Figure 7B] 1 shows various possible connections of the hole collector metal to p-type GaN. [Figure 7C] 1 shows various possible connections of the hole collector metal to p-type GaN. [Figure 7D] 1 shows various possible connections of the hole collector metal to p-type GaN. [Figure 8] 1 shows a depletion mode GaN FET configured as a linear power supply in a negative voltage generating circuit of the present invention. [Figure 9] 1 shows a depletion mode GaN FET in the sensor circuit of a voltage generation circuit. [Figure 10] FIG. 2 is a circuit diagram of a charge pump circuit of the negative voltage generating circuit. [Figure 11] FIG. 2 is a circuit diagram of the entire negative voltage generating circuit. DETAILED DESCRIPTION OF THE INVENTION

[0013] In the following detailed description, reference is made to specific embodiments. This detailed description is intended merely to teach those skilled in the art further details for implementing preferred aspects of the present teachings, and is not intended to limit the scope of the claims. Therefore, the combinations of features disclosed in the following detailed description are not necessarily intended to embody the teachings in the broadest sense, but are merely intended to illustrate particularly representative examples of the present teachings. It should be understood that other embodiments may be employed, and that various structural, logical, and electrical changes may be made.

[0014] Figure 2 is a top view of the prior art GaN device of Figure 1, showing gate metal 30 disposed between ohmic contacts 19, 20 for the drain (D) and source (S), respectively. Gate metal 30 is not visible in the top view of Figure 2 because it is disposed entirely on top of the p-type GaN gate material.

[0015] 3 shows a top view of a first embodiment of a GaN device of the present invention, including a hole collector metal contact feature for removing holes that accumulate under the gate metal. In a preferred embodiment of the present invention, the holes are removed by recombining with electrons. As disclosed in more detail below, the electrons are supplied by a negative voltage generating circuit and injected into the p-type gate material of the enhancement mode GaN device.

[0016] As shown in the center portion of the top view of FIG. 3 , the p-type GaN gate material is formed from three portions: (1) a portion where gate metal 30 is disposed on top of the p-type GaN gate material of the gate line; (2) a portion where hole collector electrode 32 contacts the p-type GaN gate material, as disclosed in further detail below with reference to FIGS. 7A-7D ; and (3) a portion 34 where the p-type GaN gate material does not have metal thereon, i.e., a space 34 that exists between gate metal 30 and hole collector metal 32.

[0017] The p-type GaN gate material under the contact metal in portion 32 may be thinner than the p-type GaN gate material of gate line 30 (as in the recessed embodiment shown in FIG. 7B). Similarly, bridge portion 34 of the p-type GaN gate material can have the same thickness as the p-type GaN gate material of gate line 30, or can be thinner than the gate line.

[0018] A cross-sectional view of a first embodiment of the present invention is shown in Figure 4A. The gate metal 30 is preferably TiN. The hole collector metal 32 may be formed of the same metal as the gate metal 30, or a different metal. The hole collector metal 32 contact to the p-type GaN gate material 15 preferably has a lower barrier height than the gate metal contact contact to the p-type GaN gate material 15, attracting holes and, in preferred embodiments, serving as a preferential site for mutualizing holes and electrons.

[0019] There are several mechanisms by which holes can be removed from the gate. 1. Direct implantation into p-type GaN using ohmic contact metal. 2. Tunneling through a Schottky contact. 3. Surface and sidewall recombination. 4. Thermionic emission on a Schottky contact, preferably assisted by a negative voltage applied to the metal.

[0020] 3 and 4A / 4B , with the hole removal mechanism 3 described above, in which the hole collector metal 50 contacts the p-type GaN gate material on top and on the p-GaN sidewalls. Contacting the sidewalls in addition to contacting the top surface of the p-GaN facilitates hole and electron recombination by increasing the contact surface area and providing a lower resistance (lower barrier height) connection for applying a hole collection voltage.

[0021] 6 shows an alternative arrangement in which the gate line 30 forms a racetrack surrounding the drain contact 19. In this embodiment, the p-type GaN (reference numeral 60) without an overlying metal contact and the metal 62 contacting the p-type GaN are both positioned outside the racetrack.

[0022] 7A-7D illustrate various possible connections of the hole collector metal 32 to the p-type GaN 15. FIG. 7A illustrates an embodiment in which the hole collector metal contacts the top surface of the p-type GaN gate material 15. FIG. 7B illustrates an embodiment in which the hole collector metal extends into a recess in the p-type GaN 15. FIG. 7C illustrates an embodiment in which the hole collector metal extends completely through the p-type GaN 15. FIG. 7D illustrates an embodiment in which a thin insulator 70, such as Si3N4, AlN, or Al2O3, is disposed between the metal contacts 30, 32 and the p-type GaN 15. In this embodiment, mobile holes tunnel from the p-type GaN 15 through the insulator 70 to the hole collector metal 32. A fifth embodiment, not shown, is a combination of the embodiments of FIGS. 7B and 7D, in which the hole collector metal extends through the insulator 70 into a recess in the p-type GaN 15.

[0023] According to the present invention, the hole collector metal 32 may be connected to the source 20 of the GaN device. More preferably, to improve hole removal, the hole collector metal 32 is connected to a negative voltage. The negative voltage may be provided externally via an I / O terminal, or more preferably, internally via an integrated GaN circuit that generates the negative voltage.

[0024] Next, we describe a preferred embodiment of an internal negative voltage generation circuit (Figure 11). This circuit is implemented entirely in GaN so that it can be integrated with GaN transistors, and uses a charge pump (Figure 10) to generate the negative voltage. The circuit generates a negative voltage in the range of -2V to -14V with extremely low current consumption of less than 10µA.

[0025] The internal voltage generation circuit uses a depletion-mode GaN FET 80 as a linear power supply. As shown in Figure 8, the enhancement-mode GaN FET is changed to a depletion-mode GaN FET. By connecting the gate to ground and applying a voltage greater than the absolute value of the threshold voltage Vth to the drain of the GaN FET 80, the source of the GaN FET 80 generates a supply voltage of 14V, which is approximately equal to the absolute value of the threshold voltage of the GaN FET 80. Therefore, the source generates a supply voltage of approximately -14V.

[0026] To reduce the total current the circuit can sink from the power supply to 10 μA, a circuit is included that senses negative voltages and activates the charge pump only when necessary. As shown in FIG. 9, the sensor circuit includes a depletion-mode GaN FET 90 with its gate connected to the negative output of the voltage generator circuit of FIG. 9 (see FIG. 11). The GaN FET 90 of FIG. 9 functions as an up-level shifter. The voltage at the source of the GaN FET 90 is equal to the negative output of the voltage generator circuit plus the absolute value of the threshold voltage (approximately 14 V). As described below with respect to the complete circuit of FIG. 11, the charge pump (FIG. 10) is activated when the negative output of the voltage generator circuit plus 14 V, subtracted by Voffset, and multiplied by a factor R1 / (R1+R2) is greater than the threshold voltage of the inverter 120.

[0027] The operation of the charge pump circuit 100 shown in FIG. 10 is as follows. In steady state, the charge pump enhancement-mode GaN FET 102 is off, the top plate of the charge pump capacitor 104 is charged to a low-voltage (LV) supply by resistor 105, and the bottom plate of the charge pump capacitor 104 is near ground due to diode 106. The charge pump is activated by turning on the GaN FET 102. When the GaN FET 102 conducts, the top plate of the capacitor 104 is pulled to ground and the bottom plate of the capacitor 104 is pulled below ground. At this point, diode 106 turns on, and the negative output of the voltage generation circuit is also pulled below ground. The diodes 106 and 108 in the circuit of FIG. 10 can be pn junction diodes, Schottky diodes, or diode-connected GaN FETs.

[0028] The operation of the sensing circuit will now be described with reference to FIG. 11, which shows the overall negative voltage generating circuit 110. FET 80 in depletion mode generates a low voltage power supply for the circuit. FET 90 in depletion mode senses the negative voltage generated by charge pump circuit 100. The source of FET 90 is approximately 14 V higher than the gate. The source voltage can be lowered by a voltage offset (Voffset) through FET 112, connected to the drain via the gate, to reduce current consumption, and charges capacitor 114 through a voltage divider formed by resistors R1 and R2.

[0029] Voltage of capacitor 114

number

[0030] The above description and drawings should be considered to be merely illustrative of specific embodiments that achieve the features and advantages described herein, and therefore, embodiments of the present invention should not be considered limited by the foregoing description and drawings. More generally, it should be understood that the present disclosure and exemplary embodiments have been described above with reference to examples in the accompanying drawings, but are not limited thereto. Rather, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in many ways without departing from the scope of the disclosure herein. Moreover, the terms and descriptions used herein are set forth for purposes of illustration only and are not meant to be limiting. Those skilled in the art will recognize that many variations are possible within the spirit and scope of the present disclosure, as defined in the following claims and their equivalents, and that, unless otherwise specified, all terms should be understood in the broadest possible sense. [Explanation of symbols]

[0031] 10 Silicon substrate 12 Transition layer 13 Undoped GaN buffer material 14 Undoped AlGaN barrier layer 15 p-type GaN gate materials 17 Gate Metal 18 Dielectric Materials 19 Drain ohmic contact 20 Source Ohmic Contact 30 Gate Metal 32 Hole collector metal 34 Space 50 Hole collector metal 60 p-type GaN 62 metal 70 Insulator 80, 90, 102, 112, 118 GaN FETs 100 Charge Pump Circuit 104 Charge Pump Capacitor 105 resistor 106, 108 Diodes 110 Negative voltage generation circuit 114 Capacitor 116, 120 inverter R1, R2 resistor

Claims

1. An enhancement-mode gallium nitride (GaN) transistor, comprising: The source, gate, and drain Equipped with the gate includes a p-type GaN material, a gate electrode, and a hole collector electrode for removing holes accumulated under the gate electrode; Enhancement-mode gallium nitride (GaN) transistors.

2. 10. The enhancement-mode gallium nitride (GaN) transistor of claim 1, wherein when a negative voltage is applied to the hole collector electrode, holes accumulated under the gate electrode recombine with electrons provided by the negative voltage connected to the hole collector electrode, thereby substantially removing the holes accumulated under the gate electrode.

3. 2. The enhancement-mode gallium nitride (GaN) transistor of claim 1, wherein the gate electrode and the hole collector electrode are disposed on the p-type GaN material, and the hole collector electrode is laterally spaced from the gate electrode.

4. The enhancement-mode gallium nitride (GaN) transistor of claim 3 , wherein the hole collector electrode contacts a top surface of the p-type GaN material.

5. The enhancement-mode gallium nitride (GaN) transistor of claim 3 , wherein the hole collector electrode extends into a recess in the p-type GaN material.

6. The enhancement-mode gallium nitride (GaN) transistor of claim 3 , wherein the hole collector electrode extends completely through the p-type GaN material.

7. The enhancement-mode gallium nitride (GaN) transistor of claim 3 , wherein an insulator is disposed between the hole collector electrode and the p-type GaN material.

8. The enhancement-mode gallium nitride (GaN) transistor of claim 1 , wherein the hole collector electrode is electrically connected to the source.

9. The enhancement-mode gallium nitride (GaN) transistor of claim 1 , wherein the hole collector electrode is electrically connected to a negative voltage generating circuit.

10. 10. The enhancement-mode gallium nitride (GaN) transistor of claim 9, wherein the negative voltage generating circuit is implemented in GaN and integrated with the transistor.

11. The enhancement-mode gallium nitride (GaN) transistor of claim 10 , wherein the negative voltage generation circuit comprises a charge pump for generating a negative voltage.

12. 12. The enhancement-mode gallium nitride (GaN) transistor of claim 11, wherein the negative voltage generation circuitry comprises circuitry for sensing the negative voltage and for activating the charge pump as needed.

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