String driver connection structure for wafer-on-wafer packaging

Abstract

The present disclosure relates to a semiconductor device assembly, the assembly including a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, each of which includes a field-effect transistor (FET), a global word line connected to a source of the FET, and a local word line extending vertically through the FET. The assembly further includes a second wafer having a memory array including a plurality of word lines, each of which is connected to a corresponding string driver of the first wafer through a local word line of the corresponding string driver. The backside of the first wafer is bonded to the front side of the second wafer, thereby forming a wafer-on-wafer (WOW) bond.

Description

[Technical Field]

[0001] The present disclosure relates to string drivers, and more particularly to direct connection of source and drain of string drivers in wafer-on-wafer (WOW) packaging. [Background technology]

[0002] Microelectronic devices typically include a wafer, such as a complementary metal-oxide semiconductor wafer (CMOS wafer), bonded with a memory array wafer to form a wafer-on-chip (WOW) structure. The CMOS wafer and memory array wafer may be further mounted on a package substrate or carrier wafer and covered with a protective cover. The CMOS wafer may include integrated circuits with a high density of very small components, including processor circuits, imager devices, string drivers, and / or high-voltage (HV) circuits. Meanwhile, the memory array wafer may include memory arrays, including NAND flash memory arrays, dynamic random access memory (DRAM) arrays, and / or phase-change memory (PCM) arrays. These memory arrays are connected to the HV circuits of the CMOS wafer for the transmission of data and control signals. The conventional CMOS wafer and memory array wafer bonding process includes electrically connecting the HV circuitry of the CMOS wafer and the memory array through string driver circuits, and forming hybrid bonds at the interface between the surface of the CMOS wafer and the surface of the memory array wafer to form pad-over-array (POA, front-to-front bonding) or pad-over-CMOS (POC, front-to-front bonding) WOW packaging. [Brief explanation of the drawings]

[0003] [Figure 1] 1 is a schematic diagram of WOW bonding for assembling a semiconductor device according to an embodiment of the present technology; [Figure 2] FIG. 1 is a schematic diagram of a string driver in conventional WOW packaging. [Figure 3A]FIG. 1 is a schematic diagram of string drivers in which local word lines are arranged between adjacent string drivers. [Figure 3B] FIG. 1 is a schematic diagram of a string driver with a local word line passing therethrough, according to an embodiment of the present technology. [Figure 4A] 1 is a schematic diagram of a CMOS wafer to be subjected to a WOW bonding method according to an embodiment of the present technology. [Figure 4B] 1A-1C are schematic diagrams of a CMOS wafer and a memory array wafer before a WOW bonding process, according to an embodiment of the present technology. [Figure 4C] 1 is a schematic diagram of WOW packaging including a CMOS wafer and a memory array wafer, according to an embodiment of the present technology; [Figure 5] 1A and 1B are plan views of various string drivers according to embodiments of the present technology; [Figure 6A] 1 is a cross-sectional view of a string driver including a corresponding local word line according to an embodiment of the present technology. [Figure 6B] 1 is a cross-sectional view of a string driver including corresponding global word lines according to an embodiment of the present technology. [Figure 7] 1A-1C are plan views of string driver columns having various shallow trench isolation and local deep trench isolation configurations in accordance with embodiments of the present technology; [Figure 8] 1 is a flowchart illustrating a method for processing WOW bonds for fabricating semiconductor devices, according to an embodiment of the present technology. [Figure 9] 1 is a schematic diagram of a system including a semiconductor device according to an embodiment of the present technology; DETAILED DESCRIPTION OF THE INVENTION

[0004] The drawings depict only exemplary embodiments and therefore should not be construed as limiting the scope of the present disclosure. The elements and features shown in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of construction of exemplary embodiments. Additionally, certain dimensions and arrangements may be exaggerated to help visually communicate such principles. In the drawings, the same reference numerals in different embodiments refer to similar or corresponding, but not necessarily identical, elements.

[0005] WOW packaging typically separates the manufacturing processes for CMOS devices and memory arrays. For example, CMOS devices are fabricated on a CMOS wafer, while the memory array is fabricated on a separate memory array wafer, eliminating thermal constraints between the two processes. This separation allows the CMOS devices to be fabricated at higher temperatures than the memory array wafer, improving device performance. Furthermore, the CMOS wafer and memory array wafer can be bonded at some stage in the manufacturing process after completing their respective front-end-of-line (FEOL) processes.

[0006] FIG. 1 shows a schematic diagram of a WOW bonding scheme 100 for fabricating semiconductor devices in accordance with an embodiment of the present technology. The WOW structure includes a CMOS wafer 110, a memory array wafer 120, and a carrier wafer 130. As shown, the CMOS wafer 110 is bonded onto the memory array wafer 120, which is further mounted on the carrier wafer 130. In this WOW bonding scheme 100, the backside of the CMOS wafer 110 is bonded to the frontside of the memory array wafer 120 using a direct bonding technique, such as dielectric-dielectric fusion bonding with strong covalent bonds. The CMOS wafer may include a substrate 111, multiple CMOS devices 112 disposed in or on the substrate 111, multiple metal wiring layers 113, and multiple bonding pads 115 disposed on the front side of the CMOS wafer 110. Meanwhile, memory array wafer 120 may include memory array 121, a plurality of bit lines 122 extending vertically through memory array 121, and a plurality of bonding pads 123 connected to each bit line 122. Notably, CMOS wafer 110 and memory array wafer 120 include dielectric layers 116 and 125 disposed on their back and front surfaces, respectively. These dielectric layers 116 and 125 provide electrical insulation between the components included in CMOS wafer 110 and memory array wafer 120. A direct bonding interface between CMOS wafer 110 and memory array wafer 120 through fusion bonding may be formed by bringing dielectric layers 116 and 125 into close contact and applying heat or pressure therebetween.

[0007] As shown in FIG. 1 , WOW bonding scheme 100 further includes electrical contacts 114 electrically connecting each layer of metal interconnect layer 113 to a corresponding layer of multiple metal layers 124 for transmitting high-voltage and control signals from CMOS wafer 110 to memory array wafer 120. Electrical contacts 114 are configured to transmit high-voltage or data signals to bit lines 122 or word lines (not shown) in the memory array to enable key operations such as reading and writing flash pages and erasing memory blocks. In this example, final metal layers, such as metal interconnect layer 113 of the CMOS wafer (e.g., formed at relatively low processing temperatures (e.g., on the order of 300° C.)), may be processed after the WOW direct bonding step. In some embodiments, it is desirable for the size of the CMOS wafer to be no larger than the corresponding memory array wafer for cost reduction and packaging process control.

[0008] The WOW packaging approach typically utilizes multiple string drivers disposed within a CMOS wafer to transmit voltages from high-voltage (HV) circuits to corresponding word lines of the memory arrays of the memory array wafer. FIG. 2 shows a schematic diagram of an example of multiple string drivers 200 disposed near the backside of a CMOS wafer 210. This example includes two string drivers 212 with a common drain region. Each string driver is a high-voltage transistor with gate electrodes 218a and 218b, respectively. In this example, the two string drivers 212 share a common global word line (GWL) 216 connecting the common drain region to the high-voltage circuitry. Furthermore, each string driver 212 has a dedicated local word line (LWL) 214a and 214b, respectively, connecting the source region of the string driver transistor to a corresponding word line of the memory array.

[0009] In a conventional single-wafer configuration, the gate and low-level wiring layers (GWLs) all extend vertically from the string driver transistors to the metal layer of the CMOS wafer. The gate and low-level wiring layers further extend from the metal layer to the high-voltage circuitry for voltage signal transmission. Furthermore, the low-level wiring layers (LWLs) extend from the metal layer of the CMOS wafer to the memory array, e.g., to metal pads connected to the word lines of the memory array, to provide interconnect and voltage transmission paths between the string driver transistors and the memory array. As shown in Figure 2, the low-level wiring layers (LWLs) 214a and 214b extend through the dielectric region of the CMOS wafer and are located between adjacent string driver transistors. The interconnect density within such a CMOS wafer is constrained by string driver-specific requirements, such as isolation, high-voltage tolerance, and device performance.

[0010] FIG. 3A shows a schematic diagram of a string driver in which an LWL is disposed between adjacent string drivers in a conventional WOW packaging technique. For example, FIG. 3A shows two string driver transistors 312a and 312b horizontally aligned near the backside of a CMOS wafer 310. As shown, the backside of the CMOS wafer 310 is bonded to the front side of a memory array wafer 320. Furthermore, each string driver 312a and 312b is connected to a GWL and an LWL for transmitting control and data signals for the memory array. In this example, an LWL 316 connects the drain region of the string driver 312a to a metal pad of the memory array wafer 320. Specifically, the LWL 316 first extends from the top surface of the drain region toward the metal layer and then is routed through the metal layer to a metal pad 322 for transmitting a voltage signal. Here, the LWL 316 is disposed between the string driver transistors 312a and 312b and extends through the dielectric material between them. Such LWL configuration in conventional WOW packaging approach limits the pitch spacing of string drivers and requires isolation control between string drivers and adjacent LWL wiring.

[0011] To address the above-mentioned challenges and others, the present technology introduces a novel LWL connection in a WOW packaging structure. Specifically, the present technology configures the LWL to penetrate the string driver. Specifically, the LWL vertically penetrates the drain region of the string driver transistor, allowing voltage transfer from the transistor to a corresponding metal pad on the memory array wafer. For example, FIG. 3B shows a schematic diagram of a string driver having an LWL penetrating the drain region according to an embodiment of the present technology. As shown, a CMOS wafer 310′ is bonded to a memory array wafer 320′. The CMOS wafer 310′ includes two string driver transistors 312a′ and 312b′, each with an LWL 316a′ and 316b′ penetrating their respective drain regions. The LWLs 316a′ and 316b′ transfer voltage to metal pads 322a′ and 322b′ via the string driver transistors 312a′ and 312b′, respectively. This technology allows the distance between adjacent string drivers to be further reduced, enabling higher density CMOS devices, while providing better isolation for string driver devices with this configuration, preventing breakdown during high-voltage operation.

[0012] 4A shows a schematic diagram of a CMOS wafer 400 subjected to WOW bonding according to an embodiment of the present technology. The CMOS wafer 400 includes multiple string drivers, each having a gate electrode 408, a source region 404, a drain region 406, and a local deep trench (LDT) region 412. The multiple string drivers may be disposed, for example, at various locations on the surface of a substrate 402 of the CMOS wafer 400. Furthermore, the multiple string drivers may be covered by a dielectric layer 414 for electrical insulation.

[0013] In some embodiments, each of the multiple string drivers of the CMOS wafer 400 subjected to the WOW bonding method may be composed of a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, FIG. 4A shows an n-channel MOSFET in which a gate electrode 408 including a gate oxide layer 410 is disposed on the surface of a substrate 402. A source region 404 and a drain region 406 are disposed on either side of the gate 408. The gate electrode 408 may be composed of polysilicon, a silicide material, and / or a metal composite material such as tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). The gate oxide layer 410 is disposed below the gate electrode 408 and is configured to electrically isolate the gate electrode 408 from the source region 404 and the drain region 406 located directly below it. Typically, the gate oxide layer 410 may be formed by a thermal oxidation process using a high-k material such as SiO2, ZrO2, or HfO2. In an exemplary embodiment, the substrate 402 may be a p-type substrate (e.g., doped with boron and / or gallium). Additionally, the source region 404 may be an n-type doped N + Regions 404a and N - It may include region 404b. + Region 404a is n-type doped with phosphorus, arsenic, and / or antimony, and N - region 404b, which has a higher doping concentration than region 404b and is located below the surface of substrate 402 and is N - The drain region 406 is buried in the region 404b. + Regions 406a and N - region 406b, both of which are vertically aligned within the substrate 402. Specifically, N - Region 406b is N + The region 406a is n-type with a lower doping concentration than the region 406b. +In other embodiments, the string drivers may be p-channel MOSFETs, such as those with an n-type (doped with phosphorus, arsenic, and / or antimony) substrate and p-type (doped with boron and / or gallium) regions at the source 404 and drain 406. A p-channel MOSFET is similar to the N-type of the source and drain regions in an n-channel MOSFET. + Area and N - Similar to the configuration of the region, P + Area and P - It may include a region.

[0014] The string driver transistor shown in FIG. 4A is a voltage-controlled device configured to switch or amplify voltages within a string driver. The transistor has four terminals: a gate electrode 408, a source region 404, a drain region 406, and a substrate (body) 402. The upper surface of the substrate 402, i.e., the region below the gate oxide layer 410 and located between the source region 404 and the drain region 406, can be inverted from p-type to n-type by applying a positive gate voltage. In the example of an n-channel MOSFET shown in FIG. 4A, holes present below the gate oxide layer 410 are pushed downward, and the application of a positive gate voltage creates a depletion region due to the immobile negative charges from the acceptor atoms. A channel is then formed between the source region 404 and the drain region 406. In this state, current flows freely between the source region 404 and the drain region 406, and the gate voltage controls the electrons in the channel. In another embodiment, if the string driver includes p-type doped regions in the source and drain, applying a negative voltage to the gate can create a hole channel under the gate oxide layer 410.

[0015] Each of the plurality of string drivers also includes a global word line (GWL) 414 that connects the string driver to a high voltage (HV) circuit. The HV circuit may be located in a CMOS wafer that is subjected to a WOW bonding scheme and is connected to the string driver through multiple layers of metal wiring. Specifically, as shown in FIG. 4A, the GWL 414 is connected to an N + The GWL 414 is connected to the region 404a and transmits a voltage signal from the HV circuit to the source region of the string driver. In this technology, the GWL 414 can be formed by etching an insulating material above the MOSFET to create a formation space and filling it with a conductive material such as a metal or metal alloy. + Using region 404a for this connection significantly reduces the contact resistance between GWL 414 and the source region 404 of the MOSFET. - Region 404b acts as a voltage drop region that carries most of the applied source voltage and provides a potential gradient due to the increased on-resistance.

[0016] Additionally, adjacent to the drain region 406 of the MOSFET shown in FIG. 4A, each of the multiple string drivers includes a local deep trench (LDT) region 412. The LDT region 412 may be filled with an electrically non-conductive material, including tetraethylorthosilicate (TEOS), silicon oxide (SiO), silicon nitride (SiN), boron-carbon-nitrogen silicon (SiBCN), oxygen-carbon-nitrogen silicon (SiOCN), oxygen-carbon-nitrogen silicon (SiOC), carbon-nitrogen silicon (SiCN), boron-nitrogen silicon (SiBN), a low-k dielectric constant (low-k) insulating material, or a combination thereof. The LDT region 412 may have a thickness, for example, approaching approximately 8000 angstroms (8 kÅ), which may be equal to or less than the thickness of the n-doped drain region 406. As shown in FIG. 4A, the LDT region 412 may be filled with at least N +The distal end surface of region 406a is surrounded by an LDT region 412. In some embodiments, the LDT region 412 may extend further along the length of the MOSFET to surround the other two sidewall surfaces of drain region 406. Additionally, the CMOS wafer 400 subjected to the WOW bonding scheme also includes shallow trench isolation (STI) regions (not shown) disposed between adjacent string driver transistors. Specifically, the STI regions may be disposed below the surface of the substrate 402 and between the parallel gates of adjacent string driver transistors. The STI regions may have a thickness of approximately 4000 angstroms (4 kÅ) or less to provide electrical isolation between adjacent string driver transistors.

[0017] In some other embodiments, each of the multiple string drivers of the CMOS wafer 400 subjected to the WOW bonding method may be composed of other types of transistors, such as FinFETs. For example, the substrate 402 may be a p-type doped silicon fin of a FinFET extending horizontally within the CMOS wafer 400. A gate electrode 408 may be disposed on the top surface and both sidewalls of the fin 402. The source region 404 and drain region 406 of the FinFET may be n-type N-type, similar to a MOSFET. + Area and N - The doping profile of the region may be located at both ends of the fin 402 .

[0018] In the string driver transistor described above, the gate electrode 408 and gate oxide layer 410 are N - Regions 404b and 406b and N + It is formed prior to the ion implantation of regions 404a and 406a and can function as a mask in these implantation processes. That is, source region 404 and drain region 406 are formed in a self-aligned manner with gate electrode 408. In addition, N -Regions 404b and 406b may diffuse laterally into the channel region underlying gate electrode 408 during the ion implantation process or during a subsequent thermal annealing process.

[0019] 4B shows a schematic diagram of a CMOS wafer 400 and a memory array wafer 420 before WOW bonding, according to an embodiment of the present technology. Prior to WOW bonding and subsequent metal formation within the CMOS wafer 400, the CMOS wafer 400 is thinned from the backside by a suitable technique, such as wafer backgrinding, to remove most of the excess substrate / wafer thickness. The thinning process of the CMOS wafer may be stopped upon reaching the bottom of the LDT regions 412, resulting in the multiple string drivers being completely isolated by the LDT regions 412. As previously mentioned, because the thickness of the STI regions provided for the multiple string drivers is smaller than the LDT regions 412, in the backside-thinned CMOS wafer 400, the multiple string drivers continue to share a silicon bridge below the STI regions, preventing transistor floating-body issues.

[0020] After backside thinning of the CMOS wafer, a dielectric layer 418, e.g., an oxide layer, may be deposited on the backside of the CMOS wafer. The oxide layer may be comprised of silicon oxide processed at temperatures below or near 400°C by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, electroless plating, spin coating, and / or other suitable thin film deposition techniques. In this example, the dielectric layer may have a thickness ranging from 50 nm to 200 nm.

[0021] After the dielectric layer 418 is deposited, the backside of the CMOS wafer 400 may be bonded to the front side of a memory array wafer 420 via a WOW bonding process. In some embodiments, the memory array wafer 420 includes one or more memory arrays with multiple word lines, each of which may be connected to a metal pad 422. Furthermore, the memory arrays (not shown) and the corresponding metal pads 422 are covered by a dielectric layer 424, e.g., an oxide layer, for electrical isolation.

[0022] In some other embodiments, CMOS wafer 400 may have a silicon-on-insulator (SOI) substrate. Backside thinning of CMOS wafer 400 can reduce its thickness until an insulating layer (e.g., an oxide layer) is exposed. The oxide layer in the SOI substrate can be bonded to dielectric layer 424 of a memory array wafer for WOW bonding.

[0023] In this technique, the CMOS wafer 400 and the memory array wafer 420 can be bonded by forming a dielectric-to-dielectric bond (e.g., a strong covalent bond) without gaps or voids between the dielectric layers 418 and 424. Applying heat and / or pressure to the WOW bond can fuse the dielectric layers 418 and 424 together, as shown in Figure 4C. The WOW bond shown in Figure 4B also includes a configuration in which metal pads 422 corresponding to each memory array word line are aligned with the drain region 406 of the respective string driver transistor to enable local word line (LWL) connection.

[0024] 4C shows a schematic diagram of a WOW packaging including a CMOS wafer 400 and a memory array wafer 420, according to an embodiment of the present technology. Specifically, the WOW structure includes local word lines (LWLs) 418 that vertically penetrate string drivers in the CMOS wafer 400 and connect to corresponding metal pads 422 on the memory array wafer 420.

[0025] In some embodiments, the LWL 418 is configured to penetrate the drain region 406 of the MOSFET and the dielectric-to-dielectric interface and connect to the metal pad 422. In the present technique, the LWL 418 can be formed by etching holes in the overlying dielectric layer of the CMOS wafer 400, the drain region 406, and the dielectric layers 418 and 424 disposed between the drain region 406 and the metal pad 422. As shown in FIG. 4C, the holes are formed by etching holes in the N-type electrode at the drain of the MOSFET to ensure uniformity of the etching. + The hole may be located entirely within region 406a, in this example, by an anisotropic etching technique, such as a reactive ion etching (RIE) process with endpoint detection, which may be controlled to stop at metal pad 422.

[0026] In some other embodiments, LWL418 is N + The holes may extend through a portion of region 406a and a portion of the adjacent LDT region 412. In this case, the hole formation process may be performed using a single anisotropic etch process or multiple selective etch processes to improve etch uniformity control. For example, a silicon etch process selective to the dielectric material may be used to etch N. + A portion of region 406a may be vertically etched, followed by a portion of LDT region 412 using a directional oxide etch process that is selective to silicon.

[0027] After etching a hole through the CMOS wafer to the metal pad 422, a standard contact alloy may be formed on the sidewall of the hole. A metallization process is then performed to fill the hole with a conductive material, including a metal or metal alloy, to form the LWL 418. In this technique, the top of the LWL 418 is not connected to other devices in the CMOS wafer 400. For example, the LWL 418 located on a MOSFET is covered with a dielectric material or processed using a dual damascene process to maintain electrical isolation. The gate electrode 408 may also be connected to a high-voltage circuit (HV circuit) via a dedicated switch or passive components.

[0028] In some embodiments, a metal-last process may be utilized to form an intermediate layer of metal wiring within the CMOS wafer 400. Through this metal layer, the GWL 414 connects with the HV circuitry and general circuit wiring. Furthermore, as shown in FIG. 4C, the LWL 418 is connected to the N - It is separated from the gate electrode 408 via a region 406b. - The region 406b is an N through which the LWL 418 penetrates. + The region 406a is disposed vertically in the substrate 420 so as to insulate the region 406a from the gate electrode 408. - The width of the region 406b is N + It may be close to or larger than the minimum design width of the region. + Region 406a is depleted N - The region 406b may be configured to prevent a short circuit from occurring between the gate electrode 408 and the LWL 418. In addition, the LWL 418 may be configured to prevent a short circuit from occurring between the gate electrode 408 and the LWL 418. + By passing through region 406a, low contact resistance is achieved.

[0029] Referring to FIG. 5, various configurations of string drivers 500 are shown in plan view, in accordance with embodiments of the present technology. Specifically, FIG. 5 illustrates a three-column by three-row device arrangement as part of a larger string driver array. In this example, three columns of string drivers 500a, 500b, and 500c are aligned horizontally and separated from one another by LDT regions 512. Within each column, three pairs of string drivers are arranged in parallel, each separated vertically by STI regions 510. Additionally, each vertically aligned string driver pair shares a common gate electrode 504. As shown in FIG. 5, each string driver pair is comprised of two transistors (e.g., MOSFETs) having a common source region. Furthermore, each string driver includes a GWL 506 connected to the source region and a LWL 508 connected to the drain region of the corresponding transistor.

[0030] In some embodiments, the string driver 500 may be configured such that the STI extends partially into the LWL region, such as in the string driver 500a shown in the left column of Figure 5. In this example, pairs of vertically aligned string driver transistors are electrically isolated by STI regions 510. Furthermore, the STI regions 510 extend partially into the LWL 508 region, e.g., the LDT regions 512 overlap the LWL 508 along the length of the common gate electrode 504. In this configuration, the drain regions of each string driver transistor pair are partially surrounded by the LDT regions 512.

[0031] In some other embodiments, the string driver may be configured such that the STI extends partially into the gate electrode, such as string driver 500b shown in the center column of Figure 5. In this example, pairs of vertically aligned string driver transistors are electrically separated primarily by LDT regions 512. In particular, the STI regions 510 extend partially into the gate electrode 504, meaning that the lateral outer edges of the STI regions 510 overlap the gate electrode 504. In this example, the LDT regions 512 surround not only the entire drain region of each string driver transistor, but also a portion of the gate region.

[0032] In still other embodiments, the string driver may be configured such that the ends of the STIs are located within the GWL regions (see string driver 500c in the right column of FIG. 5). In this example, the STI regions are limited in dimension along the length of the string driver pair, which may be close to or smaller than the diameter of the GWL 506, or may be configured to leave only a very narrow area in that direction. As shown, the vertically aligned string driver transistor pairs are electrically isolated primarily by the LDT regions 512. In this configuration, the LDT regions 512 may be formed to completely surround at least a portion of the drain region, gate region, and shared source region of each string driver transistor.

[0033] 6A illustrates a cross-sectional view of a string driver along the AB plane of FIG. 5, in accordance with some embodiments of the present technology. In particular, FIG. 6A illustrates adjacent string driver transistors with LWLs through corresponding drain regions and isolated by LDT regions 512. In this example, each adjacent string driver transistor includes a gate electrode 504, a source region (not shown), a substrate 503, and a drain region 406. As previously mentioned, the drain region of each string driver transistor is formed of a lightly doped N - Region 406b and heavily doped N+ The regions 406a are aligned vertically in the substrate 503, and N - The region 406b is provided adjacent to the gate electrode 504, and the gate and N + The LWL 508 is configured to vertically penetrate the drain regions of adjacent string driver transistors to transmit a control voltage from a high voltage circuit (HV circuit) to a corresponding word line of the memory array. As shown, the LDT region 512 is configured to vertically penetrate the drain regions of adjacent string driver transistors, i.e., N + The drain region 406a and the LWL 508 passing through it are completely isolated. Furthermore, the LWL contacts are located along the sidewalls of the LWL 508, providing a good interface between the N-type and N-type electrodes in the backside-thinned CMOS wafer 400. + The LWL is formed over the entire depth of the drain region 406a and extends toward the dielectric-to-dielectric bonding interface at the WOW junction. In conventional string drivers, the LWL passes through the insulating region between adjacent transistors, but this technology effectively utilizes the drain region of the string driver transistor to improve the packing density of string driver devices for WOW packaging on a CMOS wafer.

[0034] 6B shows a cross-sectional view of a string driver along the B-C plane of FIG. 5 according to an embodiment of the present technology. In particular, FIG. 6B shows string drivers aligned in parallel, each of which has N + A GWL 506 is connected to the top of the source region 404a. As shown, the parallel aligned string drivers are partially isolated by STI regions 510. In this example, the depth of the STI regions 510 is N - source region 404b and does not extend further into the string driver transistor substrate 503. This configuration allows the STI region 510 to be isolated from the adjacent active source region (e.g., N -404b) and prevents short circuits between the transistors. Furthermore, a substrate 503 (e.g., a p-type doped substrate in a MOSFET of the CMOS wafer 400) extends between the parallel-arranged string driver transistors and beneath the STI regions 510. In such a configuration, the bridge-like substrate 503 can be biased to ground or a fixed potential to prevent floating body problems in the transistors.

[0035] 7, a plan view of a column of string driver pairs with various STI and LDT configurations is shown, in accordance with an embodiment of the present technology. In this example, multiple string driver transistor pairs are aligned vertically in parallel, each isolated by a different pattern of STI and LDT. In particular, the string driver column in this figure shows three different isolation configurations 700a, 700b, and 700c.

[0036] The string driver isolation configuration 700a has a medium active area spacing and is isolated by STI 710. As shown, and in some embodiments, the isolation configuration 700a includes STI regions 710 that terminate at the GWL region 706. The LDT region 712 completely surrounds portions of the drain, gate, and source regions of the parallel-arranged string driver transistors. In this configuration, the silicon bridge connection between the parallel-arranged string driver transistors is limited to the area below the STI regions 710 in the isolation configuration 700a. In this example, the isolation performance between the parallel-arranged string driver transistors is limited by the ability of the STI regions 710 to suppress punch-through and sustain a high breakdown voltage below the area below.

[0037] In some other embodiments, the isolation configuration 700b has a wide active area spacing with STI regions 710 and silicon body connections disposed therebetween. As shown, the isolation configuration 700b between the parallel-arranged string driver transistors has a wider spacing than the isolation configuration 700a, which has a medium active area spacing. Furthermore, the isolation configuration 700b includes a substrate 702 connected by a gate-wire lands 706. The substrate 702 is electrically isolated from the upper and lower parallel string driver transistors by STI regions 710 disposed at its top and bottom edges, respectively. In this example, the widths of the STI regions 710 disposed at the top and bottom edges of the substrate 702 are approximately the diameter of the gate-wire lands 706. Such an isolation configuration 700b is suitable for applications requiring electrical isolation between the string driver elements and the body connections, particularly for GWL connections.

[0038] In yet other embodiments, the isolation configuration 700c includes tight active area spacing using LDTs ​​712. As shown, the parallel-arranged string drivers are fully isolated by the LDTs ​​712, with no silicon body / substrate bridge connection between them. In this example, the spacing between the parallel-arranged string driver transistors is constrained by the dielectric breakdown between adjacent active areas, i.e., adjacent source regions between the parallel-arranged string driver transistors. Other factors limiting the tight active spacing in the isolation configuration 700c include capacitive coupling effects that may occur between the parallel-arranged string driver transistors and through the isolation regions 700c.

[0039] It should be noted that the isolation structures 700a, 700b, and 700c described above can be arranged in various patterns between the parallel-aligned string driver transistors. For example, in the string driver device region, an alternating vertical arrangement such as "700b-700c-700b-700c" can be used to form an H-shaped structure surrounded by the LDT region 712. In this case, the average active area spacing between 700b and 700c can be set to comply with design rules. This arrangement provides an opportunity to introduce body bias to improve the performance of the string driver transistors. For example, a positive voltage can be applied to the body / substrate bridge connection to reduce the floating body effect. As another example, a periodic body contact pattern such as "700a-700a-700b-700a-700a" can be arranged between the vertically aligned string driver transistors in the string driver device region.

[0040] FIG. 8 is a flowchart illustrating a WOW bonding process method 800 for fabricating semiconductor devices according to an embodiment of the present technology. For example, the method 800 may include, at 802, providing a first wafer having complementary metal-oxide-semiconductor (CMOS) devices. The CMOS devices include a plurality of string drivers, each including a field-effect transistor (FET). For example, as shown in FIG. 4A, a CMOS wafer 400 may be provided for WOW bonding. The CMOS wafer 400 may include a plurality of string driver devices, each including a MOSFET transistor. Further, the MOSFET of each string driver device may include a gate electrode 410, a source region 404, a drain region 406, and a substrate / body 402. In some other examples, the transistors included in the string driver devices may be FinFETs.

[0041] The method 800 also includes forming a plurality of global word lines (GWLs) correspondingly connected to the FETs of each of the plurality of string drivers, at 804. For example, each string driver device shown in FIG. 4A includes a GWL 414 connected to the source region of the MOSFET. Specifically, the GWL 414 is connected to the N-type, heavily doped region of the MOSFET. + By connecting to the region 404a, a low resistance contact can be formed between them.

[0042] Method 800 further includes, at 806, thinning the wafer from the backside of the first wafer. For example, CMOS wafer 400 may be thinned by removing excess substrate / wafer thickness from the backside using a suitable technique, such as wafer backgrinding. The backside wafer thinning process may stop at LDT region 412 of CMOS wafer 400. In another example, after backside wafer thinning, a dielectric layer, such as dielectric layer 418, may be deposited on the backside of CMOS wafer 400.

[0043] Further, the method 800 includes, at 808, providing a second wafer including a memory array including a plurality of word lines. For example, a memory array wafer 420 can be provided for WOW bonding. As shown in FIG. 4B, the memory array wafer 420 can include one or more memory arrays including a plurality of word lines, each connected to a corresponding metal pad 422 for LWL connection. Furthermore, the one or more memory arrays are covered by a dielectric layer 424 disposed on the front side of the memory array wafer 420.

[0044] Finally, method 800 includes bonding the backside of the first wafer to the front side of the second wafer to form a WOW bond at 810. For example, a dielectric-to-dielectric bond (e.g., an oxide-to-oxide diffusion bond) may be formed between dielectric layers 418 and 424. Heat and / or pressure may be applied to the WOW bond to form a strong covalent bond between CMOS wafer 400 and memory array wafer 420.

[0045] Any of the semiconductor structures described above with reference to FIGS. 1-7 can be incorporated into numerous larger and / or more complex systems. A representative example is system 900, shown schematically in FIG. 9. System 900 may include a semiconductor device 910, a power supply 920, a driver 930, a processor 940, and / or other subsystems or components 950. Semiconductor device 910 may have a configuration generally similar to the semiconductor devices described above and may include the string driver connections and direct string driver connections described in the present technology. The resulting system 900 may perform a variety of functions, such as memory storage, data processing, and other suitable functions. Accordingly, exemplary system 900 may include, but is not limited to, mobile devices (e.g., mobile phones, tablets, e-readers, digital audio players), computers, consumer electronics, and the like. The components of system 900 may be housed in a single unit or distributed across multiple units interconnected via a communications network or the like. Furthermore, the components of system 900 may include remote devices and various types of computer-readable media.

[0046] Specific details of several embodiments of semiconductor devices and related systems and methods are described below. Those skilled in the relevant art will understand that appropriate steps of the methods described herein can be performed at the wafer level or die level. Thus, depending on the context in which it is used, the term "substrate" can refer to either a wafer-level substrate or a separated die-level substrate. Furthermore, unless the context specifically dictates otherwise, the structures disclosed herein can be formed using conventional semiconductor fabrication techniques. For example, materials can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, electroless plating, spin coating, or other suitable techniques. Similarly, material removal can be performed by plasma etching, wet etching, chemical mechanical polishing (CMP), or other suitable techniques.

[0047] In one aspect of the present disclosure, the semiconductor devices shown above may be memory dies, such as dynamic random access memory (DRAM) dies, NAND memory dies, NOR memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, etc. Additionally, in embodiments in which multiple dies are included in an assembly, the semiconductor devices may be homogeneous memory dies (e.g., all NAND, all DRAM, etc.) or heterogeneous memory dies (e.g., one DRAM and one NAND, etc.). In yet another aspect, the semiconductor dies of the assemblies shown and described above may be logic dies (e.g., controller dies, processor dies, etc.) or may be a combination of logic and memory dies (e.g., a memory controller die and a memory die controlled by the controller).

[0048] The devices (e.g., memory devices) described herein can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide (GaAs), or gallium nitride (GaN). In some embodiments, the substrate can be a semiconductor wafer. In other embodiments, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material formed on another substrate. The conductivity of the entire substrate or subregions thereof can be controlled by doping with species such as phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping means.

[0049] The functions described herein may be implemented by hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are also within the scope of this disclosure and the accompanying claims. Components for implementing the functions may be physically located in various locations, and may also be configured in a distributed manner so that parts of each function are executed in different physical locations.

[0050] Throughout this specification (including the claims), the word "or," when used in a list of items (e.g., following phrases such as "at least one of" or "one or more of"), refers to an inclusive alternative. For example, "at least one of A, B, or C" means any one of A, B, or C; A and B; A and C; B and C; or all of A, B, and C (i.e., A, B, and C). Additionally, the phrase "based on" as used herein should not be construed as indicating a limiting set of conditions. For example, an exemplary step described as "based on condition A" would fall within the scope of the present disclosure even if it were based on both condition A and condition B. In other words, the phrase "based on" as used herein should be interpreted in the same way as the phrase "based at least in part on."

[0051] As used herein, terms such as "top," "bottom," "over," "under," "above," and "below" refer to the relative direction and position of structures within a semiconductor device based on the orientation shown in the drawings. However, these terms should be interpreted broadly to include situations where the device is inverted or tilted, and terms such as "top / bottom," "upper / lower," "upper / lower," "upward / downward," "left / right," and the like are interchangeable depending on the device orientation.

[0052] It should be noted that the method described above is one possible implementation example. The order of these processes and steps may be changed or other modifications may be made, and other implementation examples are possible. Also, the embodiments described in multiple methods may be used in combination.

[0053] As is apparent from the foregoing description, while specific embodiments of the present invention have been described for illustrative purposes, various modifications may be made without departing from the scope of the present invention. Rather, numerous specific details are disclosed herein to provide a thorough and enabling description of embodiments of the present technology. However, those skilled in the art will understand that the technology of the present disclosure may be practiced without some or all of these specific details. Additionally, well-known structures and processes generally associated with memory systems and devices may not be shown or described in detail to avoid obscuring other features of the present technology. In general, it should be understood that the scope of the present technology may include various other apparatus, systems, and methods, without being limited to the specific embodiments disclosed herein.

Claims

1. 1. A semiconductor device assembly comprising: a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, each string driver comprising a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line passing vertically through the FET; a second wafer having a memory array, the memory array having a plurality of word lines, each word line connected to a corresponding string driver of the first wafer via the local word line; the backside of the first wafer is bonded to the front side of the second wafer to form a wafer-on-wafer (WOW) bond; 1. A semiconductor device assembly comprising:

2. 2. The semiconductor device assembly of claim 1, the FET of each of the plurality of string drivers of the first wafer is a metal oxide semiconductor FET (MOSFET) including a gate, a source, and a drain.

3. 3. The semiconductor device assembly according to claim 2, a global word line of each of the plurality of string drivers is connected to a source of the MOSFET; and a local word line of each of said plurality of string drivers vertically passing through at least a portion of the drain of said MOSFET;

4. 4. The semiconductor device assembly of claim 3, a drain of each MOSFET of the plurality of string drivers includes both a lightly doped drain region and a heavily doped drain region that vertically penetrates a substrate of the MOSFET, the lightly doped drain region being disposed between the gate of the MOSFET and the heavily doped drain region.

5. 5. The semiconductor device assembly of claim 4, a local word line of each of said plurality of string drivers vertically passing through a heavily doped drain region of a corresponding MOSFET;

6. 5. The semiconductor device assembly of claim 4, the first wafer includes a plurality of local deep trench (LDT) regions including a dielectric material, each of the plurality of LDT regions being disposed adjacent to a corresponding one of the plurality of string driver heavily doped drain regions.

7. 7. The semiconductor device assembly of claim 6, a local word line for each of said plurality of string drivers vertically passing through a corresponding heavily doped drain region of said string driver and an adjacent LDT region;

8. 3. The semiconductor device assembly according to claim 2, a source of each MOSFET of the plurality of string drivers includes a lightly doped source region and a heavily doped source region buried within the lightly doped source region; and a global word line of each of the plurality of string drivers is connected to a high concentration source region of a corresponding string driver.

9. 2. The semiconductor device assembly of claim 1, the first wafer includes a dielectric layer disposed on a back surface of the first wafer and below the plurality of string drivers; a dielectric layer of said first wafer bonded to a dielectric layer disposed on a surface of a second wafer to form said WOW bond;

10. 2. The semiconductor device assembly of claim 1, a local word line for each of the plurality of string drivers extends vertically through the first wafer, including the FET of the corresponding string driver and a dielectric layer of the first wafer; further extending into the second wafer through the WOW bonded interface and connecting to a metal pad; the metal pads are connected to corresponding word lines of a memory array on the second wafer.

11. a gate disposed on at least a top surface of the substrate; a source disposed on one end side of the gate and within the substrate; the source has a lightly doped source region and a heavily doped source region; the heavily doped source region is buried within the lightly doped source region; a drain disposed on the other end side of the gate and within the substrate; the drain has a lightly doped drain region and a heavily doped drain region; the drain regions extend vertically through a substrate of the semiconductor device; 2. A semiconductor device comprising: a first insulating film formed on the first insulating film; a second insulating film formed on the second insulating film; a first insulating film formed on the first insulating film;

12. 12. The semiconductor device according to claim 11, further comprising: a global word line connected to a heavily doped source region of the semiconductor device; a local word line that passes through the drain of the semiconductor device in a vertical direction.

13. 13. The semiconductor device according to claim 12, 2. A semiconductor device, wherein the local word line passes through a heavily doped drain of the semiconductor device in a vertical direction.

14. 13. The semiconductor device according to claim 12, further comprising a local deep trench (LDT) region comprising a dielectric material; the LDT region is disposed adjacent to a heavily doped drain region of the semiconductor device; a local word line extending vertically through the heavily doped drain region and the adjacent LDT region;

15. 15. The semiconductor device according to claim 14, further comprising a shallow trench isolation (STI) region comprising a dielectric material; the STI region is disposed adjacent to and parallel to a gate of the semiconductor device; 1. A semiconductor device, wherein the depth of the STI region is smaller than the depth of the LDT region.

16. 1. A method of forming a semiconductor device assembly, comprising: providing a first wafer having complementary metal oxide semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, each of the plurality of string drivers including a field effect transistor (FET); forming a plurality of global word lines connected to FETs corresponding to each of the plurality of string drivers; thinning the first wafer from a backside of the first wafer; providing a second wafer having a memory array including a plurality of word lines; and bonding the backside of the first wafer to the front side of the second wafer to form a wafer-on-wafer (WOW) bond; 1. A method of forming a semiconductor device assembly, comprising:

17. 17. The method of forming a semiconductor device assembly of claim 16, further comprising: Providing the first wafer comprises the steps of: forming at least a gate on an upper surface of a substrate of each of the plurality of string drivers; forming a source at one end of the gate and in the substrate, the source having a lightly doped source region and a heavily doped source region, the heavily doped source region being embedded in the lightly doped source region; forming a drain at the other end of the gate and in the substrate, the drain having a lightly doped drain region and a heavily doped drain region, both of which extend vertically through the substrate of the semiconductor device; and the lightly doped drain region is disposed between the gate and the heavily doped drain region. A method comprising:

18. 20. The method of forming a semiconductor device assembly of claim 17, further comprising: Providing the first wafer further comprises: forming a local deep trench (LDT) region comprising a dielectric material in the substrate of each of the plurality of string drivers, the LDT region being located adjacent to a heavily doped drain region of the semiconductor device; forming a shallow trench isolation (STI) region comprising a dielectric material in the substrate of each of the plurality of string drivers, the STI region being adjacent to and parallel to a gate of the semiconductor device, the STI region having a depth less than that of the LDT region; A forming method comprising:

19. 20. The method of forming a semiconductor device assembly of claim 18, further comprising: further comprising forming a plurality of local word lines passing through the plurality of string drivers, the plurality of local word lines further extend through the WOW bonding interface into a second wafer; each of the plurality of local word lines is connected to a corresponding one of a plurality of metal pads in the second wafer; the plurality of metal pads are respectively connected to a plurality of word lines of a memory array in the second wafer.

20. 20. The method of forming a semiconductor device assembly of claim 19, further comprising: the method comprising: each of the plurality of local word lines passing at least partially through a heavy drain region of a corresponding one of the plurality of string drivers.

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