Electrical switching device for level conversion of digital signals

Abstract

An electrical switching device for level-translating a digital input signal in a first voltage domain to a digital output signal in a second voltage domain different from the first voltage domain is described, the electrical switching device comprising a first transistor, the first transistor being controlled by the digital input signal and having an assigned source-drain section connected between ground potential and an input of a current mirror having an output connected via a first contact to an intermediate storage device, the intermediate storage device having a second contact connected to a gate terminal of a second transistor, the assigned source-drain section of the second transistor being arranged in series with the source-drain section of the first transistor between the input of the current mirror and the first transistor.

Description

[Technical Field]

[0001] The present invention relates to an electrical switching device for level-translating a digital input signal in a first voltage domain to a digital output signal in a second voltage domain different from the first voltage domain, the electrical switching device comprising a first transistor controlled by the digital input signal, the source-drain section assigned to the first transistor being connected between ground potential and an input of a current mirror having an output connected to an intermediate storage device via a first contact. [Background technology]

[0002] In digital technology in particular, electrical switching devices for level conversion, also known as level converters, level translators, or level shifters, are used to convert digital signals from one voltage domain to another, allowing digital electronic switching elements designed for higher power supplies and operating voltages to be combined and operated within the electrical switching device with digital switching elements designed for lower power supplies and operating voltages.

[0003] For example, using such a level converter, it is possible to convert digital signals having signal levels of, for example, 0 to 1.8 V into a higher voltage range, so that their assigned signal levels are, for example, 10 to 11.8 V.

[0004] Known electrical switching devices of this type comprise, for example, a current mirror, the input potential of which is used to control two transistors, the output of which is connected to an intermediate storage device, a so-called latch. Such switching devices are known, for example, from the following published documents: US 5,973,508, and, for example, the article by Qiang Li et al., "A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique", Sensors 2022, 22 (5), 1774. A comparable switching configuration is also described in US Patent Application Publication No. 2013 / 0049808.

[0005] The design and concept of this type of electrical switching device poses a challenge in achieving the shortest possible transition or transfer time for changing levels, which typically involves significant voltage fluctuations of approximately ±20 V or more. To control or operate the current mirror and its associated intermediate storage devices, known switching devices use capacitors and / or pulse signal generators, whose inherent time constants set limits for achieving the shortest possible level transition times and switching processes. Furthermore, when operating such switching configurations, there are power-consuming conduction paths that are not involved in the switching and / or signal level transfer process. This results in unnecessary current consumption. Summary of the Invention

[0006] The present invention is based on the problem of further developing an electrical switching device for level conversion of a digital input signal in a first voltage domain to a digital output signal in a second voltage domain, preferably higher than the first voltage domain, the electrical switching device having a first transistor controlled by the digital input signal, the source-drain section assigned to the first transistor being connected between ground potential and an input of a current mirror having an output connected via a first contact to an intermediate storage device, thereby avoiding the above-mentioned drawbacks of the prior art. In particular, it is important to further reduce the switching or transmission time for level conversion of the digital input signal, in addition to avoiding unnecessary power consumption in the switching arrangement.

[0007] The solution to the problem forming the basis of the present invention is set out in claim 1. Features which advantageously further develop the inventive concept are the subject matter of the dependent claims and are further explained with reference to the drawings.

[0008] The electrical switching device for level translation of a digital input signal according to the invention, based on the features of the preamble of claim 1, is characterized in that the intermediate storage device has a second contact connected to a gate terminal of a second transistor, the source-drain part of the second transistor being arranged in series with the source-drain section of the first transistor between the input of the current mirror and the first transistor.

[0009] By providing a second transistor, preferably a high-voltage transistor, along the so-called bias path between the first transistor and the input of the current mirror, and by directly controlling the second transistor through the intermediate storage device, it is ensured that only currents related exclusively to level conversion of the digital signal flow along the bias path. In all other operating states where a constant current can flow along the bias path, the second transistor blocks any current flow. Control of the second transistor is achieved directly through positive feedback from the intermediate storage device. To this end, the second transistor is connected to the intermediate storage device through a second contact, which is positioned opposite the first contact of the intermediate storage device. That is, a component of the intermediate storage device, preferably a transistor, is connected between both contacts, which introduces an inherent time delay (metasability) into the system regarding signal transmission between both contacts.

[0010] Preferably, a delay element is incorporated between the gate terminal of the second transistor and the intermediate storage device, which ensures that the second transistor is closed, i.e., set "off" to block the constant bias current when the first transistor is set "on", immediately after the intermediate storage device is set. The use of a delay element creates additional operational reliability to ensure a time margin or time buffer, improving the operational robustness of the switching arrangement in the event of various transient phenomena (signal rise and fall times, process conditions, etc.).

[0011] Since the switching arrangement according to this solution does not require the use of capacitors or pulse generators, the switching arrangement according to this solution allows for significantly improved, i.e. very short, transmission times for converting digital signals from a preferably lower first voltage domain to a higher second voltage domain.

[0012] A further advantage of the innovative switching arrangement is its autonomous response, i.e., the second transistor is closed once the intermediate storage device (latch) is "set". Furthermore, since the switch does not depend on the circuit's inherent time constants, e.g., from other RC elements present, the switching arrangement according to the present solution can be efficiently deployed and used at different voltage levels, e.g., in the range of 1.8V to 18V. [Brief explanation of the drawings]

[0013] The invention will now be described by way of example, without limiting the general inventive concept, by way of example of embodiments, with reference to the drawings, in which: [Figure 1] 1 shows the circuit topology of an electrical switching arrangement according to a solution for level conversion of a digital input signal; [Figure 2] 1 shows a diagram of the switching arrangement of the associated voltage domains. DETAILED DESCRIPTION OF THE INVENTION

[0014] Figure 1 shows a preferred example of an embodiment of an electrical switching device capable of converting a digital input signal from a first low voltage domain VB to a second high voltage domain VD. The voltage potentials identified by the range arrows in Figure 2, respectively, and the distinct low voltage domain VB and high voltage domain VD therein, indicate the range of the electrical switching arrangement according to Figure 1, in which digital signals belonging to the first low voltage domain VB and the second high voltage domain VD, respectively, are generated and / or processed.

[0015] The switching device 1 comprises an input "in" on which a digital input signal is present, the signal level of which corresponds to a first voltage domain VB, i.e. the digital signal is defined by voltage potentials 0 V, equivalent to the ground potential GND, and +1.8 V. In the illustrated embodiment example, the supply voltage VO is 18 V. The specific potential diagrams are to be understood as exemplary values ​​without further limiting the electrical switching device 1 itself.

[0016] The input potential of the input signal present at the input "in" controls the first transistor T1, the source-gate part SD-T1 assigned to which is connected on the one hand to the ground potential GND and on the other hand to the input "em" of the current mirror M. This connection path corresponds to the bias path B along which flows the bias current for feeding the current mirror M.

[0017] The current mirror M has a known circuit design, which comprises two transistors, a third transistor T3 and a fourth transistor T4, whose gate terminals are connected to the input "em" of the current mirror M, and whose drain-gate sections DS-T3, DS-T4 are connected on the one hand to the supply voltage V0, which at the same time corresponds to the potential limit of the second voltage domain VD. The two transistors T3, T4 of the current mirror M are each of the same doping type, i.e., are designed as either NMOS or PMOS transistors.

[0018] The source-drain section SD-T4 of the fourth transistor T4 forms the output am of the current mirror M, opposite the supply voltage VO, which is simultaneously connected to a contact op of an intermediate store "latch". In a known manner, the intermediate store "latch" comprises two pairs of transistors (1T and 2T) and (3T and 4T) connected in series, respectively, the gate terminals of which are connected to each other in a four-way switch as shown in Figure 1a, i.e., the gate terminals of the series-connected latch transistors 1T and 2T are connected to the second contact "on" of the intermediate store, and the gate terminals of the series-connected latch transistors 3T and 4T are connected to the first contact "op" of the intermediate store "latch". The intermediate store "latch" is also connected between the supply potential VO and a further voltage potential VI corresponding to the lower limit of a second voltage domain VD.

[0019] Along the basic path B, a second transistor T2 is arranged between the first transistor T1 and the input "em" of the current mirror M, the source-drain section of which is connected in series with the source-drain section of the first transistor T1 to the input "em" of the current mirror M. The gate terminal of the second transistor T2 is connected to and controlled by the second contact "on" of the intermediate storage "latch". Preferably, a delay element "delay" is integrated between the second contact "on" of the intermediate storage "latch" and the gate terminal of the second transistor T2, which is biased between a voltage potential VI and a supply potential VO.

[0020] The output "out" of the electrical switching device 1 is connected to the output "am" of the current mirror M.

[0021] To reset the voltage stored in the intermediate storage "latch" located on the second contact "on" controlled or switched by the second transistor T2, a symmetrical layout of the switching arrangement with an inverted controlled signal is formed, providing another current mirror M'. Its input "em" is connected to the ground voltage GND via two series-connected transistors T1' and T2', one of which, T1', is controlled by the input signal at the input "in" via a delay element "delay" that primarily functions as an inverter, while the other, T2', is controlled by the output signal present at the output "out" and at the output "am" of the current mirror M via a further delay element "delay". Thanks to the symmetrical circuit layout with an inverted controlled signal, the switches operate fully differentially, i.e., differential input signals at T1 and T1' can also generate differential signals at "op" and "on".

[0022] Optionally, a switch SM is also arranged on the current mirror M, which in the closed position shorts the gates of the third and fourth transistors T3, T4 with the supply voltage V. A corresponding switch SM' is also preferably arranged in the symmetrically configured current mirror M'.

[0023] This switch SM or SM' can improve the efficiency of the switching arrangement: as soon as the second transistor T2 closes, a charge remains in the current mirror M or M', which ensures that the current in the intermediate storage "latch" is not completely switched off. Thus, the switch SM or SM' allows for a complete switch-off and also increases the mirroring speed, since charge can be removed more quickly from the parasitic capacitance of the current mirror.

[0024] Principle of operation: When a digital input signal is present on the input "in" of the electrical switching device 1, the first transistor T1 is switched "on", resulting in a bias current along bias path B through the second transistor T2, which is also switched on. The bias current present on the input "em" of the current mirror M is scaled by the current mirror M and introduced via its output into the intermediate storage "latch" at the first contact "op". By positive feedback, the gate terminal of the second transistor T2 is directly controlled by the intermediate storage "latch", through which T2 is set to the closed position "off". In this way, any bias current along bias path B is eliminated.

[0025] To ensure that the intermediate storage "latch" has fully completed the storage procedure, in particular since the second transistor T2 should be in a conducting state for this period, a delay element "delay" is incorporated just before the gate terminal of the second transistor T2.

[0026] For the purpose of resetting the stored value in the intermediate storage "latch", the closed first transistor T1' is set "on", which switches it into conduction via the second transistor T2', allowing current to flow through the current mirror M' and reset the intermediate storage "latch" via the second contact "on". Again, due to positive feedback by the intermediate storage "latch" via the first contact "op", the second transistor T2' is immediately closed in order to prevent unnecessary constant leakage current along the further bias path B'.

[0027] Each selectively provided switch SM and SM' is controlled by an intermediate storage "latch" through connection of the contacts "op" and "on" to more quickly reset the bias voltage on the current mirror M and on the current mirror M', thus further increasing the switching speed of the selective switching device. Additionally, the switches SM and SM help to prevent further leakage currents from occurring. [Explanation of symbols]

[0028] 1 Electrical switching device in Input B Bias Pass M, M' current mirror, another current mirror Latch Intermediate storage SM, SM' Current mirror switches em, em' current mirror input, another current mirror input am, am' current mirror output, another current mirror output op First node of intermediate memory on Second node of intermediate memory oq The third node of intermediate memory delay element T1, T2, T3, T4, T1', T2', T3', T4' transistors out Output VB First voltage domain VD Second voltage domain VO supply potential VI voltage potential HV High Voltage GND Ground

Claims

1. 1. An electrical switching device for level converting a digital input signal in a first voltage domain (VB) to a digital output signal in a second voltage domain (VD) different from the first voltage domain, comprising: a first transistor (T1) controlled by said digital input signal; the source-drain section assigned to said first transistor is connected between a ground potential (GND) and an input (em) of a current mirror (M) having an output (am) connected to an intermediate store (latch) via a first contact (op), the intermediate storage (latch) has a second contact (on) connected to the gate terminal of a second transistor (T2), the source-drain section assigned to the second transistor being arranged in series with the source-drain section of the first transistor (T1) between the input (em) of the current mirror (M) and the first transistor (T1); Electrical switching devices.

2. 2. An electrical switching device according to claim 1, wherein said current mirror (M) and said intermediate store (latch) are connected to a supply potential (VO) equal to the upper limit of said second voltage domain (VD).

3. 3. An electrical switching device according to claim 1, wherein said intermediate store (latch) has a third contact (oq) connected to a voltage potential (VI) equal to the lower limit of said second voltage domain (VD).

4. 4. An electrical switching device according to claim 1, further comprising a delay element (delay) arranged between the gate terminal of the second transistor (T2) and the second contact (on).

5. 5. An electrical switching device according to claim 2 or claim 4, wherein the delay element (delay) is biased between the voltage potential (VI) and the supply potential (VO).

6. 6. An electrical switching device according to any one of claims 2 to 5, wherein the input (em) of the current mirror (M) is connected to the supply potential (VO) by a switch (SM).

7. 7. An electrical switching device according to claim 2, wherein the second contact (on) of the intermediate store (latch) is connected to the output (am') of another current mirror (M'), the input (em') of which is connected to ground potential (GND) via two series-connected source-drain sections of two transistors (T1', T2'), one transistor (T1') of which is controlled by the input signal and the other transistor (T2') is controlled by an output signal applied to the output via another delay element (delay').

8. 8. An electrical switching device according to claim 7, wherein said further current mirror (M') is connected to said supply potential (VO).

9. 9. An electrical switching device according to claim 7 or 8, wherein the input (em') of the further current mirror (M') is connected to the supply potential (VO) via a further switch (SM').

10. a) the current mirror (M) and the other current mirror (M'); b) the first transistor (T1) and the other transistor (T1'); c) the second transistor (T2) and the other transistor (T2'); 10. An electrical switching device according to claim 7, wherein each of the first and second electrodes is arranged in a pair / symmetrical fashion.

11. 11. The electrical switching device of claim 3, wherein the first voltage region (VB) has an upper voltage limit (VBoG) that is less than, equal to, or greater than a voltage potential (VI) corresponding to a lower limit of the upper voltage region (VD).

12. 12. An electrical switching device according to any one of claims 1 to 11, wherein the second contact (on) is opposite the first contact (op) on the intermediate store (latch).

13. 13. An electrical switching device according to any one of claims 1 to 12, wherein the current level comprises two transistors (T3, T4) connected to each other via their gate contacts and each having the same doping type.

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