Redundancy for an array of nonvolatile memory cells using tag registers

Abstract

Numerous examples of systems and methods for implementing redundancy are disclosed. In one example, a system includes an array of non-volatile memory cells, a redundant array of non-volatile memory cells, and an input block coupled to each row in the array and each row in the redundant array, the input block including a row tag register and a redundant row tag register.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 442,723, filed February 1, 2023, entitled "Redundancy for Artificial Neural Network Array," and U.S. Patent Application No. 18 / 134,928, filed April 14, 2023, entitled "Redundancy For An Array Of Non-Volatile Memory Cells Using Tag Registers."

[0002] FIELD OF THE INVENTION Numerous examples of circuits and methods for implementing redundancy for an array of non-volatile memory cells using tag registers are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that can depend on multiple inputs and are generally unknown. Artificial neural networks typically contain layers of interconnected "neurons" that exchange messages between each other.

[0004] Figure 1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons and an output layer of neurons that provide the neural network's output. Neurons at each level make decisions, individually or collectively, based on the data they receive from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. Indeed, practical neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency, compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, the synapses of most CMOS implementations are too large given the large number of neurons and synapses.

[0006] Applicant previously disclosed in U.S. Patent Application Publication No. 2017 / 0337466 A1, which is incorporated by reference, an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as synapses. The non-volatile memory array operates as an analog neural memory and comprises non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed insulated above a first portion of the channel region, and a non-floating gate disposed insulated above a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to the number of electrons in the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight value to generate the first plurality of outputs. <Nonvolatile memory cell>

[0007] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed above and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed above and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16 .

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by source side injection (SSI) of hot electrons (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 2 [Table 1]

[0012] Other split-gate memory cell configurations, including other types of flash memory cells, are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, meaning they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 of FIG. 3 [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 of FIG. 4 [Table 3]

[0016] 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of FIG. 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are accomplished by electrons flowing from the source region 14 toward the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 510 of FIG. 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable), and CeRAM (correlated electron ram).

[0019] In order to utilize a memory array containing one of the non-volatile memory cell types in the above artificial neural network, two modifications are made. First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array. Second, continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is essentially analog, or at a minimum, capable of storing one of a number of discrete values ​​(such as 16 or 64 different values), making every memory cell in the memory array very precisely and individually tunable and making memory arrays ideal for storage and for fine-tuning adjustments to the synaptic weights of neural networks. <Neural network using nonvolatile memory cell array>

[0021] 6 conceptually illustrates a non-limiting example of a neural network utilizing the present example non-volatile memory array. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and, after summing the outputs of the multiplications, determines a single output value, which is applied by the first synapse of CB1 to generate one pixel of layer C1's feature map. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all of layer C1's feature maps have been calculated.

[0023] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. The purpose of pooling function P1 is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for this purpose. A vector-by-matrix multiplication (VMM) array 32 contains nonvolatile memory cells and is used as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of nonvolatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the nonvolatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and sums them for each output line (source line or bit line) to produce an output that becomes the input to the next layer or the input to the last layer. Having the non-volatile memory cell array 33 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also more power efficient due to in-memory computation.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output values ​​of the differential summer 38 are then provided to an activation function block 39, which normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6 ) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving inputs from a previous layer of neurons or from an input layer such as an image database), and the summing operational amplifiers 38 and the activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, input (denoted Inputx) is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or current. The first layer's input D / A conversion can be performed by using a function or LUT (look up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which generates an output that is provided as input to the next VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that a system may alternatively include more than two hidden layers and more than two fully connected layers. <Vector × Matrix Multiplication (VMM) Array>

[0033] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In VMM array 900, control gate lines, such as control gate line 903, run vertically (thus, row-oriented reference array 902 is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run horizontally. Here, inputs to VMM array 900 are provided on control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 900 appear on source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current on each source line (SL0, SL1, respectively) performs the function of summing all the currents from the memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, i.e., memory cells 310 of VMM array 900, may be configured to optionally operate in the sub-threshold region.

[0036] The nonvolatile reference memory cells and nonvolatile memory cells described herein are biased in weak inversion (subthreshold region) as follows: Ids=Io×e (Vg-Vth) / nVt =w×Io×e (Vg) / nVt , In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, k is Boltzmann's constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n×Vt×log[Ids / wp×Io] where wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector x matrix multiplier VMM array with current inputs, the output current is: Iout=wa×Io×e (Vg) / nVt , i.e. Iout=(wa / wp)×Iin=W×Iin W=e (Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as: Vth=Vth0+gamma(SQRT|Vsb-2×φF)-SQRT|2×φF|) where Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and gamma is the body effect parameter.

[0039] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids = Beta × (Vgs-Vth) × Vds, Beta = u × Cox × Wt / L W=α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth)

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0042] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2×beta×(Vgs-Vth) 2 , Beta = u × Cox × Wt / L W ∝ (Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0044] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0046] 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. The reference arrays 1001 and 1002, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1014 (only partially shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level, which is provided by a reference mini-array matrix (not shown).

[0048] Memory array 1003 serves two purposes. First, it stores the weights used by VMM array 1000 in each memory cell. Second, memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert to input voltages provided to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1003, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which serve as inputs to the next layer or the last layer. By performing the multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are applied to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current on each of the bit lines BL0-BLN performs the function of summing the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines extend vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during a read operation. The current on each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each of the multiplexers 1212 includes a respective multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on each bit line (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation, where the reference cells are tuned to a target reference level.

[0053] Memory array 1203 serves two purposes. First, it stores the weights used by VMM array 1200. Second, memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1201 and 1202 convert these current inputs to input voltages provided to control gates (CG0, CG1, CG2, and CG3)) and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current on each bit line performs the function of summing all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 implements one-way tuning of the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (causing an incorrect value to be stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (e.g., EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] FIG. 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 or first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, meaning that each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0 through BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] 14 shows a neuron VMM array 1400 that is particularly suited to the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In the VMM array 1400, inputs INPUT0...., INPUT N are bit lines BL0, ...BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 15 shows a neuron VMM array 1500 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0060] 16 shows a neuron VMM array 1600 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0061] 17 shows a neuron VMM array 1700 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUTM are the word lines WL0, ..., WL M Received and output OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0062] 18 shows a neuron VMM array 1800 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 19 shows a neuron VMM array 1900 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT N are the bit lines BL0, ..., BL N , 1901-(N-1) and 1901-N, which are coupled to the gates of the bit line control gates 1901-1, 1901-2, ..., 1901-(N-1) and 1901-N. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] 20 shows a neuron VMM array 2000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0065] 21 shows a neuron VMM array 2100 that is particularly suited to memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0066] 22 shows a neuron VMM array 2200 that is particularly suited to memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i.

[0067] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in which case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0068] Typically, for each memory cell in a VMM array, each weight W can be provided by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to provide the weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to provide the weight W as the average of the two cells.

[0069] FIG. 23 illustrates a VMM system 2300. In some examples, the weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 2300, half of the bit lines are designated as W+ lines, i.e., bit lines connecting to memory cells that will store a positive weight W+, and the other half of the bit lines are designated as W− lines, i.e., bit lines connecting to memory cells that provide a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by summing circuits, such as summing circuits 2301 and 2302, that receive current from the W+ and W− lines. The outputs of the W+ and W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells of all pairs of (W+, W−) lines. Although described above with respect to W- lines interspersed alternately among W+ lines, in other examples, the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0070] 24 shows another example: In a VMM system 2410, positive weights W+ are provided in a first array 2411 and negative weights W− are provided in a second array 2412 that is separate from the first array, and the resulting weights are appropriately combined together by a summing circuit 2413.

[0071] FIG. 25 illustrates a VMM system 2500. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). VMM system 2500 includes array 2501 and array 2502. Half of the bit lines in each of arrays 2501 and 2502 are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines in each of arrays 2501 and 2502 are designated as W− lines, i.e., bit lines connecting to memory cells that provide a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 2503, 2504, 2505, and 2506, that receive current from the W+ and W− lines. The outputs on the W+ and W- lines from each array 2501, 2502 are combined together, respectively, to effectively give W = W+ - W- for each pair of (W+, W-) cells on every pair of (W+, W-) lines. Additionally, the W values ​​from each array 2501 and 2502 may be further combined via adder circuits 2507 and 2508, meaning that each W value is the result of subtracting the W value from array 2502 from the W value from array 2501, and the final result from adder circuits 2507 and 2508 is one of two difference values.

[0072] Each non-volatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge, or number of electrons, in its floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0073] Prior art non-volatile memory systems outside of VMM and neural network contexts provide redundant rows. During manufacturing and testing, rows containing one or more faulty cells are identified, and the addresses of such faulty rows are recorded in a non-volatile table along with their mapping to specific redundant rows. During computation, if the address of a faulty row is received during a write or read operation, the system disables the read or write of that row and instead enables the read or write of the specific redundant row associated with the faulty row in the non-volatile table.

[0074] 26 discloses a prior art memory system 2600 for replacing a row with one or more redundant rows. The memory system 2600 includes an address comparator 2601, an inverter 2602, a row decoder 2603, a redundant row decoder 2604, an array 2605, a redundancy array 2606, and a table 2607. During manufacturing and testing, the table 2607 is populated with addresses XA'[10:0] of faulty rows and addresses XRA[10:0] of respective redundant rows assigned to replace the respective faulty rows. The table 2607 is stored in a non-volatile storage device such as a ROM, flash memory, or a set of fuses.

[0075] During a read or write operation, an address XA[10:0] is received for the read or write operation. Address comparator 2601 compares that address to the addresses of bad rows stored in table 2607. In this example, an exemplary bad address XRA[10:0] is shown. If address comparator 2601 identifies a match, as indicated by ADDR MATCH, then the received address XA[10:0] is a known bad address. Signal ADDR MATCH is applied to redundant row decoder 2604 as enable signal EN_RED_XDEC, and the inverse of ADDR MATCH is applied to row decoder 2603 as disable signal DISABLE_XDEC_B. Row decoder 2603 also receives address XA[10:0]. However, because it receives the disable signal, row decoder 2603 takes no action on array 2605. Instead, redundant row decoder 2604 is enabled to enable the respective rows in redundancy array 2606 corresponding to the respective redundant rows previously assigned to the respective bad rows indicated by XA[10:0], which are obtained as XRA[10:0] from table 2607. Thus, write or read operations are performed to the respective redundant rows instead of the respective bad rows.

[0076] This prior art redundancy mechanism does not work for neural read operations in a VMM within an artificial neural network because during a neural read operation, multiple rows are read at once and no individual address XA is received that can form the basis for comparison against a set of addresses of known bad rows. Therefore, a redundancy mechanism is needed in an artificial neural network for use during a neural read operation. Summary of the Invention

[0077] Numerous examples of circuits and methods for implementing redundancy for an array of non-volatile memory cells using tag registers are disclosed.

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[0112] [Brief explanation of the drawings]

[0113] [Figure 1] FIG. 1 illustrates an artificial neural network. [Figure 2] 1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an artificial neural network utilizing one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a VMM system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems. [Figure 9] 1 shows another example of a VMM system. [Figure 10] 1 shows another example of a VMM system. [Figure 11] 1 shows another example of a VMM system. [Figure 12]1 shows another example of a VMM system. [Figure 13] 1 shows another example of a VMM system. [Figure 14] 1 shows another example of a VMM system. [Figure 15] 1 shows another example of a VMM system. [Figure 16] 1 shows another example of a VMM system. [Figure 17] 1 shows another example of a VMM system. [Figure 18] 1 shows another example of a VMM system. [Figure 19] 1 shows another example of a VMM system. [Figure 20] 1 shows another example of a VMM system. [Figure 21] 1 shows another example of a VMM system. [Figure 22] 1 shows another example of a VMM system. [Figure 23] 1 shows another example of a VMM system. [Figure 24] 1 shows another example of a VMM system. [Figure 25] 1 shows another example of a VMM system. [Figure 26] 1 illustrates a prior art memory system with redundancy. [Figure 27] 1 shows a VMM system. [Figure 28] 1 illustrates an exemplary input block for implementing row redundancy in a VMM array. [Figure 29] 1 illustrates an exemplary input block for implementing row redundancy in a VMM array. [Figure 30] 1 shows a row tag register load circuit. [Figure 31] 1 shows a row register load circuit. [Figure 32] 10 shows a row register load operation. [Figure 33] 10 illustrates a row tag register load operation. [Figure 34] The neural readout method is shown. [Figure 35]An output block for implementing column redundancy in a VMM array is shown. [Figure 36] A neural readout method is shown.

Best Mode for Carrying Out the Invention

[0114] <Structure of the VMM System> Figure 27 shows a block diagram of a VMM system 2700. The VMM system 2700 includes a VMM array 2701, a redundant array 3519A (redundant row array), a redundant array 3519B (redundant column array), a row decoder 2702, a high-voltage decoder 2703, a column decoder 2704, a bit-line driver 2705 (such as a bit-line control circuit for programming), an input circuit 2706, an output circuit 2707, control logic 2708, and a bias generator 2709. The VMM system 2700 further includes a high-voltage generation block 2710 including a charge pump 2711, a charge pump regulator 2712, and a high-voltage level generator 2713. The VMM system 2700 further includes a (program / erase, or weight tuning) algorithm controller 2714, an analog circuit 2715, a control engine 2716 (which may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, etc., but is not limited thereto), test control logic 2717, and a static random access memory (SRAM) block 2718 for storing intermediate data such as for the input circuit (e.g., activation data) or the output circuit (neuron output data, partial sum output neuron data), or data input for programming (data input for the entire row or multiple rows, etc.). Here, the redundant arrays 3519A and 3519B are shown as part of the same physical array as the VMM array 2701, but those skilled in the art will understand that the redundant arrays 3519A and 3519B and the VMM array 2701 may instead be located in separate physical arrays respectively.

[0115] The input circuit 2706 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 2706 may implement one or more of a normalization, a linear or nonlinear up / downscaling function, or an arithmetic function. The input circuit 2706 may implement a temperature compensation function for the input level. The input circuit 2706 may implement an activation function such as a ReLU or a sigmoid. The input circuit 2706 may store digital activation data that is applied as an input signal or combined with an input signal during a program or read operation. The digital activation data may be stored in a register. The input circuitry 2706 may include circuitry for driving the array terminals, such as the CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. DACs can be used to convert digital activation data into analog input voltages that are applied to the array.

[0116] The output circuit 2707 may include circuits such as an ITV (current-to-voltage circuit), an ADC (an analog-to-digital converter for converting neuron analog outputs to digital bits), an AAC (an analog-to-analog converter, such as, but not limited to, a current-to-voltage converter or a logarithmic converter), an APC (an analog-to-pulse converter, an analog-to-time modulated pulse converter), or any other type of converter. The output circuit 2707 can convert the array output into activation data. The output circuit 2707 may implement activation functions such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 2707 may implement one or more of statistical normalization, regularization, up / downscaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, log) of the neuron output. The output circuit 2707 may implement a temperature compensation function for the neuron outputs or array outputs (such as bit line outputs) to keep the power consumption of the array approximately constant over temperature changes, or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same over temperature changes. The output circuit 2707 may also include registers to store the output data.

[0117] VMM array 2701, redundant array 3519A, and redundant array 3519B each include an array of non-volatile memory cells arranged in rows and columns, where the non-volatile memory cells are of the type shown in Figures 2, 3, 4, or 5 as memory cells 210, 310, 410, or 510, respectively, or other types known to those skilled in the art. In one example, the non-volatile memory cells are split-gate flash memory cells, such as those in Figure 2, 3, or 4. In another example, the non-volatile memory cells are stacked-gate flash memory cells, such as those in Figure 5.

[0118] FIG. 28 shows an input block 2800 that provides row (or sector) redundancy during neural read operations of a VMM array 2701. Input block 2800 includes address decoders 2801-0 to 2801-n, each corresponding to one of row numbers 0 to n in VMM array 2701; redundant address decoders 2811-0 to 2811-m, each corresponding to one of redundant row numbers 0 to m in redundant array 3519A; row registers 2802-0 to 2802-n, each corresponding to one of rows numbered 0 to n in VMM array 2701 and coupled to associated address decoder 2801; redundant row registers 2812-0 to 2812-m, each corresponding to one of redundant row numbers 0 to m in redundant array 3519A and coupled to associated redundant address decoder 2811; 802, redundant row tag registers 2813-0 to 2813-m corresponding to one of the redundant row numbers 0 to m in the redundant array 3519A and coupled to an associated redundant address decoder 2811 and redundant row register 2812, digital-to-analog (which may also be referred to as DAC, row DAC, or local DAC) converters 2804-0 to 2804-n corresponding to one of the row numbers 0 to n in the VMM array 2701 and coupled to an associated row register 2802 and row tag register 2803, and redundant digital-to-analog converters 2814-0 to 2814-m corresponding to one of the row numbers 0 to m in the redundant array 3519A and coupled to an associated redundant row register 2812 and redundant row tag register 2813, respectively.

[0119] Optionally, rows are organized into sectors, and sectors are organized into sector groups. In one example, each sector includes two rows, and each sector group includes four sectors. Optionally, row register 2802 and redundant row register 2812 can each store 8 bits, 4 bits, 16 bits, or any other number of bits. Optionally, row tag register 2803 and redundant row tag register 2813 can each store 1 bit that acts as a tag bit for its associated row.

[0120] At the start of a neural read operation, row registers 2802-0 through 2802-n and redundant row registers 2812-0 through 2812-m are loaded with digital input bits DINx (where x is the number of bits in DIN, such as 128 bits), which can be from raw input data (e.g., an image) or from the output of a previous network layer, to be applied to that particular row during the neural read operation. ENRR is an enable signal that enables the loading of the row registers. When enabled, the clock signal CLK is used to load the digital input bits DINx into the respective row registers 2802 and redundant row registers 2812. In one example, x=128, and row registers 2802 and redundant row registers 2812 each store 8 bits, in which case 16 row registers 2802 and redundant row registers 2812 can be loaded per clock cycle. If a particular row of VMM array 2701 is known to be bad, its associated redundant row register is loaded instead of, or in addition to, the row register of the bad row. This register loading operation is described in more detail below with reference to Figure 32.

[0121] 28, at the start of or prior to a neural read operation, row tag registers 2803-0 and 2803-n are each loaded with a first value (e.g., “1”) if the associated row is a good row and enabled (indicated by a DIN received for its row tag bit = “1”), and a second value (e.g., “0”) if the associated row is a bad row (indicated by a DIN received for its row tag bit = “0”). Similarly, redundant row tag registers 2813-0 through 2813-m are each loaded with a third value (e.g., “1”) if a redundant row is used and enabled (indicated by a DIN received for its redundant row tag bit = “1”), and a fourth value (e.g., “0”) if a redundant row is not used (indicated by a DIN received for its redundant row tag bit = “0”). The DINx, ENRT (which is an enable signal that enables the loading of the row tag registers), and CLK signals are used for this tag register loading operation, along with tag bit load circuitry 3000, which is described in more detail below with reference to Figure 30. In an example where x=128, 128 row tag registers 2803 and redundant row tag registers 2813 are loaded every clock cycle. An example of this row tag register loading is described in more detail below with reference to Figure 33.

[0122] Alternatively, instead of loading tag bit values ​​into all row tag registers 2803 and all redundant row tag registers 2813, row address XA[k:0] is used to access one bad row or one redundant row at a time, and a second value indicating the bad row (e.g., "0") is loaded directly into the associated row tag register 2803, and a third value indicating that a redundant row is used (e.g., "1") is loaded into the associated redundant row tag register 2813.

[0123] Referring again to FIG. 28 , after the row register 2802, redundant row register 2812, row tag register 2803, and redundant row tag register 2813 are loaded, a neural read operation can be performed. In a neural read operation, all rows in the VMM array are read at once, so no addresses (XA[k:0]) are required; instead, the read operations for those rows can be enabled by a global enable signal ENRDG. All row registers 2802 that receive the enable signal ENRDG output their stored activation data to their associated digital-to-analog converters 2804. If the tag bit in the row tag register 2803 indicates a good row (e.g., tag bit="1"), the row tag register 2803 asserts an output enable signal (e.g., output="1") to the associated digital-to-analog converter 2804. If the tag bit in row tag register 2803 indicates a bad row (e.g., tag bit="0"), row tag register 2803 deasserts the output enable signal (e.g., output="0") to the associated digital-to-analog converter 2804. Digital-to-analog converter 2804, which receives the asserted output enable signal from row tag register 2803, converts the received digital value received from the associated row register 2802 into analog voltages CG0-CGn that are applied to respective control gate lines in VMM array 2701.

[0124] In another example, the global enable signal ENRDG enables the DAC to convert inputs from the row register and tag bits into an analog voltage CGx that is applied to each control gate in the VMM array 2701. In this case, the row register and tag bits are pre-enabled. In another example, the global enable signal ENRDG enables the analog output CGx of the DAC to be applied to each control gate in the VMM array 2701 via an output mux (not shown) at the DAC output. In this case, the row register, tag bits, and DAC are pre-enabled.

[0125] Similarly, during a neural read operation, the redundant address (XRA[k:0]) is not required; instead, the redundant row read operation may be enabled by a global enable signal ENRDG. All redundant row registers 2812 that receive the enable signal ENRDG output their stored activation data to their associated redundant digital-to-analog converters 2814. If the tag bit in the row tag register 2813 indicates that a redundant row is used (e.g., redundant tag bit="1"), the redundant row tag register 2813 will assert an output enable signal (e.g., output="1") to the associated redundant digital-to-analog converter 2814. If the tag bit in the redundant row tag register 2813 indicates that a redundant row is not used (e.g., redundant tag bit="0"), the redundant row tag register 2814 deasserts the output enable signal (e.g., output="0") to the associated redundant digital-to-analog converter 2814. A redundant digital-to-analog converter 2814, which receives an asserted output enable signal from the redundant row tag register 2813, converts the digital value received from the associated redundant row register 2812 into an analog voltage CGR0-CGRm that is applied to each control gate line in the redundant array 2719A. As with the normal rows, alternatively, a global enable signal ENRDG enables the output of the DAC, or DACs in the case of normal rows.

[0126] The end result is that all good rows but not the bad rows in VMM array 2701 receive the input values, the redundant rows in redundant array 2719 associated with the bad rows in VMM array 2701 receive the input values, and the desired output current is received from VMM array 2701 and redundant array 3519A (e.g., in the form of currents from bit lines of VMM array 2701 and redundant array 3519A) as the output of the neural read operation. The row tag register and redundant row tag register are used to identify the row and redundant row to be read during the neural read operation.

[0127] Figure 29 shows an input block 2900 similar to input block 2800 of Figure 28, except that DAC 2804 and redundant DAC 2814 have been replaced by respective sample and hold (S / H) logic and buffer 2904 and redundant sample and hold logic and buffer 2914, as well as a global digital-to-analog converter (DAC) 2920 and sample and hold (S / H) and DAC logic circuit 2910. During a neural read operation, activation data from row register 2802 and redundant row register 2812 is provided to the respective S / H logic and buffer 2804. S / H and DAC logic 2910 controls global DAC 2920 to provide a global DAC analog voltage to local S / H logic and buffer 2904. S / H and DAC logic 2920, in conjunction with logic in logic S / H logic and buffer 2904, samples the corresponding global DAC analog voltage into a local buffer in logic S / H and logic buffer. Further details regarding the implementation of the sample and hold buffers, global digital-to-analog converter, and S / H and DAC logic are contained in U.S. patent application Ser. No. 18 / 077,686, filed Dec. 8, 2022, entitled "Input Circuit for Artificial Neural Network Array," which is incorporated herein by reference. Row tag register 2803 and redundant row tag register 2813 generate asserted or deasserted output enable signals in the same manner as described above for FIG. 28. Sample and hold buffer 2904 and redundant sample and hold buffers that receive asserted output enable signals from row tag register 2803 or redundant row tag register 2813 apply their held analog voltages CGR0-CGRm to respective control gate lines in redundant array 2719A.

[0128] FIG. 30 shows row tag register load circuit 3000, which includes address comparators 3001 and 3011 and switches 3002, 3003, 3012 and 3013, and is used to load tag bits and redundant tag bits received as DIN into row tag register 2803 and redundant row tag register 2813 during a load operation.

[0129] Address comparator 3001 and switches 3002 and 3003 are used to load data into row tag register 2803. Address comparator 3001 compares the received row address XA[k:0] with the known bad address XA'[k:0] stored in table 2607. If there is a match, switch 3003 is closed and switch 3002 is open, and DIN_INT, an input to the respective tag register, is tied to ground (i.e., DIN_INT="0"), resulting in a tag bit loaded into the tag bit register of "0". If there is no match, switch 3003 is open and switch 3002 is closed, and DIN_INT is the same value as the received DIN value, which defaults to "1". This action results in a stored tag bit of "1" (first value) if the row is a good row, or "0" (second value) if the row is a bad row.

[0130] Address comparator 3011 and switches 3012 and 3013 are used to program redundant tag bit register 2813. Address comparator 3011 compares the received row address XA[k:0] with the known bad address XA'[k:0] stored in table 2607. If there is a match, switch 3013 is closed, switch 3012 is open, and DIN_INT has the same value as the received DIN value, which is "1" by default. This causes the redundant tag bit loaded into the redundant tag bit register to be "1". If there is no match, switch 3013 is open and switch 3012 is closed, which couples DIN_INT to ground (i.e., DIN_INT="0"), which causes the redundant tag bit loaded into the redundant tag bit register to be "0". This action results in the stored redundant tag bit being "1" (first value) if a redundant row is used, or "0" (second value) if a redundant row is not used.

[0131] FIG. 31 shows row register load circuit 3100, which includes address comparators 3101 and 3111, and switches 3102, 3103, 3112, and 3113, and is used to activate data received as DIN to row register 2802 and redundant row register 2812 during a load operation.

[0132] Address comparator 3101 and switches 3102 and 3103 are used to load data into row register 2802. Address comparator 3101 compares the received row address XA[k:0] with the known bad address XA′[k:0] stored in table 2607. If there is a match, switch 3103 is closed, switch 3102 is open, and DIN_INT, the input to each row register 2802, is tied to ground (i.e., DIN_INT[7:0]="0"), which causes all bits loaded into each row register 2802 to be "0". If there is no match, switch 3103 is open, switch 3102 is closed, and DIN_INT[7:0] is the same value as the received DIN[7:0] value, meaning the received activation data is loaded into row register 2802. As a result of this action, if the row is a good row, the activation data is stored, and if the row is a bad row, all zeros are stored.

[0133] Address comparator 3111 and switches 3112 and 3113 are used to program redundant row register 2812. Address comparator 3111 compares the received row address XA[k:0] with the known bad address XA'[k:0] stored in table 2607. If there is a match, switch 3113 is closed, switch 3112 is open, and DIN_INT[7:0] has the same value as the received DIN[7:0] value, meaning that the received activation data is loaded into redundant row register 2812. If there is no match, switch 3113 is opened and switch 3112 is closed, which couples DIN_INT[7:0] to ground (DIN_INT[7:0]="0"). This causes all bits loaded into each redundant row register 2812 to be "0". As a result of this operation, activation data is stored if a redundant row is used, or all zeros are stored if a redundant row is not used.

[0134] FIG. 32 illustrates a row register load operation 3200 used to load row group i data into the row registers 2802 and redundant row registers 2812 described above with reference to FIGS.

[0135] In operation 3201, input block 2800 receives the row group address of row group i (including a first set of bits included in address XA[k:0] to indicate a particular row group), the row address of a row within row group i (including a second set of bits included in address XA[k:0] to identify a particular row within the row group), and data DIN[127:0] to be loaded into the row registers corresponding to those row addresses within row group i.

[0136] In operation 3202, the system determines whether the row group address matches any stored row group address that contains a bad row as shown in table 2607. If no, row group i and its rows do not contain a bad row, and the load operation proceeds to operation 3204. If yes, row group i contains at least one bad row, and the load operation proceeds to operation 3203.

[0137] In operation 3203, the system identifies a redundant row register associated with the row address of a faulty row in row group i and loads the bits in DIN[127:0] that correspond to the associated faulty row address. For example, if table 2607 indicates that row address X1 in row group i is a faulty row, table 2607 further identifies a redundant row to use in place of row X1. The data in DIN[127:0] of the faulty row X1 is then loaded into the associated redundant row register.

[0138] In operation 3204, the system loads DIN[127:0] into the row registers in row group i. This includes loading data into bad row X1. The data in bad row X1 is not actually used in subsequent read or neural read operations because its associated row tag bits indicate it is a bad row. Alternatively, the system can instead load no data into any bad rows, such as row X1, or load data with a known pattern, such as all "0s."

[0139] FIG. 33 illustrates a row tag register load operation 3300 used to load data into row tag register 2803 and redundant row tag register 2813 described above with reference to FIGS. 28, 36B, and 37A.

[0140] In operation 3301, the system receives a row group address for row group i (including a first set of bits included in address XA[k:0] to indicate a particular row group), a row address for a row within row group i (including a second set of bits included in address XA[k:0] to identify a particular row within the row group), and data DIN[127:0] to be loaded into the row tag registers corresponding to those row addresses within row group i.

[0141] In operation 3302, the system determines whether the row group address matches any stored row group addresses that contain bad rows as shown in table 2607. If no, row group I does not contain any bad rows, and the load operation proceeds to operation 3303. If yes, row group I contains at least one bad row, and the load operation proceeds to operation 3304.

[0142] In operation 3303, the system loads DIN[127:0] into the row tag register in row group i.

[0143] In operation 3304, the system identifies the redundant row tag register associated with the faulty row in row group i by consulting table 2607, and loads the bits in DIN[127:0] (which may be all "1") into the redundant row tag register corresponding to the associated row address. For example, if table 2607 indicates that row address X1 in group i is a faulty row, table 2607 further identifies the redundant row to use in place of row X1. The row tag data in the row tag data register associated with the faulty row X1 is then loaded with "0" to indicate that the row is a faulty row. The redundant row tag data in the associated redundant row tag data register is loaded with "1" to indicate that a redundant row will be used. The row tag data in DIN[127:0] associated with row address X1 is stored in the redundant row tag register associated with redundant row address R1.

[0144] In operation 3305, the system loads DIN[127:0] into the row tag registers in row group i for rows associated with redundant rows that are not bad rows, and loads "0" into the row tag registers for bad rows associated with redundant rows.

[0145] In this way, the row tag register is loaded with bits indicating which rows are good rows and which rows are bad rows, and the redundant row tag register is loaded with bits indicating which redundant rows are used during a read or neural read operation and which redundant rows are not used during a read or neural read operation.

[0146] 34 shows a neural readout method 3400. The neural readout method 3400 includes operations 3401, 3402, and 3403.

[0147] Operation 3401 includes converting data stored in the row register to a first set of analog voltages based on values ​​stored in the row tag register, and applying the first set of analog voltages to respective rows of non-volatile memory cells in the array of non-volatile memory cells. Under one option, converting the data stored in the row register includes receiving, by a digital-to-analog converter, digital data from the row tag register and generating the first set of analog voltages. Under another option, converting the data stored in the row register includes sampling and holding, by a sample-and-hold buffer, the first set of analog voltages in response to the digital data from the row tag register.

[0148] Operation 3402 includes converting the data stored in the redundant row register to a second set of analog voltages based on the value stored in the redundant row tag register, and applying the second set of analog voltages to respective rows of non-volatile memory cells in the redundant array of non-volatile memory cells. Under one option, converting the data stored in the redundant row register includes receiving, by a redundant digital-to-analog converter, digital data from the redundant row tag register and generating the second set of analog signals. Under another option, converting the data stored in the redundant row register includes sampling and holding, by a sample-and-hold buffer, the second set of analog voltages in response to the digital data from the redundant row tag register.

[0149] Operation 3403 includes receiving current from the array of non-volatile memory cells and the redundant array of non-volatile memory cells.

[0150] The array in method 3400 may include an array of non-volatile memory cells. The non-volatile memory cells may include stacked gate flash memory cells (such as the type shown as memory cell 510 in FIG. 5) or split gate flash memory cells (such as the types shown as memory cells 210, 310, and 410 in FIGS. 2-4).

[0151] Redundancy can also be implemented on a column basis instead of a row basis. Figure 35 shows an output block 3500 that implements column redundancy for a VMM array 2701 using the redundant array 2719B of Figure 27. Each column in the VMM array 2701 is associated with a respective column multiplexer 3501, a respective analog-to-digital converter 3502, a respective address comparator 3504, and a switch, as shown. Prior to a neural read operation, a set of column addresses known to be bad columns (which may be determined by comparison with addresses in table 3513) are identified, and tag bits in column tag register 3503 are set to identify those bad columns. For example, a tag bit of "0" can indicate a bad column, and a tag bit of "1" can indicate a good column. Thereafter, during a neural read operation, columns with tag bits indicating bad columns are not coupled to the output by the switch. For these columns, the corresponding redundant columns in redundant array 2719B are instead read using redundant column multiplexer 3511, redundant analog-to-digital converter 3512, and associated switches as shown. Thus, data from the good columns rather than the bad columns in VMM array 2701 is output, and the redundant data in redundant array 2719 associated with the bad columns is output. Tag bits in column tag register 3503 are used to indicate the good columns that will be used during the neural read operation and the bad columns that will not be used. One or more analog-to-digital converters 3502 convert the analog signal from column multiplexer 3501 to one or more bits, and one or more redundant analog-to-digital converters 3512 convert the analog signal from redundant column multiplexer 3511 to one or more bits.

[0152] Figure 36 shows a neural readout method 3600 utilizing output block 3400. Method 3600 includes operations 3601, 3602, and 3603. Operation 3601 includes setting a column tag bit in a column tag bit register associated with a column in the array to a first value or a second value based on data in a table. Operation 3602 includes receiving a current from a column in the array associated with a column tag bit of the first value and converting, by one or more analog-to-digital converters, the current received from the column in the array to digital data. Operation 3603 includes receiving a current from a redundant column in the redundant array when the redundant column is associated with a column in the array associated with a column tag bit of the second value and converting, by one or more redundant analog-to-digital converters, the current received from the redundant column in the redundant array to digital data.

[0153] The array in method 3600 may include an array of non-volatile memory cells. The non-volatile memory cells may include stacked gate flash memory cells (such as the type shown as memory cell 510 in FIG. 5) or split gate flash memory cells (such as the types shown as memory cells 210, 310, and 410 in FIGS. 2-4).

[0154] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a redundant array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; an input block coupled to each row in the array and each row in the redundant array, the input block comprising a plurality of row tag registers and a plurality of redundant row tag registers; a plurality of row tag registers each storing one of a first value indicating that a respective row of the array of non-volatile memory cells is used and a second value indicating that the respective row of the array of non-volatile memory cells is not used; a plurality of redundant row tag registers each storing one of a third value indicating that a respective row of the redundant array of non-volatile memory cells is used and a fourth value indicating that the respective row of the redundant array of non-volatile memory cells is not used; and the plurality of row tag registers and the plurality of redundant row tag registers identifying rows and redundant rows to be read during a neural read operation.

2. 2. The system of claim 1, wherein the input block comprises a plurality of row registers respectively coupled to the plurality of row tag registers.

3. 3. The system of claim 2, wherein said input block comprises a plurality of address decoders respectively coupled to said plurality of row registers.

4. 4. The system of claim 3, wherein the input block comprises one or more digital-to-analog converters coupled to the plurality of row tag registers.

5. 4. The system of claim 3, wherein the input block comprises a plurality of sample and hold buffers respectively coupled to the plurality of row tag registers.

6. 10. The system of claim 1, wherein the non-volatile memory cells in the array of non-volatile memory cells and the non-volatile memory cells in the redundant array of non-volatile memory cells are split-gate flash memory cells.

7. 10. The system of claim 1, wherein the non-volatile memory cells in the array of non-volatile memory cells and the non-volatile memory cells in the redundant array of non-volatile memory cells are stacked gate flash memory cells.

8. 1. A method comprising: converting data stored in a plurality of row registers into a first set of analog voltages based on values ​​stored in a plurality of row tag registers, and applying the first set of analog voltages to respective rows of non-volatile memory cells in the array of non-volatile memory cells; converting the data stored in the plurality of redundant row registers into a second set of analog voltages based on the values ​​stored in the plurality of redundant row tag registers, and applying the second set of analog voltages to respective rows of non-volatile memory cells in the redundant array of non-volatile memory cells; receiving current from the array of non-volatile memory cells and the redundant array of non-volatile memory cells.

9. converting the data stored in the row register includes receiving, by a digital-to-analog converter, digital data from the row tag register and generating the first set of analog voltages; 9. The method of claim 8, wherein converting the data stored in the redundant row register comprises receiving, by a redundant digital-to-analog converter, digital data from the redundant row tag register; and generating the second set of analog voltages.

10. converting the data stored in the row register includes sampling and holding the first set of analog voltages with a sample and hold buffer in response to digital data from the row tag register; 9. The method of claim 8, wherein converting the data stored in the redundant row register comprises sampling and holding the second set of analog voltages with a sample and hold buffer in response to digital data from the redundant row tag register.

11. 1. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a redundant array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; an output block coupled to each column in the array and each column in the redundant array, the output block comprising a column multiplexer, a column tag register, and a redundant column multiplexer; a plurality of column tag registers each storing one of a first value indicating that a respective column of the array of non-volatile memory cells is to be used and a second value indicating that the respective column of the array of non-volatile memory cells is not to be used and that an associated redundant column of the redundant array of non-volatile memory cells is to be used, the plurality of column tag registers identifying a plurality of columns to be used during a neural read operation.

12. 12. The system of claim 11, wherein the output block comprises one or more analog-to-digital converters for converting analog signals from the column multiplexers to one or more bits, and one or more redundant analog-to-digital converters for converting analog signals from the redundant column multiplexers to one or more bits.

13. 12. The system of claim 11, wherein the non-volatile memory cells in the array of non-volatile memory cells and the non-volatile memory cells in the redundant array of non-volatile memory cells are split-gate flash memory cells.

14. 12. The system of claim 11, wherein the non-volatile memory cells in the array of non-volatile memory cells and the non-volatile memory cells in the redundant array of non-volatile memory cells are stacked gate flash memory cells.

15. 1. A method comprising: receiving currents from a plurality of columns in the array associated with column tag bits of a first value; receiving current from a plurality of redundant columns in a redundant array when the plurality of redundant columns are associated with a plurality of columns in the array associated with a column tag bit of a second value.

16. converting the currents received from the plurality of columns in the array into digital data by one or more analog-to-digital converters; and converting the currents received from the plurality of redundant columns in the redundant array into digital data by one or more redundant analog-to-digital converters.

17. 16. The method of claim 15, comprising setting column tag bits in a plurality of column tag bit registers associated with a plurality of columns in the array to a first value or a second value based on data in a table.

18. 16. The method of claim 15, wherein the array comprises an array of non-volatile memory cells, and the redundant array comprises an array of non-volatile memory cells.

19. 20. The method of claim 18, wherein the non-volatile memory cells in the array of non-volatile memory cells and the non-volatile memory cells in the redundant array of non-volatile memory cells are split-gate flash memory cells.

20. 20. The method of claim 18, wherein the non-volatile memory cells in the array of non-volatile memory cells and the non-volatile memory cells in the redundant array of non-volatile memory cells are stacked gate flash memory cells.

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